[U-Boot] [PATCH 0/7] ppc/p4080: infrastructure patches
This patch series includes the underpinings for the p4080 support. Its mostly focussed on the differenes in cpu/mpc85xx code between a PQ3/85xx platform and the p4080/CoreNet platforms.
The p4080 SoC has a significant amount of commonality with the 85xx/PQ3 platform. We reuse the 85xx immap and just add new definitions for local access and global utils. The global utils is now broken into global utils, clocking and run control/power management.
The offsets from CCSR for a number of blocks have also changed. We introduce the CONFIG_FSL_CORENET define to distinquish the PQ3 style of platform from the new p4080 platform. We don't use QoirQ as there are products (like p2020) that are PQ3 based platforms but have the QoirQ name.
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- include/asm-ppc/fsl_lbc.h | 4 + include/asm-ppc/immap_85xx.h | 408 +++++++++++++++++++++++++++++++++++++++-- 2 files changed, 392 insertions(+), 20 deletions(-)
diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h index 08d31e1..5723de6 100644 --- a/include/asm-ppc/fsl_lbc.h +++ b/include/asm-ppc/fsl_lbc.h @@ -317,6 +317,10 @@ #define LCRR_CLKDIV_2 0x00000002 #define LCRR_CLKDIV_4 0x00000004 #define LCRR_CLKDIV_8 0x00000008 +#elif defined(CONFIG_FSL_CORENET) +#define LCRR_CLKDIV_8 0x00000002 +#define LCRR_CLKDIV_16 0x00000004 +#define LCRR_CLKDIV_32 0x00000008 #else #define LCRR_CLKDIV_4 0x00000002 #define LCRR_CLKDIV_8 0x00000004 diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index e7d412d..cfcfa5d 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -16,6 +16,150 @@ #include <asm/fsl_i2c.h> #include <asm/fsl_lbc.h>
+typedef struct ccsr_local { + u32 ccsrbarh; /* 0x0 - Control Configuration Status Registers Base Address Register High */ + u32 ccsrbarl; /* 0x4 - Control Configuration Status Registers Base Address Register Low */ + u32 ccsrar; /* 0x8 - Configuration, Control, and Status Attribute Register */ +#define CCSRAR_C 0x80000000 /* Commit */ + u8 res1[4]; + u32 altcbarh; /* 0x10 - Alternate Configuration Base Address Register High */ + u32 altcbarl; /* 0x14 - Alternate Configuration Base Address Register Low */ + u32 altcar; /* 0x18 - Alternate Configuration Attribute Register */ + u8 res2[4]; + u32 bstrh; /* 0x20 - Boot space translation register high */ + u32 bstrl; /* 0x24 - Boot space translation register Low */ + u32 bstrar; /* 0x28 - Boot space translation attributes register */ + u8 res3[0xbd4]; + u32 lawbarh0; /* 0xc00 - LAW0 base address register high */ + u32 lawbarl0; /* 0xc04 - LAW0 base address register low */ + u32 lawar0; /* 0xc08 - LAW0 attributes register */ + u8 res4[4]; + u32 lawbarh1; /* 0xc10 - LAW1 base address register high */ + u32 lawbarl1; /* 0xc14 - LAW1 base address register low */ + u32 lawar1; /* 0xc18 - LAW1 attributes register */ + u8 res5[4]; + u32 lawbarh2; /* 0xc20 - LAW2 base address register high */ + u32 lawbarl2; /* 0xc24 - LAW2 base address register low */ + u32 lawar2; /* 0xc28 - LAW2 attributes register */ + u8 res6[4]; + u32 lawbarh3; /* 0xc30 - LAW3 base address register high */ + u32 lawbarl3; /* 0xc34 - LAW3 base address register low */ + u32 lawar3; /* 0xc38 - LAW3 attributes register */ + u8 res7[4]; + u32 lawbarh4; /* 0xc40 - LAW4 base address register high */ + u32 lawbarl4; /* 0xc44 - LAW4 base address register low */ + u32 lawar4; /* 0xc48 - LAW4 attributes register */ + u8 res8[4]; + u32 lawbarh5; /* 0xc50 - LAW5 base address register high */ + u32 lawbarl5; /* 0xc54 - LAW5 base address register low */ + u32 lawar5; /* 0xc58 - LAW5 attributes register */ + u8 res9[4]; + u32 lawbarh6; /* 0xc60 - LAW6 base address register high */ + u32 lawbarl6; /* 0xc64 - LAW6 base address register low */ + u32 lawar6; /* 0xc68 - LAW6 attributes register */ + u8 res10[4]; + u32 lawbarh7; /* 0xc70 - LAW7 base address register high */ + u32 lawbarl7; /* 0xc74 - LAW7 base address register low */ + u32 lawar7; /* 0xc78 - LAW7 attributes register */ + u8 res11[4]; + u32 lawbarh8; /* 0xc80 - LAW8 base address register high */ + u32 lawbarl8; /* 0xc84 - LAW8 base address register low */ + u32 lawar8; /* 0xc88 - LAW8 attributes register */ + u8 res12[4]; + u32 lawbarh9; /* 0xc90 - LAW9 base address register high */ + u32 lawbarl9; /* 0xc94 - LAW9 base address register low */ + u32 lawar9; /* 0xc98 - LAW9 attributes register */ + u8 res13[4]; + u32 lawbarh10; /* 0xca0 - LAW10 base address register high */ + u32 lawbarl10; /* 0xca4 - LAW10 base address register low */ + u32 lawar10; /* 0xca8 - LAW10 attributes register */ + u8 res14[4]; + u32 lawbarh11; /* 0xcb0 - LAW11 base address register high */ + u32 lawbarl11; /* 0xcb4 - LAW11 base address register low */ + u32 lawar11; /* 0xcb8 - LAW11 attributes register */ + u8 res15[4]; + u32 lawbarh12; /* 0xcc0 - LAW12 base address register high */ + u32 lawbarl12; /* 0xcc4 - LAW12 base address register low */ + u32 lawar12; /* 0xcc8 - LAW12 attributes register */ + u8 res16[4]; + u32 lawbarh13; /* 0xcd0 - LAW13 base address register high */ + u32 lawbarl13; /* 0xcd4 - LAW13 base address register low */ + u32 lawar13; /* 0xcd8 - LAW13 attributes register */ + u8 res17[4]; + u32 lawbarh14; /* 0xce0 - LAW14 base address register high */ + u32 lawbarl14; /* 0xce4 - LAW14 base address register low */ + u32 lawar14; /* 0xce8 - LAW14 attributes register */ + u8 res18[4]; + u32 lawbarh15; /* 0xcf0 - LAW15 base address register high */ + u32 lawbarl15; /* 0xcf4 - LAW15 base address register low */ + u32 lawar15; /* 0xcf8 - LAW15 attributes register */ + u8 res19[4]; + u32 lawbarh16; /* 0xd00 - LAW16 base address register high */ + u32 lawbarl16; /* 0xd04 - LAW16 base address register low */ + u32 lawar16; /* 0xd08 - LAW16 attributes register */ + u8 res20[4]; + u32 lawbarh17; /* 0xd10 - LAW17 base address register high */ + u32 lawbarl17; /* 0xd14 - LAW17 base address register low */ + u32 lawar17; /* 0xd18 - LAW17 attributes register */ + u8 res21[4]; + u32 lawbarh18; /* 0xd20 - LAW18 base address register high */ + u32 lawbarl18; /* 0xd24 - LAW18 base address register low */ + u32 lawar18; /* 0xd28 - LAW18 attributes register */ + u8 res22[4]; + u32 lawbarh19; /* 0xd30 - LAW19 base address register high */ + u32 lawbarl19; /* 0xd34 - LAW19 base address register low */ + u32 lawar19; /* 0xd38 - LAW19 attributes register */ + u8 res23[4]; + u32 lawbarh20; /* 0xd40 - LAW20 base address register high */ + u32 lawbarl20; /* 0xd44 - LAW20 base address register low */ + u32 lawar20; /* 0xd48 - LAW20 attributes register */ + u8 res24[4]; + u32 lawbarh21; /* 0xd50 - LAW21 base address register high */ + u32 lawbarl21; /* 0xd54 - LAW21 base address register low */ + u32 lawar21; /* 0xd58 - LAW21 attributes register */ + u8 res25[4]; + u32 lawbarh22; /* 0xd60 - LAW22 base address register high */ + u32 lawbarl22; /* 0xd64 - LAW22 base address register low */ + u32 lawar22; /* 0xd68 - LAW22 attributes register */ + u8 res26[4]; + u32 lawbarh23; /* 0xd70 - LAW23 base address register high */ + u32 lawbarl23; /* 0xd74 - LAW23 base address register low */ + u32 lawar23; /* 0xd78 - LAW23 attributes register */ + u8 res27[4]; + u32 lawbarh24; /* 0xd80 - LAW24 base address register high */ + u32 lawbarl24; /* 0xd84 - LAW24 base address register low */ + u32 lawar24; /* 0xd88 - LAW24 attributes register */ + u8 res28[4]; + u32 lawbarh25; /* 0xd90 - LAW25 base address register high */ + u32 lawbarl25; /* 0xd94 - LAW25 base address register low */ + u32 lawar25; /* 0xd98 - LAW25 attributes register */ + u8 res29[4]; + u32 lawbarh26; /* 0xda0 - LAW26 base address register high */ + u32 lawbarl26; /* 0xda4 - LAW26 base address register low */ + u32 lawar26; /* 0xda8 - LAW26 attributes register */ + u8 res30[4]; + u32 lawbarh27; /* 0xdb0 - LAW27 base address register high */ + u32 lawbarl27; /* 0xdb4 - LAW27 base address register low */ + u32 lawar27; /* 0xdb8 - LAW27 attributes register */ + u8 res31[4]; + u32 lawbarh28; /* 0xdc0 - LAW28 base address register high */ + u32 lawbarl28; /* 0xdc4 - LAW28 base address register low */ + u32 lawar28; /* 0xdc8 - LAW28 attributes register */ + u8 res32[4]; + u32 lawbarh29; /* 0xdd0 - LAW29 base address register high */ + u32 lawbarl29; /* 0xdd4 - LAW29 base address register low */ + u32 lawar29; /* 0xdd8 - LAW29 attributes register */ + u8 res33[4]; + u32 lawbarh30; /* 0xde0 - LAW30 base address register high */ + u32 lawbarl30; /* 0xde4 - LAW30 base address register low */ + u32 lawar30; /* 0xde8 - LAW30 attributes register */ + u8 res34[4]; + u32 lawbarh31; /* 0xdf0 - LAW31 base address register high */ + u32 lawbarl31; /* 0xdf4 - LAW31 base address register low */ + u32 lawar31; /* 0xdf8 - LAW31 attributes register */ + u8 res35[0x204]; +} ccsr_local_t; + /* * Local-Access Registers and ECM Registers(0x0000-0x2000) */ @@ -165,7 +309,21 @@ typedef struct ccsr_ddr { uint debug_2; uint debug_3; uint debug_4; - char res12[240]; + uint debug_5; + uint debug_6; + uint debug_7; + uint debug_8; + uint debug_9; + uint debug_10; + uint debug_11; + uint debug_12; + uint debug_13; /* +0xF30 */ + uint debug_14; + uint debug_15; + uint debug_16; + uint debug_17; + uint debug_18; /* +0xF44 */ + char res12[184]; } ccsr_ddr_t;
/* @@ -1531,6 +1689,193 @@ typedef struct par_io { /* * Global Utilities Register Block(0xe_0000-0xf_ffff) */ +#ifdef CONFIG_FSL_CORENET +typedef struct ccsr_gur { + uint porsr1; /* 0xe0000 - POR status register */ + char res1[28]; /* 0xe0004 - 0xe001c Reserved: PORSRn */ + uint gpporcr1; /* 0xe0020 - General-purpose POR configuration register */ + char res2[12]; + uint gpiocr; /* 0xe0030 - GPIO control register */ + char res3[12]; + uint gpoutdr; /* 0xe0040 - General-purpose output data register */ + char res4[12]; + uint gpindr; /* 0xe0050 - General-purpose input data register */ + char res5[12]; + uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */ + char res6[12]; + uint devdisr; /* 0xe0070 - Device disable control */ +#define FSL_CORENET_DEVDISR_PCIE1 0x80000000 +#define FSL_CORENET_DEVDISR_PCIE2 0x40000000 +#define FSL_CORENET_DEVDISR_PCIE3 0x20000000 +#define FSL_CORENET_DEVDISR_RMU 0x08000000 +#define FSL_CORENET_DEVDISR_SRIO1 0x04000000 +#define FSL_CORENET_DEVDISR_SRIO2 0x02000000 +#define FSL_CORENET_DEVDISR_DMA1 0x00400000 +#define FSL_CORENET_DEVDISR_DMA2 0x00200000 +#define FSL_CORENET_DEVDISR_DDR1 0x00100000 +#define FSL_CORENET_DEVDISR_DDR2 0x00080000 +#define FSL_CORENET_DEVDISR_DBG 0x00010000 +#define FSL_CORENET_DEVDISR_NAL 0x00008000 +#define FSL_CORENET_DEVDISR_ELBC 0x00001000 +#define FSL_CORENET_DEVDISR_USB1 0x00000800 +#define FSL_CORENET_DEVDISR_USB2 0x00000400 +#define FSL_CORENET_DEVDISR_ESDHC 0x00000100 +#define FSL_CORENET_DEVDISR_GPIO 0x00000080 +#define FSL_CORENET_DEVDISR_ESPI 0x00000040 +#define FSL_CORENET_DEVDISR_I2C1 0x00000020 +#define FSL_CORENET_DEVDISR_I2C2 0x00000010 +#define FSL_CORENET_DEVDISR_DUART1 0x00000002 +#define FSL_CORENET_DEVDISR_DUART2 0x00000001 + char res7[12]; + uint powmgtcsr; /* 0xe0080 - Power management status and control register */ + char res8[12]; + uint coredisru; /* 0xe0090 - uppper portion for support of 64 cores */ + uint coredisrl; /* 0xe0094 - lower portion for support of 64 cores */ + char res9[8]; + uint pvr; /* 0xe00a0 - Processor version register */ + uint svr; /* 0xe00a4 - System version register */ + char res10[8]; + uint rstcr; /* 0xe00b0 - Reset control register */ + uint rstrqpblsr; /* 0xe00b4 - Reset request preboot loader status register */ + char res11[8]; + uint rstrqmr1; /* 0xe00c0 - Reset request mask register */ + char res12[4]; /* Reserved: RSTRQMR2 */ + uint rstrqsr1; /* 0xe00c8 - Reset request status register */ + char res13[4]; /* Reserved: RSTRQSR2 */ + char res14[4]; /* Reserved: RSTRQWDTMRU */ + uint rstrqwdtmrl; /* 0xe00d4 - Reset request WDT mask register */ + char res15[4]; /* Reserved: RSTRQWDTSRU */ + uint rstrqwdtsrl; /* 0xe00dc - Reset request WDT status register */ + char res16[4]; /* Reserved: BRRU max total of 2 for up to 64 cores */ + uint brrl; /* 0xe00e4 Boot release register */ + char res17[24]; + uint rcwsr[16]; /* 0xe0100 - 0xe013c: Reset control word status register */ +#define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000 +#define FSL_CORENET_RCWSR5_DDR_SYNC 0x00008000 +#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 15 +#define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000 +#define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000 +#define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000 + char res18[192]; /* Reserved: RCWSRn (max total of 64)*/ + uint scratchrw[4]; /* 0xe0200 - 0xe020c: Scratch Read/Write register */ + char res19[240]; /* Reserved: SCRATCHRWn (max total of 64)*/ + uint scratchw1r[4]; /* 0xe0300 - 0xe030c: Scratch Read register (Write once) */ + char res20[240]; /* Reserved: SCRATCHW1Rn (max total of 64)*/ + uint scrtsr[8]; /* 0xe0400 - 0xe041c: Core reset status register */ + char res21[224]; /* Reserved: CRSTSRn (max total of 64 for up to 64 cores)*/ + uint pex1liodnr; /* 0xe0500 PCI Express 1 Logical I/O Device Number register*/ + uint pex2liodnr; /* 0xe0504 PCI Express 2 Logical I/O Device Number register*/ + uint pex3liodnr; /* 0xe0508 PCI Express 3 Logical I/O Device Number register*/ + uint pex4liodnr; /* 0xe050c PCI Express 4 Logical I/O Device Number register*/ + uint rio1liodnr; /* 0xe0510 RIO 1 Logical I/O Device Number register*/ + uint rio2liodnr; /* 0xe0514 RIO 2 Logical I/O Device Number register*/ + uint rio3liodnr; /* 0xe0518 RIO 3 Logical I/O Device Number register*/ + uint rio4liodnr; /* 0xe051c RIO 4 Logical I/O Device Number register*/ + uint usb1liodnr; /* 0xe0520 USB 1 Logical I/O Device Number register*/ + uint usb2liodnr; /* 0xe0524 USB 2 Logical I/O Device Number register*/ + uint usb3liodnr; /* 0xe0528 USB 3 Logical I/O Device Number register*/ + uint usb4liodnr; /* 0xe052c USB 4 Logical I/O Device Number register*/ + uint sdmmc1liodnr; /* 0xe0530 SD/MMC 1 Logical I/O Device Number register*/ + uint sdmmc2liodnr; /* 0xe0534 SD/MMC 2 Logical I/O Device Number register*/ + uint sdmmc3liodnr; /* 0xe0538 SD/MMC 3 Logical I/O Device Number register*/ + uint sdmmc4liodnr; /* 0xe053c SD/MMC 4 Logical I/O Device Number register*/ + uint rmuliodnr; /* 0xe0540 RIO Message Unit Logical I/O Device Number register*/ + uint rduliodnr; /* 0xe0544 RIO Doorbell Unit Logical I/O Device Number register*/ + uint rpwuliodnr; /* 0xe0548 RIO Port Write Unit Logical I/O Device Number register*/ + char res22[52]; /* Reserved: for future LIODN register expansion */ + uint dma1liodnr; /* 0xe0580 DMA 1 Logical I/O Device Number register*/ + uint dma2liodnr; /* 0xe0584 DMA 2 Logical I/O Device Number register*/ + uint dma3liodnr; /* 0xe0588 DMA 3 Logical I/O Device Number register*/ + uint dma4liodnr; /* 0xe058c DMA 4 Logical I/O Device Number register*/ + char res23[48]; /* Reserved: for future LIODN register expansion */ + char res24[64]; /* Reserved */ + uint pblsr; /* 0xe0600 Preboot loader status register*/ + uint pamubypenr; /* 0xe0604 PAMU bypass enable register*/ + uint dmacr1; /* 0xe0608 DMA control register*/ + char res25[4]; /* Reserved: DMACR2 (max total of 2)*/ + uint gensr1; /* 0xe0610 General status register*/ + char res26[12]; /* Reserved: GENSRn (max total of 4)*/ + uint gencr1; /* 0xe0620 General control register*/ + char res27[12]; /* Reserved: GENCRn (max total of 4)*/ + char res28[4]; /* Reserved: CGENSRU (upper portion for support of 64 cores) */ + uint cgensrl; /* 0xe0634 Core general status register*/ + char res29[8]; /* Reserved */ + char res30[4]; /* Reserved: CGENCRU (upper portion for support of 64 cores) */ + uint cgencrl; /* 0xe0634 Core general control register*/ + char res31[184]; /* Reserved 0xe0648 - 0xe06fc */ + uint sriopstecr; /* 0xe0700 SRIO prescaler timer enable control register*/ + char res32[2300]; /* Reserved 0xe0704 - 0xe0ffc */ +} ccsr_gur_t; + +typedef struct ccsr_clk { + u32 clkc0csr; /* 0xe1000 - Core 0 Clock control/status register */ + u8 res1[0x1c]; + u32 clkc1csr; /* 0xe1020 - Core 1 Clock control/status register */ + u8 res2[0x1c]; + u32 clkc2csr; /* 0xe1040 - Core 2 Clock control/status register */ + u8 res3[0x1c]; + u32 clkc3csr; /* 0xe1060 - Core 3 Clock control/status register */ + u8 res4[0x1c]; + u32 clkc4csr; /* 0xe1080 - Core 4 Clock control/status register */ + u8 res5[0x1c]; + u32 clkc5csr; /* 0xe10a0 - Core 5 Clock control/status register */ + u8 res6[0x1c]; + u32 clkc6csr; /* 0xe10c0 - Core 6 Clock control/status register */ + u8 res7[0x1c]; + u32 clkc7csr; /* 0xe10e0 - Core 7 Clock control/status register */ + u8 res8[0x71c]; + u32 pllc1gsr; /* 0xe1800 - Cluster PLL 1 General Status Register */ + u8 res10[0x1c]; + u32 pllc2gsr; /* 0xe1820 - Cluster PLL 2 General Status Register */ + u8 res11[0x1c]; + u32 pllc3gsr; /* 0xe1840 - Cluster PLL 3 General Status Register */ + u8 res12[0x1c]; + u32 pllc4gsr; /* 0xe1860 - Cluster PLL 4 General Status Register */ + u8 res13[0x39c]; + u32 pllpgsr; /* 0xe1c00 - Platform PLL General Status Register */ + u8 res14[0x1c]; + u32 plldgsr; /* 0xe1c20 - DDR PLL General Status Register */ + u8 res15[0x3dc]; +} ccsr_clk_t; + +typedef struct ccsr_rcpm { + u8 res1[4]; /* 0xe2000 - Reserved */ + u32 cdozsrl; /* 0xe2004 - Core Doze Status Register */ + u8 res2[4]; /* 0xe2008 - Reserved */ + u32 cdozcrl; /* 0xe200c - Core Doze Control Register */ + u8 res3[4]; /* 0xe2010 - Reserved */ + u32 cnapsrl; /* 0xe2014 - Core Nap Status Register */ + u8 res4[4]; /* 0xe2018 - Reserved */ + u32 cnapcrl; /* 0xe201c - Core Nap Control Register */ + u8 res5[4]; /* 0xe2020 - Reserved */ + u32 cdozpsrl; /* 0xe2024 - Core Doze Previous Status Register */ + u8 res6[4]; /* 0xe2028 - Reserved */ + u32 cdozpcrl; /* 0xe202c - Core Doze Previous Control Register */ + u8 res7[4]; /* 0xe2030 - Reserved */ + u32 cwaitsrl; /* 0xe2034 - Core Wait Status Register */ + u8 res8[8]; /* Reserved */ + u32 powmgtcsr; /* 0xe2040 - Power Mangement Control & Status Register */ + u8 res9[12]; /* Reserved */ + u32 ippdexpcr0; /* 0xe2050 - IP Powerdown Exception Control Register 0 */ + u8 res10[12]; /* Reserved */ + u8 res11[4]; /* Reserved */ + u32 cpmimrl; /* 0xe2064 - Core Power Management Interrupt Masking Register */ + u8 res12[4]; /* Reserved */ + u32 cpmcimrl; /* 0xe206c - Core Power Management Critical Interrupt Masking Register */ + u8 res13[4]; /* Reserved */ + u32 cpmmcimrl; /* 0xe2074 - Core Power Management Machine Check Interrupt Masking Register */ + u8 res14[4]; /* Reserved */ + u32 cpmnmimrl; /* 0xe207c - Core Power Management NMI Masking Register */ + u8 res15[4]; /* Reserved */ + u32 ctbenrl; /* 0xe2084 - Core Time Base Enable Register */ + u8 res16[4]; /* Reserved */ + u32 ctbclkselrl; /* 0xe208c - Core Time Base Clock Select Register */ + u8 res17[4]; /* Reserved */ + u32 ctbhltcrl; /* 0xe2094 - Core Time Base Halt Control Register */ + u8 res18[0xf68]; +} ccsr_rcpm_t; + +#else typedef struct ccsr_gur { uint porpllsr; /* 0xe0000 - POR PLL ratio status register */ #ifdef CONFIG_MPC8536 @@ -1645,42 +1990,65 @@ typedef struct ccsr_gur { uint tsec34ioovcr; /* 0xe0f2c - eTSEC 3/4 IO override control */ char res15[61648]; /* 0xe0f30 to 0xefffff */ } ccsr_gur_t; +#endif
-#define CONFIG_SYS_MPC85xx_GUTS_OFFSET (0xE0000) +#ifdef CONFIG_FSL_CORENET +#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET (0x0000) +#define CONFIG_SYS_MPC85xx_DDR_OFFSET (0x8000) +#define CONFIG_SYS_MPC85xx_DDR2_OFFSET (0x9000) +#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET (0xE1000) +#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET (0xE2000) +#define CONFIG_SYS_MPC85xx_DMA_OFFSET (0x100000) +#define CONFIG_SYS_MPC85xx_ESPI_OFFSET (0x110000) +#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET (0x114000) +#define CONFIG_SYS_MPC85xx_LBC_OFFSET (0x124000) +#define CONFIG_SYS_MPC85xx_GPIO_OFFSET (0x130000) +#define CONFIG_SYS_MPC85xx_QMAN_OFFSET (0x318000) +#define CONFIG_SYS_MPC85xx_BMAN_OFFSET (0x31a000) +#else +#define CONFIG_SYS_MPC85xx_ECM_OFFSET (0x0000) +#define CONFIG_SYS_MPC85xx_DDR_OFFSET (0x2000) +#define CONFIG_SYS_MPC85xx_LBC_OFFSET (0x5000) +#define CONFIG_SYS_MPC85xx_DDR2_OFFSET (0x6000) +#define CONFIG_SYS_MPC85xx_ESPI_OFFSET (0x7000) +#define CONFIG_SYS_MPC85xx_PCIX_OFFSET (0x8000) +#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET (0x9000) +#define CONFIG_SYS_MPC85xx_GPIO_OFFSET (0xF000) +#define CONFIG_SYS_MPC85xx_SATA1_OFFSET (0x18000) +#define CONFIG_SYS_MPC85xx_SATA2_OFFSET (0x19000) +#define CONFIG_SYS_MPC85xx_L2_OFFSET (0x20000) +#define CONFIG_SYS_MPC85xx_DMA_OFFSET (0x21000) +#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET (0x2e000) +#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET (0xE3100) +#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET (0xE3000) +#define CONFIG_SYS_MPC85xx_CPM_OFFSET (0x80000) +#endif + +#define CONFIG_SYS_MPC85xx_PIC_OFFSET (0x40000) +#define CONFIG_SYS_MPC85xx_GUTS_OFFSET (0xE0000) + +#define CONFIG_SYS_MPC85xx_QMAN_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_QMAN_OFFSET) +#define CONFIG_SYS_MPC85xx_BMAN_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_BMAN_OFFSET) #define CONFIG_SYS_MPC85xx_GUTS_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET) -#define CONFIG_SYS_MPC85xx_ECM_OFFSET (0x0000) +#define CONFIG_SYS_FSL_CORENET_CCM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET) +#define CONFIG_SYS_FSL_CORENET_CLK_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET) +#define CONFIG_SYS_FSL_CORENET_RCPM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET) #define CONFIG_SYS_MPC85xx_ECM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET) -#define CONFIG_SYS_MPC85xx_DDR_OFFSET (0x2000) #define CONFIG_SYS_MPC85xx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET) -#define CONFIG_SYS_MPC85xx_DDR2_OFFSET (0x6000) #define CONFIG_SYS_MPC85xx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET) -#define CONFIG_SYS_MPC85xx_LBC_OFFSET (0x5000) #define CONFIG_SYS_MPC85xx_LBC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET) -#define CONFIG_SYS_MPC85xx_ESPI_OFFSET (0x7000) #define CONFIG_SYS_MPC85xx_ESPI_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET) -#define CONFIG_SYS_MPC85xx_PCIX_OFFSET (0x8000) #define CONFIG_SYS_MPC85xx_PCIX_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET) -#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET (0x9000) #define CONFIG_SYS_MPC85xx_PCIX2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET) -#define CONFIG_SYS_MPC85xx_GPIO_OFFSET (0xF000) -#define CONFIG_SYS_MPC85xx_GPIO_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET) -#define CONFIG_SYS_MPC85xx_SATA1_OFFSET (0x18000) +#define CONFIG_SYS_MPC85xx_GPIO_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET) #define CONFIG_SYS_MPC85xx_SATA1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET) -#define CONFIG_SYS_MPC85xx_SATA2_OFFSET (0x19000) #define CONFIG_SYS_MPC85xx_SATA2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET) -#define CONFIG_SYS_MPC85xx_L2_OFFSET (0x20000) #define CONFIG_SYS_MPC85xx_L2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET) -#define CONFIG_SYS_MPC85xx_DMA_OFFSET (0x21000) #define CONFIG_SYS_MPC85xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET) -#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET (0x2e000) #define CONFIG_SYS_MPC85xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET) -#define CONFIG_SYS_MPC85xx_PIC_OFFSET (0x40000) #define CONFIG_SYS_MPC85xx_PIC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET) -#define CONFIG_SYS_MPC85xx_CPM_OFFSET (0x80000) #define CONFIG_SYS_MPC85xx_CPM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET) -#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET (0xE3000) #define CONFIG_SYS_MPC85xx_SERDES1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) -#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET (0xE3100) #define CONFIG_SYS_MPC85xx_SERDES2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) #define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000 #define CONFIG_SYS_MPC85xx_USB_ADDR \
On CoreNet based platforms the LAW address is split between an high & low register and we no longer shift the address. Also, the target IDs on CoreNet platforms have been completely re-assigned.
Additionally, added a new find_law() API to which LAW an address hits in. This is need for the CoreNet style boot release code since it will need to determine what the target ID should be set to for boot window translation.
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- drivers/misc/fsl_law.c | 99 ++++++++++++++++++++++++++++++++++++++++++++- include/asm-ppc/fsl_law.h | 29 +++++++++++++ 2 files changed, 127 insertions(+), 1 deletions(-)
diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c index aa877c6..fba16ed 100644 --- a/drivers/misc/fsl_law.c +++ b/drivers/misc/fsl_law.c @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2009 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -48,6 +48,24 @@ DECLARE_GLOBAL_DATA_PTR;
void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id) { +#ifdef CONFIG_FSL_CORENET + volatile ccsr_local_t *ccm; + volatile u32 *base, *lawbarh, *lawbarl, *lawar; + + ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR); + + base = &(ccm->lawbarh0); + lawbarh = base + idx * 4; + lawbarl = lawbarh + 1; + lawar = lawbarl + 1; + + gd->used_laws |= (1 << idx); + + out_be32(lawar, 0); + out_be32(lawbarh, ((u64)addr >> 32)); + out_be32(lawbarl, addr & 0xffffffff); + out_be32(lawar, LAWAR_EN | ((u32)id << 20) | (u32)sz); +#else volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08); volatile u32 *lawbar = base + 8 * idx; volatile u32 *lawar = base + 8 * idx + 2; @@ -57,6 +75,7 @@ void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id) out_be32(lawar, 0); out_be32(lawbar, addr >> 12); out_be32(lawar, LAWAR_EN | ((u32)id << 20) | (u32)sz); +#endif
/* Read back so that we sync the writes */ in_be32(lawar); @@ -96,6 +115,23 @@ int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
void disable_law(u8 idx) { +#ifdef CONFIG_FSL_CORENET + volatile ccsr_local_t *ccm; + volatile u32 *base, *lawbarh, *lawbarl, *lawar; + + ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR); + + base = &(ccm->lawbarh0); + lawbarh = base + idx * 4; + lawbarl = lawbarh + 1; + lawar = lawbarl + 1; + + gd->used_laws &= ~(1 << idx); + + out_be32(lawar, 0); + out_be32(lawbarh, 0); + out_be32(lawbarl, 0); +#else volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08); volatile u32 *lawbar = base + 8 * idx; volatile u32 *lawar = base + 8 * idx + 2; @@ -104,10 +140,65 @@ void disable_law(u8 idx)
out_be32(lawar, 0); out_be32(lawbar, 0); +#endif
return; }
+#ifdef CONFIG_FSL_CORENET +#define GET_LAW_ADDR ((u64)in_be32(lawbarh) << 32) | in_be32(lawbarl) +#else +#define GET_LAW_ADDR ((u64)in_be32(lawbar) << 12) +#endif + +struct law_entry find_law(phys_addr_t addr) +{ + struct law_entry entry; + int i; + + entry.index = -1; + entry.addr = 0; + entry.size = 0; + entry.trgt_id = 0; + + for(i = 0; i < FSL_HW_NUM_LAWS; i++) { + + u64 upper; + u32 temp; +#ifdef CONFIG_FSL_CORENET + volatile ccsr_local_t *ccm; + volatile u32 *base, *lawbarh, *lawbarl, *lawar; + + ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR); + + base = &(ccm->lawbarh0); + lawbarh = base + i * 4; + lawbarl = lawbarh + 1; + lawar = lawbarl + 1; +#else + volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08); + volatile u32 *lawbar = base + 8 * i; + volatile u32 *lawar = base + 8 * i + 2; +#endif + temp = in_be32(lawar); + + if (!(temp & LAWAR_EN)) + continue; + + entry.addr = GET_LAW_ADDR; + entry.size = temp & 0x3f; + entry.trgt_id = (temp >> 20) & 0xff; + + upper = entry.addr + (2ull << entry.size); + if ((addr >= entry.addr) && (addr < upper)) { + entry.index = i; + break; + } + } + + return entry; +} + void print_laws(void) { volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08); @@ -173,7 +264,13 @@ void init_laws(void) { int i;
+#if FSL_HW_NUM_LAWS < 32 gd->used_laws = ~((1 << FSL_HW_NUM_LAWS) - 1); +#elif FSL_HW_NUM_LAWS == 32 + gd->used_laws = 0; +#else +#error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes +#endif
for (i = 0; i < num_law_entries; i++) { if (law_table[i].index == -1) diff --git a/include/asm-ppc/fsl_law.h b/include/asm-ppc/fsl_law.h index e06a1a6..d80b30b 100644 --- a/include/asm-ppc/fsl_law.h +++ b/include/asm-ppc/fsl_law.h @@ -1,3 +1,11 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + #ifndef _FSL_LAW_H_ #define _FSL_LAW_H_
@@ -36,6 +44,25 @@ enum law_size { LAW_SIZE_32G, };
+#ifdef CONFIG_FSL_CORENET +enum law_trgt_if { + LAW_TRGT_IF_PCIE_1 = 0x00, + LAW_TRGT_IF_PCIE_2 = 0x01, + LAW_TRGT_IF_PCIE_3 = 0x02, + LAW_TRGT_IF_RIO_1 = 0x08, + LAW_TRGT_IF_RIO_2 = 0x09, + + LAW_TRGT_IF_DDR_1 = 0x10, + LAW_TRGT_IF_DDR_2 = 0x11, /* 2nd controller */ + LAW_TRGT_IF_DDR_INTRLV = 0x14, + + LAW_TRGT_IF_BMAN = 0x18, + LAW_TRGT_IF_DCSR = 0x1d, + LAW_TRGT_IF_LBC = 0x1f, + LAW_TRGT_IF_QMAN = 0x3c, +}; +#define LAW_TRGT_IF_DDR LAW_TRGT_IF_DDR_1 +#else enum law_trgt_if { LAW_TRGT_IF_PCI = 0x00, LAW_TRGT_IF_PCI_2 = 0x01, @@ -64,6 +91,7 @@ enum law_trgt_if { #if defined(CONFIG_MPC8572) || defined(CONFIG_P2020) #define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI #endif +#endif /* CONFIG_FSL_CORENET */
struct law_entry { int index; @@ -76,6 +104,7 @@ extern void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if extern int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id); extern int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id); extern int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id); +extern struct law_entry find_law(phys_addr_t addr); extern void disable_law(u8 idx); extern void init_laws(void); extern void print_laws(void);
On CoreNet based platforms the CCSRBAR address is split between an high & low register and we no longer shift the address.
Signed-off-by: Kumar Gala galak@kernel.crashing.org Signed-off-by: Scott Wood scottwood@freescale.com --- cpu/mpc85xx/cpu_init_early.c | 27 +++++++++++++++++++++++++++ 1 files changed, 27 insertions(+), 0 deletions(-)
diff --git a/cpu/mpc85xx/cpu_init_early.c b/cpu/mpc85xx/cpu_init_early.c index 7886f86..bb31709 100644 --- a/cpu/mpc85xx/cpu_init_early.c +++ b/cpu/mpc85xx/cpu_init_early.c @@ -54,6 +54,9 @@ void cpu_init_early_f(void) u32 temp; volatile u32 *ccsr_virt = (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000); +#ifdef CONFIG_FSL_CORENET + volatile ccsr_local_t *ccm; +#endif
mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(1); /* mas1 is the same as above */ @@ -64,9 +67,33 @@ void cpu_init_early_f(void)
write_tlb(mas0, mas1, mas2, mas3, mas7);
+#ifdef CONFIG_FSL_CORENET + /* + * We can't call set_law() because we haven't moved + * CCSR yet. + */ + ccm = (void *)ccsr_virt; + + out_be32(&ccm->lawbarh0, (u64)CONFIG_SYS_CCSRBAR_PHYS >> 32); + out_be32(&ccm->lawbarl0, (u32)CONFIG_SYS_CCSRBAR_PHYS); + out_be32(&ccm->lawar0, LAWAR_EN | (0x1e << 20) | LAW_SIZE_4K); + + in_be32((u32 *)(ccsr_virt + 0)); + in_be32((u32 *)(ccsr_virt + 1)); + isync(); + + ccm = (void *)CONFIG_SYS_CCSRBAR; + /* Now use the temporary LAW to move CCSR */ + out_be32(&ccm->ccsrbarh, (u64)CONFIG_SYS_CCSRBAR_PHYS >> 32); + out_be32(&ccm->ccsrbarl, (u32)CONFIG_SYS_CCSRBAR_PHYS); + out_be32(&ccm->ccsrar, CCSRAR_C); + temp = in_be32(&ccm->ccsrar); + disable_law(0); +#else temp = in_be32(ccsr_virt); out_be32(ccsr_virt, CONFIG_SYS_CCSRBAR_PHYS >> 12); temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR); +#endif } #endif
The CoreNet platform style of bringing secondary cores out of reset is a bit different that the PQ3 style. Mostly the registers that we use to setup boot translation, enable time bases, and boot release the cores have moved around.
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- cpu/mpc85xx/mp.c | 68 +++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 67 insertions(+), 1 deletions(-)
diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c index fa65bed..b474218 100644 --- a/cpu/mpc85xx/mp.c +++ b/cpu/mpc85xx/mp.c @@ -26,6 +26,7 @@ #include <lmb.h> #include <asm/io.h> #include <asm/mmu.h> +#include <asm/fsl_law.h> #include "mp.h"
DECLARE_GLOBAL_DATA_PTR; @@ -135,6 +136,66 @@ ulong get_spin_addr(void) return addr; }
+#ifdef CONFIG_FSL_CORENET +static void corenet_mp_up(unsigned long bootpg) +{ + u32 up, cpu_up_mask, whoami; + u32 *table = (u32 *)get_spin_addr(); + volatile ccsr_gur_t *gur; + volatile ccsr_local_t *ccm; + volatile ccsr_rcpm_t *rcpm; + volatile ccsr_pic_t *pic; + int timeout = 10; + u32 nr_cpus; + struct law_entry e; + + gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR); + rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); + pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); + + nr_cpus = ((in_be32(&pic->frr) >> 8) & 0xff) + 1; + + whoami = in_be32(&pic->whoami); + cpu_up_mask = 1 << whoami; + out_be32(&ccm->bstrl, bootpg); + + e = find_law(bootpg); + out_be32(&ccm->bstrar, LAWAR_EN | e.trgt_id << 20 | LAWAR_SIZE_4K); + + /* disable time base at the platform */ + out_be32(&rcpm->ctbenrl, cpu_up_mask); + + /* release the hounds */ + up = ((1 << nr_cpus) - 1); + out_be32(&gur->brrl, up); + + /* wait for everyone */ + while (timeout) { + int i; + for (i = 0; i < nr_cpus; i++) { + if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER]) + cpu_up_mask |= (1 << i); + }; + + if ((cpu_up_mask & up) == up) + break; + + udelay(100); + timeout--; + } + + if (timeout == 0) + printf("CPU up timeout. CPU up mask is %x should be %x\n", + cpu_up_mask, up); + + /* enable time base at the platform */ + out_be32(&rcpm->ctbenrl, 0); + mtspr(SPRN_TBWU, 0); + mtspr(SPRN_TBWL, 0); + out_be32(&rcpm->ctbenrl, (1 << nr_cpus) - 1); +} +#else static void pq3_mp_up(unsigned long bootpg) { u32 up, cpu_up_mask, whoami; @@ -196,6 +257,7 @@ static void pq3_mp_up(unsigned long bootpg) devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1); out_be32(&gur->devdisr, devdisr); } +#endif
void cpu_mp_lmb_reserve(struct lmb *lmb) { @@ -217,7 +279,7 @@ void setup_mp(void) if (i != -1) { /* map reset page to bootpg so we can copy code there */ disable_tlb(i); - + set_tlb(1, 0xfffff000, bootpg, /* tlb, epn, rpn */ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, /* perms, wimge */ 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */ @@ -234,7 +296,11 @@ void setup_mp(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, /* perms, wimge */ 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
+#ifdef CONFIG_FSL_CORENET + corenet_mp_up(bootpg); +#else pq3_mp_up(bootpg); +#endif } else { puts("WARNING: No reset page TLB. " "Skipping secondary core setup\n");
There are various locations that we have chip specific info:
* Makefile for which ddr code to build * Added p4080 & p4040 to cpu_type_list and SVR list * Added number of LAWs for p4080 * Set CONFIG_MAX_CPUS to 8 for p4080
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- cpu/mpc85xx/Makefile | 1 + cpu/mpc8xxx/cpu.c | 4 ++++ drivers/misc/fsl_law.c | 2 ++ include/asm-ppc/config.h | 6 ++++-- include/asm-ppc/processor.h | 4 ++++ 5 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile index 3ef00e8..56de7eb 100644 --- a/cpu/mpc85xx/Makefile +++ b/cpu/mpc85xx/Makefile @@ -53,6 +53,7 @@ COBJS-$(CONFIG_P1011) += ddr-gen3.o COBJS-$(CONFIG_P1020) += ddr-gen3.o COBJS-$(CONFIG_P2010) += ddr-gen3.o COBJS-$(CONFIG_P2020) += ddr-gen3.o +COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o
COBJS-$(CONFIG_CPM2) += ether_fcc.o COBJS-$(CONFIG_OF_LIBFDT) += fdt.o diff --git a/cpu/mpc8xxx/cpu.c b/cpu/mpc8xxx/cpu.c index 00791e1..d191263 100644 --- a/cpu/mpc8xxx/cpu.c +++ b/cpu/mpc8xxx/cpu.c @@ -72,6 +72,10 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(P2010, P2010_E, 1), CPU_TYPE_ENTRY(P2020, P2020, 2), CPU_TYPE_ENTRY(P2020, P2020_E, 2), + CPU_TYPE_ENTRY(P4040, P4040, 4), + CPU_TYPE_ENTRY(P4040, P4040_E, 4), + CPU_TYPE_ENTRY(P4080, P4080, 8), + CPU_TYPE_ENTRY(P4080, P4080_E, 8), #elif defined(CONFIG_MPC86xx) CPU_TYPE_ENTRY(8610, 8610, 1), CPU_TYPE_ENTRY(8641, 8641, 2), diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c index fba16ed..626bab2 100644 --- a/drivers/misc/fsl_law.c +++ b/drivers/misc/fsl_law.c @@ -42,6 +42,8 @@ DECLARE_GLOBAL_DATA_PTR; defined(CONFIG_P1011) || defined(CONFIG_P1020) || \ defined(CONFIG_P2010) || defined(CONFIG_P2020) #define FSL_HW_NUM_LAWS 12 +#elif defined(CONFIG_PPC_P4080) +#define FSL_HW_NUM_LAWS 32 #else #error FSL_HW_NUM_LAWS not defined for this platform #endif diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h index 5670d06..e35b0b7 100644 --- a/include/asm-ppc/config.h +++ b/include/asm-ppc/config.h @@ -40,9 +40,11 @@
#if defined(CONFIG_MPC8572) || defined(CONFIG_P1020) || \ defined(CONFIG_P2020) || defined(CONFIG_MPC8641) -#define CONFIG_MAX_CPUS 2 +#define CONFIG_MAX_CPUS 2 +#elif defined(CONFIG_PPC_P4080) +#define CONFIG_MAX_CPUS 8 #else -#define CONFIG_MAX_CPUS 1 +#define CONFIG_MAX_CPUS 1 #endif
#endif /* _ASM_CONFIG_H_ */ diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 3764a5a..d009957 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -1031,6 +1031,10 @@ #define SVR_P2010_E 0x80EB00 #define SVR_P2020 0x80E200 #define SVR_P2020_E 0x80EA00 +#define SVR_P4040 0x820100 +#define SVR_P4040_E 0x820900 +#define SVR_P4080 0x820000 +#define SVR_P4080_E 0x820800
#define SVR_8610 0x80A000 #define SVR_8641 0x809000
On CoreNet style platforms the timebase frequency is the bus frequency defined by 16 (on PQ3 it is divide by 8). Also on the CoreNet platforms the core not longer controls the enabling of the timebase. We now need to enable the boot core's timebase via CCSR register writes.
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- cpu/mpc85xx/cpu.c | 4 ++++ cpu/mpc85xx/cpu_init.c | 12 ++++++++++++ cpu/mpc85xx/fdt.c | 7 ++++++- 3 files changed, 22 insertions(+), 1 deletions(-)
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index bdd9ee4..25c0416 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -184,7 +184,11 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) */ unsigned long get_tbclk (void) { +#ifdef CONFIG_FSL_CORENET + return (gd->bus_clk + 8) / 16; +#else return (gd->bus_clk + 4UL)/8UL; +#endif }
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index a6d1e99..428b461 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -229,6 +229,18 @@ void cpu_init_f (void) #if defined(CONFIG_FSL_DMA) dma_init(); #endif +#ifdef CONFIG_FSL_CORENET + { + volatile ccsr_rcpm_t *rcpm = + (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); + volatile ccsr_pic_t *pic = + (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); + u32 whoami = in_be32(&pic->whoami); + + /* Enable the timebase register for this core */ + out_be32(&rcpm->ctbenrl, (1 << whoami)); + } +#endif }
diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index 723f473..ff5824b 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -1,5 +1,5 @@ /* - * Copyright 2007 Freescale Semiconductor, Inc. + * Copyright 2007-2009 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -286,8 +286,13 @@ void ft_cpu_setup(void *blob, bd_t *bd)
fdt_add_enet_stashing(blob);
+#ifdef CONFIG_FSL_CORENET + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, + "timebase-frequency", bd->bi_busfreq / 16, 1); +#else do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "timebase-frequency", bd->bi_busfreq / 8, 1); +#endif do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "bus-frequency", bd->bi_busfreq, 1); get_sys_info(&sysinfo);
The means to determine the core, bus, and DDR frequencies are completely new on CoreNet style platforms. Additionally on p4080 we can have different frequencies for FMAN and PME IP blocks. We need to keep track of the FMAN & PME frequencies since they are used for time stamping capabilities inside each block.
Signed-off-by: Kumar Gala galak@kernel.crashing.org --- cpu/mpc85xx/cpu.c | 29 +++++++++++++++++ cpu/mpc85xx/speed.c | 85 +++++++++++++++++++++++++++++++++++++++++++++++++++ include/e500.h | 6 +++ 3 files changed, 120 insertions(+), 0 deletions(-)
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 25c0416..1c0f2b2 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -46,11 +46,20 @@ int checkcpu (void) char buf1[32], buf2[32]; #ifdef CONFIG_DDR_CLK_FREQ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#ifdef CONFIG_FSL_CORENET + u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) + >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; +#else u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; +#endif +#else +#ifdef CONFIG_FSL_CORENET + u32 ddr_sync = 0; #else u32 ddr_ratio = 0; #endif +#endif int i;
svr = get_svr(); @@ -111,6 +120,16 @@ int checkcpu (void) } printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
+#ifdef CONFIG_FSL_CORENET + if (ddr_sync == 1) + printf(" DDR:%-4s MHz (%s MT/s data rate) (Synchronous), ", + strmhz(buf1, sysinfo.freqDDRBus/2), + strmhz(buf2, sysinfo.freqDDRBus)); + else + printf(" DDR:%-4s MHz (%s MT/s data rate) (Asynchronous), ", + strmhz(buf1, sysinfo.freqDDRBus/2), + strmhz(buf2, sysinfo.freqDDRBus)); +#else switch (ddr_ratio) { case 0x0: printf(" DDR:%-4s MHz (%s MT/s data rate), ", @@ -128,6 +147,7 @@ int checkcpu (void) strmhz(buf2, sysinfo.freqDDRBus)); break; } +#endif
if (sysinfo.freqLocalBus > LCRR_CLKDIV) printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); @@ -143,6 +163,15 @@ int checkcpu (void) printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); #endif
+#ifdef CONFIG_SYS_DPAA_FMAN + for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) + printf(" FMAN%d: %s MHz\n", i, strmhz(buf1, sysinfo.freqFMan[i])); +#endif + +#ifdef CONFIG_SYS_DPAA_PME + printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME)); +#endif + puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
return 0; diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 2fdcefb..dc18798 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -1,5 +1,6 @@ /* * Copyright 2004, 2007-2009 Freescale Semiconductor, Inc. + * * (C) Copyright 2003 Motorola Inc. * Xianghua Xiao, (X.Xiao@motorola.com) * @@ -37,6 +38,89 @@ DECLARE_GLOBAL_DATA_PTR; void get_sys_info (sys_info_t * sysInfo) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#ifdef CONFIG_FSL_CORENET + volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR); + + const u8 core_cplx_PLL[16] = { + [ 0] = 0, /* CC1 PPL / 1 */ + [ 1] = 0, /* CC1 PPL / 2 */ + [ 2] = 0, /* CC1 PPL / 4 */ + [ 4] = 1, /* CC2 PPL / 1 */ + [ 5] = 1, /* CC2 PPL / 2 */ + [ 6] = 1, /* CC2 PPL / 4 */ + [ 8] = 2, /* CC3 PPL / 1 */ + [ 9] = 2, /* CC3 PPL / 2 */ + [10] = 2, /* CC3 PPL / 4 */ + [12] = 3, /* CC4 PPL / 1 */ + [13] = 3, /* CC4 PPL / 2 */ + [14] = 3, /* CC4 PPL / 4 */ + }; + + const u8 core_cplx_PLL_div[16] = { + [ 0] = 1, /* CC1 PPL / 1 */ + [ 1] = 2, /* CC1 PPL / 2 */ + [ 2] = 4, /* CC1 PPL / 4 */ + [ 4] = 1, /* CC2 PPL / 1 */ + [ 5] = 2, /* CC2 PPL / 2 */ + [ 6] = 4, /* CC2 PPL / 4 */ + [ 8] = 1, /* CC3 PPL / 1 */ + [ 9] = 2, /* CC3 PPL / 2 */ + [10] = 4, /* CC3 PPL / 4 */ + [12] = 1, /* CC4 PPL / 1 */ + [13] = 2, /* CC4 PPL / 2 */ + [14] = 4, /* CC4 PPL / 4 */ + }; + uint lcrr_div, i, freqCC_PLL[4], rcw_tmp; + unsigned long sysclk = CONFIG_SYS_CLK_FREQ; + + sysInfo->freqSystemBus = sysclk; + sysInfo->freqDDRBus = sysclk; + freqCC_PLL[0] = sysclk; + freqCC_PLL[1] = sysclk; + freqCC_PLL[2] = sysclk; + freqCC_PLL[3] = sysclk; + + sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0xf; + sysInfo->freqDDRBus *= ((in_be32(&gur->rcwsr[0]) >> 17) & 0xf); + freqCC_PLL[0] *= (in_be32(&clk->pllc1gsr) >> 1) & 0x3f; + freqCC_PLL[1] *= (in_be32(&clk->pllc2gsr) >> 1) & 0x3f; + freqCC_PLL[2] *= (in_be32(&clk->pllc3gsr) >> 1) & 0x3f; + freqCC_PLL[3] *= (in_be32(&clk->pllc4gsr) >> 1) & 0x3f; + + rcw_tmp = in_be32(&gur->rcwsr[3]); + for (i = 0; i < cpu_numcores(); i++) { + u32 c_pll_sel = (in_be32(&clk->clkc0csr + i*8) >> 27) & 0xf; + u32 cplx_pll = core_cplx_PLL[c_pll_sel]; + + sysInfo->freqProcessor[i] = freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel]; + } + +#define PME_CLK_SEL 0x80000000 +#define FM1_CLK_SEL 0x40000000 +#define FM2_CLK_SEL 0x20000000 + rcw_tmp = in_be32(&gur->rcwsr[7]); + +#ifdef CONFIG_SYS_DPAA_PME + if (rcw_tmp & PME_CLK_SEL) + sysInfo->freqPME = freqCC_PLL[2] / 2; + else + sysInfo->freqPME = sysInfo->freqSystemBus / 2; +#endif + +#ifdef CONFIG_SYS_DPAA_FMAN + if (rcw_tmp & FM1_CLK_SEL) + sysInfo->freqFMan[0] = freqCC_PLL[2] / 2; + else + sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2; +#if (CONFIG_SYS_NUM_FMAN) == 2 + if (rcw_tmp & FM2_CLK_SEL) + sysInfo->freqFMan[1] = freqCC_PLL[2] / 2; + else + sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2; +#endif +#endif + +#else uint plat_ratio,e500_ratio,half_freqSystemBus; uint lcrr_div; int i; @@ -67,6 +151,7 @@ void get_sys_info (sys_info_t * sysInfo) sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ; } #endif +#endif
#ifdef CONFIG_QE qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) diff --git a/include/e500.h b/include/e500.h index f8c8266..e1708b9 100644 --- a/include/e500.h +++ b/include/e500.h @@ -15,6 +15,12 @@ typedef struct unsigned long freqDDRBus; unsigned long freqLocalBus; unsigned long freqQE; +#ifdef CONFIG_SYS_DPAA_FMAN + unsigned long freqFMan[CONFIG_SYS_NUM_FMAN]; +#endif +#ifdef CONFIG_SYS_DPAA_PME + unsigned long freqPME; +#endif } MPC85xx_SYS_INFO;
#endif /* _ASMLANGUAGE */
Kumar Gala wrote:
On CoreNet style platforms the timebase frequency is the bus frequency defined by 16 (on PQ3 it is divide by 8). Also on the CoreNet platforms the core not longer controls the enabling of the timebase. We now need to enable the boot core's timebase via CCSR register writes.
Signed-off-by: Kumar Gala galak@kernel.crashing.org
cpu/mpc85xx/cpu.c | 4 ++++ cpu/mpc85xx/cpu_init.c | 12 ++++++++++++ cpu/mpc85xx/fdt.c | 7 ++++++- 3 files changed, 22 insertions(+), 1 deletions(-)
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index bdd9ee4..25c0416 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -184,7 +184,11 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) */ unsigned long get_tbclk (void) { +#ifdef CONFIG_FSL_CORENET
- return (gd->bus_clk + 8) / 16;
+#else return (gd->bus_clk + 4UL)/8UL; +#endif }
[snip]
+#ifdef CONFIG_FSL_CORENET
- do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"timebase-frequency", bd->bi_busfreq / 16, 1);+#else do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "timebase-frequency", bd->bi_busfreq / 8, 1); +#endif
We could just use get_tbclk() here and not have to maintain the knowledge in two places.
-Scott
Dear Kumar Gala,
In message 1253307595-28655-7-git-send-email-galak@kernel.crashing.org you wrote:
On CoreNet style platforms the timebase frequency is the bus frequency defined by 16 (on PQ3 it is divide by 8). Also on the CoreNet platforms the core not longer controls the enabling of the timebase. We now need to enable the boot core's timebase via CCSR register writes.
Signed-off-by: Kumar Gala galak@kernel.crashing.org
cpu/mpc85xx/cpu.c | 4 ++++ cpu/mpc85xx/cpu_init.c | 12 ++++++++++++ cpu/mpc85xx/fdt.c | 7 ++++++- 3 files changed, 22 insertions(+), 1 deletions(-)
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index bdd9ee4..25c0416 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -184,7 +184,11 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) */ unsigned long get_tbclk (void) { +#ifdef CONFIG_FSL_CORENET
- return (gd->bus_clk + 8) / 16;
+#else return (gd->bus_clk + 4UL)/8UL; +#endif }
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index a6d1e99..428b461 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -229,6 +229,18 @@ void cpu_init_f (void) #if defined(CONFIG_FSL_DMA) dma_init(); #endif +#ifdef CONFIG_FSL_CORENET
- {
volatile ccsr_rcpm_t *rcpm =(void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);volatile ccsr_pic_t *pic =(void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);u32 whoami = in_be32(&pic->whoami);/* Enable the timebase register for this core */out_be32(&rcpm->ctbenrl, (1 << whoami));- }
+#endif }
Please do not declare variables right in the middle of the code. Consider moving this into a separate function if needed.
Best regards,
Wolfgang Denk
Dear Kumar Gala,
In message 1253307595-28655-5-git-send-email-galak@kernel.crashing.org you wrote:
The CoreNet platform style of bringing secondary cores out of reset is a bit different that the PQ3 style. Mostly the registers that we use to setup boot translation, enable time bases, and boot release the cores have moved around.
Signed-off-by: Kumar Gala galak@kernel.crashing.org
cpu/mpc85xx/mp.c | 68 +++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 67 insertions(+), 1 deletions(-)
diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c index fa65bed..b474218 100644 --- a/cpu/mpc85xx/mp.c +++ b/cpu/mpc85xx/mp.c @@ -26,6 +26,7 @@ #include <lmb.h> #include <asm/io.h> #include <asm/mmu.h> +#include <asm/fsl_law.h> #include "mp.h"
DECLARE_GLOBAL_DATA_PTR; @@ -135,6 +136,66 @@ ulong get_spin_addr(void) return addr; }
+#ifdef CONFIG_FSL_CORENET +static void corenet_mp_up(unsigned long bootpg) +{
- u32 up, cpu_up_mask, whoami;
- u32 *table = (u32 *)get_spin_addr();
- volatile ccsr_gur_t *gur;
- volatile ccsr_local_t *ccm;
- volatile ccsr_rcpm_t *rcpm;
- volatile ccsr_pic_t *pic;
- int timeout = 10;
- u32 nr_cpus;
- struct law_entry e;
- gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
- rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
- pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
- nr_cpus = ((in_be32(&pic->frr) >> 8) & 0xff) + 1;
- whoami = in_be32(&pic->whoami);
- cpu_up_mask = 1 << whoami;
- out_be32(&ccm->bstrl, bootpg);
- e = find_law(bootpg);
- out_be32(&ccm->bstrar, LAWAR_EN | e.trgt_id << 20 | LAWAR_SIZE_4K);
- /* disable time base at the platform */
- out_be32(&rcpm->ctbenrl, cpu_up_mask);
- /* release the hounds */
- up = ((1 << nr_cpus) - 1);
- out_be32(&gur->brrl, up);
- /* wait for everyone */
- while (timeout) {
int i;for (i = 0; i < nr_cpus; i++) {if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])cpu_up_mask |= (1 << i);};if ((cpu_up_mask & up) == up)break;udelay(100);timeout--;- }
- if (timeout == 0)
printf("CPU up timeout. CPU up mask is %x should be %x\n",cpu_up_mask, up);- /* enable time base at the platform */
- out_be32(&rcpm->ctbenrl, 0);
- mtspr(SPRN_TBWU, 0);
- mtspr(SPRN_TBWL, 0);
- out_be32(&rcpm->ctbenrl, (1 << nr_cpus) - 1);
+} +#else static void pq3_mp_up(unsigned long bootpg) { u32 up, cpu_up_mask, whoami; @@ -196,6 +257,7 @@ static void pq3_mp_up(unsigned long bootpg) devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1); out_be32(&gur->devdisr, devdisr); } +#endif
This is becoming a terrible mess of #ifdef's. Would it not make sense to move the new code into separate files?
Best regards,
Wolfgang Denk
On Sep 22, 2009, at 3:07 PM, Wolfgang Denk wrote:
Dear Kumar Gala,
In message <1253307595-28655-5-git-send-email-galak@kernel.crashing.org
you wrote: The CoreNet platform style of bringing secondary cores out of reset is a bit different that the PQ3 style. Mostly the registers that we use to setup boot translation, enable time bases, and boot release the cores have moved around.
Signed-off-by: Kumar Gala galak@kernel.crashing.org
cpu/mpc85xx/mp.c | 68 ++++++++++++++++++++++++++++++++++++++++++++ +++++++++- 1 files changed, 67 insertions(+), 1 deletions(-)
diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c index fa65bed..b474218 100644 --- a/cpu/mpc85xx/mp.c +++ b/cpu/mpc85xx/mp.c @@ -26,6 +26,7 @@ #include <lmb.h> #include <asm/io.h> #include <asm/mmu.h> +#include <asm/fsl_law.h> #include "mp.h"
DECLARE_GLOBAL_DATA_PTR; @@ -135,6 +136,66 @@ ulong get_spin_addr(void) return addr; }
+#ifdef CONFIG_FSL_CORENET +static void corenet_mp_up(unsigned long bootpg) +{
- u32 up, cpu_up_mask, whoami;
- u32 *table = (u32 *)get_spin_addr();
- volatile ccsr_gur_t *gur;
- volatile ccsr_local_t *ccm;
- volatile ccsr_rcpm_t *rcpm;
- volatile ccsr_pic_t *pic;
- int timeout = 10;
- u32 nr_cpus;
- struct law_entry e;
- gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
- rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
- pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
- nr_cpus = ((in_be32(&pic->frr) >> 8) & 0xff) + 1;
- whoami = in_be32(&pic->whoami);
- cpu_up_mask = 1 << whoami;
- out_be32(&ccm->bstrl, bootpg);
- e = find_law(bootpg);
- out_be32(&ccm->bstrar, LAWAR_EN | e.trgt_id << 20 | LAWAR_SIZE_4K);
- /* disable time base at the platform */
- out_be32(&rcpm->ctbenrl, cpu_up_mask);
- /* release the hounds */
- up = ((1 << nr_cpus) - 1);
- out_be32(&gur->brrl, up);
- /* wait for everyone */
- while (timeout) {
int i;for (i = 0; i < nr_cpus; i++) {if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])cpu_up_mask |= (1 << i);};if ((cpu_up_mask & up) == up)break;udelay(100);timeout--;- }
- if (timeout == 0)
printf("CPU up timeout. CPU up mask is %x should be %x\n",cpu_up_mask, up);- /* enable time base at the platform */
- out_be32(&rcpm->ctbenrl, 0);
- mtspr(SPRN_TBWU, 0);
- mtspr(SPRN_TBWL, 0);
- out_be32(&rcpm->ctbenrl, (1 << nr_cpus) - 1);
+} +#else static void pq3_mp_up(unsigned long bootpg) { u32 up, cpu_up_mask, whoami; @@ -196,6 +257,7 @@ static void pq3_mp_up(unsigned long bootpg) devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1); out_be32(&gur->devdisr, devdisr); } +#endif
This is becoming a terrible mess of #ifdef's. Would it not make sense to move the new code into separate files?
Is this a general comment or specific to this patch?
In general I would say no. In this specific case we only have two #ifdef's. I can remove the one at the call site by naming the functions the same thing if desired.
- k
- k
Kumar Gala wrote:
void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id) { +#ifdef CONFIG_FSL_CORENET
- volatile ccsr_local_t *ccm;
- volatile u32 *base, *lawbarh, *lawbarl, *lawar;
We don't really need the volatile...
void disable_law(u8 idx) { +#ifdef CONFIG_FSL_CORENET
- volatile ccsr_local_t *ccm;
- volatile u32 *base, *lawbarh, *lawbarl, *lawar;
- ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
- base = &(ccm->lawbarh0);
Use in_be32(). Likewise in find_law.
+struct law_entry find_law(phys_addr_t addr) +{
- struct law_entry entry;
- int i;
- entry.index = -1;
- entry.addr = 0;
- entry.size = 0;
- entry.trgt_id = 0;
- for(i = 0; i < FSL_HW_NUM_LAWS; i++) {
u64 upper;u32 temp;+#ifdef CONFIG_FSL_CORENET
volatile ccsr_local_t *ccm;volatile u32 *base, *lawbarh, *lawbarl, *lawar;ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);base = &(ccm->lawbarh0);lawbarh = base + i * 4;lawbarl = lawbarh + 1;lawar = lawbarl + 1;
So the consequence of not using an array in the reg struct, is that we don't use the reg struct. :-(
-Scott
Scott Wood wrote:
Scott Wood wrote:
- base = &(ccm->lawbarh0);
Use in_be32(). Likewise in find_law.
Grr, ignore me. I just had my brain baked by an ISO9000 presentation.
You should always just go home after those things. Let someone else drive, though :)
Ben
On Sep 18, 2009, at 4:55 PM, Scott Wood wrote:
+#ifdef CONFIG_FSL_CORENET
volatile ccsr_local_t *ccm;volatile u32 *base, *lawbarh, *lawbarl, *lawar;ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);base = &(ccm->lawbarh0);lawbarh = base + i * 4;lawbarl = lawbarh + 1;lawar = lawbarl + 1;So the consequence of not using an array in the reg struct, is that we don't use the reg struct. :-(
Maybe I'll get motivated and rework the code to have this as an array. (The thought did cross my mind about how it would have been nicer if there was an array. :)
I think the reason we didn't have an array on PQ3 was the # kept growing. However I'm pretty sure 32 will be the max # for a while on CoreNet platforms.
- k
Dear Kumar Gala,
In message 1253307595-28655-3-git-send-email-galak@kernel.crashing.org you wrote:
On CoreNet based platforms the LAW address is split between an high & low register and we no longer shift the address. Also, the target IDs on CoreNet platforms have been completely re-assigned.
Additionally, added a new find_law() API to which LAW an address hits in. This is need for the CoreNet style boot release code since it will need to determine what the target ID should be set to for boot window translation.
Signed-off-by: Kumar Gala galak@kernel.crashing.org
drivers/misc/fsl_law.c | 99 ++++++++++++++++++++++++++++++++++++++++++++- include/asm-ppc/fsl_law.h | 29 +++++++++++++ 2 files changed, 127 insertions(+), 1 deletions(-)
diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c index aa877c6..fba16ed 100644 --- a/drivers/misc/fsl_law.c +++ b/drivers/misc/fsl_law.c @@ -1,5 +1,5 @@ /*
- Copyright 2008 Freescale Semiconductor, Inc.
- Copyright 2008-2009 Freescale Semiconductor, Inc.
- (C) Copyright 2000
- Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -48,6 +48,24 @@ DECLARE_GLOBAL_DATA_PTR;
void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id) { +#ifdef CONFIG_FSL_CORENET
- volatile ccsr_local_t *ccm;
- volatile u32 *base, *lawbarh, *lawbarl, *lawar;
- ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
- base = &(ccm->lawbarh0);
- lawbarh = base + idx * 4;
- lawbarl = lawbarh + 1;
- lawar = lawbarl + 1;
- gd->used_laws |= (1 << idx);
- out_be32(lawar, 0);
- out_be32(lawbarh, ((u64)addr >> 32));
- out_be32(lawbarl, addr & 0xffffffff);
- out_be32(lawar, LAWAR_EN | ((u32)id << 20) | (u32)sz);
+#else volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08); volatile u32 *lawbar = base + 8 * idx; volatile u32 *lawar = base + 8 * idx + 2;
This is ugly. Now we have code and variable declarations intermixed. Please don't. Especially not when it's the same variables.
Best regards,
Wolfgang Denk
On Sep 22, 2009, at 3:05 PM, Wolfgang Denk wrote:
Dear Kumar Gala,
In message <1253307595-28655-3-git-send-email-galak@kernel.crashing.org
you wrote: On CoreNet based platforms the LAW address is split between an high & low register and we no longer shift the address. Also, the target IDs on CoreNet platforms have been completely re-assigned.
Additionally, added a new find_law() API to which LAW an address hits in. This is need for the CoreNet style boot release code since it will need to determine what the target ID should be set to for boot window translation.
Signed-off-by: Kumar Gala galak@kernel.crashing.org
drivers/misc/fsl_law.c | 99 +++++++++++++++++++++++++++++++++++ +++++++++- include/asm-ppc/fsl_law.h | 29 +++++++++++++ 2 files changed, 127 insertions(+), 1 deletions(-)
diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c index aa877c6..fba16ed 100644 --- a/drivers/misc/fsl_law.c +++ b/drivers/misc/fsl_law.c @@ -1,5 +1,5 @@ /*
- Copyright 2008 Freescale Semiconductor, Inc.
- Copyright 2008-2009 Freescale Semiconductor, Inc.
- (C) Copyright 2000
- Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -48,6 +48,24 @@ DECLARE_GLOBAL_DATA_PTR;
void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id) { +#ifdef CONFIG_FSL_CORENET
- volatile ccsr_local_t *ccm;
- volatile u32 *base, *lawbarh, *lawbarl, *lawar;
- ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
- base = &(ccm->lawbarh0);
- lawbarh = base + idx * 4;
- lawbarl = lawbarh + 1;
- lawar = lawbarl + 1;
- gd->used_laws |= (1 << idx);
- out_be32(lawar, 0);
- out_be32(lawbarh, ((u64)addr >> 32));
- out_be32(lawbarl, addr & 0xffffffff);
- out_be32(lawar, LAWAR_EN | ((u32)id << 20) | (u32)sz);
+#else volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08); volatile u32 *lawbar = base + 8 * idx; volatile u32 *lawar = base + 8 * idx + 2;
This is ugly. Now we have code and variable declarations intermixed. Please don't. Especially not when it's the same variables.
Will fix this in a subsequent patch.
- k
Kumar Gala wrote:
- u32 lawbarh0; /* 0xc00 - LAW0 base address register high */
- u32 lawbarl0; /* 0xc04 - LAW0 base address register low */
- u32 lawar0; /* 0xc08 - LAW0 attributes register */
- u8 res4[4];
- u32 lawbarh1; /* 0xc10 - LAW1 base address register high */
- u32 lawbarl1; /* 0xc14 - LAW1 base address register low */
- u32 lawar1; /* 0xc18 - LAW1 attributes register */
- u8 res5[4];
- u32 lawbarh2; /* 0xc20 - LAW2 base address register high */
- u32 lawbarl2; /* 0xc24 - LAW2 base address register low */
- u32 lawar2; /* 0xc28 - LAW2 attributes register */
- u8 res6[4];
- u32 lawbarh3; /* 0xc30 - LAW3 base address register high */
- u32 lawbarl3; /* 0xc34 - LAW3 base address register low */
- u32 lawar3; /* 0xc38 - LAW3 attributes register */
- u8 res7[4];
- u32 lawbarh4; /* 0xc40 - LAW4 base address register high */
- u32 lawbarl4; /* 0xc44 - LAW4 base address register low */
- u32 lawar4; /* 0xc48 - LAW4 attributes register */
- u8 res8[4];
- u32 lawbarh5; /* 0xc50 - LAW5 base address register high */
- u32 lawbarl5; /* 0xc54 - LAW5 base address register low */
- u32 lawar5; /* 0xc58 - LAW5 attributes register */
Can we use an array for this? Likewise many other parts.
- char res7[12];
- uint powmgtcsr; /* 0xe0080 - Power management status and control register */
- char res8[12];
- uint coredisru; /* 0xe0090 - uppper portion for support of 64 cores */
- uint coredisrl; /* 0xe0094 - lower portion for support of 64 cores */
- char res9[8];
- uint pvr; /* 0xe00a0 - Processor version register */
- uint svr; /* 0xe00a4 - System version register */
- char res10[8];
- uint rstcr; /* 0xe00b0 - Reset control register */
- uint rstrqpblsr; /* 0xe00b4 - Reset request preboot loader status register */
- char res11[8];
- uint rstrqmr1; /* 0xe00c0 - Reset request mask register */
- char res12[4]; /* Reserved: RSTRQMR2 */
- uint rstrqsr1; /* 0xe00c8 - Reset request status register */
- char res13[4]; /* Reserved: RSTRQSR2 */
- char res14[4]; /* Reserved: RSTRQWDTMRU */
- uint rstrqwdtmrl; /* 0xe00d4 - Reset request WDT mask register */
- char res15[4]; /* Reserved: RSTRQWDTSRU */
- uint rstrqwdtsrl; /* 0xe00dc - Reset request WDT status register */
- char res16[4]; /* Reserved: BRRU max total of 2 for up to 64 cores */
If those fields have a name, why not use the name instead of "res13" etc?
If all these fields are 32 bit, why are the reserved fields char[4] rather than u32? It's very visually distracting.
For that matter, s/uint/u32/.
-#define CONFIG_SYS_MPC85xx_GUTS_OFFSET (0xE0000) +#ifdef CONFIG_FSL_CORENET +#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET (0x0000) +#define CONFIG_SYS_MPC85xx_DDR_OFFSET (0x8000) +#define CONFIG_SYS_MPC85xx_DDR2_OFFSET (0x9000) +#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET (0xE1000) +#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET (0xE2000) +#define CONFIG_SYS_MPC85xx_DMA_OFFSET (0x100000) +#define CONFIG_SYS_MPC85xx_ESPI_OFFSET (0x110000) +#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET (0x114000) +#define CONFIG_SYS_MPC85xx_LBC_OFFSET (0x124000) +#define CONFIG_SYS_MPC85xx_GPIO_OFFSET (0x130000) +#define CONFIG_SYS_MPC85xx_QMAN_OFFSET (0x318000) +#define CONFIG_SYS_MPC85xx_BMAN_OFFSET (0x31a000) +#else +#define CONFIG_SYS_MPC85xx_ECM_OFFSET (0x0000) +#define CONFIG_SYS_MPC85xx_DDR_OFFSET (0x2000) +#define CONFIG_SYS_MPC85xx_LBC_OFFSET (0x5000) +#define CONFIG_SYS_MPC85xx_DDR2_OFFSET (0x6000) +#define CONFIG_SYS_MPC85xx_ESPI_OFFSET (0x7000) +#define CONFIG_SYS_MPC85xx_PCIX_OFFSET (0x8000) +#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET (0x9000) +#define CONFIG_SYS_MPC85xx_GPIO_OFFSET (0xF000) +#define CONFIG_SYS_MPC85xx_SATA1_OFFSET (0x18000) +#define CONFIG_SYS_MPC85xx_SATA2_OFFSET (0x19000) +#define CONFIG_SYS_MPC85xx_L2_OFFSET (0x20000) +#define CONFIG_SYS_MPC85xx_DMA_OFFSET (0x21000) +#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET (0x2e000) +#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET (0xE3100) +#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET (0xE3000) +#define CONFIG_SYS_MPC85xx_CPM_OFFSET (0x80000) +#endif
+#define CONFIG_SYS_MPC85xx_PIC_OFFSET (0x40000) +#define CONFIG_SYS_MPC85xx_GUTS_OFFSET (0xE0000)
Unnecessary parens.
-Scott
On Sep 18, 2009, at 4:20 PM, Scott Wood wrote:
Kumar Gala wrote:
- u32 lawbarh0; /* 0xc00 - LAW0 base address register high */
- u32 lawbarl0; /* 0xc04 - LAW0 base address register low */
- u32 lawar0; /* 0xc08 - LAW0 attributes register */
- u8 res4[4];
- u32 lawbarh1; /* 0xc10 - LAW1 base address register high */
- u32 lawbarl1; /* 0xc14 - LAW1 base address register low */
- u32 lawar1; /* 0xc18 - LAW1 attributes register */
- u8 res5[4];
- u32 lawbarh2; /* 0xc20 - LAW2 base address register high */
- u32 lawbarl2; /* 0xc24 - LAW2 base address register low */
- u32 lawar2; /* 0xc28 - LAW2 attributes register */
- u8 res6[4];
- u32 lawbarh3; /* 0xc30 - LAW3 base address register high */
- u32 lawbarl3; /* 0xc34 - LAW3 base address register low */
- u32 lawar3; /* 0xc38 - LAW3 attributes register */
- u8 res7[4];
- u32 lawbarh4; /* 0xc40 - LAW4 base address register high */
- u32 lawbarl4; /* 0xc44 - LAW4 base address register low */
- u32 lawar4; /* 0xc48 - LAW4 attributes register */
- u8 res8[4];
- u32 lawbarh5; /* 0xc50 - LAW5 base address register high */
- u32 lawbarl5; /* 0xc54 - LAW5 base address register low */
- u32 lawar5; /* 0xc58 - LAW5 attributes register */
Can we use an array for this? Likewise many other parts.
we could, but we didn't do this on PQ3 and I've got some other code that depends on lawbar{h,l}0.
- char res7[12];
- uint powmgtcsr; /* 0xe0080 - Power management status and control
register */
- char res8[12];
- uint coredisru; /* 0xe0090 - uppper portion for support of 64
cores */
- uint coredisrl; /* 0xe0094 - lower portion for support of 64
cores */
- char res9[8];
- uint pvr; /* 0xe00a0 - Processor version register */
- uint svr; /* 0xe00a4 - System version register */
- char res10[8];
- uint rstcr; /* 0xe00b0 - Reset control register */
- uint rstrqpblsr; /* 0xe00b4 - Reset request preboot loader status
register */
- char res11[8];
- uint rstrqmr1; /* 0xe00c0 - Reset request mask register */
- char res12[4]; /* Reserved: RSTRQMR2 */
- uint rstrqsr1; /* 0xe00c8 - Reset request status register */
- char res13[4]; /* Reserved: RSTRQSR2 */
- char res14[4]; /* Reserved: RSTRQWDTMRU */
- uint rstrqwdtmrl; /* 0xe00d4 - Reset request WDT mask register */
- char res15[4]; /* Reserved: RSTRQWDTSRU */
- uint rstrqwdtsrl; /* 0xe00dc - Reset request WDT status register */
- char res16[4]; /* Reserved: BRRU max total of 2 for up to 64
cores */
If those fields have a name, why not use the name instead of "res13" etc?
For right now I'm leaving this alone. These registers are architected but we just dont implement them in p4080. To catch any issues I'll stick with it as is for now.
If all these fields are 32 bit, why are the reserved fields char[4] rather than u32? It's very visually distracting.
I'll change char -> u8. However I'm not making u8[4] -> u32. For historically reasons we used u8 since we autogen'd these in the past. I'm sticking with u8 for reserved fields.
For that matter, s/uint/u32/.
I'll make this change.
-#define CONFIG_SYS_MPC85xx_GUTS_OFFSET (0xE0000) +#ifdef CONFIG_FSL_CORENET +#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET (0x0000) +#define CONFIG_SYS_MPC85xx_DDR_OFFSET (0x8000) +#define CONFIG_SYS_MPC85xx_DDR2_OFFSET (0x9000) +#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET (0xE1000) +#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET (0xE2000) +#define CONFIG_SYS_MPC85xx_DMA_OFFSET (0x100000) +#define CONFIG_SYS_MPC85xx_ESPI_OFFSET (0x110000) +#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET (0x114000) +#define CONFIG_SYS_MPC85xx_LBC_OFFSET (0x124000) +#define CONFIG_SYS_MPC85xx_GPIO_OFFSET (0x130000) +#define CONFIG_SYS_MPC85xx_QMAN_OFFSET (0x318000) +#define CONFIG_SYS_MPC85xx_BMAN_OFFSET (0x31a000) +#else +#define CONFIG_SYS_MPC85xx_ECM_OFFSET (0x0000) +#define CONFIG_SYS_MPC85xx_DDR_OFFSET (0x2000) +#define CONFIG_SYS_MPC85xx_LBC_OFFSET (0x5000) +#define CONFIG_SYS_MPC85xx_DDR2_OFFSET (0x6000) +#define CONFIG_SYS_MPC85xx_ESPI_OFFSET (0x7000) +#define CONFIG_SYS_MPC85xx_PCIX_OFFSET (0x8000) +#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET (0x9000) +#define CONFIG_SYS_MPC85xx_GPIO_OFFSET (0xF000) +#define CONFIG_SYS_MPC85xx_SATA1_OFFSET (0x18000) +#define CONFIG_SYS_MPC85xx_SATA2_OFFSET (0x19000) +#define CONFIG_SYS_MPC85xx_L2_OFFSET (0x20000) +#define CONFIG_SYS_MPC85xx_DMA_OFFSET (0x21000) +#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET (0x2e000) +#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET (0xE3100) +#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET (0xE3000) +#define CONFIG_SYS_MPC85xx_CPM_OFFSET (0x80000) +#endif
+#define CONFIG_SYS_MPC85xx_PIC_OFFSET (0x40000) +#define CONFIG_SYS_MPC85xx_GUTS_OFFSET (0xE0000)
Unnecessary parens.
will fix.
- k
participants (4)
-
Ben Warren -
Kumar Gala -
Scott Wood -
Wolfgang Denk