[U-Boot] [PATCH 1/1] LPC2468 support
This patch includes the LPC2468 processor from NXP. Included is a working board example.
Signed-off-by: Remco Poelstra remco.poelstra+u-boot@duran-audio.com --- http://www.beryllium.net/~remco/u-boot.diff (144kb)
Dear Remco Poelstra,
In message 49C0F362.50803@duran-audio.com you wrote:
This patch includes the LPC2468 processor from NXP. Included is a working board example.
Signed-off-by: Remco Poelstra remco.poelstra+u-boot@duran-audio.com
Please split this into a series of independent parts (each smaller than the size limit of the list)
Best regards,
Wolfgang Denk
This patch includes support for the LPC2468 processor from NXP.
Signed-off-by: Remco Poelstra remco.poelstra+u-boot@duran-audio.com --- diff -upNr u-boot-orig/cpu/arm720t/cpu.c u-boot/cpu/arm720t/cpu.c --- u-boot-orig/cpu/arm720t/cpu.c 2009-03-18 00:42:12.000000000 +0100 +++ u-boot/cpu/arm720t/cpu.c 2009-03-18 09:54:58.000000000 +0100 @@ -78,6 +78,23 @@ int cleanup_before_linux (void) /* Nothing more needed */ #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No cleanup before linux for IntegratorAP/CM720T as yet */ +#elif defined(CONFIG_LPC2468) + disable_interrupts (); + { + volatile unsigned char dummy,i; + + U0IER = 0; + U1IER = 0; + for(i=0; i<16; i++) + { + dummy=U0RBR; + dummy=U0LSR; + dummy=U0IIR; + dummy=U1RBR; + dummy=U1LSR; + dummy=U1IIR; + } + } #else #error No cleanup_before_linux() defined for this CPU type #endif @@ -252,7 +269,7 @@ int dcache_status (void) void icache_enable (void) { } -#elif defined(CONFIG_LPC2292) /* just to satisfy the compiler */ +#elif defined(CONFIG_LPC2292) || defined(CONFIG_LPC2468) /* just to satisfy the compiler */ #else #error No icache/dcache enable/disable functions defined for this CPU type #endif diff -upNr u-boot-orig/cpu/arm720t/interrupts.c u-boot/cpu/arm720t/interrupts.c --- u-boot-orig/cpu/arm720t/interrupts.c 2009-03-18 00:42:12.000000000 +0100 +++ u-boot/cpu/arm720t/interrupts.c 2009-03-18 09:52:30.000000000 +0100 @@ -40,6 +40,11 @@ #ifdef CONFIG_LPC2292 #undef READ_TIMER #define READ_TIMER (0xFFFFFFFF - GET32(T0TC)) +#elif defined(CONFIG_LPC2468) +#undef TIMER_LOAD_VAL +#define TIMER_LOAD_VAL 0 +#undef READ_TIMER +#define READ_TIMER (0xFFFFFFFF - T0TC) #endif
#else @@ -73,7 +78,7 @@ void do_irq (struct pt_regs *pt_regs) } #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No do_irq() for IntegratorAP/CM720T as yet */ -#elif defined(CONFIG_LPC2292) +#elif defined(CONFIG_LPC2292) || defined(CONFIG_LPC2468)
void (*pfnct)(void);
@@ -185,7 +190,13 @@ int interrupt_init (void) PUT32(T0MCR, 0); PUT32(T0TC, 0); PUT32(T0TCR, 1); /* enable timer0 */ - +#elif defined(CONFIG_LPC2468) + T0IR = 0; /*disable all timer0 interupts*/ + T0TCR = 0; /*disable timer0*/ + T0PR = CFG_SYS_CLK_FREQ / CONFIG_SYS_HZ-1; + T0MCR = 0; + T0TC = 0; + T0TCR = 1; #else #error No interrupt_init() defined for this CPU type #endif @@ -201,7 +212,7 @@ int interrupt_init (void) */
-#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO) || defined(CONFIG_LPC2292) +#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO) || defined(CONFIG_LPC2292) || defined(CONFIG_LPC2468)
void reset_timer (void) { @@ -229,7 +240,7 @@ void udelay (unsigned long usec) tmo += get_timer (0);
while (get_timer_masked () < tmo) -#ifdef CONFIG_LPC2292 +#if defined(CONFIG_LPC2292) || defined(CONFIG_LPC2468) /* GJ - not sure whether this is really needed or a misunderstanding */ __asm__ __volatile__(" nop"); #else diff -upNr u-boot-orig/cpu/arm720t/lpc24xx/flash.c u-boot/cpu/arm720t/lpc24xx/flash.c --- u-boot-orig/cpu/arm720t/lpc24xx/flash.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot/cpu/arm720t/lpc24xx/flash.c 2009-03-18 09:31:10.000000000 +0100 @@ -0,0 +1,249 @@ +/* + * (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/hardware.h> + +/* IAP commands use 32 bytes at the top of CPU internal sram, we + use 512 bytes below that */ +#define COPY_BUFFER_LOCATION 0x4000fde0 + +#define IAP_LOCATION 0x7ffffff1 +#define IAP_CMD_PREPARE 50 +#define IAP_CMD_COPY 51 +#define IAP_CMD_ERASE 52 +#define IAP_CMD_CHECK 53 +#define IAP_CMD_ID 54 +#define IAP_CMD_VERSION 55 +#define IAP_CMD_COMPARE 56 + +#define IAP_RET_CMD_SUCCESS 0 + +static unsigned long command[5]; +static unsigned long result[2]; + +extern void iap_entry(unsigned long * command, unsigned long * result); + +/*----------------------------------------------------------------------- + * + */ +int get_flash_sector(flash_info_t * info, ulong flash_addr) +{ + int i; + + for(i=1; i < (info->sector_count); i++) { + if (flash_addr < (info->start[i])) + break; + } + + return (i-1); +} + +/*----------------------------------------------------------------------- + * This function assumes that flash_addr is aligned on 512 bytes boundary + * in flash. This function also assumes that prepare have been called + * for the sector in question. + */ +int lpc24xx_copy_buffer_to_flash(flash_info_t * info, ulong flash_addr) +{ + int first_sector; + int last_sector; + + first_sector = get_flash_sector(info, flash_addr); + last_sector = get_flash_sector(info, flash_addr + 512 - 1); + + /* prepare sectors for write */ + command[0] = IAP_CMD_PREPARE; + command[1] = first_sector; + command[2] = last_sector; + iap_entry(command, result); + if (result[0] != IAP_RET_CMD_SUCCESS) { + printf("IAP prepare failed\n"); + return ERR_PROG_ERROR; + } + + command[0] = IAP_CMD_COPY; + command[1] = flash_addr; + command[2] = COPY_BUFFER_LOCATION; + command[3] = 512; + command[4] = CFG_SYS_CLK_FREQ >> 10; + iap_entry(command, result); + if (result[0] != IAP_RET_CMD_SUCCESS) { + printf("IAP copy failed\n"); + return 1; + } + + return 0; +} + +int lpc24xx_flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag; + int prot; + int sect; + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) + return ERR_PROTECTED; + + + flag = disable_interrupts(); + + printf ("Erasing %d sectors starting at sector %2d.\n" + "This make take some time ... ", + s_last - s_first + 1, s_first); + + command[0] = IAP_CMD_PREPARE; + command[1] = s_first; + command[2] = s_last; + iap_entry(command, result); + if (result[0] != IAP_RET_CMD_SUCCESS) { + printf("IAP prepare failed\n"); + return ERR_PROTECTED; + } + + command[0] = IAP_CMD_ERASE; + command[1] = s_first; + command[2] = s_last; + command[3] = CFG_SYS_CLK_FREQ >> 10; + iap_entry(command, result); + if (result[0] != IAP_RET_CMD_SUCCESS) { + printf("IAP erase failed\n"); + return ERR_PROTECTED; + } + + if (flag) + enable_interrupts(); + + return ERR_OK; +} + +int lpc24xx_write_buff (flash_info_t * info, + uchar * src, + ulong addr, + ulong cnt) +{ + int first_copy_size; + int last_copy_size; + int first_block; + int last_block; + int nbr_mid_blocks; + uchar memmap_value; + ulong i; + uchar* src_org; + uchar* dst_org; + int ret = ERR_OK; + + src_org = src; + dst_org = (uchar*)addr; + + first_block = addr / 512; + last_block = (addr + cnt) / 512; + nbr_mid_blocks = last_block - first_block - 1; + + first_copy_size = 512 - (addr % 512); + last_copy_size = (addr + cnt) % 512; + + debug("\ncopy first block: (1) %lX -> %lX 0x200 bytes, " + "(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX 0x200 bytes\n", + (ulong)(first_block * 512), + (ulong)COPY_BUFFER_LOCATION, + (ulong)src, + (ulong)(COPY_BUFFER_LOCATION + 512 - first_copy_size), + first_copy_size, + (ulong)COPY_BUFFER_LOCATION, + (ulong)(first_block * 512)); + + /* copy first block */ + memcpy((void*)COPY_BUFFER_LOCATION, + (void*)(first_block * 512), + 512); + memcpy((void*)(COPY_BUFFER_LOCATION + 512 - first_copy_size), + src, + first_copy_size); + lpc24xx_copy_buffer_to_flash(info, first_block * 512); + src += first_copy_size; + addr += first_copy_size; + + /* copy middle blocks */ + for (i = 0; i < nbr_mid_blocks; i++) { + debug("copy middle block: %lX -> %lX 512 bytes, " + "%lX -> %lX 512 bytes\n", + (ulong)src, + (ulong)COPY_BUFFER_LOCATION, + (ulong)COPY_BUFFER_LOCATION, + (ulong)addr); + memcpy((void*)COPY_BUFFER_LOCATION, + src, + 512); + lpc24xx_copy_buffer_to_flash(info, addr); + src += 512; + addr += 512; + } + + + if (last_copy_size > 0) { + debug("copy last block: (1) %lX -> %lX 0x200 bytes, " + "(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX x200 bytes\n", + (ulong)(last_block * 512), + (ulong)COPY_BUFFER_LOCATION, + (ulong)src, + (ulong)(COPY_BUFFER_LOCATION), + last_copy_size, + (ulong)COPY_BUFFER_LOCATION, + (ulong)addr); + /* copy last block */ + memcpy((void*)COPY_BUFFER_LOCATION, + (void*)(last_block * 512), + 512); + memcpy((void*)COPY_BUFFER_LOCATION, + src, + last_copy_size); + lpc24xx_copy_buffer_to_flash(info, addr); + } + + /* verify write */ + memmap_value = MEMMAP; + + disable_interrupts(); + + MEMMAP = 01; /* we must make sure that initial 64 + bytes are taken from flash when we + do the compare */ + + for (i = 0; i < cnt; i++) { + if (*dst_org != *src_org){ + printf("Write failed. Byte %lX differs\n", i); + ret = ERR_PROG_ERROR; + break; + } + dst_org++; + src_org++; + } + + MEMMAP = memmap_value; + enable_interrupts(); + + return ret; +} diff -upNr u-boot-orig/cpu/arm720t/lpc24xx/iap_entry.S u-boot/cpu/arm720t/lpc24xx/iap_entry.S --- u-boot-orig/cpu/arm720t/lpc24xx/iap_entry.S 1970-01-01 01:00:00.000000000 +0100 +++ u-boot/cpu/arm720t/lpc24xx/iap_entry.S 2009-03-18 09:31:10.000000000 +0100 @@ -0,0 +1,7 @@ +IAP_ADDRESS: .word 0x7FFFFFF1 + +.globl iap_entry +iap_entry: + ldr r2, IAP_ADDRESS + bx r2 + mov pc, lr diff -upNr u-boot-orig/cpu/arm720t/lpc24xx/Makefile u-boot/cpu/arm720t/lpc24xx/Makefile --- u-boot-orig/cpu/arm720t/lpc24xx/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ u-boot/cpu/arm720t/lpc24xx/Makefile 2009-03-18 10:28:10.000000000 +0100 @@ -0,0 +1,50 @@ +# +# (C) Copyright 2000-2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = flash.o +SOBJS = $(obj)iap_entry.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +# this MUST be compiled as thumb code! +$(SOBJS): + $(CC) $(AFLAGS) -march=armv4t -c -o $(SOBJS) iap_entry.S + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff -upNr u-boot-orig/cpu/arm720t/serial.c u-boot/cpu/arm720t/serial.c --- u-boot-orig/cpu/arm720t/serial.c 2009-03-18 00:42:12.000000000 +0100 +++ u-boot/cpu/arm720t/serial.c 2009-03-18 12:29:00.000000000 +0100 @@ -199,4 +199,91 @@ int serial_tstc (void) return (GET8(U0LSR) & 1); }
+#elif defined(CONFIG_LPC2468) +#include <asm/arch/hardware.h> + +int serial_init (void) +{ + unsigned long pinsel0; + + //enable uart #0 pins in GPIO (P0.2 = TxD0, P0.3 = RxD0) + pinsel0 = PINSEL0; + pinsel0 &= ~(0x000000f0); + pinsel0 |= 0x00000050; + PINSEL0 = pinsel0; + + serial_setbrg (); + + return (0); +} + +void serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + unsigned short divisor = 0; + unsigned long fractional = 0; + + switch (gd->baudrate) { + case 1200: divisor = 3000; fractional = 0xF0; break; + case 9600: divisor = 375; fractional = 0xF0; break; +// case 19200: divisor = 188; fractional = 0; break; + case 19200: divisor = 175; fractional = 0xAF; break; + case 38400: divisor = 94; fractional = 0; break; +// case 38400: divisor = 75; fractional = 0xC3; break; +// case 57600: divisor = 63; fractional = 0; break; + case 57600: divisor = 50; fractional = 0xC3; break; +// case 115200: divisor = 31; fractional = 0; break; + case 115200: divisor = 39; fractional = 0xC3; break; + default: hang (); break; + } + +//#if 0 + /* init serial UART0 */ + U0FCR = 0; /* Disable RX and TX FIFOs */ + U0LCR = 0; + U0IER = 0; + U0LCR = 0x80; /* DLAB=1 */ + U0DLL = (unsigned char)(divisor & 0x00FF); + U0DLM = (unsigned char)(divisor >> 8); + U0LCR = 0x03; /* 8N1, DLAB=0 */ + /* U0FDR = fractional; */ /* Fractional divisor */ + U0FCR = 0x7; /* Enable RX and TX FIFOs */ +// U0FCR = 1; /* Enable RX and TX FIFOs */ +//#endif + +} + +void serial_putc (const char c) +{ + if (c == '\n') + { + while((U0LSR & (1<<5)) == 0); /* Wait for empty U0THR */ + U0THR = '\r'; + } + + while((U0LSR & (1<<5)) == 0); /* Wait for empty U0THR */ + U0THR = c; +} + +int serial_getc (void) +{ + while((U0LSR & 1) == 0); + return U0RBR; +} + +void +serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +/* Test if there is a byte to read */ +int serial_tstc (void) +{ + return (U0LSR & 1); +} + #endif diff -upNr u-boot-orig/cpu/arm720t/start.S u-boot/cpu/arm720t/start.S --- u-boot-orig/cpu/arm720t/start.S 2009-03-18 00:42:12.000000000 +0100 +++ u-boot/cpu/arm720t/start.S 2009-03-18 12:18:29.000000000 +0100 @@ -127,7 +127,7 @@ reset: bl cpu_init_crit #endif
-#ifdef CONFIG_LPC2292 +#if defined(CONFIG_LPC2292) || defined(CONFIG_LPC2468) bl lowlevel_init #endif
@@ -368,6 +368,10 @@ lock_loop: ldr r0, VPBDIV_ADR mov r1, #0x01 /* VPB clock is same as process clock */ str r1, [r0] +#elif defined(CONFIG_LPC2468) + ldr r0, =0x40008000 /*0x40000000 is internal SRAM, 0x4000FFFF is end of SRAM*/ + mov sp,r0 + sub sl,sp,#0x2000 #else #error No cpu_init_crit() defined for current CPU type #endif @@ -383,7 +387,8 @@ lock_loop: str r1, [r0] #endif
-#ifndef CONFIG_LPC2292 +//#ifndef CONFIG_LPC2292 +#if !defined(CONFIG_LPC2292) && !defined(CONFIG_LPC2468) mov ip, lr /* * before relocating, we have to setup RAM timing @@ -601,7 +606,7 @@ reset_cpu: * on external peripherals such as watchdog timers, etc. */ #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No specific reset actions for IntegratorAP/CM720T as yet */ -#elif defined(CONFIG_LPC2292) +#elif defined(CONFIG_LPC2292) || defined(CONFIG_LPC2468) .align 5 .globl reset_cpu reset_cpu: diff -upNr u-boot-orig/include/asm-arm/arch-lpc24xx/hardware.h u-boot/include/asm-arm/arch-lpc24xx/hardware.h --- u-boot-orig/include/asm-arm/arch-lpc24xx/hardware.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot/include/asm-arm/arch-lpc24xx/hardware.h 2009-03-18 09:31:46.000000000 +0100 @@ -0,0 +1,33 @@ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +/* + * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) + * Curt Brune curt@cucy.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#if defined(CONFIG_LPC2468) +#include <asm-arm/arch-lpc24xx/lpc24xx_registers.h> +#else +#error No hardware file defined for this configuration +#endif + +#endif /* __ASM_ARCH_HARDWARE_H */ diff -upNr u-boot-orig/include/asm-arm/arch-lpc24xx/lpc24xx_registers.h u-boot/include/asm-arm/arch-lpc24xx/lpc24xx_registers.h --- u-boot-orig/include/asm-arm/arch-lpc24xx/lpc24xx_registers.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot/include/asm-arm/arch-lpc24xx/lpc24xx_registers.h 2009-03-18 15:43:41.000000000 +0100 @@ -0,0 +1,1123 @@ +#ifndef __LPC24XX_REGISTERS_H +#define __LPC24XX_REGISTERS_H + +#include <config.h> + +/* Macros for reading/writing registers */ +//#define PUT8(reg, value) (*(volatile unsigned char*)(reg) = (value)) +//#define PUT16(reg, value) (*(volatile unsigned short*)(reg) = (value)) +//#define PUT32(reg, value) (*(volatile unsigned int*)(reg) = (value)) +//#define GET8(reg) (*(volatile unsigned char*)(reg)) +//#define GET16(reg) (*(volatile unsigned short*)(reg)) +//#define GET32(reg) (*(volatile unsigned int*)(reg)) + + +/* Vectored Interrupt Controller (VIC) */ +#define VIC_BASE_ADDR 0xFFFFF000 +#define VICIRQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x000)) +#define VICFIQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x004)) +#define VICRawIntr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x008)) +#define VICIntSelect (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x00C)) +#define VICIntEnable (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x010)) +#define VICIntEnClr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x014)) +#define VICSoftInt (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x018)) +#define VICSoftIntClr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x01C)) +#define VICProtection (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x020)) +#define VICSWPrioMask (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x024)) + +#define VICVectAddr0 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x100)) +#define VICVectAddr1 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x104)) +#define VICVectAddr2 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x108)) +#define VICVectAddr3 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x10C)) +#define VICVectAddr4 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x110)) +#define VICVectAddr5 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x114)) +#define VICVectAddr6 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x118)) +#define VICVectAddr7 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x11C)) +#define VICVectAddr8 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x120)) +#define VICVectAddr9 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x124)) +#define VICVectAddr10 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x128)) +#define VICVectAddr11 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x12C)) +#define VICVectAddr12 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x130)) +#define VICVectAddr13 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x134)) +#define VICVectAddr14 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x138)) +#define VICVectAddr15 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x13C)) +#define VICVectAddr16 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x140)) +#define VICVectAddr17 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x144)) +#define VICVectAddr18 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x148)) +#define VICVectAddr19 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x14C)) +#define VICVectAddr20 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x150)) +#define VICVectAddr21 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x154)) +#define VICVectAddr22 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x158)) +#define VICVectAddr23 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x15C)) +#define VICVectAddr24 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x160)) +#define VICVectAddr25 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x164)) +#define VICVectAddr26 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x168)) +#define VICVectAddr27 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x16C)) +#define VICVectAddr28 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x170)) +#define VICVectAddr29 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x174)) +#define VICVectAddr30 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x178)) +#define VICVectAddr31 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x17C)) + +/* The name convention below is from previous LPC2000 family MCUs, in LPC230x, +these registers are known as "VICVectPriority(x)". */ +#define VICVectCntl0 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x200)) +#define VICVectCntl1 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x204)) +#define VICVectCntl2 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x208)) +#define VICVectCntl3 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x20C)) +#define VICVectCntl4 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x210)) +#define VICVectCntl5 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x214)) +#define VICVectCntl6 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x218)) +#define VICVectCntl7 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x21C)) +#define VICVectCntl8 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x220)) +#define VICVectCntl9 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x224)) +#define VICVectCntl10 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x228)) +#define VICVectCntl11 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x22C)) +#define VICVectCntl12 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x230)) +#define VICVectCntl13 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x234)) +#define VICVectCntl14 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x238)) +#define VICVectCntl15 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x23C)) +#define VICVectCntl16 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x240)) +#define VICVectCntl17 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x244)) +#define VICVectCntl18 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x248)) +#define VICVectCntl19 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x24C)) +#define VICVectCntl20 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x250)) +#define VICVectCntl21 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x254)) +#define VICVectCntl22 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x258)) +#define VICVectCntl23 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x25C)) +#define VICVectCntl24 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x260)) +#define VICVectCntl25 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x264)) +#define VICVectCntl26 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x268)) +#define VICVectCntl27 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x26C)) +#define VICVectCntl28 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x270)) +#define VICVectCntl29 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x274)) +#define VICVectCntl30 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x278)) +#define VICVectCntl31 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x27C)) + +#define VICVectAddr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0xF00)) + + +/* Pin Connect Block */ +#define PINSEL_BASE_ADDR 0xE002C000 +#define PINSEL0 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x00)) +#define PINSEL1 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x04)) +#define PINSEL2 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x08)) +#define PINSEL3 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x0C)) +#define PINSEL4 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x10)) +#define PINSEL5 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x14)) +#define PINSEL6 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x18)) +#define PINSEL7 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x1C)) +#define PINSEL8 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x20)) +#define PINSEL9 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x24)) +#define PINSEL10 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x28)) + +#define PINMODE0 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x40)) +#define PINMODE1 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x44)) +#define PINMODE2 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x48)) +#define PINMODE3 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x4C)) +#define PINMODE4 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x50)) +#define PINMODE5 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x54)) +#define PINMODE6 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x58)) +#define PINMODE7 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x5C)) +#define PINMODE8 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x60)) +#define PINMODE9 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x64)) + +/* General Purpose Input/Output (GPIO) */ +#define GPIO_BASE_ADDR 0xE0028000 +#define IOPIN0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x00)) +#define IOSET0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x04)) +#define IODIR0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x08)) +#define IOCLR0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x0C)) +#define IOPIN1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x10)) +#define IOSET1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x14)) +#define IODIR1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x18)) +#define IOCLR1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x1C)) + +/* GPIO Interrupt Registers */ +#define IO0_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x90)) +#define IO0_INT_EN_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x94)) +#define IO0_INT_STAT_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x84)) +#define IO0_INT_STAT_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x88)) +#define IO0_INT_CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x8C)) + +#define IO2_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB0)) +#define IO2_INT_EN_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB4)) +#define IO2_INT_STAT_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA4)) +#define IO2_INT_STAT_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA8)) +#define IO2_INT_CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xAC)) + +#define IO_INT_STAT (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x80)) + +#define PARTCFG_BASE_ADDR 0x3FFF8000 +#define PARTCFG (*(volatile unsigned long *)(PARTCFG_BASE_ADDR + 0x00)) + +/* Fast I/O setup */ +#define FIO_BASE_ADDR 0x3FFFC000 +#define FIO0DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x00)) +#define FIO0MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x10)) +#define FIO0PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x14)) +#define FIO0SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x18)) +#define FIO0CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x1C)) + +#define FIO1DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x20)) +#define FIO1MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x30)) +#define FIO1PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x34)) +#define FIO1SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x38)) +#define FIO1CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x3C)) + +#define FIO2DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x40)) +#define FIO2MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x50)) +#define FIO2PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x54)) +#define FIO2SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x58)) +#define FIO2CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x5C)) + +#define FIO3DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x60)) +#define FIO3MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x70)) +#define FIO3PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x74)) +#define FIO3SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x78)) +#define FIO3CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x7C)) + +#define FIO4DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x80)) +#define FIO4MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x90)) +#define FIO4PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x94)) +#define FIO4SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x98)) +#define FIO4CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x9C)) + +/* FIOs can be accessed through WORD, HALF-WORD or BYTE. */ +#define FIO0DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x01)) +#define FIO1DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) +#define FIO2DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x41)) +#define FIO3DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x61)) +#define FIO4DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x81)) + +#define FIO0DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x02)) +#define FIO1DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x22)) +#define FIO2DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x42)) +#define FIO3DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x62)) +#define FIO4DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x82)) + +#define FIO0DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x03)) +#define FIO1DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x23)) +#define FIO2DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x43)) +#define FIO3DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x63)) +#define FIO4DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x83)) + +#define FIO0DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x04)) +#define FIO1DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x24)) +#define FIO2DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x44)) +#define FIO3DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x64)) +#define FIO4DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x84)) + +#define FIO0DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x00)) +#define FIO1DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x20)) +#define FIO2DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x40)) +#define FIO3DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x60)) +#define FIO4DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x80)) + +#define FIO0DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x02)) +#define FIO1DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x22)) +#define FIO2DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x42)) +#define FIO3DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x62)) +#define FIO4DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x82)) + +#define FIO0MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x10)) +#define FIO1MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x30)) +#define FIO2MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x50)) +#define FIO3MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x70)) +#define FIO4MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x90)) + +#define FIO0MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x11)) +#define FIO1MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) +#define FIO2MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x51)) +#define FIO3MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x71)) +#define FIO4MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x91)) + +#define FIO0MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x12)) +#define FIO1MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x32)) +#define FIO2MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x52)) +#define FIO3MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x72)) +#define FIO4MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x92)) + +#define FIO0MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x13)) +#define FIO1MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x33)) +#define FIO2MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x53)) +#define FIO3MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x73)) +#define FIO4MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x93)) + +#define FIO0MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x10)) +#define FIO1MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x30)) +#define FIO2MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x50)) +#define FIO3MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x70)) +#define FIO4MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x90)) + +#define FIO0MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x12)) +#define FIO1MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x32)) +#define FIO2MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x52)) +#define FIO3MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x72)) +#define FIO4MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x92)) + +#define FIO0PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x14)) +#define FIO1PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x34)) +#define FIO2PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x54)) +#define FIO3PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x74)) +#define FIO4PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x94)) + +#define FIO0PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x15)) +#define FIO1PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x25)) +#define FIO2PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x55)) +#define FIO3PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x75)) +#define FIO4PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x95)) + +#define FIO0PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x16)) +#define FIO1PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x36)) +#define FIO2PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x56)) +#define FIO3PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x76)) +#define FIO4PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x96)) + +#define FIO0PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x17)) +#define FIO1PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x37)) +#define FIO2PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x57)) +#define FIO3PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x77)) +#define FIO4PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x97)) + +#define FIO0PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x14)) +#define FIO1PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x34)) +#define FIO2PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x54)) +#define FIO3PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x74)) +#define FIO4PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x94)) + +#define FIO0PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x16)) +#define FIO1PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x36)) +#define FIO2PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x56)) +#define FIO3PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x76)) +#define FIO4PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x96)) + +#define FIO0SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x18)) +#define FIO1SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x38)) +#define FIO2SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x58)) +#define FIO3SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x78)) +#define FIO4SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x98)) + +#define FIO0SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x19)) +#define FIO1SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x29)) +#define FIO2SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x59)) +#define FIO3SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x79)) +#define FIO4SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x99)) + +#define FIO0SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1A)) +#define FIO1SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3A)) +#define FIO2SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5A)) +#define FIO3SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7A)) +#define FIO4SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9A)) + +#define FIO0SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1B)) +#define FIO1SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3B)) +#define FIO2SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5B)) +#define FIO3SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7B)) +#define FIO4SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9B)) + +#define FIO0SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x18)) +#define FIO1SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x38)) +#define FIO2SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x58)) +#define FIO3SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x78)) +#define FIO4SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x98)) + +#define FIO0SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1A)) +#define FIO1SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3A)) +#define FIO2SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5A)) +#define FIO3SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7A)) +#define FIO4SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9A)) + +#define FIO0CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1C)) +#define FIO1CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3C)) +#define FIO2CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5C)) +#define FIO3CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7C)) +#define FIO4CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9C)) + +#define FIO0CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1D)) +#define FIO1CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x2D)) +#define FIO2CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5D)) +#define FIO3CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7D)) +#define FIO4CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9D)) + +#define FIO0CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1E)) +#define FIO1CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3E)) +#define FIO2CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5E)) +#define FIO3CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7E)) +#define FIO4CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9E)) + +#define FIO0CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1F)) +#define FIO1CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3F)) +#define FIO2CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5F)) +#define FIO3CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7F)) +#define FIO4CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9F)) + +#define FIO0CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1C)) +#define FIO1CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3C)) +#define FIO2CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5C)) +#define FIO3CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7C)) +#define FIO4CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9C)) + +#define FIO0CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1E)) +#define FIO1CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3E)) +#define FIO2CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5E)) +#define FIO3CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7E)) +#define FIO4CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9E)) + + +/* System Control Block(SCB) modules include Memory Accelerator Module, +Phase Locked Loop, VPB divider, Power Control, External Interrupt, +Reset, and Code Security/Debugging */ +#define SCB_BASE_ADDR 0xE01FC000 + +/* Memory Accelerator Module (MAM) */ +#define MAMCR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x000)) +#define MAMTIM (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x004)) +#define MEMMAP (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x040)) + +/* Phase Locked Loop (PLL) */ +#define PLLCON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x080)) +#define PLLCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x084)) +#define PLLSTAT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x088)) +#define PLLFEED (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x08C)) + +/* Power Control */ +#define PCON (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C0)) +#define PCONP (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x0C4)) + +/* Clock Divider */ +// #define APBDIV (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x100)) +#define CCLKCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x104)) +#define USBCLKCFG (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x108)) +#define CLKSRCSEL (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x10C)) +#define PCLKSEL0 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A8)) +#define PCLKSEL1 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1AC)) + +/* External Interrupts */ +#define EXTINT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x140)) +#define INTWAKE (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x144)) +#define EXTMODE (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x148)) +#define EXTPOLAR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x14C)) + +/* Reset, reset source identification */ +#define RSIR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x180)) + +/* RSID, code security protection */ +#define CSPR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x184)) + +/* AHB configuration */ +#define AHBCFG1 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x188)) +#define AHBCFG2 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x18C)) + +/* System Controls and Status */ +#define SCS (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A0)) + + +/* External Memory Controller (EMC) */ +#define EMC_BASE_ADDR 0xFFE08000 +#define EMC_CTRL (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x000)) +#define EMC_STAT (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x004)) +#define EMC_CONFIG (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x008)) + +/* Dynamic RAM access registers */ +#define EMC_DYN_CTRL (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x020)) +#define EMC_DYN_RFSH (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x024)) +#define EMC_DYN_RD_CFG (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x028)) +#define EMC_DYN_RP (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x030)) +#define EMC_DYN_RAS (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x034)) +#define EMC_DYN_SREX (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x038)) +#define EMC_DYN_APR (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x03C)) +#define EMC_DYN_DAL (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x040)) +#define EMC_DYN_WR (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x044)) +#define EMC_DYN_RC (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x048)) +#define EMC_DYN_RFC (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x04C)) +#define EMC_DYN_XSR (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x050)) +#define EMC_DYN_RRD (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x054)) +#define EMC_DYN_MRD (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x058)) + +#define EMC_DYN_CFG0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x100)) +#define EMC_DYN_RASCAS0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x104)) +#define EMC_DYN_CFG1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x140)) +#define EMC_DYN_RASCAS1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x144)) +#define EMC_DYN_CFG2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x160)) +#define EMC_DYN_RASCAS2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x164)) +#define EMC_DYN_CFG3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x180)) +#define EMC_DYN_RASCAS3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x184)) + +/* static RAM access registers */ +#define EMC_STA_CFG0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x200)) +#define EMC_STA_WAITWEN0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x204)) +#define EMC_STA_WAITOEN0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x208)) +#define EMC_STA_WAITRD0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x20C)) +#define EMC_STA_WAITPAGE0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x210)) +#define EMC_STA_WAITWR0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x214)) +#define EMC_STA_WAITTURN0 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x218)) + +#define EMC_STA_CFG1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x220)) +#define EMC_STA_WAITWEN1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x224)) +#define EMC_STA_WAITOEN1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x228)) +#define EMC_STA_WAITRD1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x22C)) +#define EMC_STA_WAITPAGE1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x230)) +#define EMC_STA_WAITWR1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x234)) +#define EMC_STA_WAITTURN1 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x238)) + +#define EMC_STA_CFG2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x240)) +#define EMC_STA_WAITWEN2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x244)) +#define EMC_STA_WAITOEN2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x248)) +#define EMC_STA_WAITRD2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x24C)) +#define EMC_STA_WAITPAGE2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x250)) +#define EMC_STA_WAITWR2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x254)) +#define EMC_STA_WAITTURN2 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x258)) + +#define EMC_STA_CFG3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x260)) +#define EMC_STA_WAITWEN3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x264)) +#define EMC_STA_WAITOEN3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x268)) +#define EMC_STA_WAITRD3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x26C)) +#define EMC_STA_WAITPAGE3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x270)) +#define EMC_STA_WAITWR3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x274)) +#define EMC_STA_WAITTURN3 (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x278)) + +#define EMC_STA_EXT_WAIT (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x880)) + + +/* Timer 0 */ +#define TMR0_BASE_ADDR 0xE0004000 +#define T0IR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x00)) +#define T0TCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x04)) +#define T0TC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x08)) +#define T0PR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x0C)) +#define T0PC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x10)) +#define T0MCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x14)) +#define T0MR0 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x18)) +#define T0MR1 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x1C)) +#define T0MR2 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x20)) +#define T0MR3 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x24)) +#define T0CCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x28)) +#define T0CR0 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x2C)) +#define T0CR1 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x30)) +#define T0CR2 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x34)) +#define T0CR3 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x38)) +#define T0EMR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x3C)) +#define T0CTCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x70)) + +/* Timer 1 */ +#define TMR1_BASE_ADDR 0xE0008000 +#define T1IR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x00)) +#define T1TCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x04)) +#define T1TC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x08)) +#define T1PR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x0C)) +#define T1PC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x10)) +#define T1MCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x14)) +#define T1MR0 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x18)) +#define T1MR1 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x1C)) +#define T1MR2 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x20)) +#define T1MR3 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x24)) +#define T1CCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x28)) +#define T1CR0 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x2C)) +#define T1CR1 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x30)) +#define T1CR2 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x34)) +#define T1CR3 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x38)) +#define T1EMR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x3C)) +#define T1CTCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x70)) + +/* Timer 2 */ +#define TMR2_BASE_ADDR 0xE0070000 +#define T2IR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x00)) +#define T2TCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x04)) +#define T2TC (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x08)) +#define T2PR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x0C)) +#define T2PC (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x10)) +#define T2MCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x14)) +#define T2MR0 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x18)) +#define T2MR1 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x1C)) +#define T2MR2 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x20)) +#define T2MR3 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x24)) +#define T2CCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x28)) +#define T2CR0 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x2C)) +#define T2CR1 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x30)) +#define T2CR2 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x34)) +#define T2CR3 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x38)) +#define T2EMR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x3C)) +#define T2CTCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x70)) + +/* Timer 3 */ +#define TMR3_BASE_ADDR 0xE0074000 +#define T3IR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x00)) +#define T3TCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x04)) +#define T3TC (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x08)) +#define T3PR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x0C)) +#define T3PC (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x10)) +#define T3MCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x14)) +#define T3MR0 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x18)) +#define T3MR1 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x1C)) +#define T3MR2 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x20)) +#define T3MR3 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x24)) +#define T3CCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x28)) +#define T3CR0 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x2C)) +#define T3CR1 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x30)) +#define T3CR2 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x34)) +#define T3CR3 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x38)) +#define T3EMR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x3C)) +#define T3CTCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x70)) + + +/* Pulse Width Modulator (PWM) */ +#define PWM0_BASE_ADDR 0xE0014000 +#define PWM0IR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x00)) +#define PWM0TCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x04)) +#define PWM0TC (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x08)) +#define PWM0PR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x0C)) +#define PWM0PC (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x10)) +#define PWM0MCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x14)) +#define PWM0MR0 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x18)) +#define PWM0MR1 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x1C)) +#define PWM0MR2 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x20)) +#define PWM0MR3 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x24)) +#define PWM0CCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x28)) +#define PWM0CR0 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x2C)) +#define PWM0CR1 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x30)) +#define PWM0CR2 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x34)) +#define PWM0CR3 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x38)) +#define PWM0EMR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x3C)) +#define PWM0MR4 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x40)) +#define PWM0MR5 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x44)) +#define PWM0MR6 (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x48)) +#define PWM0PCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x4C)) +#define PWM0LER (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x50)) +#define PWM0CTCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x70)) + +#define PWM1_BASE_ADDR 0xE0018000 +#define PWM1IR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x00)) +#define PWM1TCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x04)) +#define PWM1TC (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x08)) +#define PWM1PR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x0C)) +#define PWM1PC (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x10)) +#define PWM1MCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x14)) +#define PWM1MR0 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x18)) +#define PWM1MR1 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x1C)) +#define PWM1MR2 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x20)) +#define PWM1MR3 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x24)) +#define PWM1CCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x28)) +#define PWM1CR0 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x2C)) +#define PWM1CR1 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x30)) +#define PWM1CR2 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x34)) +#define PWM1CR3 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x38)) +#define PWM1EMR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x3C)) +#define PWM1MR4 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x40)) +#define PWM1MR5 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x44)) +#define PWM1MR6 (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x48)) +#define PWM1PCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x4C)) +#define PWM1LER (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x50)) +#define PWM1CTCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x70)) + + +/* Universal Asynchronous Receiver Transmitter 0 (UART0) */ +#define UART0_BASE_ADDR 0xE000C000 +#define U0RBR (*(volatile unsigned char *)(UART0_BASE_ADDR + 0x00)) +#define U0THR (*(volatile unsigned char *)(UART0_BASE_ADDR + 0x00)) +#define U0DLL (*(volatile unsigned char *)(UART0_BASE_ADDR + 0x00)) +#define U0DLM (*(volatile unsigned char *)(UART0_BASE_ADDR + 0x04)) +#define U0IER (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04)) +#define U0IIR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08)) +#define U0FCR (*(volatile unsigned char *)(UART0_BASE_ADDR + 0x08)) +#define U0LCR (*(volatile unsigned char *)(UART0_BASE_ADDR + 0x0C)) +#define U0LSR (*(volatile unsigned char *)(UART0_BASE_ADDR + 0x14)) +#define U0SCR (*(volatile unsigned char *)(UART0_BASE_ADDR + 0x1C)) +#define U0ACR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x20)) +#define U0FDR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x28)) +#define U0TER (*(volatile unsigned char *)(UART0_BASE_ADDR + 0x30)) + +/* Universal Asynchronous Receiver Transmitter 1 (UART1) */ +#define UART1_BASE_ADDR 0xE0010000 +#define U1RBR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00)) +#define U1THR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00)) +#define U1DLL (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00)) +#define U1DLM (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04)) +#define U1IER (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x04)) +#define U1IIR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08)) +#define U1FCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x08)) +#define U1LCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x0C)) +#define U1MCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x10)) +#define U1LSR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x14)) +#define U1MSR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x18)) +#define U1SCR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x1C)) +#define U1ACR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x20)) +#define U1FDR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x28)) +#define U1TER (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x30)) + +/* Universal Asynchronous Receiver Transmitter 2 (UART2) */ +#define UART2_BASE_ADDR 0xE0078000 +#define U2RBR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00)) +#define U2THR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00)) +#define U2DLL (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00)) +#define U2DLM (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x04)) +#define U2IER (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x04)) +#define U2IIR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x08)) +#define U2FCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x08)) +#define U2LCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x0C)) +#define U2LSR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x14)) +#define U2SCR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x1C)) +#define U2ACR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x20)) +#define U2ICR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x24)) +#define U2FDR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x28)) +#define U2TER (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x30)) + +/* Universal Asynchronous Receiver Transmitter 3 (UART3) */ +#define UART3_BASE_ADDR 0xE007C000 +#define U3RBR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00)) +#define U3THR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00)) +#define U3DLL (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00)) +#define U3DLM (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x04)) +#define U3IER (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x04)) +#define U3IIR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x08)) +#define U3FCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x08)) +#define U3LCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x0C)) +#define U3LSR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x14)) +#define U3SCR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x1C)) +#define U3ACR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x20)) +#define U3ICR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x24)) +#define U3FDR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x28)) +#define U3TER (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x30)) + +/* I2C Interface 0 */ +#define I2C0_BASE_ADDR 0xE001C000 +#define I20CONSET (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x00)) +#define I20STAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x04)) +#define I20DAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x08)) +#define I20ADR (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x0C)) +#define I20SCLH (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x10)) +#define I20SCLL (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x14)) +#define I20CONCLR (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x18)) + +/* I2C Interface 1 */ +#define I2C1_BASE_ADDR 0xE005C000 +#define I21CONSET (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x00)) +#define I21STAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x04)) +#define I21DAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x08)) +#define I21ADR (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x0C)) +#define I21SCLH (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x10)) +#define I21SCLL (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x14)) +#define I21CONCLR (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x18)) + +/* I2C Interface 2 */ +#define I2C2_BASE_ADDR 0xE0080000 +#define I22CONSET (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x00)) +#define I22STAT (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x04)) +#define I22DAT (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x08)) +#define I22ADR (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x0C)) +#define I22SCLH (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x10)) +#define I22SCLL (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x14)) +#define I22CONCLR (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x18)) + +/* SPI0 (Serial Peripheral Interface 0) */ +#define SPI0_BASE_ADDR 0xE0020000 +#define S0SPCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x00)) +#define S0SPSR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x04)) +#define S0SPDR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x08)) +#define S0SPCCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x0C)) +#define S0SPINT (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x1C)) + +/* SSP0 Controller */ +#define SSP0_BASE_ADDR 0xE0068000 +#define SSP0CR0 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x00)) +#define SSP0CR1 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x04)) +#define SSP0DR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x08)) +#define SSP0SR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x0C)) +#define SSP0CPSR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x10)) +#define SSP0IMSC (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x14)) +#define SSP0RIS (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x18)) +#define SSP0MIS (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x1C)) +#define SSP0ICR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x20)) +#define SSP0DMACR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x24)) + +/* SSP1 Controller */ +#define SSP1_BASE_ADDR 0xE0030000 +#define SSP1CR0 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x00)) +#define SSP1CR1 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x04)) +#define SSP1DR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x08)) +#define SSP1SR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x0C)) +#define SSP1CPSR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x10)) +#define SSP1IMSC (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x14)) +#define SSP1RIS (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x18)) +#define SSP1MIS (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x1C)) +#define SSP1ICR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x20)) +#define SSP1DMACR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x24)) + + +/* Real Time Clock */ +#define RTC_BASE_ADDR 0xE0024000 +#define RTC_ILR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x00)) +#define RTC_CTC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x04)) +#define RTC_CCR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x08)) +#define RTC_CIIR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x0C)) +#define RTC_AMR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x10)) +#define RTC_CTIME0 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x14)) +#define RTC_CTIME1 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x18)) +#define RTC_CTIME2 (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x1C)) +#define RTC_SEC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x20)) +#define RTC_MIN (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x24)) +#define RTC_HOUR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x28)) +#define RTC_DOM (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x2C)) +#define RTC_DOW (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x30)) +#define RTC_DOY (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x34)) +#define RTC_MONTH (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x38)) +#define RTC_YEAR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x3C)) +#define RTC_CISS (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x40)) +#define RTC_ALSEC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x60)) +#define RTC_ALMIN (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x64)) +#define RTC_ALHOUR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x68)) +#define RTC_ALDOM (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x6C)) +#define RTC_ALDOW (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x70)) +#define RTC_ALDOY (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x74)) +#define RTC_ALMON (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x78)) +#define RTC_ALYEAR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x7C)) +#define RTC_PREINT (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x80)) +#define RTC_PREFRAC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x84)) + + +/* A/D Converter 0 (AD0) */ +#define AD0_BASE_ADDR 0xE0034000 +#define AD0CR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x00)) +#define AD0GDR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x04)) +#define AD0INTEN (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x0C)) +#define AD0DR0 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x10)) +#define AD0DR1 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x14)) +#define AD0DR2 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x18)) +#define AD0DR3 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x1C)) +#define AD0DR4 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x20)) +#define AD0DR5 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x24)) +#define AD0DR6 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x28)) +#define AD0DR7 (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x2C)) +#define AD0STAT (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x30)) + + +/* D/A Converter */ +#define DAC_BASE_ADDR 0xE006C000 +#define DACR (*(volatile unsigned long *)(DAC_BASE_ADDR + 0x00)) + + +/* Watchdog */ +#define WDG_BASE_ADDR 0xE0000000 +#define WDMOD (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x00)) +#define WDTC (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x04)) +#define WDFEED (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x08)) +#define WDTV (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x0C)) +#define WDCLKSEL (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x10)) + +/* CAN CONTROLLERS AND ACCEPTANCE FILTER */ +#define CAN_ACCEPT_BASE_ADDR 0xE003C000 +#define CAN_AFMR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x00)) +#define CAN_SFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x04)) +#define CAN_SFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x08)) +#define CAN_EFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x0C)) +#define CAN_EFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x10)) +#define CAN_EOT (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x14)) +#define CAN_LUT_ERR_ADR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x18)) +#define CAN_LUT_ERR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x1C)) + +#define CAN_CENTRAL_BASE_ADDR 0xE0040000 +#define CAN_TX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x00)) +#define CAN_RX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x04)) +#define CAN_MSR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x08)) + +#define CAN1_BASE_ADDR 0xE0044000 +#define CAN1MOD (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x00)) +#define CAN1CMR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x04)) +#define CAN1GSR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x08)) +#define CAN1ICR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x0C)) +#define CAN1IER (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x10)) +#define CAN1BTR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x14)) +#define CAN1EWL (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x18)) +#define CAN1SR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x1C)) +#define CAN1RFS (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x20)) +#define CAN1RID (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x24)) +#define CAN1RDA (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x28)) +#define CAN1RDB (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x2C)) + +#define CAN1TFI1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x30)) +#define CAN1TID1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x34)) +#define CAN1TDA1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x38)) +#define CAN1TDB1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x3C)) +#define CAN1TFI2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x40)) +#define CAN1TID2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x44)) +#define CAN1TDA2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x48)) +#define CAN1TDB2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x4C)) +#define CAN1TFI3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x50)) +#define CAN1TID3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x54)) +#define CAN1TDA3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x58)) +#define CAN1TDB3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x5C)) + +#define CAN2_BASE_ADDR 0xE0048000 +#define CAN2MOD (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x00)) +#define CAN2CMR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x04)) +#define CAN2GSR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x08)) +#define CAN2ICR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x0C)) +#define CAN2IER (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x10)) +#define CAN2BTR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x14)) +#define CAN2EWL (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x18)) +#define CAN2SR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x1C)) +#define CAN2RFS (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x20)) +#define CAN2RID (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x24)) +#define CAN2RDA (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x28)) +#define CAN2RDB (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x2C)) + +#define CAN2TFI1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x30)) +#define CAN2TID1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x34)) +#define CAN2TDA1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x38)) +#define CAN2TDB1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x3C)) +#define CAN2TFI2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x40)) +#define CAN2TID2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x44)) +#define CAN2TDA2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x48)) +#define CAN2TDB2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x4C)) +#define CAN2TFI3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x50)) +#define CAN2TID3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x54)) +#define CAN2TDA3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x58)) +#define CAN2TDB3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x5C)) + + +/* MultiMedia Card Interface(MCI) Controller */ +#define MCI_BASE_ADDR 0xE008C000 +#define MCI_POWER (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x00)) +#define MCI_CLOCK (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x04)) +#define MCI_ARGUMENT (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x08)) +#define MCI_COMMAND (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x0C)) +#define MCI_RESP_CMD (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x10)) +#define MCI_RESP0 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x14)) +#define MCI_RESP1 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x18)) +#define MCI_RESP2 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x1C)) +#define MCI_RESP3 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x20)) +#define MCI_DATA_TMR (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x24)) +#define MCI_DATA_LEN (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x28)) +#define MCI_DATA_CTRL (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x2C)) +#define MCI_DATA_CNT (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x30)) +#define MCI_STATUS (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x34)) +#define MCI_CLEAR (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x38)) +#define MCI_MASK0 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x3C)) +#define MCI_MASK1 (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x40)) +#define MCI_FIFO_CNT (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x48)) +#define MCI_FIFO (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x80)) + + +/* I2S Interface Controller (I2S) */ +#define I2S_BASE_ADDR 0xE0088000 +#define I2S_DAO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x00)) +#define I2S_DAI (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x04)) +#define I2S_TX_FIFO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x08)) +#define I2S_RX_FIFO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x0C)) +#define I2S_STATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x10)) +#define I2S_DMA1 (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x14)) +#define I2S_DMA2 (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x18)) +#define I2S_IRQ (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x1C)) +#define I2S_TXRATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x20)) +#define I2S_RXRATE (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x24)) + + +/* General-purpose DMA Controller */ +#define DMA_BASE_ADDR 0xFFE04000 +#define GPDMA_INT_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x000)) +#define GPDMA_INT_TCSTAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x004)) +#define GPDMA_INT_TCCLR (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x008)) +#define GPDMA_INT_ERR_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x00C)) +#define GPDMA_INT_ERR_CLR (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x010)) +#define GPDMA_RAW_INT_TCSTAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x014)) +#define GPDMA_RAW_INT_ERR_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x018)) +#define GPDMA_ENABLED_CHNS (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x01C)) +#define GPDMA_SOFT_BREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x020)) +#define GPDMA_SOFT_SREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x024)) +#define GPDMA_SOFT_LBREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x028)) +#define GPDMA_SOFT_LSREQ (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x02C)) +#define GPDMA_CONFIG (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x030)) +#define GPDMA_SYNC (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x034)) + +/* DMA channel 0 registers */ +#define GPDMA_CH0_SRC (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x100)) +#define GPDMA_CH0_DEST (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x104)) +#define GPDMA_CH0_LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x108)) +#define GPDMA_CH0_CTRL (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x10C)) +#define GPDMA_CH0_CFG (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x110)) + +/* DMA channel 1 registers */ +#define GPDMA_CH1_SRC (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x120)) +#define GPDMA_CH1_DEST (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x124)) +#define GPDMA_CH1_LLI (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x128)) +#define GPDMA_CH1_CTRL (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x12C)) +#define GPDMA_CH1_CFG (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x130)) + + +/* USB Controller */ +#define USB_INT_BASE_ADDR 0xE01FC1C0 +#define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */ + +#define USB_INT_STAT (*(volatile unsigned long *)(USB_INT_BASE_ADDR + 0x00)) + +/* USB Device Interrupt Registers */ +#define DEV_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x00)) +#define DEV_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x04)) +#define DEV_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x08)) +#define DEV_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x0C)) +#define DEV_INT_PRIO (*(volatile unsigned long *)(USB_BASE_ADDR + 0x2C)) + +/* USB Device Endpoint Interrupt Registers */ +#define EP_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x30)) +#define EP_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x34)) +#define EP_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x38)) +#define EP_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x3C)) +#define EP_INT_PRIO (*(volatile unsigned long *)(USB_BASE_ADDR + 0x40)) + +/* USB Device Endpoint Realization Registers */ +#define REALIZE_EP (*(volatile unsigned long *)(USB_BASE_ADDR + 0x44)) +#define EP_INDEX (*(volatile unsigned long *)(USB_BASE_ADDR + 0x48)) +#define MAXPACKET_SIZE (*(volatile unsigned long *)(USB_BASE_ADDR + 0x4C)) + +/* USB Device Command Reagisters */ +#define CMD_CODE (*(volatile unsigned long *)(USB_BASE_ADDR + 0x10)) +#define CMD_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x14)) + +/* USB Device Data Transfer Registers */ +#define RX_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x18)) +#define TX_DATA (*(volatile unsigned long *)(USB_BASE_ADDR + 0x1C)) +#define RX_PLENGTH (*(volatile unsigned long *)(USB_BASE_ADDR + 0x20)) +#define TX_PLENGTH (*(volatile unsigned long *)(USB_BASE_ADDR + 0x24)) +#define USB_CTRL (*(volatile unsigned long *)(USB_BASE_ADDR + 0x28)) + +/* USB Device DMA Registers */ +#define DMA_REQ_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x50)) +#define DMA_REQ_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0x54)) +#define DMA_REQ_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0x58)) +#define UDCA_HEAD (*(volatile unsigned long *)(USB_BASE_ADDR + 0x80)) +#define EP_DMA_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x84)) +#define EP_DMA_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x88)) +#define EP_DMA_DIS (*(volatile unsigned long *)(USB_BASE_ADDR + 0x8C)) +#define DMA_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0x90)) +#define DMA_INT_EN (*(volatile unsigned long *)(USB_BASE_ADDR + 0x94)) +#define EOT_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA0)) +#define EOT_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA4)) +#define EOT_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0xA8)) +#define NDD_REQ_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0xAC)) +#define NDD_REQ_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB0)) +#define NDD_REQ_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB4)) +#define SYS_ERR_INT_STAT (*(volatile unsigned long *)(USB_BASE_ADDR + 0xB8)) +#define SYS_ERR_INT_CLR (*(volatile unsigned long *)(USB_BASE_ADDR + 0xBC)) +#define SYS_ERR_INT_SET (*(volatile unsigned long *)(USB_BASE_ADDR + 0xC0)) + + +/* USB Host Controller */ +#define USBHC_BASE_ADDR 0xFFE0C000 +#define HC_REVISION (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x00)) +#define HC_CONTROL (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x04)) +#define HC_CMD_STAT (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x08)) +#define HC_INT_STAT (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x0C)) +#define HC_INT_EN (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x10)) +#define HC_INT_DIS (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x14)) +#define HC_HCCA (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x18)) +#define HC_PERIOD_CUR_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x1C)) +#define HC_CTRL_HEAD_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x20)) +#define HC_CTRL_CUR_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x24)) +#define HC_BULK_HEAD_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x28)) +#define HC_BULK_CUR_ED (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x2C)) +#define HC_DONE_HEAD (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x30)) +#define HC_FM_INTERVAL (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x34)) +#define HC_FM_REMAINING (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x38)) +#define HC_FM_NUMBER (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x3C)) +#define HC_PERIOD_START (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x40)) +#define HC_LS_THRHLD (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x44)) +#define HC_RH_DESCA (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x48)) +#define HC_RH_DESCB (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x4C)) +#define HC_RH_STAT (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x50)) +#define HC_RH_PORT_STAT1 (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x54)) +#define HC_RH_PORT_STAT2 (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x58)) + +/* USB OTG Controller */ +#define USBOTG_BASE_ADDR 0xFFE0C100 +#define OTG_INT_STAT (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x00)) +#define OTG_INT_EN (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x04)) +#define OTG_INT_SET (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x08)) +#define OTG_INT_CLR (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x0C)) +#define OTG_STAT_CTRL (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10)) +#define OTG_TIMER (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x14)) + +#define USBOTG_I2C_BASE_ADDR 0xFFE0C300 +#define OTG_I2C_RX (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00)) +#define OTG_I2C_TX (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00)) +#define OTG_I2C_STS (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x04)) +#define OTG_I2C_CTL (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x08)) +#define OTG_I2C_CLKHI (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x0C)) +#define OTG_I2C_CLKLO (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x10)) + +#define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0 +#define OTG_CLK_CTRL (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04)) +#define OTG_CLK_STAT (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08)) + + +/* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */ +#define MAC_BASE_ADDR 0xFFE00000 /* AHB Peripheral # 0 */ +#define MAC_MAC1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */ +#define MAC_MAC2 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */ +#define MAC_IPGT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */ +#define MAC_IPGR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */ +#define MAC_CLRT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */ +#define MAC_MAXF (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */ +#define MAC_SUPP (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */ +#define MAC_TEST (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x01C)) /* TEST reg */ +#define MAC_MCFG (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */ +#define MAC_MCMD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */ +#define MAC_MADR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */ +#define MAC_MWTD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */ +#define MAC_MRDD (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */ +#define MAC_MIND (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */ + +#define MAC_SA0 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */ +#define MAC_SA1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */ +#define MAC_SA2 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */ + +#define MAC_COMMAND (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x100)) /* Command reg */ +#define MAC_STATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */ +#define MAC_RXDESCRIPTOR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */ +#define MAC_RXSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x10C)) /* Rx status base address reg */ +#define MAC_RXDESCRIPTORNUM (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x110)) /* Rx number of descriptors reg */ +#define MAC_RXPRODUCEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x114)) /* Rx produce index reg (RO) */ +#define MAC_RXCONSUMEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x118)) /* Rx consume index reg */ +#define MAC_TXDESCRIPTOR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x11C)) /* Tx descriptor base address reg */ +#define MAC_TXSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x120)) /* Tx status base address reg */ +#define MAC_TXDESCRIPTORNUM (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x124)) /* Tx number of descriptors reg */ +#define MAC_TXPRODUCEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x128)) /* Tx produce index reg */ +#define MAC_TXCONSUMEINDEX (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x12C)) /* Tx consume index reg (RO) */ + +#define MAC_TSV0 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x158)) /* Tx status vector 0 reg (RO) */ +#define MAC_TSV1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x15C)) /* Tx status vector 1 reg (RO) */ +#define MAC_RSV (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x160)) /* Rx status vector reg (RO) */ + +#define MAC_FLOWCONTROLCNT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x170)) /* Flow control counter reg */ +#define MAC_FLOWCONTROLSTS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x174)) /* Flow control status reg */ + +#define MAC_RXFILTERCTRL (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x200)) /* Rx filter ctrl reg */ +#define MAC_RXFILTERWOLSTS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x204)) /* Rx filter WoL status reg (RO) */ +#define MAC_RXFILTERWOLCLR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x208)) /* Rx filter WoL clear reg (WO) */ + +#define MAC_HASHFILTERL (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x210)) /* Hash filter LSBs reg */ +#define MAC_HASHFILTERH (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x214)) /* Hash filter MSBs reg */ + +#define MAC_INTSTATUS (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE0)) /* Interrupt status reg (RO) */ +#define MAC_INTENABLE (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE4)) /* Interrupt enable reg */ +#define MAC_INTCLEAR (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFE8)) /* Interrupt clear reg (WO) */ +#define MAC_INTSET (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFEC)) /* Interrupt set reg (WO) */ + +#define MAC_POWERDOWN (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */ +#define MAC_MODULEID (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */ + + + + + + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + + + + +#endif diff -upNr u-boot-orig/include/flash.h u-boot/include/flash.h --- u-boot-orig/include/flash.h 2009-03-18 00:42:12.000000000 +0100 +++ u-boot/include/flash.h 2009-03-18 10:42:45.000000000 +0100 @@ -338,8 +338,8 @@ extern flash_info_t *flash_get_info(ulon
#define TOSH_ID_FVT160 0xC2 /* TC58FVT160 ID (16 M, top ) */ #define TOSH_ID_FVB160 0x43 /* TC58FVT160 ID (16 M, bottom ) */ -#define PHILIPS_LPC2292 0x0401FF13 /* LPC2292 internal FLASH */ - +#define PHILIPS_LPC2292 0x0401FF13 /* LPC2292 internal FLASH */ +#define PHILIPS_LPC2468 0x0603FF35 /* LPC2468 internal FLASH */ /*----------------------------------------------------------------------- * Internal FLASH identification codes *
Dear Remco Poelstra,
In message 49C10B37.1070506@duran-audio.com you wrote:
This patch includes support for the LPC2468 processor from NXP.
Signed-off-by: Remco Poelstra remco.poelstra+u-boot@duran-audio.com
General comment: There are lots of coding style issues: trailing white space, incorrect brace style, lines too long, C++ comments, incorrect indentation, indentation not by TAB, etc.
Please clean up.
diff -upNr u-boot-orig/cpu/arm720t/cpu.c u-boot/cpu/arm720t/cpu.c --- u-boot-orig/cpu/arm720t/cpu.c 2009-03-18 00:42:12.000000000 +0100 +++ u-boot/cpu/arm720t/cpu.c 2009-03-18 09:54:58.000000000 +0100 @@ -78,6 +78,23 @@ int cleanup_before_linux (void) /* Nothing more needed */ #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No cleanup before linux for IntegratorAP/CM720T as yet */ +#elif defined(CONFIG_LPC2468)
- disable_interrupts ();
- {
volatile unsigned char dummy,i;
Please do not use arbitrary blocks to declare variables right in the middle of the function.
U0IER = 0;U1IER = 0;for(i=0; i<16; i++){
Incorrect brace style, here and in many other places. Indetation not by TAB, here and in many other places.
dummy=U0RBR;dummy=U0LSR;dummy=U0IIR;dummy=U1RBR;dummy=U1LSR;dummy=U1IIR;}
What sort of magic is this "code" supposed to perform?
diff -upNr u-boot-orig/cpu/arm720t/serial.c u-boot/cpu/arm720t/serial.c --- u-boot-orig/cpu/arm720t/serial.c 2009-03-18 00:42:12.000000000 +0100 +++ u-boot/cpu/arm720t/serial.c 2009-03-18 12:29:00.000000000 +0100 @@ -199,4 +199,91 @@ int serial_tstc (void) return (GET8(U0LSR) & 1); }
+#elif defined(CONFIG_LPC2468) +#include <asm/arch/hardware.h>
+int serial_init (void) +{
- unsigned long pinsel0;
- //enable uart #0 pins in GPIO (P0.2 = TxD0, P0.3 = RxD0)
- pinsel0 = PINSEL0;
- pinsel0 &= ~(0x000000f0);
- pinsel0 |= 0x00000050;
- PINSEL0 = pinsel0;
Please use proper accessor functions to access device registers, here and everywhere else.
+void serial_setbrg (void) +{
- DECLARE_GLOBAL_DATA_PTR;
- unsigned short divisor = 0;
- unsigned long fractional = 0;
- switch (gd->baudrate) {
- case 1200: divisor = 3000; fractional = 0xF0; break;
- case 9600: divisor = 375; fractional = 0xF0; break;
+// case 19200: divisor = 188; fractional = 0; break;
- case 19200: divisor = 175; fractional = 0xAF; break;
- case 38400: divisor = 94; fractional = 0; break;
+// case 38400: divisor = 75; fractional = 0xC3; break; +// case 57600: divisor = 63; fractional = 0; break;
- case 57600: divisor = 50; fractional = 0xC3; break;
+// case 115200: divisor = 31; fractional = 0; break;
...
+//#if 0
...
No such dead code, please!
diff -upNr u-boot-orig/include/asm-arm/arch-lpc24xx/lpc24xx_registers.h u-boot/include/asm-arm/arch-lpc24xx/lpc24xx_registers.h --- u-boot-orig/include/asm-arm/arch-lpc24xx/lpc24xx_registers.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot/include/asm-arm/arch-lpc24xx/lpc24xx_registers.h 2009-03-18 15:43:41.000000000 +0100 @@ -0,0 +1,1123 @@ +#ifndef __LPC24XX_REGISTERS_H +#define __LPC24XX_REGISTERS_H
+#include <config.h>
+/* Macros for reading/writing registers */ +//#define PUT8(reg, value) (*(volatile unsigned char*)(reg) = (value)) +//#define PUT16(reg, value) (*(volatile unsigned short*)(reg) = (value)) +//#define PUT32(reg, value) (*(volatile unsigned int*)(reg) = (value)) +//#define GET8(reg) (*(volatile unsigned char*)(reg)) +//#define GET16(reg) (*(volatile unsigned short*)(reg)) +//#define GET32(reg) (*(volatile unsigned int*)(reg))
No dead code, here and elsewhere, please.
+/* Vectored Interrupt Controller (VIC) */ +#define VIC_BASE_ADDR 0xFFFFF000 +#define VICIRQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x000)) +#define VICFIQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x004)) +#define VICRawIntr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x008)) +#define VICIntSelect (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x00C)) +#define VICIntEnable (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x010)) +#define VICIntEnClr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x014)) +#define VICSoftInt (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x018)) +#define VICSoftIntClr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x01C)) +#define VICProtection (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x020)) +#define VICSWPrioMask (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x024))
Please do not use offset lists, but define a proper C data structure instead. And never ever access device regiters through simple volatile pointers. Use proper accessor functions. Here and elsewhere.
The whole code needs a *major* cleanup before resubmitting.
[Note: I do not spend time on the second part this time.]
Best regards,
Wolfgang Denk
Wolfgang Denk schreef:
+/* Vectored Interrupt Controller (VIC) */ +#define VIC_BASE_ADDR 0xFFFFF000 +#define VICIRQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x000)) +#define VICFIQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x004)) +#define VICRawIntr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x008)) +#define VICIntSelect (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x00C)) +#define VICIntEnable (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x010)) +#define VICIntEnClr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x014)) +#define VICSoftInt (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x018)) +#define VICSoftIntClr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x01C)) +#define VICProtection (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x020)) +#define VICSWPrioMask (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x024))
Please do not use offset lists, but define a proper C data structure instead. And never ever access device regiters through simple volatile pointers. Use proper accessor functions. Here and elsewhere.
Hi,
All examples I checked use the same syntax for defining registers, so I left it in the code. If that is a problem, can you indicate an example which does The Right Thing (tm)?
The whole code needs a *major* cleanup before resubmitting.
I think the patch now matches the other criteria. The patch is a bit bigger, since other code did not follow the Coding Styles either. I used indent to fix my code and it fixed the other code as well.
The second patch will follow when this patch is OK.
Regards,
Remco Poelstra
---- --- u-boot-orig/cpu/arm720t/cpu.c 2009-03-18 00:42:12.000000000 +0100 +++ u-boot/cpu/arm720t/cpu.c 2009-03-19 16:00:04.000000000 +0100 @@ -41,7 +41,9 @@ int cpu_init (void) * setup up stacks if necessary */ #ifdef CONFIG_USE_IRQ - IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4; + IRQ_STACK_START = + _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - + 4; FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; #endif return 0; @@ -63,17 +65,17 @@ int cleanup_before_linux (void) disable_interrupts ();
/* turn off I-cache */ - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); i &= ~0x1000; - asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
/* flush I-cache */ - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); + asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); #ifdef CONFIG_ARM7_REVD /* go to high speed */ IO_SYSCON3 = (IO_SYSCON3 & ~CLKCTL) | CLKCTL_73; #endif -#elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) || defined(CONFIG_LPC2292) +#elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) || defined(CONFIG_LPC2292)|| defined(CONFIG_LPC2468) disable_interrupts (); /* Nothing more needed */ #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) @@ -84,12 +86,11 @@ int cleanup_before_linux (void) return 0; }
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { disable_interrupts (); reset_cpu (0); - /*NOTREACHED*/ - return (0); + /*NOTREACHED*/ return (0); }
/* @@ -99,30 +100,26 @@ int do_reset (cmd_tbl_t *cmdtp, int flag
#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO) /* read co-processor 15, register #1 (control register) */ -static unsigned long read_p15_c1(void) +static unsigned long read_p15_c1 (void) { unsigned long value;
- __asm__ __volatile__( - "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" - : "=r" (value) - : - : "memory"); + __asm__ __volatile__ ("mrc p15, 0, %0, c1, c0, 0 @ read control reg\n":"=r" (value) + ::"memory"); /* printf("p15/c1 is = %08lx\n", value); */ return value; }
/* write to co-processor 15, register #1 (control register) */ -static void write_p15_c1(unsigned long value) +static void write_p15_c1 (unsigned long value) { /* printf("write %08lx to p15/c1\n", value); */ - __asm__ __volatile__( - "mcr p15, 0, %0, c1, c0, 0 @ write it back\n" - : - : "r" (value) - : "memory"); + __asm__ + __volatile__ + ("mcr p15, 0, %0, c1, c0, 0 @ write it back\n"::"r" (value) + : "memory");
- read_p15_c1(); + read_p15_c1 (); }
static void cp_delay (void) @@ -130,7 +127,7 @@ static void cp_delay (void) volatile int i;
/* copro seems to need some delay between reading and writing */ - for (i = 0; i < 100; i++); + for (i = 0; i < 100; i++) ; }
/* See also ARM Ref. Man. */ @@ -196,63 +193,63 @@ void icache_enable (void) s32 i;
/* disable all cache bits */ - CLR_REG( REG_SYSCFG, 0x3F); + CLR_REG (REG_SYSCFG, 0x3F);
/* 8KB cache, write enable */ - SET_REG( REG_SYSCFG, CACHE_WRITE_BUFF | CACHE_MODE_01); + SET_REG (REG_SYSCFG, CACHE_WRITE_BUFF | CACHE_MODE_01);
/* clear TAG RAM bits */ - for ( i = 0; i < 256; i++) - PUT_REG( CACHE_TAG_RAM + 4*i, 0x00000000); + for (i = 0; i < 256; i++) + PUT_REG (CACHE_TAG_RAM + 4 * i, 0x00000000);
/* clear SET0 RAM */ - for(i=0; i < 1024; i++) - PUT_REG( CACHE_SET0_RAM + 4*i, 0x00000000); + for (i = 0; i < 1024; i++) + PUT_REG (CACHE_SET0_RAM + 4 * i, 0x00000000);
/* clear SET1 RAM */ - for(i=0; i < 1024; i++) - PUT_REG( CACHE_SET1_RAM + 4*i, 0x00000000); + for (i = 0; i < 1024; i++) + PUT_REG (CACHE_SET1_RAM + 4 * i, 0x00000000);
/* enable cache */ - SET_REG( REG_SYSCFG, CACHE_ENABLE); + SET_REG (REG_SYSCFG, CACHE_ENABLE);
}
void icache_disable (void) { /* disable all cache bits */ - CLR_REG( REG_SYSCFG, 0x3F); + CLR_REG (REG_SYSCFG, 0x3F); }
int icache_status (void) { - return GET_REG( REG_SYSCFG) & CACHE_ENABLE; + return GET_REG (REG_SYSCFG) & CACHE_ENABLE; }
void dcache_enable (void) { /* we don't have seperate instruction/data caches */ - icache_enable(); + icache_enable (); }
void dcache_disable (void) { /* we don't have seperate instruction/data caches */ - icache_disable(); + icache_disable (); }
int dcache_status (void) { /* we don't have seperate instruction/data caches */ - return icache_status(); + return icache_status (); }
#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No specific cache setup for IntegratorAP/CM720T as yet */ - void icache_enable (void) - { - } -#elif defined(CONFIG_LPC2292) /* just to satisfy the compiler */ +void icache_enable (void) +{ +} +#elif defined(CONFIG_LPC2292) || defined(CONFIG_LPC2468) /* just to satisfy the compiler */ #else #error No icache/dcache enable/disable functions defined for this CPU type #endif diff -upNr u-boot-orig/cpu/arm720t/interrupts.c u-boot/cpu/arm720t/interrupts.c --- u-boot-orig/cpu/arm720t/interrupts.c 2009-03-18 00:42:12.000000000 +0100 +++ u-boot/cpu/arm720t/interrupts.c 2009-03-19 15:11:29.000000000 +0100 @@ -40,6 +40,11 @@ #ifdef CONFIG_LPC2292 #undef READ_TIMER #define READ_TIMER (0xFFFFFFFF - GET32(T0TC)) +#elif defined(CONFIG_LPC2468) +#undef TIMER_LOAD_VAL +#define TIMER_LOAD_VAL 0 +#undef READ_TIMER +#define READ_TIMER (0xFFFFFFFF - T0TC) #endif
#else @@ -57,7 +62,7 @@ # else static struct _irq_handler IRQ_HANDLER[N_IRQS]; # endif -#endif /* CONFIG_S3C4510B */ +#endif /* CONFIG_S3C4510B */
#ifdef CONFIG_USE_IRQ void do_irq (struct pt_regs *pt_regs) @@ -65,21 +70,22 @@ void do_irq (struct pt_regs *pt_regs) #if defined(CONFIG_S3C4510B) unsigned int pending;
- while ( (pending = GET_REG( REG_INTOFFSET)) != 0x54) { /* sentinal value for no pending interrutps */ - IRQ_HANDLER[pending>>2].m_func( IRQ_HANDLER[pending>>2].m_data); + while ((pending = GET_REG (REG_INTOFFSET)) != 0x54) { /* sentinal value for no pending interrutps */ + IRQ_HANDLER[pending >> 2].m_func (IRQ_HANDLER[pending >> 2]. + m_data);
/* clear pending interrupt */ - PUT_REG( REG_INTPEND, (1<<(pending>>2))); + PUT_REG (REG_INTPEND, (1 << (pending >> 2))); } #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No do_irq() for IntegratorAP/CM720T as yet */ -#elif defined(CONFIG_LPC2292) +#elif defined(CONFIG_LPC2292) || defined(CONFIG_LPC2468)
- void (*pfnct)(void); + void (*pfnct) (void);
- pfnct = (void (*)(void))VICVectAddr; + pfnct = (void (*)(void))VICVectAddr;
- (*pfnct)(); + (*pfnct) (); #else #error do_irq() not defined for this CPU type #endif @@ -87,17 +93,19 @@ void do_irq (struct pt_regs *pt_regs) #endif
#ifdef CONFIG_S3C4510B -static void default_isr( void *data) { +static void default_isr (void *data) +{ printf ("default_isr(): called for IRQ %d\n", (int)data); }
-static void timer_isr( void *data) { +static void timer_isr (void *data) +{ unsigned int *pTime = (unsigned int *)data;
(*pTime)++; - if ( !(*pTime % (CONFIG_SYS_HZ/4))) { + if (!(*pTime % (CONFIG_SYS_HZ / 4))) { /* toggle LED 0 */ - PUT_REG( REG_IOPDATA, GET_REG(REG_IOPDATA) ^ 0x1); + PUT_REG (REG_IOPDATA, GET_REG (REG_IOPDATA) ^ 0x1); }
} @@ -118,9 +126,9 @@ int interrupt_init (void) IRQEN = 0;
/* operate timer 2 in non-prescale mode */ - TM2CTRL = ( NETARM_GEN_TIMER_SET_HZ(CONFIG_SYS_HZ) | - NETARM_GEN_TCTL_ENABLE | - NETARM_GEN_TCTL_INIT_COUNT(TIMER_LOAD_VAL)); + TM2CTRL = (NETARM_GEN_TIMER_SET_HZ (CONFIG_SYS_HZ) | + NETARM_GEN_TCTL_ENABLE | + NETARM_GEN_TCTL_INIT_COUNT (TIMER_LOAD_VAL));
/* set timer 2 counter */ lastdec = TIMER_LOAD_VAL; @@ -140,15 +148,15 @@ int interrupt_init (void) int i;
/* install default interrupt handlers */ - for ( i = 0; i < N_IRQS; i++) { + for (i = 0; i < N_IRQS; i++) { IRQ_HANDLER[i].m_data = (void *)i; IRQ_HANDLER[i].m_func = default_isr; }
/* configure interrupts for IRQ mode */ - PUT_REG( REG_INTMODE, 0x0); + PUT_REG (REG_INTMODE, 0x0); /* clear any pending interrupts */ - PUT_REG( REG_INTPEND, 0x1FFFFF); + PUT_REG (REG_INTPEND, 0x1FFFFF);
lastdec = 0;
@@ -157,35 +165,41 @@ int interrupt_init (void) IRQ_HANDLER[INT_TIMER0].m_func = timer_isr;
/* configure free running timer 0 */ - PUT_REG( REG_TMOD, 0x0); + PUT_REG (REG_TMOD, 0x0); /* Stop timer 0 */ - CLR_REG( REG_TMOD, TM0_RUN); + CLR_REG (REG_TMOD, TM0_RUN);
/* Configure for interval mode */ - CLR_REG( REG_TMOD, TM1_TOGGLE); + CLR_REG (REG_TMOD, TM1_TOGGLE);
/* * Load Timer data register with count down value. * count_down_val = CONFIG_SYS_SYS_CLK_FREQ/CONFIG_SYS_HZ */ - PUT_REG( REG_TDATA0, (CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ)); + PUT_REG (REG_TDATA0, (CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ));
/* * Enable global interrupt * Enable timer0 interrupt */ - CLR_REG( REG_INTMASK, ((1<<INT_GLOBAL) | (1<<INT_TIMER0))); + CLR_REG (REG_INTMASK, ((1 << INT_GLOBAL) | (1 << INT_TIMER0)));
/* Start timer */ - SET_REG( REG_TMOD, TM0_RUN); + SET_REG (REG_TMOD, TM0_RUN); #elif defined(CONFIG_LPC2292) - PUT32(T0IR, 0); /* disable all timer0 interrupts */ - PUT32(T0TCR, 0); /* disable timer0 */ - PUT32(T0PR, CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ); - PUT32(T0MCR, 0); - PUT32(T0TC, 0); - PUT32(T0TCR, 1); /* enable timer0 */ - + PUT32 (T0IR, 0); /* disable all timer0 interrupts */ + PUT32 (T0TCR, 0); /* disable timer0 */ + PUT32 (T0PR, CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ); + PUT32 (T0MCR, 0); + PUT32 (T0TC, 0); + PUT32 (T0TCR, 1); /* enable timer0 */ +#elif defined(CONFIG_LPC2468) + PUT32 (T0IR, 0); /*disable all timer0 interupts */ + PUT32 (T0TCR, 0); /*disable timer0 */ + PUT32 (T0PR, CFG_SYS_CLK_FREQ / CONFIG_SYS_HZ - 1); + PUT32 (T0MCR, 0); + PUT32 (T0TC, 0); + PUT32 (T0TCR, 1); #else #error No interrupt_init() defined for this CPU type #endif @@ -200,8 +214,7 @@ int interrupt_init (void) * timer without interrupts */
- -#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO) || defined(CONFIG_LPC2292) +#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO) || defined(CONFIG_LPC2292) || defined(CONFIG_LPC2468)
void reset_timer (void) { @@ -229,11 +242,11 @@ void udelay (unsigned long usec) tmo += get_timer (0);
while (get_timer_masked () < tmo) -#ifdef CONFIG_LPC2292 +#if defined(CONFIG_LPC2292) || defined(CONFIG_LPC2468) /* GJ - not sure whether this is really needed or a misunderstanding */ - __asm__ __volatile__(" nop"); + __asm__ __volatile__ (" nop"); #else - /*NOP*/; + /*NOP*/; #endif }
@@ -272,7 +285,7 @@ void udelay_masked (unsigned long usec) tmo /= 1000; } else { tmo = usec * CONFIG_SYS_HZ; - tmo /= (1000*1000); + tmo /= (1000 * 1000); }
endtime = get_timer_masked () + tmo; diff -upNr u-boot-orig/cpu/arm720t/lpc24xx/flash.c u-boot/cpu/arm720t/lpc24xx/flash.c --- u-boot-orig/cpu/arm720t/lpc24xx/flash.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot/cpu/arm720t/lpc24xx/flash.c 2009-03-19 15:16:57.000000000 +0100 @@ -0,0 +1,232 @@ +/* + * (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/hardware.h> + +/* IAP commands use 32 bytes at the top of CPU internal sram, we + use 512 bytes below that */ +#define COPY_BUFFER_LOCATION 0x4000fde0 + +#define IAP_LOCATION 0x7ffffff1 +#define IAP_CMD_PREPARE 50 +#define IAP_CMD_COPY 51 +#define IAP_CMD_ERASE 52 +#define IAP_CMD_CHECK 53 +#define IAP_CMD_ID 54 +#define IAP_CMD_VERSION 55 +#define IAP_CMD_COMPARE 56 + +#define IAP_RET_CMD_SUCCESS 0 + +static unsigned long command[5]; +static unsigned long result[2]; + +extern void iap_entry (unsigned long *command, unsigned long *result); + +/*----------------------------------------------------------------------- + * + */ +int get_flash_sector (flash_info_t * info, ulong flash_addr) +{ + int i; + + for (i = 1; i < (info->sector_count); i++) { + if (flash_addr < (info->start[i])) + break; + } + + return (i - 1); +} + +/*----------------------------------------------------------------------- + * This function assumes that flash_addr is aligned on 512 bytes boundary + * in flash. This function also assumes that prepare have been called + * for the sector in question. + */ +int lpc24xx_copy_buffer_to_flash (flash_info_t * info, ulong flash_addr) +{ + int first_sector; + int last_sector; + + first_sector = get_flash_sector (info, flash_addr); + last_sector = get_flash_sector (info, flash_addr + 512 - 1); + + /* prepare sectors for write */ + command[0] = IAP_CMD_PREPARE; + command[1] = first_sector; + command[2] = last_sector; + iap_entry (command, result); + if (result[0] != IAP_RET_CMD_SUCCESS) { + printf ("IAP prepare failed\n"); + return ERR_PROG_ERROR; + } + + command[0] = IAP_CMD_COPY; + command[1] = flash_addr; + command[2] = COPY_BUFFER_LOCATION; + command[3] = 512; + command[4] = CFG_SYS_CLK_FREQ >> 10; + iap_entry (command, result); + if (result[0] != IAP_RET_CMD_SUCCESS) { + printf ("IAP copy failed\n"); + return 1; + } + + return 0; +} + +int lpc24xx_flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag; + int prot; + int sect; + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) + return ERR_PROTECTED; + + flag = disable_interrupts (); + + printf ("Erasing %d sectors starting at sector %2d.\n" + "This make take some time ... ", s_last - s_first + 1, s_first); + + command[0] = IAP_CMD_PREPARE; + command[1] = s_first; + command[2] = s_last; + iap_entry (command, result); + if (result[0] != IAP_RET_CMD_SUCCESS) { + printf ("IAP prepare failed\n"); + return ERR_PROTECTED; + } + + command[0] = IAP_CMD_ERASE; + command[1] = s_first; + command[2] = s_last; + command[3] = CFG_SYS_CLK_FREQ >> 10; + iap_entry (command, result); + if (result[0] != IAP_RET_CMD_SUCCESS) { + printf ("IAP erase failed\n"); + return ERR_PROTECTED; + } + + if (flag) + enable_interrupts (); + + return ERR_OK; +} + +int lpc24xx_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + int first_copy_size; + int last_copy_size; + int first_block; + int last_block; + int nbr_mid_blocks; + uchar memmap_value; + ulong i; + uchar *src_org; + uchar *dst_org; + int ret = ERR_OK; + + src_org = src; + dst_org = (uchar *) addr; + + first_block = addr / 512; + last_block = (addr + cnt) / 512; + nbr_mid_blocks = last_block - first_block - 1; + + first_copy_size = 512 - (addr % 512); + last_copy_size = (addr + cnt) % 512; + + debug ("\ncopy first block: (1) %lX -> %lX 0x200 bytes, " + "(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX 0x200 bytes\n", + (ulong) (first_block * 512), + (ulong) COPY_BUFFER_LOCATION, + (ulong) src, + (ulong) (COPY_BUFFER_LOCATION + 512 - first_copy_size), + first_copy_size, + (ulong) COPY_BUFFER_LOCATION, (ulong) (first_block * 512)); + + /* copy first block */ + memcpy ((void *)COPY_BUFFER_LOCATION, (void *)(first_block * 512), 512); + memcpy ((void *)(COPY_BUFFER_LOCATION + 512 - first_copy_size), + src, first_copy_size); + lpc24xx_copy_buffer_to_flash (info, first_block * 512); + src += first_copy_size; + addr += first_copy_size; + + /* copy middle blocks */ + for (i = 0; i < nbr_mid_blocks; i++) { + debug ("copy middle block: %lX -> %lX 512 bytes, " + "%lX -> %lX 512 bytes\n", + (ulong) src, + (ulong) COPY_BUFFER_LOCATION, + (ulong) COPY_BUFFER_LOCATION, (ulong) addr); + memcpy ((void *)COPY_BUFFER_LOCATION, src, 512); + lpc24xx_copy_buffer_to_flash (info, addr); + src += 512; + addr += 512; + } + + if (last_copy_size > 0) { + debug ("copy last block: (1) %lX -> %lX 0x200 bytes, " + "(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX x200 bytes\n", + (ulong) (last_block * 512), + (ulong) COPY_BUFFER_LOCATION, + (ulong) src, + (ulong) (COPY_BUFFER_LOCATION), + last_copy_size, + (ulong) COPY_BUFFER_LOCATION, (ulong) addr); + /* copy last block */ + memcpy ((void *)COPY_BUFFER_LOCATION, + (void *)(last_block * 512), 512); + memcpy ((void *)COPY_BUFFER_LOCATION, src, last_copy_size); + lpc24xx_copy_buffer_to_flash (info, addr); + } + + /* verify write */ + memmap_value = GET32(MEMMAP); + + disable_interrupts (); + + PUT32(MEMMAP, 01); /* we must make sure that initial 64 + bytes are taken from flash when we + do the compare */ + + for (i = 0; i < cnt; i++) { + if (*dst_org != *src_org) { + printf ("Write failed. Byte %lX differs\n", i); + ret = ERR_PROG_ERROR; + break; + } + dst_org++; + src_org++; + } + + PUT32(MEMMAP, memmap_value); + enable_interrupts (); + + return ret; +} diff -upNr u-boot-orig/cpu/arm720t/lpc24xx/iap_entry.S u-boot/cpu/arm720t/lpc24xx/iap_entry.S --- u-boot-orig/cpu/arm720t/lpc24xx/iap_entry.S 1970-01-01 01:00:00.000000000 +0100 +++ u-boot/cpu/arm720t/lpc24xx/iap_entry.S 2009-03-19 10:56:19.000000000 +0100 @@ -0,0 +1,7 @@ +IAP_ADDRESS: .word 0x7FFFFFF1 + +.globl iap_entry +iap_entry: + ldr r2, IAP_ADDRESS + bx r2 + mov pc, lr diff -upNr u-boot-orig/cpu/arm720t/lpc24xx/Makefile u-boot/cpu/arm720t/lpc24xx/Makefile --- u-boot-orig/cpu/arm720t/lpc24xx/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ u-boot/cpu/arm720t/lpc24xx/Makefile 2009-03-19 10:56:53.000000000 +0100 @@ -0,0 +1,50 @@ +# +# (C) Copyright 2000-2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = flash.o +SOBJS = $(obj)iap_entry.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +# this MUST be compiled as thumb code! +$(SOBJS): + $(CC) $(AFLAGS) -march=armv4t -c -o $(SOBJS) iap_entry.S + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff -upNr u-boot-orig/cpu/arm720t/serial.c u-boot/cpu/arm720t/serial.c --- u-boot-orig/cpu/arm720t/serial.c 2009-03-18 00:42:12.000000000 +0100 +++ u-boot/cpu/arm720t/serial.c 2009-03-19 15:10:03.000000000 +0100 @@ -41,13 +41,27 @@ void serial_setbrg (void) unsigned int reg = 0;
switch (gd->baudrate) { - case 1200: reg = 191; break; - case 9600: reg = 23; break; - case 19200: reg = 11; break; - case 38400: reg = 5; break; - case 57600: reg = 3; break; - case 115200: reg = 1; break; - default: hang (); break; + case 1200: + reg = 191; + break; + case 9600: + reg = 23; + break; + case 19200: + reg = 11; + break; + case 38400: + reg = 5; + break; + case 57600: + reg = 3; + break; + case 115200: + reg = 1; + break; + default: + hang (); + break; }
/* init serial serial 1,2 */ @@ -60,7 +74,6 @@ void serial_setbrg (void) IO_UBRLCR2 = reg; }
- /* * Initialise the serial port with the given baudrate. The settings * are always 8 data bits, no parity, 1 stop bit, no start bits. @@ -73,7 +86,6 @@ int serial_init (void) return (0); }
- /* * Output a single byte to the serial port. */ @@ -110,47 +122,92 @@ int serial_tstc (void) */ int serial_getc (void) { - while (IO_SYSFLG1 & SYSFLG1_URXFE); + while (IO_SYSFLG1 & SYSFLG1_URXFE) ;
return IO_UARTDR1 & 0xff; }
-void -serial_puts (const char *s) +void serial_puts (const char *s) { while (*s) { serial_putc (*s++); } }
-#elif defined(CONFIG_LPC2292) +#elif defined(CONFIG_LPC2292) || defined(CONFIG_LPC2468)
DECLARE_GLOBAL_DATA_PTR;
#include <asm/arch/hardware.h>
+void serial_putc (const char c) +{ + if (c == '\n') { + while ((GET8 (U0LSR) & (1 << 5)) == 0) ; /* Wait for empty U0THR */ + PUT8 (U0THR, '\r'); + } + + while ((GET8 (U0LSR) & (1 << 5)) == 0) ; /* Wait for empty U0THR */ + PUT8 (U0THR, c); +} + +int serial_getc (void) +{ + while ((GET8 (U0LSR) & 1) == 0) ; + return GET8 (U0RBR); +} + +void serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +/* Test if there is a byte to read */ +int serial_tstc (void) +{ + return (GET8 (U0LSR) & 1); +} + +#if defined(CONFIG_LPC2292) + void serial_setbrg (void) { unsigned short divisor = 0;
switch (gd->baudrate) { - case 1200: divisor = 3072; break; - case 9600: divisor = 384; break; - case 19200: divisor = 192; break; - case 38400: divisor = 96; break; - case 57600: divisor = 64; break; - case 115200: divisor = 32; break; - default: hang (); break; + case 1200: + divisor = 3072; + break; + case 9600: + divisor = 384; + break; + case 19200: + divisor = 192; + break; + case 38400: + divisor = 96; + break; + case 57600: + divisor = 64; + break; + case 115200: + divisor = 32; + break; + default: + hang (); + break; }
/* init serial UART0 */ - PUT8(U0LCR, 0); - PUT8(U0IER, 0); - PUT8(U0LCR, 0x80); /* DLAB=1 */ - PUT8(U0DLL, (unsigned char)(divisor & 0x00FF)); - PUT8(U0DLM, (unsigned char)(divisor >> 8)); - PUT8(U0LCR, 0x03); /* 8N1, DLAB=0 */ - PUT8(U0FCR, 1); /* Enable RX and TX FIFOs */ + PUT8 (U0LCR, 0); + PUT8 (U0IER, 0); + PUT8 (U0LCR, 0x80); /* DLAB=1 */ + PUT8 (U0DLL, (unsigned char)(divisor & 0x00FF)); + PUT8 (U0DLM, (unsigned char)(divisor >> 8)); + PUT8 (U0LCR, 0x03); /* 8N1, DLAB=0 */ + PUT8 (U0FCR, 1); /* Enable RX and TX FIFOs */ }
int serial_init (void) @@ -159,44 +216,59 @@ int serial_init (void)
serial_setbrg ();
- pinsel0 = GET32(PINSEL0); + pinsel0 = GET32 (PINSEL0); pinsel0 &= ~(0x00000003); pinsel0 |= 5; - PUT32(PINSEL0, pinsel0); + PUT32 (PINSEL0, pinsel0);
return (0); }
-void serial_putc (const char c) -{ - if (c == '\n') - { - while((GET8(U0LSR) & (1<<5)) == 0); /* Wait for empty U0THR */ - PUT8(U0THR, '\r'); - } - - while((GET8(U0LSR) & (1<<5)) == 0); /* Wait for empty U0THR */ - PUT8(U0THR, c); -} +#else
-int serial_getc (void) +void serial_setbrg (void) { - while((GET8(U0LSR) & 1) == 0); - return GET8(U0RBR); -} + unsigned short divisor;
-void -serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); + switch (gd->baudrate) { + case 1200: + case 9600: + case 19200: + case 38400: + case 57600: + case 115200: + divisor = CFG_SYS_CLK_FREQ / (gd->baudrate * 16); + break; + default: + hang (); + break; } + + /* init serial UART0 */ + PUT8 (U0FCR, 0); /* Disable RX and TX FIFOs */ + PUT8 (U0LCR, 0); + PUT8 (U0IER, 0); + PUT8 (U0LCR, 0x80); /* DLAB=1 */ + PUT8 (U0DLL, (unsigned char)(divisor & 0x00FF)); + PUT8 (U0DLM, (unsigned char)(divisor >> 8)); + PUT8 (U0LCR, 0x03); /* 8N1, DLAB=0 */ + PUT8 (U0FCR, 0x7); /* Enable RX and TX FIFOs */ }
-/* Test if there is a byte to read */ -int serial_tstc (void) +int serial_init (void) { - return (GET8(U0LSR) & 1); + unsigned long pinsel0; + + /*enable uart #0 pins in GPIO (P0.2 = TxD0, P0.3 = RxD0) */ + pinsel0 = GET32 (PINSEL0); + pinsel0 &= ~(0x000000f0); + pinsel0 |= 0x00000050; + PUT32 (PINSEL0, pinsel0); + + serial_setbrg (); + + return (0); }
#endif +#endif /*defined(CONFIG_LPC2292) || defined(CONFIG_LPC2468) */ diff -upNr u-boot-orig/cpu/arm720t/start.S u-boot/cpu/arm720t/start.S --- u-boot-orig/cpu/arm720t/start.S 2009-03-18 00:42:12.000000000 +0100 +++ u-boot/cpu/arm720t/start.S 2009-03-19 11:21:20.000000000 +0100 @@ -127,7 +127,7 @@ reset: bl cpu_init_crit #endif
-#ifdef CONFIG_LPC2292 +#if defined(CONFIG_LPC2292) || defined(CONFIG_LPC2468) bl lowlevel_init #endif
@@ -368,6 +368,10 @@ lock_loop: ldr r0, VPBDIV_ADR mov r1, #0x01 /* VPB clock is same as process clock */ str r1, [r0] +#elif defined(CONFIG_LPC2468) + ldr r0, =0x40008000 /*0x40000000 is internal SRAM, 0x4000FFFF is end of SRAM*/ + mov sp,r0 + sub sl,sp,#0x2000 #else #error No cpu_init_crit() defined for current CPU type #endif @@ -383,7 +387,7 @@ lock_loop: str r1, [r0] #endif
-#ifndef CONFIG_LPC2292 +#if !defined(CONFIG_LPC2292) && !defined(CONFIG_LPC2468) mov ip, lr /* * before relocating, we have to setup RAM timing @@ -601,7 +605,7 @@ reset_cpu: * on external peripherals such as watchdog timers, etc. */ #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No specific reset actions for IntegratorAP/CM720T as yet */ -#elif defined(CONFIG_LPC2292) +#elif defined(CONFIG_LPC2292) || defined(CONFIG_LPC2468) .align 5 .globl reset_cpu reset_cpu: diff -upNr u-boot-orig/include/asm-arm/arch-lpc24xx/hardware.h u-boot/include/asm-arm/arch-lpc24xx/hardware.h --- u-boot-orig/include/asm-arm/arch-lpc24xx/hardware.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot/include/asm-arm/arch-lpc24xx/hardware.h 2009-03-18 09:31:46.000000000 +0100 @@ -0,0 +1,33 @@ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +/* + * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) + * Curt Brune curt@cucy.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#if defined(CONFIG_LPC2468) +#include <asm-arm/arch-lpc24xx/lpc24xx_registers.h> +#else +#error No hardware file defined for this configuration +#endif + +#endif /* __ASM_ARCH_HARDWARE_H */ diff -upNr u-boot-orig/include/asm-arm/arch-lpc24xx/lpc24xx_registers.h u-boot/include/asm-arm/arch-lpc24xx/lpc24xx_registers.h --- u-boot-orig/include/asm-arm/arch-lpc24xx/lpc24xx_registers.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot/include/asm-arm/arch-lpc24xx/lpc24xx_registers.h 2009-03-19 14:19:36.000000000 +0100 @@ -0,0 +1,1101 @@ +#ifndef __LPC24XX_REGISTERS_H +#define __LPC24XX_REGISTERS_H + +#include <config.h> + +/* Macros for reading/writing registers */ +#define PUT8(reg, value) (*(volatile unsigned char*)(reg) = (value)) +#define PUT16(reg, value) (*(volatile unsigned short*)(reg) = (value)) +#define PUT32(reg, value) (*(volatile unsigned int*)(reg) = (value)) +#define GET8(reg) (*(volatile unsigned char*)(reg)) +#define GET16(reg) (*(volatile unsigned short*)(reg)) +#define GET32(reg) (*(volatile unsigned int*)(reg)) + +#define BFS32(reg,value) (*(volatile unsigned int*)(reg) |= (value)) +#define BFC32(reg, value) (*(volatile unsigned int*)(reg) &= (~value)) + +/* Vectored Interrupt Controller (VIC) */ +#define VIC_BASE_ADDR 0xFFFFF000 +#define VICIRQStatus VIC_BASE_ADDR + 0x000 +#define VICFIQStatus VIC_BASE_ADDR + 0x004 +#define VICRawIntr VIC_BASE_ADDR + 0x008 +#define VICIntSelect VIC_BASE_ADDR + 0x00C +#define VICIntEnable VIC_BASE_ADDR + 0x010 +#define VICIntEnClr VIC_BASE_ADDR + 0x014 +#define VICSoftInt VIC_BASE_ADDR + 0x018 +#define VICSoftIntClr VIC_BASE_ADDR + 0x01C +#define VICProtection VIC_BASE_ADDR + 0x020 +#define VICSWPrioMask VIC_BASE_ADDR + 0x024 + +#define VICVectAddr0 VIC_BASE_ADDR + 0x100 +#define VICVectAddr1 VIC_BASE_ADDR + 0x104 +#define VICVectAddr2 VIC_BASE_ADDR + 0x108 +#define VICVectAddr3 VIC_BASE_ADDR + 0x10C +#define VICVectAddr4 VIC_BASE_ADDR + 0x110 +#define VICVectAddr5 VIC_BASE_ADDR + 0x114 +#define VICVectAddr6 VIC_BASE_ADDR + 0x118 +#define VICVectAddr7 VIC_BASE_ADDR + 0x11C +#define VICVectAddr8 VIC_BASE_ADDR + 0x120 +#define VICVectAddr9 VIC_BASE_ADDR + 0x124 +#define VICVectAddr10 VIC_BASE_ADDR + 0x128 +#define VICVectAddr11 VIC_BASE_ADDR + 0x12C +#define VICVectAddr12 VIC_BASE_ADDR + 0x130 +#define VICVectAddr13 VIC_BASE_ADDR + 0x134 +#define VICVectAddr14 VIC_BASE_ADDR + 0x138 +#define VICVectAddr15 VIC_BASE_ADDR + 0x13C +#define VICVectAddr16 VIC_BASE_ADDR + 0x140 +#define VICVectAddr17 VIC_BASE_ADDR + 0x144 +#define VICVectAddr18 VIC_BASE_ADDR + 0x148 +#define VICVectAddr19 VIC_BASE_ADDR + 0x14C +#define VICVectAddr20 VIC_BASE_ADDR + 0x150 +#define VICVectAddr21 VIC_BASE_ADDR + 0x154 +#define VICVectAddr22 VIC_BASE_ADDR + 0x158 +#define VICVectAddr23 VIC_BASE_ADDR + 0x15C +#define VICVectAddr24 VIC_BASE_ADDR + 0x160 +#define VICVectAddr25 VIC_BASE_ADDR + 0x164 +#define VICVectAddr26 VIC_BASE_ADDR + 0x168 +#define VICVectAddr27 VIC_BASE_ADDR + 0x16C +#define VICVectAddr28 VIC_BASE_ADDR + 0x170 +#define VICVectAddr29 VIC_BASE_ADDR + 0x174 +#define VICVectAddr30 VIC_BASE_ADDR + 0x178 +#define VICVectAddr31 VIC_BASE_ADDR + 0x17C + +/* The name convention below is from previous LPC2000 family MCUs, in LPC230x, +these registers are known as "VICVectPriority(x)". */ +#define VICVectCntl0 VIC_BASE_ADDR + 0x200 +#define VICVectCntl1 VIC_BASE_ADDR + 0x204 +#define VICVectCntl2 VIC_BASE_ADDR + 0x208 +#define VICVectCntl3 VIC_BASE_ADDR + 0x20C +#define VICVectCntl4 VIC_BASE_ADDR + 0x210 +#define VICVectCntl5 VIC_BASE_ADDR + 0x214 +#define VICVectCntl6 VIC_BASE_ADDR + 0x218 +#define VICVectCntl7 VIC_BASE_ADDR + 0x21C +#define VICVectCntl8 VIC_BASE_ADDR + 0x220 +#define VICVectCntl9 VIC_BASE_ADDR + 0x224 +#define VICVectCntl10 VIC_BASE_ADDR + 0x228 +#define VICVectCntl11 VIC_BASE_ADDR + 0x22C +#define VICVectCntl12 VIC_BASE_ADDR + 0x230 +#define VICVectCntl13 VIC_BASE_ADDR + 0x234 +#define VICVectCntl14 VIC_BASE_ADDR + 0x238 +#define VICVectCntl15 VIC_BASE_ADDR + 0x23C +#define VICVectCntl16 VIC_BASE_ADDR + 0x240 +#define VICVectCntl17 VIC_BASE_ADDR + 0x244 +#define VICVectCntl18 VIC_BASE_ADDR + 0x248 +#define VICVectCntl19 VIC_BASE_ADDR + 0x24C +#define VICVectCntl20 VIC_BASE_ADDR + 0x250 +#define VICVectCntl21 VIC_BASE_ADDR + 0x254 +#define VICVectCntl22 VIC_BASE_ADDR + 0x258 +#define VICVectCntl23 VIC_BASE_ADDR + 0x25C +#define VICVectCntl24 VIC_BASE_ADDR + 0x260 +#define VICVectCntl25 VIC_BASE_ADDR + 0x264 +#define VICVectCntl26 VIC_BASE_ADDR + 0x268 +#define VICVectCntl27 VIC_BASE_ADDR + 0x26C +#define VICVectCntl28 VIC_BASE_ADDR + 0x270 +#define VICVectCntl29 VIC_BASE_ADDR + 0x274 +#define VICVectCntl30 VIC_BASE_ADDR + 0x278 +#define VICVectCntl31 VIC_BASE_ADDR + 0x27C + +#define VICVectAddr VIC_BASE_ADDR + 0xF00 + +/* Pin Connect Block */ +#define PINSEL_BASE_ADDR 0xE002C000 +#define PINSEL0 PINSEL_BASE_ADDR + 0x00 +#define PINSEL1 PINSEL_BASE_ADDR + 0x04 +#define PINSEL2 PINSEL_BASE_ADDR + 0x08 +#define PINSEL3 PINSEL_BASE_ADDR + 0x0C +#define PINSEL4 PINSEL_BASE_ADDR + 0x10 +#define PINSEL5 PINSEL_BASE_ADDR + 0x14 +#define PINSEL6 PINSEL_BASE_ADDR + 0x18 +#define PINSEL7 PINSEL_BASE_ADDR + 0x1C +#define PINSEL8 PINSEL_BASE_ADDR + 0x20 +#define PINSEL9 PINSEL_BASE_ADDR + 0x24 +#define PINSEL10 PINSEL_BASE_ADDR + 0x28 + +#define PINMODE0 PINSEL_BASE_ADDR + 0x40 +#define PINMODE1 PINSEL_BASE_ADDR + 0x44 +#define PINMODE2 PINSEL_BASE_ADDR + 0x48 +#define PINMODE3 PINSEL_BASE_ADDR + 0x4C +#define PINMODE4 PINSEL_BASE_ADDR + 0x50 +#define PINMODE5 PINSEL_BASE_ADDR + 0x54 +#define PINMODE6 PINSEL_BASE_ADDR + 0x58 +#define PINMODE7 PINSEL_BASE_ADDR + 0x5C +#define PINMODE8 PINSEL_BASE_ADDR + 0x60 +#define PINMODE9 PINSEL_BASE_ADDR + 0x64 + +/* General Purpose Input/Output (GPIO) */ +#define GPIO_BASE_ADDR 0xE0028000 +#define IOPIN0 GPIO_BASE_ADDR + 0x00 +#define IOSET0 GPIO_BASE_ADDR + 0x04 +#define IODIR0 GPIO_BASE_ADDR + 0x08 +#define IOCLR0 GPIO_BASE_ADDR + 0x0C +#define IOPIN1 GPIO_BASE_ADDR + 0x10 +#define IOSET1 GPIO_BASE_ADDR + 0x14 +#define IODIR1 GPIO_BASE_ADDR + 0x18 +#define IOCLR1 GPIO_BASE_ADDR + 0x1C + +/* GPIO Interrupt Registers */ +#define IO0_INT_EN_R GPIO_BASE_ADDR + 0x90 +#define IO0_INT_EN_F GPIO_BASE_ADDR + 0x94 +#define IO0_INT_STAT_R GPIO_BASE_ADDR + 0x84 +#define IO0_INT_STAT_F GPIO_BASE_ADDR + 0x88 +#define IO0_INT_CLR GPIO_BASE_ADDR + 0x8C + +#define IO2_INT_EN_R GPIO_BASE_ADDR + 0xB0 +#define IO2_INT_EN_F GPIO_BASE_ADDR + 0xB4 +#define IO2_INT_STAT_R GPIO_BASE_ADDR + 0xA4 +#define IO2_INT_STAT_F GPIO_BASE_ADDR + 0xA8 +#define IO2_INT_CLR GPIO_BASE_ADDR + 0xAC + +#define IO_INT_STAT GPIO_BASE_ADDR + 0x80 + +#define PARTCFG_BASE_ADDR 0x3FFF8000 +#define PARTCFG PARTCFG_BASE_ADDR + 0x00 + +/* Fast I/O setup */ +#define FIO_BASE_ADDR 0x3FFFC000 +#define FIO0DIR FIO_BASE_ADDR + 0x00 +#define FIO0MASK FIO_BASE_ADDR + 0x10 +#define FIO0PIN FIO_BASE_ADDR + 0x14 +#define FIO0SET FIO_BASE_ADDR + 0x18 +#define FIO0CLR FIO_BASE_ADDR + 0x1C + +#define FIO1DIR FIO_BASE_ADDR + 0x20 +#define FIO1MASK FIO_BASE_ADDR + 0x30 +#define FIO1PIN FIO_BASE_ADDR + 0x34 +#define FIO1SET FIO_BASE_ADDR + 0x38 +#define FIO1CLR FIO_BASE_ADDR + 0x3C + +#define FIO2DIR FIO_BASE_ADDR + 0x40 +#define FIO2MASK FIO_BASE_ADDR + 0x50 +#define FIO2PIN FIO_BASE_ADDR + 0x54 +#define FIO2SET FIO_BASE_ADDR + 0x58 +#define FIO2CLR FIO_BASE_ADDR + 0x5C + +#define FIO3DIR FIO_BASE_ADDR + 0x60 +#define FIO3MASK FIO_BASE_ADDR + 0x70 +#define FIO3PIN FIO_BASE_ADDR + 0x74 +#define FIO3SET FIO_BASE_ADDR + 0x78 +#define FIO3CLR FIO_BASE_ADDR + 0x7C + +#define FIO4DIR FIO_BASE_ADDR + 0x80 +#define FIO4MASK FIO_BASE_ADDR + 0x90 +#define FIO4PIN FIO_BASE_ADDR + 0x94 +#define FIO4SET FIO_BASE_ADDR + 0x98 +#define FIO4CLR FIO_BASE_ADDR + 0x9C + +/* FIOs can be accessed through WORD, HALF-WORD or BYTE. */ +#define FIO0DIR0 FIO_BASE_ADDR + 0x01 +#define FIO1DIR0 FIO_BASE_ADDR + 0x21 +#define FIO2DIR0 FIO_BASE_ADDR + 0x41 +#define FIO3DIR0 FIO_BASE_ADDR + 0x61 +#define FIO4DIR0 FIO_BASE_ADDR + 0x81 + +#define FIO0DIR1 FIO_BASE_ADDR + 0x02 +#define FIO1DIR1 FIO_BASE_ADDR + 0x22 +#define FIO2DIR1 FIO_BASE_ADDR + 0x42 +#define FIO3DIR1 FIO_BASE_ADDR + 0x62 +#define FIO4DIR1 FIO_BASE_ADDR + 0x82 + +#define FIO0DIR2 FIO_BASE_ADDR + 0x03 +#define FIO1DIR2 FIO_BASE_ADDR + 0x23 +#define FIO2DIR2 FIO_BASE_ADDR + 0x43 +#define FIO3DIR2 FIO_BASE_ADDR + 0x63 +#define FIO4DIR2 FIO_BASE_ADDR + 0x83 + +#define FIO0DIR3 FIO_BASE_ADDR + 0x04 +#define FIO1DIR3 FIO_BASE_ADDR + 0x24 +#define FIO2DIR3 FIO_BASE_ADDR + 0x44 +#define FIO3DIR3 FIO_BASE_ADDR + 0x64 +#define FIO4DIR3 FIO_BASE_ADDR + 0x84 + +#define FIO0DIRL FIO_BASE_ADDR + 0x00 +#define FIO1DIRL FIO_BASE_ADDR + 0x20 +#define FIO2DIRL FIO_BASE_ADDR + 0x40 +#define FIO3DIRL FIO_BASE_ADDR + 0x60 +#define FIO4DIRL FIO_BASE_ADDR + 0x80 + +#define FIO0DIRU FIO_BASE_ADDR + 0x02 +#define FIO1DIRU FIO_BASE_ADDR + 0x22 +#define FIO2DIRU FIO_BASE_ADDR + 0x42 +#define FIO3DIRU FIO_BASE_ADDR + 0x62 +#define FIO4DIRU FIO_BASE_ADDR + 0x82 + +#define FIO0MASK0 FIO_BASE_ADDR + 0x10 +#define FIO1MASK0 FIO_BASE_ADDR + 0x30 +#define FIO2MASK0 FIO_BASE_ADDR + 0x50 +#define FIO3MASK0 FIO_BASE_ADDR + 0x70 +#define FIO4MASK0 FIO_BASE_ADDR + 0x90 + +#define FIO0MASK1 FIO_BASE_ADDR + 0x11 +#define FIO1MASK1 FIO_BASE_ADDR + 0x21 +#define FIO2MASK1 FIO_BASE_ADDR + 0x51 +#define FIO3MASK1 FIO_BASE_ADDR + 0x71 +#define FIO4MASK1 FIO_BASE_ADDR + 0x91 + +#define FIO0MASK2 FIO_BASE_ADDR + 0x12 +#define FIO1MASK2 FIO_BASE_ADDR + 0x32 +#define FIO2MASK2 FIO_BASE_ADDR + 0x52 +#define FIO3MASK2 FIO_BASE_ADDR + 0x72 +#define FIO4MASK2 FIO_BASE_ADDR + 0x92 + +#define FIO0MASK3 FIO_BASE_ADDR + 0x13 +#define FIO1MASK3 FIO_BASE_ADDR + 0x33 +#define FIO2MASK3 FIO_BASE_ADDR + 0x53 +#define FIO3MASK3 FIO_BASE_ADDR + 0x73 +#define FIO4MASK3 FIO_BASE_ADDR + 0x93 + +#define FIO0MASKL FIO_BASE_ADDR + 0x10 +#define FIO1MASKL FIO_BASE_ADDR + 0x30 +#define FIO2MASKL FIO_BASE_ADDR + 0x50 +#define FIO3MASKL FIO_BASE_ADDR + 0x70 +#define FIO4MASKL FIO_BASE_ADDR + 0x90 + +#define FIO0MASKU FIO_BASE_ADDR + 0x12 +#define FIO1MASKU FIO_BASE_ADDR + 0x32 +#define FIO2MASKU FIO_BASE_ADDR + 0x52 +#define FIO3MASKU FIO_BASE_ADDR + 0x72 +#define FIO4MASKU FIO_BASE_ADDR + 0x92 + +#define FIO0PIN0 FIO_BASE_ADDR + 0x14 +#define FIO1PIN0 FIO_BASE_ADDR + 0x34 +#define FIO2PIN0 FIO_BASE_ADDR + 0x54 +#define FIO3PIN0 FIO_BASE_ADDR + 0x74 +#define FIO4PIN0 FIO_BASE_ADDR + 0x94 + +#define FIO0PIN1 FIO_BASE_ADDR + 0x15 +#define FIO1PIN1 FIO_BASE_ADDR + 0x25 +#define FIO2PIN1 FIO_BASE_ADDR + 0x55 +#define FIO3PIN1 FIO_BASE_ADDR + 0x75 +#define FIO4PIN1 FIO_BASE_ADDR + 0x95 + +#define FIO0PIN2 FIO_BASE_ADDR + 0x16 +#define FIO1PIN2 FIO_BASE_ADDR + 0x36 +#define FIO2PIN2 FIO_BASE_ADDR + 0x56 +#define FIO3PIN2 FIO_BASE_ADDR + 0x76 +#define FIO4PIN2 FIO_BASE_ADDR + 0x96 + +#define FIO0PIN3 FIO_BASE_ADDR + 0x17 +#define FIO1PIN3 FIO_BASE_ADDR + 0x37 +#define FIO2PIN3 FIO_BASE_ADDR + 0x57 +#define FIO3PIN3 FIO_BASE_ADDR + 0x77 +#define FIO4PIN3 FIO_BASE_ADDR + 0x97 + +#define FIO0PINL FIO_BASE_ADDR + 0x14 +#define FIO1PINL FIO_BASE_ADDR + 0x34 +#define FIO2PINL FIO_BASE_ADDR + 0x54 +#define FIO3PINL FIO_BASE_ADDR + 0x74 +#define FIO4PINL FIO_BASE_ADDR + 0x94 + +#define FIO0PINU FIO_BASE_ADDR + 0x16 +#define FIO1PINU FIO_BASE_ADDR + 0x36 +#define FIO2PINU FIO_BASE_ADDR + 0x56 +#define FIO3PINU FIO_BASE_ADDR + 0x76 +#define FIO4PINU FIO_BASE_ADDR + 0x96 + +#define FIO0SET0 FIO_BASE_ADDR + 0x18 +#define FIO1SET0 FIO_BASE_ADDR + 0x38 +#define FIO2SET0 FIO_BASE_ADDR + 0x58 +#define FIO3SET0 FIO_BASE_ADDR + 0x78 +#define FIO4SET0 FIO_BASE_ADDR + 0x98 + +#define FIO0SET1 FIO_BASE_ADDR + 0x19 +#define FIO1SET1 FIO_BASE_ADDR + 0x29 +#define FIO2SET1 FIO_BASE_ADDR + 0x59 +#define FIO3SET1 FIO_BASE_ADDR + 0x79 +#define FIO4SET1 FIO_BASE_ADDR + 0x99 + +#define FIO0SET2 FIO_BASE_ADDR + 0x1A +#define FIO1SET2 FIO_BASE_ADDR + 0x3A +#define FIO2SET2 FIO_BASE_ADDR + 0x5A +#define FIO3SET2 FIO_BASE_ADDR + 0x7A +#define FIO4SET2 FIO_BASE_ADDR + 0x9A + +#define FIO0SET3 FIO_BASE_ADDR + 0x1B +#define FIO1SET3 FIO_BASE_ADDR + 0x3B +#define FIO2SET3 FIO_BASE_ADDR + 0x5B +#define FIO3SET3 FIO_BASE_ADDR + 0x7B +#define FIO4SET3 FIO_BASE_ADDR + 0x9B + +#define FIO0SETL FIO_BASE_ADDR + 0x18 +#define FIO1SETL FIO_BASE_ADDR + 0x38 +#define FIO2SETL FIO_BASE_ADDR + 0x58 +#define FIO3SETL FIO_BASE_ADDR + 0x78 +#define FIO4SETL FIO_BASE_ADDR + 0x98 + +#define FIO0SETU FIO_BASE_ADDR + 0x1A +#define FIO1SETU FIO_BASE_ADDR + 0x3A +#define FIO2SETU FIO_BASE_ADDR + 0x5A +#define FIO3SETU FIO_BASE_ADDR + 0x7A +#define FIO4SETU FIO_BASE_ADDR + 0x9A + +#define FIO0CLR0 FIO_BASE_ADDR + 0x1C +#define FIO1CLR0 FIO_BASE_ADDR + 0x3C +#define FIO2CLR0 FIO_BASE_ADDR + 0x5C +#define FIO3CLR0 FIO_BASE_ADDR + 0x7C +#define FIO4CLR0 FIO_BASE_ADDR + 0x9C + +#define FIO0CLR1 FIO_BASE_ADDR + 0x1D +#define FIO1CLR1 FIO_BASE_ADDR + 0x2D +#define FIO2CLR1 FIO_BASE_ADDR + 0x5D +#define FIO3CLR1 FIO_BASE_ADDR + 0x7D +#define FIO4CLR1 FIO_BASE_ADDR + 0x9D + +#define FIO0CLR2 FIO_BASE_ADDR + 0x1E +#define FIO1CLR2 FIO_BASE_ADDR + 0x3E +#define FIO2CLR2 FIO_BASE_ADDR + 0x5E +#define FIO3CLR2 FIO_BASE_ADDR + 0x7E +#define FIO4CLR2 FIO_BASE_ADDR + 0x9E + +#define FIO0CLR3 FIO_BASE_ADDR + 0x1F +#define FIO1CLR3 FIO_BASE_ADDR + 0x3F +#define FIO2CLR3 FIO_BASE_ADDR + 0x5F +#define FIO3CLR3 FIO_BASE_ADDR + 0x7F +#define FIO4CLR3 FIO_BASE_ADDR + 0x9F + +#define FIO0CLRL FIO_BASE_ADDR + 0x1C +#define FIO1CLRL FIO_BASE_ADDR + 0x3C +#define FIO2CLRL FIO_BASE_ADDR + 0x5C +#define FIO3CLRL FIO_BASE_ADDR + 0x7C +#define FIO4CLRL FIO_BASE_ADDR + 0x9C + +#define FIO0CLRU FIO_BASE_ADDR + 0x1E +#define FIO1CLRU FIO_BASE_ADDR + 0x3E +#define FIO2CLRU FIO_BASE_ADDR + 0x5E +#define FIO3CLRU FIO_BASE_ADDR + 0x7E +#define FIO4CLRU FIO_BASE_ADDR + 0x9E + +/* System Control Block(SCB) modules include Memory Accelerator Module, +Phase Locked Loop, VPB divider, Power Control, External Interrupt, +Reset, and Code Security/Debugging */ +#define SCB_BASE_ADDR 0xE01FC000 + +/* Memory Accelerator Module (MAM) */ +#define MAMCR SCB_BASE_ADDR + 0x000 +#define MAMTIM SCB_BASE_ADDR + 0x004 +#define MEMMAP SCB_BASE_ADDR + 0x040 + +/* Phase Locked Loop (PLL) */ +#define PLLCON SCB_BASE_ADDR + 0x080 +#define PLLCFG SCB_BASE_ADDR + 0x084 +#define PLLSTAT SCB_BASE_ADDR + 0x088 +#define PLLFEED SCB_BASE_ADDR + 0x08C + +/* Power Control */ +#define PCON SCB_BASE_ADDR + 0x0C0 +#define PCONP SCB_BASE_ADDR + 0x0C4 + +/* Clock Divider */ +// #define APBDIV SCB_BASE_ADDR + 0x100 +#define CCLKCFG SCB_BASE_ADDR + 0x104 +#define USBCLKCFG SCB_BASE_ADDR + 0x108 +#define CLKSRCSEL SCB_BASE_ADDR + 0x10C +#define PCLKSEL0 SCB_BASE_ADDR + 0x1A8 +#define PCLKSEL1 SCB_BASE_ADDR + 0x1AC + +/* External Interrupts */ +#define EXTINT SCB_BASE_ADDR + 0x140 +#define INTWAKE SCB_BASE_ADDR + 0x144 +#define EXTMODE SCB_BASE_ADDR + 0x148 +#define EXTPOLAR SCB_BASE_ADDR + 0x14C + +/* Reset, reset source identification */ +#define RSIR SCB_BASE_ADDR + 0x180 + +/* RSID, code security protection */ +#define CSPR SCB_BASE_ADDR + 0x184 + +/* AHB configuration */ +#define AHBCFG1 SCB_BASE_ADDR + 0x188 +#define AHBCFG2 SCB_BASE_ADDR + 0x18C + +/* System Controls and Status */ +#define SCS SCB_BASE_ADDR + 0x1A0 + +/* External Memory Controller (EMC) */ +#define EMC_BASE_ADDR 0xFFE08000 +#define EMC_CTRL EMC_BASE_ADDR + 0x000 +#define EMC_STAT EMC_BASE_ADDR + 0x004 +#define EMC_CONFIG EMC_BASE_ADDR + 0x008 + +/* Dynamic RAM access registers */ +#define EMC_DYN_CTRL EMC_BASE_ADDR + 0x020 +#define EMC_DYN_RFSH EMC_BASE_ADDR + 0x024 +#define EMC_DYN_RD_CFG EMC_BASE_ADDR + 0x028 +#define EMC_DYN_RP EMC_BASE_ADDR + 0x030 +#define EMC_DYN_RAS EMC_BASE_ADDR + 0x034 +#define EMC_DYN_SREX EMC_BASE_ADDR + 0x038 +#define EMC_DYN_APR EMC_BASE_ADDR + 0x03C +#define EMC_DYN_DAL EMC_BASE_ADDR + 0x040 +#define EMC_DYN_WR EMC_BASE_ADDR + 0x044 +#define EMC_DYN_RC EMC_BASE_ADDR + 0x048 +#define EMC_DYN_RFC EMC_BASE_ADDR + 0x04C +#define EMC_DYN_XSR EMC_BASE_ADDR + 0x050 +#define EMC_DYN_RRD EMC_BASE_ADDR + 0x054 +#define EMC_DYN_MRD EMC_BASE_ADDR + 0x058 + +#define EMC_DYN_CFG0 EMC_BASE_ADDR + 0x100 +#define EMC_DYN_RASCAS0 EMC_BASE_ADDR + 0x104 +#define EMC_DYN_CFG1 EMC_BASE_ADDR + 0x140 +#define EMC_DYN_RASCAS1 EMC_BASE_ADDR + 0x144 +#define EMC_DYN_CFG2 EMC_BASE_ADDR + 0x160 +#define EMC_DYN_RASCAS2 EMC_BASE_ADDR + 0x164 +#define EMC_DYN_CFG3 EMC_BASE_ADDR + 0x180 +#define EMC_DYN_RASCAS3 EMC_BASE_ADDR + 0x184 + +/* static RAM access registers */ +#define EMC_STA_CFG0 EMC_BASE_ADDR + 0x200 +#define EMC_STA_WAITWEN0 EMC_BASE_ADDR + 0x204 +#define EMC_STA_WAITOEN0 EMC_BASE_ADDR + 0x208 +#define EMC_STA_WAITRD0 EMC_BASE_ADDR + 0x20C +#define EMC_STA_WAITPAGE0 EMC_BASE_ADDR + 0x210 +#define EMC_STA_WAITWR0 EMC_BASE_ADDR + 0x214 +#define EMC_STA_WAITTURN0 EMC_BASE_ADDR + 0x218 + +#define EMC_STA_CFG1 EMC_BASE_ADDR + 0x220 +#define EMC_STA_WAITWEN1 EMC_BASE_ADDR + 0x224 +#define EMC_STA_WAITOEN1 EMC_BASE_ADDR + 0x228 +#define EMC_STA_WAITRD1 EMC_BASE_ADDR + 0x22C +#define EMC_STA_WAITPAGE1 EMC_BASE_ADDR + 0x230 +#define EMC_STA_WAITWR1 EMC_BASE_ADDR + 0x234 +#define EMC_STA_WAITTURN1 EMC_BASE_ADDR + 0x238 + +#define EMC_STA_CFG2 EMC_BASE_ADDR + 0x240 +#define EMC_STA_WAITWEN2 EMC_BASE_ADDR + 0x244 +#define EMC_STA_WAITOEN2 EMC_BASE_ADDR + 0x248 +#define EMC_STA_WAITRD2 EMC_BASE_ADDR + 0x24C +#define EMC_STA_WAITPAGE2 EMC_BASE_ADDR + 0x250 +#define EMC_STA_WAITWR2 EMC_BASE_ADDR + 0x254 +#define EMC_STA_WAITTURN2 EMC_BASE_ADDR + 0x258 + +#define EMC_STA_CFG3 EMC_BASE_ADDR + 0x260 +#define EMC_STA_WAITWEN3 EMC_BASE_ADDR + 0x264 +#define EMC_STA_WAITOEN3 EMC_BASE_ADDR + 0x268 +#define EMC_STA_WAITRD3 EMC_BASE_ADDR + 0x26C +#define EMC_STA_WAITPAGE3 EMC_BASE_ADDR + 0x270 +#define EMC_STA_WAITWR3 EMC_BASE_ADDR + 0x274 +#define EMC_STA_WAITTURN3 EMC_BASE_ADDR + 0x278 + +#define EMC_STA_EXT_WAIT EMC_BASE_ADDR + 0x880 + +/* Timer 0 */ +#define TMR0_BASE_ADDR 0xE0004000 +#define T0IR TMR0_BASE_ADDR + 0x00 +#define T0TCR TMR0_BASE_ADDR + 0x04 +#define T0TC TMR0_BASE_ADDR + 0x08 +#define T0PR TMR0_BASE_ADDR + 0x0C +#define T0PC TMR0_BASE_ADDR + 0x10 +#define T0MCR TMR0_BASE_ADDR + 0x14 +#define T0MR0 TMR0_BASE_ADDR + 0x18 +#define T0MR1 TMR0_BASE_ADDR + 0x1C +#define T0MR2 TMR0_BASE_ADDR + 0x20 +#define T0MR3 TMR0_BASE_ADDR + 0x24 +#define T0CCR TMR0_BASE_ADDR + 0x28 +#define T0CR0 TMR0_BASE_ADDR + 0x2C +#define T0CR1 TMR0_BASE_ADDR + 0x30 +#define T0CR2 TMR0_BASE_ADDR + 0x34 +#define T0CR3 TMR0_BASE_ADDR + 0x38 +#define T0EMR TMR0_BASE_ADDR + 0x3C +#define T0CTCR TMR0_BASE_ADDR + 0x70 + +/* Timer 1 */ +#define TMR1_BASE_ADDR 0xE0008000 +#define T1IR TMR1_BASE_ADDR + 0x00 +#define T1TCR TMR1_BASE_ADDR + 0x04 +#define T1TC TMR1_BASE_ADDR + 0x08 +#define T1PR TMR1_BASE_ADDR + 0x0C +#define T1PC TMR1_BASE_ADDR + 0x10 +#define T1MCR TMR1_BASE_ADDR + 0x14 +#define T1MR0 TMR1_BASE_ADDR + 0x18 +#define T1MR1 TMR1_BASE_ADDR + 0x1C +#define T1MR2 TMR1_BASE_ADDR + 0x20 +#define T1MR3 TMR1_BASE_ADDR + 0x24 +#define T1CCR TMR1_BASE_ADDR + 0x28 +#define T1CR0 TMR1_BASE_ADDR + 0x2C +#define T1CR1 TMR1_BASE_ADDR + 0x30 +#define T1CR2 TMR1_BASE_ADDR + 0x34 +#define T1CR3 TMR1_BASE_ADDR + 0x38 +#define T1EMR TMR1_BASE_ADDR + 0x3C +#define T1CTCR TMR1_BASE_ADDR + 0x70 + +/* Timer 2 */ +#define TMR2_BASE_ADDR 0xE0070000 +#define T2IR TMR2_BASE_ADDR + 0x00 +#define T2TCR TMR2_BASE_ADDR + 0x04 +#define T2TC TMR2_BASE_ADDR + 0x08 +#define T2PR TMR2_BASE_ADDR + 0x0C +#define T2PC TMR2_BASE_ADDR + 0x10 +#define T2MCR TMR2_BASE_ADDR + 0x14 +#define T2MR0 TMR2_BASE_ADDR + 0x18 +#define T2MR1 TMR2_BASE_ADDR + 0x1C +#define T2MR2 TMR2_BASE_ADDR + 0x20 +#define T2MR3 TMR2_BASE_ADDR + 0x24 +#define T2CCR TMR2_BASE_ADDR + 0x28 +#define T2CR0 TMR2_BASE_ADDR + 0x2C +#define T2CR1 TMR2_BASE_ADDR + 0x30 +#define T2CR2 TMR2_BASE_ADDR + 0x34 +#define T2CR3 TMR2_BASE_ADDR + 0x38 +#define T2EMR TMR2_BASE_ADDR + 0x3C +#define T2CTCR TMR2_BASE_ADDR + 0x70 + +/* Timer 3 */ +#define TMR3_BASE_ADDR 0xE0074000 +#define T3IR TMR3_BASE_ADDR + 0x00 +#define T3TCR TMR3_BASE_ADDR + 0x04 +#define T3TC TMR3_BASE_ADDR + 0x08 +#define T3PR TMR3_BASE_ADDR + 0x0C +#define T3PC TMR3_BASE_ADDR + 0x10 +#define T3MCR TMR3_BASE_ADDR + 0x14 +#define T3MR0 TMR3_BASE_ADDR + 0x18 +#define T3MR1 TMR3_BASE_ADDR + 0x1C +#define T3MR2 TMR3_BASE_ADDR + 0x20 +#define T3MR3 TMR3_BASE_ADDR + 0x24 +#define T3CCR TMR3_BASE_ADDR + 0x28 +#define T3CR0 TMR3_BASE_ADDR + 0x2C +#define T3CR1 TMR3_BASE_ADDR + 0x30 +#define T3CR2 TMR3_BASE_ADDR + 0x34 +#define T3CR3 TMR3_BASE_ADDR + 0x38 +#define T3EMR TMR3_BASE_ADDR + 0x3C +#define T3CTCR TMR3_BASE_ADDR + 0x70 + +/* Pulse Width Modulator (PWM) */ +#define PWM0_BASE_ADDR 0xE0014000 +#define PWM0IR PWM0_BASE_ADDR + 0x00 +#define PWM0TCR PWM0_BASE_ADDR + 0x04 +#define PWM0TC PWM0_BASE_ADDR + 0x08 +#define PWM0PR PWM0_BASE_ADDR + 0x0C +#define PWM0PC PWM0_BASE_ADDR + 0x10 +#define PWM0MCR PWM0_BASE_ADDR + 0x14 +#define PWM0MR0 PWM0_BASE_ADDR + 0x18 +#define PWM0MR1 PWM0_BASE_ADDR + 0x1C +#define PWM0MR2 PWM0_BASE_ADDR + 0x20 +#define PWM0MR3 PWM0_BASE_ADDR + 0x24 +#define PWM0CCR PWM0_BASE_ADDR + 0x28 +#define PWM0CR0 PWM0_BASE_ADDR + 0x2C +#define PWM0CR1 PWM0_BASE_ADDR + 0x30 +#define PWM0CR2 PWM0_BASE_ADDR + 0x34 +#define PWM0CR3 PWM0_BASE_ADDR + 0x38 +#define PWM0EMR PWM0_BASE_ADDR + 0x3C +#define PWM0MR4 PWM0_BASE_ADDR + 0x40 +#define PWM0MR5 PWM0_BASE_ADDR + 0x44 +#define PWM0MR6 PWM0_BASE_ADDR + 0x48 +#define PWM0PCR PWM0_BASE_ADDR + 0x4C +#define PWM0LER PWM0_BASE_ADDR + 0x50 +#define PWM0CTCR PWM0_BASE_ADDR + 0x70 + +#define PWM1_BASE_ADDR 0xE0018000 +#define PWM1IR PWM1_BASE_ADDR + 0x00 +#define PWM1TCR PWM1_BASE_ADDR + 0x04 +#define PWM1TC PWM1_BASE_ADDR + 0x08 +#define PWM1PR PWM1_BASE_ADDR + 0x0C +#define PWM1PC PWM1_BASE_ADDR + 0x10 +#define PWM1MCR PWM1_BASE_ADDR + 0x14 +#define PWM1MR0 PWM1_BASE_ADDR + 0x18 +#define PWM1MR1 PWM1_BASE_ADDR + 0x1C +#define PWM1MR2 PWM1_BASE_ADDR + 0x20 +#define PWM1MR3 PWM1_BASE_ADDR + 0x24 +#define PWM1CCR PWM1_BASE_ADDR + 0x28 +#define PWM1CR0 PWM1_BASE_ADDR + 0x2C +#define PWM1CR1 PWM1_BASE_ADDR + 0x30 +#define PWM1CR2 PWM1_BASE_ADDR + 0x34 +#define PWM1CR3 PWM1_BASE_ADDR + 0x38 +#define PWM1EMR PWM1_BASE_ADDR + 0x3C +#define PWM1MR4 PWM1_BASE_ADDR + 0x40 +#define PWM1MR5 PWM1_BASE_ADDR + 0x44 +#define PWM1MR6 PWM1_BASE_ADDR + 0x48 +#define PWM1PCR PWM1_BASE_ADDR + 0x4C +#define PWM1LER PWM1_BASE_ADDR + 0x50 +#define PWM1CTCR PWM1_BASE_ADDR + 0x70 + +/* Universal Asynchronous Receiver Transmitter 0 (UART0) */ +#define UART0_BASE_ADDR 0xE000C000 +#define U0RBR UART0_BASE_ADDR + 0x00 +#define U0THR UART0_BASE_ADDR + 0x00 +#define U0DLL UART0_BASE_ADDR + 0x00 +#define U0DLM UART0_BASE_ADDR + 0x04 +#define U0IER UART0_BASE_ADDR + 0x04 +#define U0IIR UART0_BASE_ADDR + 0x08 +#define U0FCR UART0_BASE_ADDR + 0x08 +#define U0LCR UART0_BASE_ADDR + 0x0C +#define U0LSR UART0_BASE_ADDR + 0x14 +#define U0SCR UART0_BASE_ADDR + 0x1C +#define U0ACR UART0_BASE_ADDR + 0x20 +#define U0FDR UART0_BASE_ADDR + 0x28 +#define U0TER UART0_BASE_ADDR + 0x30 + +/* Universal Asynchronous Receiver Transmitter 1 (UART1) */ +#define UART1_BASE_ADDR 0xE0010000 +#define U1RBR UART1_BASE_ADDR + 0x00 +#define U1THR UART1_BASE_ADDR + 0x00 +#define U1DLL UART1_BASE_ADDR + 0x00 +#define U1DLM UART1_BASE_ADDR + 0x04 +#define U1IER UART1_BASE_ADDR + 0x04 +#define U1IIR UART1_BASE_ADDR + 0x08 +#define U1FCR UART1_BASE_ADDR + 0x08 +#define U1LCR UART1_BASE_ADDR + 0x0C +#define U1MCR UART1_BASE_ADDR + 0x10 +#define U1LSR UART1_BASE_ADDR + 0x14 +#define U1MSR UART1_BASE_ADDR + 0x18 +#define U1SCR UART1_BASE_ADDR + 0x1C +#define U1ACR UART1_BASE_ADDR + 0x20 +#define U1FDR UART1_BASE_ADDR + 0x28 +#define U1TER UART1_BASE_ADDR + 0x30 + +/* Universal Asynchronous Receiver Transmitter 2 (UART2) */ +#define UART2_BASE_ADDR 0xE0078000 +#define U2RBR UART2_BASE_ADDR + 0x00 +#define U2THR UART2_BASE_ADDR + 0x00 +#define U2DLL UART2_BASE_ADDR + 0x00 +#define U2DLM UART2_BASE_ADDR + 0x04 +#define U2IER UART2_BASE_ADDR + 0x04 +#define U2IIR UART2_BASE_ADDR + 0x08 +#define U2FCR UART2_BASE_ADDR + 0x08 +#define U2LCR UART2_BASE_ADDR + 0x0C +#define U2LSR UART2_BASE_ADDR + 0x14 +#define U2SCR UART2_BASE_ADDR + 0x1C +#define U2ACR UART2_BASE_ADDR + 0x20 +#define U2ICR UART2_BASE_ADDR + 0x24 +#define U2FDR UART2_BASE_ADDR + 0x28 +#define U2TER UART2_BASE_ADDR + 0x30 + +/* Universal Asynchronous Receiver Transmitter 3 (UART3) */ +#define UART3_BASE_ADDR 0xE007C000 +#define U3RBR UART3_BASE_ADDR + 0x00 +#define U3THR UART3_BASE_ADDR + 0x00 +#define U3DLL UART3_BASE_ADDR + 0x00 +#define U3DLM UART3_BASE_ADDR + 0x04 +#define U3IER UART3_BASE_ADDR + 0x04 +#define U3IIR UART3_BASE_ADDR + 0x08 +#define U3FCR UART3_BASE_ADDR + 0x08 +#define U3LCR UART3_BASE_ADDR + 0x0C +#define U3LSR UART3_BASE_ADDR + 0x14 +#define U3SCR UART3_BASE_ADDR + 0x1C +#define U3ACR UART3_BASE_ADDR + 0x20 +#define U3ICR UART3_BASE_ADDR + 0x24 +#define U3FDR UART3_BASE_ADDR + 0x28 +#define U3TER UART3_BASE_ADDR + 0x30 + +/* I2C Interface 0 */ +#define I2C0_BASE_ADDR 0xE001C000 +#define I20CONSET I2C0_BASE_ADDR + 0x00 +#define I20STAT I2C0_BASE_ADDR + 0x04 +#define I20DAT I2C0_BASE_ADDR + 0x08 +#define I20ADR I2C0_BASE_ADDR + 0x0C +#define I20SCLH I2C0_BASE_ADDR + 0x10 +#define I20SCLL I2C0_BASE_ADDR + 0x14 +#define I20CONCLR I2C0_BASE_ADDR + 0x18 + +/* I2C Interface 1 */ +#define I2C1_BASE_ADDR 0xE005C000 +#define I21CONSET I2C1_BASE_ADDR + 0x00 +#define I21STAT I2C1_BASE_ADDR + 0x04 +#define I21DAT I2C1_BASE_ADDR + 0x08 +#define I21ADR I2C1_BASE_ADDR + 0x0C +#define I21SCLH I2C1_BASE_ADDR + 0x10 +#define I21SCLL I2C1_BASE_ADDR + 0x14 +#define I21CONCLR I2C1_BASE_ADDR + 0x18 + +/* I2C Interface 2 */ +#define I2C2_BASE_ADDR 0xE0080000 +#define I22CONSET I2C2_BASE_ADDR + 0x00 +#define I22STAT I2C2_BASE_ADDR + 0x04 +#define I22DAT I2C2_BASE_ADDR + 0x08 +#define I22ADR I2C2_BASE_ADDR + 0x0C +#define I22SCLH I2C2_BASE_ADDR + 0x10 +#define I22SCLL I2C2_BASE_ADDR + 0x14 +#define I22CONCLR I2C2_BASE_ADDR + 0x18 + +/* SPI0 (Serial Peripheral Interface 0) */ +#define SPI0_BASE_ADDR 0xE0020000 +#define S0SPCR SPI0_BASE_ADDR + 0x00 +#define S0SPSR SPI0_BASE_ADDR + 0x04 +#define S0SPDR SPI0_BASE_ADDR + 0x08 +#define S0SPCCR SPI0_BASE_ADDR + 0x0C +#define S0SPINT SPI0_BASE_ADDR + 0x1C + +/* SSP0 Controller */ +#define SSP0_BASE_ADDR 0xE0068000 +#define SSP0CR0 SSP0_BASE_ADDR + 0x00 +#define SSP0CR1 SSP0_BASE_ADDR + 0x04 +#define SSP0DR SSP0_BASE_ADDR + 0x08 +#define SSP0SR SSP0_BASE_ADDR + 0x0C +#define SSP0CPSR SSP0_BASE_ADDR + 0x10 +#define SSP0IMSC SSP0_BASE_ADDR + 0x14 +#define SSP0RIS SSP0_BASE_ADDR + 0x18 +#define SSP0MIS SSP0_BASE_ADDR + 0x1C +#define SSP0ICR SSP0_BASE_ADDR + 0x20 +#define SSP0DMACR SSP0_BASE_ADDR + 0x24 + +/* SSP1 Controller */ +#define SSP1_BASE_ADDR 0xE0030000 +#define SSP1CR0 SSP1_BASE_ADDR + 0x00 +#define SSP1CR1 SSP1_BASE_ADDR + 0x04 +#define SSP1DR SSP1_BASE_ADDR + 0x08 +#define SSP1SR SSP1_BASE_ADDR + 0x0C +#define SSP1CPSR SSP1_BASE_ADDR + 0x10 +#define SSP1IMSC SSP1_BASE_ADDR + 0x14 +#define SSP1RIS SSP1_BASE_ADDR + 0x18 +#define SSP1MIS SSP1_BASE_ADDR + 0x1C +#define SSP1ICR SSP1_BASE_ADDR + 0x20 +#define SSP1DMACR SSP1_BASE_ADDR + 0x24 + +/* Real Time Clock */ +#define RTC_BASE_ADDR 0xE0024000 +#define RTC_ILR RTC_BASE_ADDR + 0x00 +#define RTC_CTC RTC_BASE_ADDR + 0x04 +#define RTC_CCR RTC_BASE_ADDR + 0x08 +#define RTC_CIIR RTC_BASE_ADDR + 0x0C +#define RTC_AMR RTC_BASE_ADDR + 0x10 +#define RTC_CTIME0 RTC_BASE_ADDR + 0x14 +#define RTC_CTIME1 RTC_BASE_ADDR + 0x18 +#define RTC_CTIME2 RTC_BASE_ADDR + 0x1C +#define RTC_SEC RTC_BASE_ADDR + 0x20 +#define RTC_MIN RTC_BASE_ADDR + 0x24 +#define RTC_HOUR RTC_BASE_ADDR + 0x28 +#define RTC_DOM RTC_BASE_ADDR + 0x2C +#define RTC_DOW RTC_BASE_ADDR + 0x30 +#define RTC_DOY RTC_BASE_ADDR + 0x34 +#define RTC_MONTH RTC_BASE_ADDR + 0x38 +#define RTC_YEAR RTC_BASE_ADDR + 0x3C +#define RTC_CISS RTC_BASE_ADDR + 0x40 +#define RTC_ALSEC RTC_BASE_ADDR + 0x60 +#define RTC_ALMIN RTC_BASE_ADDR + 0x64 +#define RTC_ALHOUR RTC_BASE_ADDR + 0x68 +#define RTC_ALDOM RTC_BASE_ADDR + 0x6C +#define RTC_ALDOW RTC_BASE_ADDR + 0x70 +#define RTC_ALDOY RTC_BASE_ADDR + 0x74 +#define RTC_ALMON RTC_BASE_ADDR + 0x78 +#define RTC_ALYEAR RTC_BASE_ADDR + 0x7C +#define RTC_PREINT RTC_BASE_ADDR + 0x80 +#define RTC_PREFRAC RTC_BASE_ADDR + 0x84 + +/* A/D Converter 0 (AD0) */ +#define AD0_BASE_ADDR 0xE0034000 +#define AD0CR AD0_BASE_ADDR + 0x00 +#define AD0GDR AD0_BASE_ADDR + 0x04 +#define AD0INTEN AD0_BASE_ADDR + 0x0C +#define AD0DR0 AD0_BASE_ADDR + 0x10 +#define AD0DR1 AD0_BASE_ADDR + 0x14 +#define AD0DR2 AD0_BASE_ADDR + 0x18 +#define AD0DR3 AD0_BASE_ADDR + 0x1C +#define AD0DR4 AD0_BASE_ADDR + 0x20 +#define AD0DR5 AD0_BASE_ADDR + 0x24 +#define AD0DR6 AD0_BASE_ADDR + 0x28 +#define AD0DR7 AD0_BASE_ADDR + 0x2C +#define AD0STAT AD0_BASE_ADDR + 0x30 + +/* D/A Converter */ +#define DAC_BASE_ADDR 0xE006C000 +#define DACR DAC_BASE_ADDR + 0x00 + +/* Watchdog */ +#define WDG_BASE_ADDR 0xE0000000 +#define WDMOD WDG_BASE_ADDR + 0x00 +#define WDTC WDG_BASE_ADDR + 0x04 +#define WDFEED WDG_BASE_ADDR + 0x08 +#define WDTV WDG_BASE_ADDR + 0x0C +#define WDCLKSEL WDG_BASE_ADDR + 0x10 + +/* CAN CONTROLLERS AND ACCEPTANCE FILTER */ +#define CAN_ACCEPT_BASE_ADDR 0xE003C000 +#define CAN_AFMR CAN_ACCEPT_BASE_ADDR + 0x00 +#define CAN_SFF_SA CAN_ACCEPT_BASE_ADDR + 0x04 +#define CAN_SFF_GRP_SA CAN_ACCEPT_BASE_ADDR + 0x08 +#define CAN_EFF_SA CAN_ACCEPT_BASE_ADDR + 0x0C +#define CAN_EFF_GRP_SA CAN_ACCEPT_BASE_ADDR + 0x10 +#define CAN_EOT CAN_ACCEPT_BASE_ADDR + 0x14 +#define CAN_LUT_ERR_ADR CAN_ACCEPT_BASE_ADDR + 0x18 +#define CAN_LUT_ERR CAN_ACCEPT_BASE_ADDR + 0x1C + +#define CAN_CENTRAL_BASE_ADDR 0xE0040000 +#define CAN_TX_SR CAN_CENTRAL_BASE_ADDR + 0x00 +#define CAN_RX_SR CAN_CENTRAL_BASE_ADDR + 0x04 +#define CAN_MSR CAN_CENTRAL_BASE_ADDR + 0x08 + +#define CAN1_BASE_ADDR 0xE0044000 +#define CAN1MOD CAN1_BASE_ADDR + 0x00 +#define CAN1CMR CAN1_BASE_ADDR + 0x04 +#define CAN1GSR CAN1_BASE_ADDR + 0x08 +#define CAN1ICR CAN1_BASE_ADDR + 0x0C +#define CAN1IER CAN1_BASE_ADDR + 0x10 +#define CAN1BTR CAN1_BASE_ADDR + 0x14 +#define CAN1EWL CAN1_BASE_ADDR + 0x18 +#define CAN1SR CAN1_BASE_ADDR + 0x1C +#define CAN1RFS CAN1_BASE_ADDR + 0x20 +#define CAN1RID CAN1_BASE_ADDR + 0x24 +#define CAN1RDA CAN1_BASE_ADDR + 0x28 +#define CAN1RDB CAN1_BASE_ADDR + 0x2C + +#define CAN1TFI1 CAN1_BASE_ADDR + 0x30 +#define CAN1TID1 CAN1_BASE_ADDR + 0x34 +#define CAN1TDA1 CAN1_BASE_ADDR + 0x38 +#define CAN1TDB1 CAN1_BASE_ADDR + 0x3C +#define CAN1TFI2 CAN1_BASE_ADDR + 0x40 +#define CAN1TID2 CAN1_BASE_ADDR + 0x44 +#define CAN1TDA2 CAN1_BASE_ADDR + 0x48 +#define CAN1TDB2 CAN1_BASE_ADDR + 0x4C +#define CAN1TFI3 CAN1_BASE_ADDR + 0x50 +#define CAN1TID3 CAN1_BASE_ADDR + 0x54 +#define CAN1TDA3 CAN1_BASE_ADDR + 0x58 +#define CAN1TDB3 CAN1_BASE_ADDR + 0x5C + +#define CAN2_BASE_ADDR 0xE0048000 +#define CAN2MOD CAN2_BASE_ADDR + 0x00 +#define CAN2CMR CAN2_BASE_ADDR + 0x04 +#define CAN2GSR CAN2_BASE_ADDR + 0x08 +#define CAN2ICR CAN2_BASE_ADDR + 0x0C +#define CAN2IER CAN2_BASE_ADDR + 0x10 +#define CAN2BTR CAN2_BASE_ADDR + 0x14 +#define CAN2EWL CAN2_BASE_ADDR + 0x18 +#define CAN2SR CAN2_BASE_ADDR + 0x1C +#define CAN2RFS CAN2_BASE_ADDR + 0x20 +#define CAN2RID CAN2_BASE_ADDR + 0x24 +#define CAN2RDA CAN2_BASE_ADDR + 0x28 +#define CAN2RDB CAN2_BASE_ADDR + 0x2C + +#define CAN2TFI1 CAN2_BASE_ADDR + 0x30 +#define CAN2TID1 CAN2_BASE_ADDR + 0x34 +#define CAN2TDA1 CAN2_BASE_ADDR + 0x38 +#define CAN2TDB1 CAN2_BASE_ADDR + 0x3C +#define CAN2TFI2 CAN2_BASE_ADDR + 0x40 +#define CAN2TID2 CAN2_BASE_ADDR + 0x44 +#define CAN2TDA2 CAN2_BASE_ADDR + 0x48 +#define CAN2TDB2 CAN2_BASE_ADDR + 0x4C +#define CAN2TFI3 CAN2_BASE_ADDR + 0x50 +#define CAN2TID3 CAN2_BASE_ADDR + 0x54 +#define CAN2TDA3 CAN2_BASE_ADDR + 0x58 +#define CAN2TDB3 CAN2_BASE_ADDR + 0x5C + +/* MultiMedia Card Interface(MCI) Controller */ +#define MCI_BASE_ADDR 0xE008C000 +#define MCI_POWER MCI_BASE_ADDR + 0x00 +#define MCI_CLOCK MCI_BASE_ADDR + 0x04 +#define MCI_ARGUMENT MCI_BASE_ADDR + 0x08 +#define MCI_COMMAND MCI_BASE_ADDR + 0x0C +#define MCI_RESP_CMD MCI_BASE_ADDR + 0x10 +#define MCI_RESP0 MCI_BASE_ADDR + 0x14 +#define MCI_RESP1 MCI_BASE_ADDR + 0x18 +#define MCI_RESP2 MCI_BASE_ADDR + 0x1C +#define MCI_RESP3 MCI_BASE_ADDR + 0x20 +#define MCI_DATA_TMR MCI_BASE_ADDR + 0x24 +#define MCI_DATA_LEN MCI_BASE_ADDR + 0x28 +#define MCI_DATA_CTRL MCI_BASE_ADDR + 0x2C +#define MCI_DATA_CNT MCI_BASE_ADDR + 0x30 +#define MCI_STATUS MCI_BASE_ADDR + 0x34 +#define MCI_CLEAR MCI_BASE_ADDR + 0x38 +#define MCI_MASK0 MCI_BASE_ADDR + 0x3C +#define MCI_MASK1 MCI_BASE_ADDR + 0x40 +#define MCI_FIFO_CNT MCI_BASE_ADDR + 0x48 +#define MCI_FIFO MCI_BASE_ADDR + 0x80 + +/* I2S Interface Controller (I2S) */ +#define I2S_BASE_ADDR 0xE0088000 +#define I2S_DAO I2S_BASE_ADDR + 0x00 +#define I2S_DAI I2S_BASE_ADDR + 0x04 +#define I2S_TX_FIFO I2S_BASE_ADDR + 0x08 +#define I2S_RX_FIFO I2S_BASE_ADDR + 0x0C +#define I2S_STATE I2S_BASE_ADDR + 0x10 +#define I2S_DMA1 I2S_BASE_ADDR + 0x14 +#define I2S_DMA2 I2S_BASE_ADDR + 0x18 +#define I2S_IRQ I2S_BASE_ADDR + 0x1C +#define I2S_TXRATE I2S_BASE_ADDR + 0x20 +#define I2S_RXRATE I2S_BASE_ADDR + 0x24 + +/* General-purpose DMA Controller */ +#define DMA_BASE_ADDR 0xFFE04000 +#define GPDMA_INT_STAT DMA_BASE_ADDR + 0x000 +#define GPDMA_INT_TCSTAT DMA_BASE_ADDR + 0x004 +#define GPDMA_INT_TCCLR DMA_BASE_ADDR + 0x008 +#define GPDMA_INT_ERR_STAT DMA_BASE_ADDR + 0x00C +#define GPDMA_INT_ERR_CLR DMA_BASE_ADDR + 0x010 +#define GPDMA_RAW_INT_TCSTAT DMA_BASE_ADDR + 0x014 +#define GPDMA_RAW_INT_ERR_STAT DMA_BASE_ADDR + 0x018 +#define GPDMA_ENABLED_CHNS DMA_BASE_ADDR + 0x01C +#define GPDMA_SOFT_BREQ DMA_BASE_ADDR + 0x020 +#define GPDMA_SOFT_SREQ DMA_BASE_ADDR + 0x024 +#define GPDMA_SOFT_LBREQ DMA_BASE_ADDR + 0x028 +#define GPDMA_SOFT_LSREQ DMA_BASE_ADDR + 0x02C +#define GPDMA_CONFIG DMA_BASE_ADDR + 0x030 +#define GPDMA_SYNC DMA_BASE_ADDR + 0x034 + +/* DMA channel 0 registers */ +#define GPDMA_CH0_SRC DMA_BASE_ADDR + 0x100 +#define GPDMA_CH0_DEST DMA_BASE_ADDR + 0x104 +#define GPDMA_CH0_LLI DMA_BASE_ADDR + 0x108 +#define GPDMA_CH0_CTRL DMA_BASE_ADDR + 0x10C +#define GPDMA_CH0_CFG DMA_BASE_ADDR + 0x110 + +/* DMA channel 1 registers */ +#define GPDMA_CH1_SRC DMA_BASE_ADDR + 0x120 +#define GPDMA_CH1_DEST DMA_BASE_ADDR + 0x124 +#define GPDMA_CH1_LLI DMA_BASE_ADDR + 0x128 +#define GPDMA_CH1_CTRL DMA_BASE_ADDR + 0x12C +#define GPDMA_CH1_CFG DMA_BASE_ADDR + 0x130 + +/* USB Controller */ +#define USB_INT_BASE_ADDR 0xE01FC1C0 +#define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */ + +#define USB_INT_STAT USB_INT_BASE_ADDR + 0x00 + +/* USB Device Interrupt Registers */ +#define DEV_INT_STAT USB_BASE_ADDR + 0x00 +#define DEV_INT_EN USB_BASE_ADDR + 0x04 +#define DEV_INT_CLR USB_BASE_ADDR + 0x08 +#define DEV_INT_SET USB_BASE_ADDR + 0x0C +#define DEV_INT_PRIO USB_BASE_ADDR + 0x2C + +/* USB Device Endpoint Interrupt Registers */ +#define EP_INT_STAT USB_BASE_ADDR + 0x30 +#define EP_INT_EN USB_BASE_ADDR + 0x34 +#define EP_INT_CLR USB_BASE_ADDR + 0x38 +#define EP_INT_SET USB_BASE_ADDR + 0x3C +#define EP_INT_PRIO USB_BASE_ADDR + 0x40 + +/* USB Device Endpoint Realization Registers */ +#define REALIZE_EP USB_BASE_ADDR + 0x44 +#define EP_INDEX USB_BASE_ADDR + 0x48 +#define MAXPACKET_SIZE USB_BASE_ADDR + 0x4C + +/* USB Device Command Reagisters */ +#define CMD_CODE USB_BASE_ADDR + 0x10 +#define CMD_DATA USB_BASE_ADDR + 0x14 + +/* USB Device Data Transfer Registers */ +#define RX_DATA USB_BASE_ADDR + 0x18 +#define TX_DATA USB_BASE_ADDR + 0x1C +#define RX_PLENGTH USB_BASE_ADDR + 0x20 +#define TX_PLENGTH USB_BASE_ADDR + 0x24 +#define USB_CTRL USB_BASE_ADDR + 0x28 + +/* USB Device DMA Registers */ +#define DMA_REQ_STAT USB_BASE_ADDR + 0x50 +#define DMA_REQ_CLR USB_BASE_ADDR + 0x54 +#define DMA_REQ_SET USB_BASE_ADDR + 0x58 +#define UDCA_HEAD USB_BASE_ADDR + 0x80 +#define EP_DMA_STAT USB_BASE_ADDR + 0x84 +#define EP_DMA_EN USB_BASE_ADDR + 0x88 +#define EP_DMA_DIS USB_BASE_ADDR + 0x8C +#define DMA_INT_STAT USB_BASE_ADDR + 0x90 +#define DMA_INT_EN USB_BASE_ADDR + 0x94 +#define EOT_INT_STAT USB_BASE_ADDR + 0xA0 +#define EOT_INT_CLR USB_BASE_ADDR + 0xA4 +#define EOT_INT_SET USB_BASE_ADDR + 0xA8 +#define NDD_REQ_INT_STAT USB_BASE_ADDR + 0xAC +#define NDD_REQ_INT_CLR USB_BASE_ADDR + 0xB0 +#define NDD_REQ_INT_SET USB_BASE_ADDR + 0xB4 +#define SYS_ERR_INT_STAT USB_BASE_ADDR + 0xB8 +#define SYS_ERR_INT_CLR USB_BASE_ADDR + 0xBC +#define SYS_ERR_INT_SET USB_BASE_ADDR + 0xC0 + +/* USB Host Controller */ +#define USBHC_BASE_ADDR 0xFFE0C000 +#define HC_REVISION USBHC_BASE_ADDR + 0x00 +#define HC_CONTROL USBHC_BASE_ADDR + 0x04 +#define HC_CMD_STAT USBHC_BASE_ADDR + 0x08 +#define HC_INT_STAT USBHC_BASE_ADDR + 0x0C +#define HC_INT_EN USBHC_BASE_ADDR + 0x10 +#define HC_INT_DIS USBHC_BASE_ADDR + 0x14 +#define HC_HCCA USBHC_BASE_ADDR + 0x18 +#define HC_PERIOD_CUR_ED USBHC_BASE_ADDR + 0x1C +#define HC_CTRL_HEAD_ED USBHC_BASE_ADDR + 0x20 +#define HC_CTRL_CUR_ED USBHC_BASE_ADDR + 0x24 +#define HC_BULK_HEAD_ED USBHC_BASE_ADDR + 0x28 +#define HC_BULK_CUR_ED USBHC_BASE_ADDR + 0x2C +#define HC_DONE_HEAD USBHC_BASE_ADDR + 0x30 +#define HC_FM_INTERVAL USBHC_BASE_ADDR + 0x34 +#define HC_FM_REMAINING USBHC_BASE_ADDR + 0x38 +#define HC_FM_NUMBER USBHC_BASE_ADDR + 0x3C +#define HC_PERIOD_START USBHC_BASE_ADDR + 0x40 +#define HC_LS_THRHLD USBHC_BASE_ADDR + 0x44 +#define HC_RH_DESCA USBHC_BASE_ADDR + 0x48 +#define HC_RH_DESCB USBHC_BASE_ADDR + 0x4C +#define HC_RH_STAT USBHC_BASE_ADDR + 0x50 +#define HC_RH_PORT_STAT1 USBHC_BASE_ADDR + 0x54 +#define HC_RH_PORT_STAT2 USBHC_BASE_ADDR + 0x58 + +/* USB OTG Controller */ +#define USBOTG_BASE_ADDR 0xFFE0C100 +#define OTG_INT_STAT USBOTG_BASE_ADDR + 0x00 +#define OTG_INT_EN USBOTG_BASE_ADDR + 0x04 +#define OTG_INT_SET USBOTG_BASE_ADDR + 0x08 +#define OTG_INT_CLR USBOTG_BASE_ADDR + 0x0C +#define OTG_STAT_CTRL USBOTG_BASE_ADDR + 0x10 +#define OTG_TIMER USBOTG_BASE_ADDR + 0x14 + +#define USBOTG_I2C_BASE_ADDR 0xFFE0C300 +#define OTG_I2C_RX USBOTG_I2C_BASE_ADDR + 0x00 +#define OTG_I2C_TX USBOTG_I2C_BASE_ADDR + 0x00 +#define OTG_I2C_STS USBOTG_I2C_BASE_ADDR + 0x04 +#define OTG_I2C_CTL USBOTG_I2C_BASE_ADDR + 0x08 +#define OTG_I2C_CLKHI USBOTG_I2C_BASE_ADDR + 0x0C +#define OTG_I2C_CLKLO USBOTG_I2C_BASE_ADDR + 0x10 + +#define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0 +#define OTG_CLK_CTRL USBOTG_CLK_BASE_ADDR + 0x04 +#define OTG_CLK_STAT USBOTG_CLK_BASE_ADDR + 0x08 + +/* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */ +#define MAC_BASE_ADDR 0xFFE00000 /* AHB Peripheral # 0 */ +#define MAC_MAC1 MAC_BASE_ADDR + 0x000 /* MAC config reg 1 */ +#define MAC_MAC2 MAC_BASE_ADDR + 0x004 /* MAC config reg 2 */ +#define MAC_IPGT MAC_BASE_ADDR + 0x008 /* b2b InterPacketGap reg */ +#define MAC_IPGR MAC_BASE_ADDR + 0x00C /* non b2b InterPacketGap reg */ +#define MAC_CLRT MAC_BASE_ADDR + 0x010 /* CoLlision window/ReTry reg */ +#define MAC_MAXF MAC_BASE_ADDR + 0x014 /* MAXimum Frame reg */ +#define MAC_SUPP MAC_BASE_ADDR + 0x018 /* PHY SUPPort reg */ +#define MAC_TEST MAC_BASE_ADDR + 0x01C /* TEST reg */ +#define MAC_MCFG MAC_BASE_ADDR + 0x020 /* MII Mgmt ConFiG reg */ +#define MAC_MCMD MAC_BASE_ADDR + 0x024 /* MII Mgmt CoMmanD reg */ +#define MAC_MADR MAC_BASE_ADDR + 0x028 /* MII Mgmt ADdRess reg */ +#define MAC_MWTD MAC_BASE_ADDR + 0x02C /* MII Mgmt WriTe Data reg (WO) */ +#define MAC_MRDD MAC_BASE_ADDR + 0x030 /* MII Mgmt ReaD Data reg (RO) */ +#define MAC_MIND MAC_BASE_ADDR + 0x034 /* MII Mgmt INDicators reg (RO) */ + +#define MAC_SA0 MAC_BASE_ADDR + 0x040 /* Station Address 0 reg */ +#define MAC_SA1 MAC_BASE_ADDR + 0x044 /* Station Address 1 reg */ +#define MAC_SA2 MAC_BASE_ADDR + 0x048 /* Station Address 2 reg */ + +#define MAC_COMMAND MAC_BASE_ADDR + 0x100 /* Command reg */ +#define MAC_STATUS MAC_BASE_ADDR + 0x104 /* Status reg (RO) */ +#define MAC_RXDESCRIPTOR MAC_BASE_ADDR + 0x108 /* Rx descriptor base address reg */ +#define MAC_RXSTATUS MAC_BASE_ADDR + 0x10C /* Rx status base address reg */ +#define MAC_RXDESCRIPTORNUM MAC_BASE_ADDR + 0x110 /* Rx number of descriptors reg */ +#define MAC_RXPRODUCEINDEX MAC_BASE_ADDR + 0x114 /* Rx produce index reg (RO) */ +#define MAC_RXCONSUMEINDEX MAC_BASE_ADDR + 0x118 /* Rx consume index reg */ +#define MAC_TXDESCRIPTOR MAC_BASE_ADDR + 0x11C /* Tx descriptor base address reg */ +#define MAC_TXSTATUS MAC_BASE_ADDR + 0x120 /* Tx status base address reg */ +#define MAC_TXDESCRIPTORNUM MAC_BASE_ADDR + 0x124 /* Tx number of descriptors reg */ +#define MAC_TXPRODUCEINDEX MAC_BASE_ADDR + 0x128 /* Tx produce index reg */ +#define MAC_TXCONSUMEINDEX MAC_BASE_ADDR + 0x12C /* Tx consume index reg (RO) */ + +#define MAC_TSV0 MAC_BASE_ADDR + 0x158 /* Tx status vector 0 reg (RO) */ +#define MAC_TSV1 MAC_BASE_ADDR + 0x15C /* Tx status vector 1 reg (RO) */ +#define MAC_RSV MAC_BASE_ADDR + 0x160 /* Rx status vector reg (RO) */ + +#define MAC_FLOWCONTROLCNT MAC_BASE_ADDR + 0x170 /* Flow control counter reg */ +#define MAC_FLOWCONTROLSTS MAC_BASE_ADDR + 0x174 /* Flow control status reg */ + +#define MAC_RXFILTERCTRL MAC_BASE_ADDR + 0x200 /* Rx filter ctrl reg */ +#define MAC_RXFILTERWOLSTS MAC_BASE_ADDR + 0x204 /* Rx filter WoL status reg (RO) */ +#define MAC_RXFILTERWOLCLR MAC_BASE_ADDR + 0x208 /* Rx filter WoL clear reg (WO) */ + +#define MAC_HASHFILTERL MAC_BASE_ADDR + 0x210 /* Hash filter LSBs reg */ +#define MAC_HASHFILTERH MAC_BASE_ADDR + 0x214 /* Hash filter MSBs reg */ + +#define MAC_INTSTATUS MAC_BASE_ADDR + 0xFE0 /* Interrupt status reg (RO) */ +#define MAC_INTENABLE MAC_BASE_ADDR + 0xFE4 /* Interrupt enable reg */ +#define MAC_INTCLEAR MAC_BASE_ADDR + 0xFE8 /* Interrupt clear reg (WO) */ +#define MAC_INTSET MAC_BASE_ADDR + 0xFEC /* Interrupt set reg (WO) */ + +#define MAC_POWERDOWN MAC_BASE_ADDR + 0xFF4 /* Power-down reg */ +#define MAC_MODULEID MAC_BASE_ADDR + 0xFFC /* Module ID reg (RO) */ + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +#endif diff -upNr u-boot-orig/include/flash.h u-boot/include/flash.h --- u-boot-orig/include/flash.h 2009-03-18 00:42:12.000000000 +0100 +++ u-boot/include/flash.h 2009-03-19 11:24:32.000000000 +0100 @@ -327,154 +329,153 @@ extern flash_info_t *flash_get_info(ulon #define INTEL_ID_28F256P30T 0x88198819 /* 256M = 128K x 255 + 32k x 4 */ #define INTEL_ID_28F256P30B 0x881C881C /* 256M = 128K x 255 + 32k x 4 */
-#define INTEL_ID_28F160S3 0x00D000D0 /* 16M = 512K x 32 (64kB x 32) */ -#define INTEL_ID_28F320S3 0x00D400D4 /* 32M = 512K x 64 (64kB x 64) */ +#define INTEL_ID_28F160S3 0x00D000D0 /* 16M = 512K x 32 (64kB x 32) */ +#define INTEL_ID_28F320S3 0x00D400D4 /* 32M = 512K x 64 (64kB x 64) */
/* Note that the Sharp 28F016SC is compatible with the Intel E28F016SC */ -#define SHARP_ID_28F016SCL 0xAAAAAAAA /* LH28F016SCT-L95 2Mx8, 32 64k blocks */ -#define SHARP_ID_28F016SCZ 0xA0A0A0A0 /* LH28F016SCT-Z4 2Mx8, 32 64k blocks */ -#define SHARP_ID_28F008SC 0xA6A6A6A6 /* LH28F008SCT-L12 1Mx8, 16 64k blocks */ - /* LH28F008SCR-L85 1Mx8, 16 64k blocks */ - -#define TOSH_ID_FVT160 0xC2 /* TC58FVT160 ID (16 M, top ) */ -#define TOSH_ID_FVB160 0x43 /* TC58FVT160 ID (16 M, bottom ) */ -#define PHILIPS_LPC2292 0x0401FF13 /* LPC2292 internal FLASH */ - +#define SHARP_ID_28F016SCL 0xAAAAAAAA /* LH28F016SCT-L95 2Mx8, 32 64k blocks */ +#define SHARP_ID_28F016SCZ 0xA0A0A0A0 /* LH28F016SCT-Z4 2Mx8, 32 64k blocks */ +#define SHARP_ID_28F008SC 0xA6A6A6A6 /* LH28F008SCT-L12 1Mx8, 16 64k blocks */ + /* LH28F008SCR-L85 1Mx8, 16 64k blocks */ + +#define TOSH_ID_FVT160 0xC2 /* TC58FVT160 ID (16 M, top ) */ +#define TOSH_ID_FVB160 0x43 /* TC58FVT160 ID (16 M, bottom ) */ +#define PHILIPS_LPC2292 0x0401FF13 /* LPC2292 internal FLASH */ +#define PHILIPS_LPC2468 0x0603FF35 /* LPC2468 internal FLASH */ /*----------------------------------------------------------------------- * Internal FLASH identification codes * * Be careful when adding new type! Odd numbers are "bottom boot sector" types! */
-#define FLASH_AM040 0x0001 /* AMD Am29F040B, Am29LV040B */ - /* Bright Micro BM29F040 */ - /* Fujitsu MBM29F040A */ - /* STM M29W040B */ - /* SGS Thomson M29F040B */ - /* 8 64K x 8 uniform sectors */ -#define FLASH_AM400T 0x0002 /* AMD AM29LV400 */ +#define FLASH_AM040 0x0001 /* AMD Am29F040B, Am29LV040B */ + /* Bright Micro BM29F040 */ + /* Fujitsu MBM29F040A */ + /* STM M29W040B */ + /* SGS Thomson M29F040B */ + /* 8 64K x 8 uniform sectors */ +#define FLASH_AM400T 0x0002 /* AMD AM29LV400 */ #define FLASH_AM400B 0x0003 -#define FLASH_AM800T 0x0004 /* AMD AM29LV800 */ +#define FLASH_AM800T 0x0004 /* AMD AM29LV800 */ #define FLASH_AM800B 0x0005 -#define FLASH_AM116DT 0x0026 /* AMD AM29LV116DT (2Mx8bit) */ -#define FLASH_AM116DB 0x0027 /* AMD AM29LV116DB (2Mx8bit) */ -#define FLASH_AM160T 0x0006 /* AMD AM29LV160 */ -#define FLASH_AM160LV 0x0046 /* AMD29LV160DB (2M = 2Mx8bit ) */ +#define FLASH_AM116DT 0x0026 /* AMD AM29LV116DT (2Mx8bit) */ +#define FLASH_AM116DB 0x0027 /* AMD AM29LV116DB (2Mx8bit) */ +#define FLASH_AM160T 0x0006 /* AMD AM29LV160 */ +#define FLASH_AM160LV 0x0046 /* AMD29LV160DB (2M = 2Mx8bit ) */ #define FLASH_AM160B 0x0007 -#define FLASH_AM320T 0x0008 /* AMD AM29LV320 */ +#define FLASH_AM320T 0x0008 /* AMD AM29LV320 */ #define FLASH_AM320B 0x0009
-#define FLASH_AM080 0x000A /* AMD Am29F080B */ - /* 16 64K x 8 uniform sectors */ +#define FLASH_AM080 0x000A /* AMD Am29F080B */ + /* 16 64K x 8 uniform sectors */
-#define FLASH_AMDL322T 0x0010 /* AMD AM29DL322 */ +#define FLASH_AMDL322T 0x0010 /* AMD AM29DL322 */ #define FLASH_AMDL322B 0x0011 -#define FLASH_AMDL323T 0x0012 /* AMD AM29DL323 */ +#define FLASH_AMDL323T 0x0012 /* AMD AM29DL323 */ #define FLASH_AMDL323B 0x0013 -#define FLASH_AMDL324T 0x0014 /* AMD AM29DL324 */ +#define FLASH_AMDL324T 0x0014 /* AMD AM29DL324 */ #define FLASH_AMDL324B 0x0015
#define FLASH_AMDLV033C 0x0018 #define FLASH_AMDLV065D 0x001A
-#define FLASH_AMDL640 0x0016 /* AMD AM29DL640D */ -#define FLASH_AMD016 0x0018 /* AMD AM29F016D */ -#define FLASH_AMDL640MB 0x0019 /* AMD AM29LV640MB (64M, bottom boot sect)*/ -#define FLASH_AMDL640MT 0x001A /* AMD AM29LV640MT (64M, top boot sect) */ - -#define FLASH_SST200A 0x0040 /* SST 39xF200A ID ( 2M = 128K x 16 ) */ -#define FLASH_SST400A 0x0042 /* SST 39xF400A ID ( 4M = 256K x 16 ) */ -#define FLASH_SST800A 0x0044 /* SST 39xF800A ID ( 8M = 512K x 16 ) */ -#define FLASH_SST160A 0x0046 /* SST 39xF160A ID ( 16M = 1M x 16 ) */ -#define FLASH_SST320 0x0048 /* SST 39xF160A ID ( 16M = 1M x 16 ) */ -#define FLASH_SST640 0x004A /* SST 39xF160A ID ( 16M = 1M x 16 ) */ -#define FLASH_SST020 0x0024 /* SST 39xF020 ID (256KB = 2Mbit x 8 ) */ -#define FLASH_SST040 0x000E /* SST 39xF040 ID (512KB = 4Mbit x 8 ) */ - -#define FLASH_STM800AB 0x0051 /* STM M29WF800AB ( 8M = 512K x 16 ) */ -#define FLASH_STMW320DT 0x0052 /* STM M29W320DT (32 M, top boot sector) */ -#define FLASH_STMW320DB 0x0053 /* STM M29W320DB (32 M, bottom boot sect)*/ -#define FLASH_STM320DB 0x00CB /* STM M29W320DB (4M = 64K x 64, bottom)*/ -#define FLASH_STM800DT 0x00D7 /* STM M29W800DT (1M = 64K x 16, top) */ -#define FLASH_STM800DB 0x005B /* STM M29W800DB (1M = 64K x 16, bottom)*/ - -#define FLASH_28F400_T 0x0062 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */ -#define FLASH_28F400_B 0x0063 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */ - -#define FLASH_INTEL800T 0x0074 /* INTEL 28F800B3T ( 8M = 512K x 16 ) */ -#define FLASH_INTEL800B 0x0075 /* INTEL 28F800B3B ( 8M = 512K x 16 ) */ -#define FLASH_INTEL160T 0x0076 /* INTEL 28F160B3T ( 16M = 1 M x 16 ) */ -#define FLASH_INTEL160B 0x0077 /* INTEL 28F160B3B ( 16M = 1 M x 16 ) */ -#define FLASH_INTEL320T 0x0078 /* INTEL 28F320B3T ( 32M = 2 M x 16 ) */ -#define FLASH_INTEL320B 0x0079 /* INTEL 28F320B3B ( 32M = 2 M x 16 ) */ -#define FLASH_INTEL640T 0x007A /* INTEL 28F320B3T ( 64M = 4 M x 16 ) */ -#define FLASH_INTEL640B 0x007B /* INTEL 28F320B3B ( 64M = 4 M x 16 ) */ - -#define FLASH_28F008S5 0x0080 /* Intel 28F008S5 ( 1M = 64K x 16 ) */ -#define FLASH_28F016SV 0x0081 /* Intel 28F016SV ( 16M = 512k x 32 ) */ -#define FLASH_28F800_B 0x0083 /* Intel E28F800B ( 1M = ? ) */ -#define FLASH_AM29F800B 0x0084 /* AMD Am29F800BB ( 1M = ? ) */ -#define FLASH_28F320J5 0x0085 /* Intel 28F320J5 ( 4M = 128K x 32 ) */ -#define FLASH_28F160S3 0x0086 /* Intel 28F160S3 ( 16M = 512K x 32 ) */ -#define FLASH_28F320S3 0x0088 /* Intel 28F320S3 ( 32M = 512K x 64 ) */ -#define FLASH_AM640U 0x0090 /* AMD Am29LV640U ( 64M = 4M x 16 ) */ -#define FLASH_AM033C 0x0091 /* AMD AM29LV033 ( 32M = 4M x 8 ) */ +#define FLASH_AMDL640 0x0016 /* AMD AM29DL640D */ +#define FLASH_AMD016 0x0018 /* AMD AM29F016D */ +#define FLASH_AMDL640MB 0x0019 /* AMD AM29LV640MB (64M, bottom boot sect) */ +#define FLASH_AMDL640MT 0x001A /* AMD AM29LV640MT (64M, top boot sect) */ + +#define FLASH_SST200A 0x0040 /* SST 39xF200A ID ( 2M = 128K x 16 ) */ +#define FLASH_SST400A 0x0042 /* SST 39xF400A ID ( 4M = 256K x 16 ) */ +#define FLASH_SST800A 0x0044 /* SST 39xF800A ID ( 8M = 512K x 16 ) */ +#define FLASH_SST160A 0x0046 /* SST 39xF160A ID ( 16M = 1M x 16 ) */ +#define FLASH_SST320 0x0048 /* SST 39xF160A ID ( 16M = 1M x 16 ) */ +#define FLASH_SST640 0x004A /* SST 39xF160A ID ( 16M = 1M x 16 ) */ +#define FLASH_SST020 0x0024 /* SST 39xF020 ID (256KB = 2Mbit x 8 ) */ +#define FLASH_SST040 0x000E /* SST 39xF040 ID (512KB = 4Mbit x 8 ) */ + +#define FLASH_STM800AB 0x0051 /* STM M29WF800AB ( 8M = 512K x 16 ) */ +#define FLASH_STMW320DT 0x0052 /* STM M29W320DT (32 M, top boot sector) */ +#define FLASH_STMW320DB 0x0053 /* STM M29W320DB (32 M, bottom boot sect) */ +#define FLASH_STM320DB 0x00CB /* STM M29W320DB (4M = 64K x 64, bottom) */ +#define FLASH_STM800DT 0x00D7 /* STM M29W800DT (1M = 64K x 16, top) */ +#define FLASH_STM800DB 0x005B /* STM M29W800DB (1M = 64K x 16, bottom) */ + +#define FLASH_28F400_T 0x0062 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */ +#define FLASH_28F400_B 0x0063 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */ + +#define FLASH_INTEL800T 0x0074 /* INTEL 28F800B3T ( 8M = 512K x 16 ) */ +#define FLASH_INTEL800B 0x0075 /* INTEL 28F800B3B ( 8M = 512K x 16 ) */ +#define FLASH_INTEL160T 0x0076 /* INTEL 28F160B3T ( 16M = 1 M x 16 ) */ +#define FLASH_INTEL160B 0x0077 /* INTEL 28F160B3B ( 16M = 1 M x 16 ) */ +#define FLASH_INTEL320T 0x0078 /* INTEL 28F320B3T ( 32M = 2 M x 16 ) */ +#define FLASH_INTEL320B 0x0079 /* INTEL 28F320B3B ( 32M = 2 M x 16 ) */ +#define FLASH_INTEL640T 0x007A /* INTEL 28F320B3T ( 64M = 4 M x 16 ) */ +#define FLASH_INTEL640B 0x007B /* INTEL 28F320B3B ( 64M = 4 M x 16 ) */ + +#define FLASH_28F008S5 0x0080 /* Intel 28F008S5 ( 1M = 64K x 16 ) */ +#define FLASH_28F016SV 0x0081 /* Intel 28F016SV ( 16M = 512k x 32 ) */ +#define FLASH_28F800_B 0x0083 /* Intel E28F800B ( 1M = ? ) */ +#define FLASH_AM29F800B 0x0084 /* AMD Am29F800BB ( 1M = ? ) */ +#define FLASH_28F320J5 0x0085 /* Intel 28F320J5 ( 4M = 128K x 32 ) */ +#define FLASH_28F160S3 0x0086 /* Intel 28F160S3 ( 16M = 512K x 32 ) */ +#define FLASH_28F320S3 0x0088 /* Intel 28F320S3 ( 32M = 512K x 64 ) */ +#define FLASH_AM640U 0x0090 /* AMD Am29LV640U ( 64M = 4M x 16 ) */ +#define FLASH_AM033C 0x0091 /* AMD AM29LV033 ( 32M = 4M x 8 ) */ #define FLASH_LH28F016SCT 0x0092 /* Sharp 28F016SCT ( 8 Meg Flash SIMM ) */ -#define FLASH_28F160F3B 0x0093 /* Intel 28F160F3B ( 16M = 1M x 16 ) */ +#define FLASH_28F160F3B 0x0093 /* Intel 28F160F3B ( 16M = 1M x 16 ) */ #define FLASH_AM065D 0x0093
-#define FLASH_28F640J5 0x0099 /* INTEL 28F640J5 ( 64M = 128K x 64) */ +#define FLASH_28F640J5 0x0099 /* INTEL 28F640J5 ( 64M = 128K x 64) */
-#define FLASH_28F800C3T 0x009A /* Intel 28F800C3T ( 8M = 512K x 16 ) */ -#define FLASH_28F800C3B 0x009B /* Intel 28F800C3B ( 8M = 512K x 16 ) */ -#define FLASH_28F160C3T 0x009C /* Intel 28F160C3T ( 16M = 1M x 16 ) */ -#define FLASH_28F160C3B 0x009D /* Intel 28F160C3B ( 16M = 1M x 16 ) */ -#define FLASH_28F320C3T 0x009E /* Intel 28F320C3T ( 32M = 2M x 16 ) */ -#define FLASH_28F320C3B 0x009F /* Intel 28F320C3B ( 32M = 2M x 16 ) */ -#define FLASH_28F640C3T 0x00A0 /* Intel 28F640C3T ( 64M = 4M x 16 ) */ -#define FLASH_28F640C3B 0x00A1 /* Intel 28F640C3B ( 64M = 4M x 16 ) */ -#define FLASH_AMLV320U 0x00A2 /* AMD 29LV320M ( 32M = 2M x 16 ) */ - -#define FLASH_AM033 0x00A3 /* AMD AmL033C90V1 (32M = 4M x 8) */ -#define FLASH_AM065 0x0093 /* AMD AmL065DU12RI (64M = 8M x 8) */ -#define FLASH_AT040 0x00A5 /* Amtel AT49LV040 (4M = 512K x 8) */ - -#define FLASH_AMLV640U 0x00A4 /* AMD 29LV640M ( 64M = 4M x 16 ) */ -#define FLASH_AMLV128U 0x00A6 /* AMD 29LV128M ( 128M = 8M x 16 ) */ -#define FLASH_AMLV320B 0x00A7 /* AMD 29LV320MB ( 32M = 2M x 16 ) */ -#define FLASH_AMLV320T 0x00A8 /* AMD 29LV320MT ( 32M = 2M x 16 ) */ -#define FLASH_AMLV256U 0x00AA /* AMD 29LV256M ( 256M = 16M x 16 ) */ -#define FLASH_MXLV320B 0x00AB /* MX 29LV320MB ( 32M = 2M x 16 ) */ -#define FLASH_MXLV320T 0x00AC /* MX 29LV320MT ( 32M = 2M x 16 ) */ -#define FLASH_28F256L18T 0x00B0 /* Intel 28F256L18T 256M = 128K x 255 + 32k x 4 */ -#define FLASH_AMDL163T 0x00B2 /* AMD AM29DL163T (2M x 16 ) */ +#define FLASH_28F800C3T 0x009A /* Intel 28F800C3T ( 8M = 512K x 16 ) */ +#define FLASH_28F800C3B 0x009B /* Intel 28F800C3B ( 8M = 512K x 16 ) */ +#define FLASH_28F160C3T 0x009C /* Intel 28F160C3T ( 16M = 1M x 16 ) */ +#define FLASH_28F160C3B 0x009D /* Intel 28F160C3B ( 16M = 1M x 16 ) */ +#define FLASH_28F320C3T 0x009E /* Intel 28F320C3T ( 32M = 2M x 16 ) */ +#define FLASH_28F320C3B 0x009F /* Intel 28F320C3B ( 32M = 2M x 16 ) */ +#define FLASH_28F640C3T 0x00A0 /* Intel 28F640C3T ( 64M = 4M x 16 ) */ +#define FLASH_28F640C3B 0x00A1 /* Intel 28F640C3B ( 64M = 4M x 16 ) */ +#define FLASH_AMLV320U 0x00A2 /* AMD 29LV320M ( 32M = 2M x 16 ) */ + +#define FLASH_AM033 0x00A3 /* AMD AmL033C90V1 (32M = 4M x 8) */ +#define FLASH_AM065 0x0093 /* AMD AmL065DU12RI (64M = 8M x 8) */ +#define FLASH_AT040 0x00A5 /* Amtel AT49LV040 (4M = 512K x 8) */ + +#define FLASH_AMLV640U 0x00A4 /* AMD 29LV640M ( 64M = 4M x 16 ) */ +#define FLASH_AMLV128U 0x00A6 /* AMD 29LV128M ( 128M = 8M x 16 ) */ +#define FLASH_AMLV320B 0x00A7 /* AMD 29LV320MB ( 32M = 2M x 16 ) */ +#define FLASH_AMLV320T 0x00A8 /* AMD 29LV320MT ( 32M = 2M x 16 ) */ +#define FLASH_AMLV256U 0x00AA /* AMD 29LV256M ( 256M = 16M x 16 ) */ +#define FLASH_MXLV320B 0x00AB /* MX 29LV320MB ( 32M = 2M x 16 ) */ +#define FLASH_MXLV320T 0x00AC /* MX 29LV320MT ( 32M = 2M x 16 ) */ +#define FLASH_28F256L18T 0x00B0 /* Intel 28F256L18T 256M = 128K x 255 + 32k x 4 */ +#define FLASH_AMDL163T 0x00B2 /* AMD AM29DL163T (2M x 16 ) */ #define FLASH_AMDL163B 0x00B3 -#define FLASH_28F64K3 0x00B4 /* Intel 28F64K3 ( 64M) */ -#define FLASH_28F128K3 0x00B6 /* Intel 28F128K3 ( 128M = 8M x 16 ) */ -#define FLASH_28F256K3 0x00B8 /* Intel 28F256K3 ( 256M = 16M x 16 ) */ - -#define FLASH_28F320J3A 0x00C0 /* INTEL 28F320J3A ( 32M = 128K x 32) */ -#define FLASH_28F640J3A 0x00C2 /* INTEL 28F640J3A ( 64M = 128K x 64) */ -#define FLASH_28F128J3A 0x00C4 /* INTEL 28F128J3A (128M = 128K x 128) */ -#define FLASH_28F256J3A 0x00C6 /* INTEL 28F256J3A (256M = 128K x 256) */ - -#define FLASH_FUJLV650 0x00D0 /* Fujitsu MBM 29LV650UE/651UE */ -#define FLASH_MT28S4M16LC 0x00E1 /* Micron MT28S4M16LC */ -#define FLASH_S29GL064M 0x00F0 /* Spansion S29GL064M-R6 */ -#define FLASH_S29GL128N 0x00F1 /* Spansion S29GL128N */ - -#define FLASH_UNKNOWN 0xFFFF /* unknown flash type */ +#define FLASH_28F64K3 0x00B4 /* Intel 28F64K3 ( 64M) */ +#define FLASH_28F128K3 0x00B6 /* Intel 28F128K3 ( 128M = 8M x 16 ) */ +#define FLASH_28F256K3 0x00B8 /* Intel 28F256K3 ( 256M = 16M x 16 ) */ + +#define FLASH_28F320J3A 0x00C0 /* INTEL 28F320J3A ( 32M = 128K x 32) */ +#define FLASH_28F640J3A 0x00C2 /* INTEL 28F640J3A ( 64M = 128K x 64) */ +#define FLASH_28F128J3A 0x00C4 /* INTEL 28F128J3A (128M = 128K x 128) */ +#define FLASH_28F256J3A 0x00C6 /* INTEL 28F256J3A (256M = 128K x 256) */ + +#define FLASH_FUJLV650 0x00D0 /* Fujitsu MBM 29LV650UE/651UE */ +#define FLASH_MT28S4M16LC 0x00E1 /* Micron MT28S4M16LC */ +#define FLASH_S29GL064M 0x00F0 /* Spansion S29GL064M-R6 */ +#define FLASH_S29GL128N 0x00F1 /* Spansion S29GL128N */
+#define FLASH_UNKNOWN 0xFFFF /* unknown flash type */
/* manufacturer offsets */ -#define FLASH_MAN_AMD 0x00000000 /* AMD */ -#define FLASH_MAN_FUJ 0x00010000 /* Fujitsu */ -#define FLASH_MAN_BM 0x00020000 /* Bright Microelectronics */ -#define FLASH_MAN_MX 0x00030000 /* MXIC */ +#define FLASH_MAN_AMD 0x00000000 /* AMD */ +#define FLASH_MAN_FUJ 0x00010000 /* Fujitsu */ +#define FLASH_MAN_BM 0x00020000 /* Bright Microelectronics */ +#define FLASH_MAN_MX 0x00030000 /* MXIC */ #define FLASH_MAN_STM 0x00040000 -#define FLASH_MAN_TOSH 0x00050000 /* Toshiba */ -#define FLASH_MAN_EXCEL 0x00060000 /* Excel Semiconductor */ +#define FLASH_MAN_TOSH 0x00050000 /* Toshiba */ +#define FLASH_MAN_EXCEL 0x00060000 /* Excel Semiconductor */ #define FLASH_MAN_SST 0x00100000 #define FLASH_MAN_INTEL 0x00300000 #define FLASH_MAN_MT 0x00400000 @@ -482,15 +483,14 @@ extern flash_info_t *flash_get_info(ulon #define FLASH_MAN_ATM 0x00600000 #define FLASH_MAN_CFI 0x01000000
+#define FLASH_TYPEMASK 0x0000FFFF /* extract FLASH type information */ +#define FLASH_VENDMASK 0xFFFF0000 /* extract FLASH vendor information */
-#define FLASH_TYPEMASK 0x0000FFFF /* extract FLASH type information */ -#define FLASH_VENDMASK 0xFFFF0000 /* extract FLASH vendor information */ - -#define FLASH_AMD_COMP 0x000FFFFF /* Up to this ID, FLASH is compatible */ - /* with AMD, Fujitsu and SST */ - /* (JEDEC standard commands ?) */ +#define FLASH_AMD_COMP 0x000FFFFF /* Up to this ID, FLASH is compatible */ + /* with AMD, Fujitsu and SST */ + /* (JEDEC standard commands ?) */
-#define FLASH_BTYPE 0x0001 /* mask for bottom boot sector type */ +#define FLASH_BTYPE 0x0001 /* mask for bottom boot sector type */
/*----------------------------------------------------------------------- * Timeout constants: @@ -498,8 +498,8 @@ extern flash_info_t *flash_get_info(ulon * We can't find any specifications for maximum chip erase times, * so these values are guestimates. */ -#define FLASH_ERASE_TIMEOUT 120000 /* timeout for erasing in ms */ -#define FLASH_WRITE_TIMEOUT 500 /* timeout for writes in ms */ +#define FLASH_ERASE_TIMEOUT 120000 /* timeout for erasing in ms */ +#define FLASH_WRITE_TIMEOUT 500 /* timeout for writes in ms */
#endif /* !CONFIG_SYS_NO_FLASH */
Dear Remco Poelstra,
In message 49C25F75.3080906@duran-audio.com you wrote:
Wolfgang Denk schreef:
+/* Vectored Interrupt Controller (VIC) */ +#define VIC_BASE_ADDR 0xFFFFF000 +#define VICIRQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x000)) +#define VICFIQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x004)) +#define VICRawIntr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x008)) +#define VICIntSelect (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x00C)) +#define VICIntEnable (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x010)) +#define VICIntEnClr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x014)) +#define VICSoftInt (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x018)) +#define VICSoftIntClr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x01C)) +#define VICProtection (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x020)) +#define VICSWPrioMask (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x024))
Please do not use offset lists, but define a proper C data structure instead. And never ever access device regiters through simple volatile pointers. Use proper accessor functions. Here and elsewhere.
All examples I checked use the same syntax for defining registers, so I left it in the code. If that is a problem, can you indicate an example which does The Right Thing (tm)?
See for example the structure declarations in include/asm-ppc/*immap*
I think the patch now matches the other criteria. The patch is a bit bigger, since other code did not follow the Coding Styles either. I used indent to fix my code and it fixed the other code as well.
I hope you didn't dop this in a single step. Codin style cleanup and adding new stuff must be done separately.
The second patch will follow when this patch is OK.
Regards,
Remco Poelstra
--- u-boot-orig/cpu/arm720t/cpu.c 2009-03-18 00:42:12.000000000 +0100 +++ u-boot/cpu/arm720t/cpu.c 2009-03-19 16:00:04.000000000 +0100 @@ -41,7 +41,9 @@ int cpu_init (void) * setup up stacks if necessary */ #ifdef CONFIG_USE_IRQ
- IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
- IRQ_STACK_START =
_armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE -4;@@ -63,17 +65,17 @@ int cleanup_before_linux (void) disable_interrupts ();
/* turn off I-cache */
- asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
- asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
What sort of patch is this? There is no commit message, no explanation what it is, no SoB, ... ?
Best regards,
Wolfgang Denk
This patch includes support for the LPC2468 processor from NXP.
The example board will follow when this patch is OK.
Signed-off-by: Remco Poelstra remco.poelstra+u-boot@duran-audio.com --- diff -upNr u-boot-orig/cpu/arm720t/interrupts.c u-boot-cleanup/cpu/arm720t/interrupts.c --- u-boot-orig/cpu/arm720t/interrupts.c 2009-03-18 00:42:12.000000000 +0100 +++ u-boot-cleanup/cpu/arm720t/interrupts.c 2009-03-24 11:48:50.000000000 +0100 @@ -29,7 +29,11 @@ #include <common.h> #include <clps7111.h> #include <asm/proc-armv/ptrace.h> +#if defined(CONFIG_LPC2468) +#include <asm/arch/immap.h> +#else #include <asm/hardware.h> +#endif
#ifndef CONFIG_NETARM /* we always count down the max. */ @@ -40,6 +44,11 @@ #ifdef CONFIG_LPC2292 #undef READ_TIMER #define READ_TIMER (0xFFFFFFFF - GET32(T0TC)) +#elif defined(CONFIG_LPC2468) +#undef TIMER_LOAD_VAL +#define TIMER_LOAD_VAL 0 +#undef READ_TIMER +#define READ_TIMER (0xFFFFFFFF - 0xE0004008) #endif
#else @@ -80,6 +89,14 @@ void do_irq (struct pt_regs *pt_regs) pfnct = (void (*)(void))VICVectAddr;
(*pfnct)(); +#elif defined(CONFIG_LPC2468) + void (*pfnct) (void); + vic_2468_t *vic = &(((immap_t *)CONFIG_SYS_IMMAP)->ahb.vic); + + pfnct = (void (*)(void))(&(vic->vicaddr)); + + (*pfnct) (); + #else #error do_irq() not defined for this CPU type #endif @@ -112,6 +129,9 @@ static ulong lastdec;
int interrupt_init (void) { +#if defined(CONFIG_LPC2468) + timer_2468_t *timer0=&(((immap_t *)CONFIG_SYS_IMMAP)->apb.timer0); +#endif
#if defined(CONFIG_NETARM) /* disable all interrupts */ @@ -185,6 +205,13 @@ int interrupt_init (void) PUT32(T0MCR, 0); PUT32(T0TC, 0); PUT32(T0TCR, 1); /* enable timer0 */ +#elif defined(CONFIG_LPC2468) + PUT32 (&(timer0->ir), 0); /*disable all timer0 interupts */ + PUT32 (&(timer0->tcr), 0); /*disable timer0 */ + PUT32 (&(timer0->pr), CFG_SYS_CLK_FREQ / CONFIG_SYS_HZ - 1); + PUT32 (&(timer0->mcr), 0); + PUT32 (&(timer0->tc), 0); + PUT32 (&(timer0->tcr), 1);
#else #error No interrupt_init() defined for this CPU type diff -upNr u-boot-orig/cpu/arm720t/lpc24xx/flash.c u-boot-cleanup/cpu/arm720t/lpc24xx/flash.c --- u-boot-orig/cpu/arm720t/lpc24xx/flash.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-cleanup/cpu/arm720t/lpc24xx/flash.c 2009-03-24 11:38:37.000000000 +0100 @@ -0,0 +1,233 @@ +/* + * (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +/*#include <asm/arch/hardware.h>*/ +#include <asm/arch/immap.h> +/* IAP commands use 32 bytes at the top of CPU internal sram, we + use 512 bytes below that */ +#define COPY_BUFFER_LOCATION 0x4000fde0 + +#define IAP_LOCATION 0x7ffffff1 +#define IAP_CMD_PREPARE 50 +#define IAP_CMD_COPY 51 +#define IAP_CMD_ERASE 52 +#define IAP_CMD_CHECK 53 +#define IAP_CMD_ID 54 +#define IAP_CMD_VERSION 55 +#define IAP_CMD_COMPARE 56 + +#define IAP_RET_CMD_SUCCESS 0 + +static unsigned long command[5]; +static unsigned long result[2]; + +extern void iap_entry (unsigned long *command, unsigned long *result); + +/*----------------------------------------------------------------------- + * + */ +int get_flash_sector (flash_info_t * info, ulong flash_addr) +{ + int i; + + for (i = 1; i < (info->sector_count); i++) { + if (flash_addr < (info->start[i])) + break; + } + + return (i - 1); +} + +/*----------------------------------------------------------------------- + * This function assumes that flash_addr is aligned on 512 bytes boundary + * in flash. This function also assumes that prepare have been called + * for the sector in question. + */ +int lpc24xx_copy_buffer_to_flash (flash_info_t * info, ulong flash_addr) +{ + int first_sector; + int last_sector; + + first_sector = get_flash_sector (info, flash_addr); + last_sector = get_flash_sector (info, flash_addr + 512 - 1); + + /* prepare sectors for write */ + command[0] = IAP_CMD_PREPARE; + command[1] = first_sector; + command[2] = last_sector; + iap_entry (command, result); + if (result[0] != IAP_RET_CMD_SUCCESS) { + printf ("IAP prepare failed\n"); + return ERR_PROG_ERROR; + } + + command[0] = IAP_CMD_COPY; + command[1] = flash_addr; + command[2] = COPY_BUFFER_LOCATION; + command[3] = 512; + command[4] = CFG_SYS_CLK_FREQ >> 10; + iap_entry (command, result); + if (result[0] != IAP_RET_CMD_SUCCESS) { + printf ("IAP copy failed\n"); + return 1; + } + + return 0; +} + +int lpc24xx_flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag; + int prot; + int sect; + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) + return ERR_PROTECTED; + + flag = disable_interrupts (); + + printf ("Erasing %d sectors starting at sector %2d.\n" + "This make take some time ... ", s_last - s_first + 1, s_first); + + command[0] = IAP_CMD_PREPARE; + command[1] = s_first; + command[2] = s_last; + iap_entry (command, result); + if (result[0] != IAP_RET_CMD_SUCCESS) { + printf ("IAP prepare failed\n"); + return ERR_PROTECTED; + } + + command[0] = IAP_CMD_ERASE; + command[1] = s_first; + command[2] = s_last; + command[3] = CFG_SYS_CLK_FREQ >> 10; + iap_entry (command, result); + if (result[0] != IAP_RET_CMD_SUCCESS) { + printf ("IAP erase failed\n"); + return ERR_PROTECTED; + } + + if (flag) + enable_interrupts (); + + return ERR_OK; +} + +int lpc24xx_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + int first_copy_size; + int last_copy_size; + int first_block; + int last_block; + int nbr_mid_blocks; + sys_con_2468_t *sys_con=&(((immap_t *)CONFIG_SYS_IMMAP)->apb.sys_con); + uchar memmap_value; + ulong i; + uchar *src_org; + uchar *dst_org; + int ret = ERR_OK; + + src_org = src; + dst_org = (uchar *) addr; + + first_block = addr / 512; + last_block = (addr + cnt) / 512; + nbr_mid_blocks = last_block - first_block - 1; + + first_copy_size = 512 - (addr % 512); + last_copy_size = (addr + cnt) % 512; + + debug ("\ncopy first block: (1) %lX -> %lX 0x200 bytes, " + "(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX 0x200 bytes\n", + (ulong) (first_block * 512), + (ulong) COPY_BUFFER_LOCATION, + (ulong) src, + (ulong) (COPY_BUFFER_LOCATION + 512 - first_copy_size), + first_copy_size, + (ulong) COPY_BUFFER_LOCATION, (ulong) (first_block * 512)); + + /* copy first block */ + memcpy ((void *)COPY_BUFFER_LOCATION, (void *)(first_block * 512), 512); + memcpy ((void *)(COPY_BUFFER_LOCATION + 512 - first_copy_size), + src, first_copy_size); + lpc24xx_copy_buffer_to_flash (info, first_block * 512); + src += first_copy_size; + addr += first_copy_size; + + /* copy middle blocks */ + for (i = 0; i < nbr_mid_blocks; i++) { + debug ("copy middle block: %lX -> %lX 512 bytes, " + "%lX -> %lX 512 bytes\n", + (ulong) src, + (ulong) COPY_BUFFER_LOCATION, + (ulong) COPY_BUFFER_LOCATION, (ulong) addr); + memcpy ((void *)COPY_BUFFER_LOCATION, src, 512); + lpc24xx_copy_buffer_to_flash (info, addr); + src += 512; + addr += 512; + } + + if (last_copy_size > 0) { + debug ("copy last block: (1) %lX -> %lX 0x200 bytes, " + "(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX x200 bytes\n", + (ulong) (last_block * 512), + (ulong) COPY_BUFFER_LOCATION, + (ulong) src, + (ulong) (COPY_BUFFER_LOCATION), + last_copy_size, + (ulong) COPY_BUFFER_LOCATION, (ulong) addr); + /* copy last block */ + memcpy ((void *)COPY_BUFFER_LOCATION, + (void *)(last_block * 512), 512); + memcpy ((void *)COPY_BUFFER_LOCATION, src, last_copy_size); + lpc24xx_copy_buffer_to_flash (info, addr); + } + + /* verify write */ + memmap_value = GET32(&(sys_con->memmap)); + + disable_interrupts (); + + PUT32(&(sys_con->memmap), 01); /* we must make sure that initial 64 + bytes are taken from flash when we + do the compare */ + + for (i = 0; i < cnt; i++) { + if (*dst_org != *src_org) { + printf ("Write failed. Byte %lX differs\n", i); + ret = ERR_PROG_ERROR; + break; + } + dst_org++; + src_org++; + } + + PUT32(&(sys_con->memmap), memmap_value); + enable_interrupts (); + + return ret; +} diff -upNr u-boot-orig/cpu/arm720t/lpc24xx/iap_entry.S u-boot-cleanup/cpu/arm720t/lpc24xx/iap_entry.S --- u-boot-orig/cpu/arm720t/lpc24xx/iap_entry.S 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-cleanup/cpu/arm720t/lpc24xx/iap_entry.S 2009-03-19 10:56:19.000000000 +0100 @@ -0,0 +1,7 @@ +IAP_ADDRESS: .word 0x7FFFFFF1 + +.globl iap_entry +iap_entry: + ldr r2, IAP_ADDRESS + bx r2 + mov pc, lr diff -upNr u-boot-orig/cpu/arm720t/lpc24xx/Makefile u-boot-cleanup/cpu/arm720t/lpc24xx/Makefile --- u-boot-orig/cpu/arm720t/lpc24xx/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-cleanup/cpu/arm720t/lpc24xx/Makefile 2009-03-19 10:56:53.000000000 +0100 @@ -0,0 +1,50 @@ +# +# (C) Copyright 2000-2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = flash.o +SOBJS = $(obj)iap_entry.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +# this MUST be compiled as thumb code! +$(SOBJS): + $(CC) $(AFLAGS) -march=armv4t -c -o $(SOBJS) iap_entry.S + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff -upNr u-boot-orig/cpu/arm720t/serial.c u-boot-cleanup/cpu/arm720t/serial.c --- u-boot-orig/cpu/arm720t/serial.c 2009-03-18 00:42:12.000000000 +0100 +++ u-boot-cleanup/cpu/arm720t/serial.c 2009-03-24 11:49:16.000000000 +0100 @@ -199,4 +199,94 @@ int serial_tstc (void) return (GET8(U0LSR) & 1); }
+#elif defined(CONFIG_LPC2468) +DECLARE_GLOBAL_DATA_PTR; + +#include <asm/arch/immap.h> + +void serial_setbrg (void) +{ + unsigned short divisor; + uart_2468_t *uart0=&(((immap_t *)CONFIG_SYS_IMMAP)->apb.uart0); + + switch (gd->baudrate) { + case 1200: + case 9600: + case 19200: + case 38400: + case 57600: + case 115200: + divisor = CFG_SYS_CLK_FREQ / (gd->baudrate * 16); + break; + default: + hang (); + break; + } + + /* init serial UART0 */ + PUT8 (&(uart0->iir_fcr), 0); /* Disable RX and TX FIFOs */ + PUT8 (&(uart0->lcr), 0); + PUT8 (&(uart0->ier_dlm), 0); + PUT8 (&(uart0->lcr), 0x80); /* DLAB=1 */ + PUT8 (&(uart0->rbr_thr_dll), (unsigned char)(divisor & 0x00FF)); + PUT8 (&(uart0->ier_dlm), (unsigned char)(divisor >> 8)); + PUT8 (&(uart0->lcr), 0x03); /* 8N1, DLAB=0 */ + PUT8 (&(uart0->iir_fcr), 0x7); /* Enable RX and TX FIFOs */ +} + +int serial_init (void) +{ + unsigned long pinsel0; + pin_connect_2468_t *pin_connect=&(((immap_t *)CONFIG_SYS_IMMAP)->apb.pin_connect); + + /*enable uart #0 pins in GPIO (P0.2 = TxD0, P0.3 = RxD0) */ + pinsel0 = GET32 (&(pin_connect->pinsel0)); + pinsel0 &= ~(0x000000f0); + pinsel0 |= 0x00000050; + PUT32 (&(pin_connect->pinsel0), pinsel0); + + serial_setbrg (); + + return (0); +} + + +void serial_putc (const char c) +{ + uart_2468_t *uart0=&(((immap_t *)CONFIG_SYS_IMMAP)->apb.uart0); + + if (c == '\n') { + while ((GET8 (&(uart0->lsr)) & (1 << 5)) == 0) ; /* Wait for empty U0THR */ + PUT8 (&(uart0->rbr_thr_dll), '\r'); + } + + while ((GET8 (&(uart0->lsr)) & (1 << 5)) == 0) ; /* Wait for empty U0THR */ + PUT8 (&(uart0->rbr_thr_dll), c); +} + +int serial_getc (void) +{ + uart_2468_t *uart0=&(((immap_t *)CONFIG_SYS_IMMAP)->apb.uart0); + + while ((GET8 (&(uart0->lsr)) & 1) == 0) ; + return GET8 (&(uart0->rbr_thr_dll)); +} + +void serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +/* Test if there is a byte to read */ +int serial_tstc (void) +{ + uart_2468_t *uart0=&(((immap_t *)CONFIG_SYS_IMMAP)->apb.uart0); + + return (GET8 (&(uart0->lsr)) & 1); +} + + + #endif diff -upNr u-boot-orig/cpu/arm720t/start.S u-boot-cleanup/cpu/arm720t/start.S --- u-boot-orig/cpu/arm720t/start.S 2009-03-18 00:42:12.000000000 +0100 +++ u-boot-cleanup/cpu/arm720t/start.S 2009-03-24 11:52:35.000000000 +0100 @@ -127,7 +127,7 @@ reset: bl cpu_init_crit #endif
-#ifdef CONFIG_LPC2292 +#if defined(CONFIG_LPC2292) || defined(CONFIG_LPC2468) bl lowlevel_init #endif
@@ -368,6 +368,10 @@ lock_loop: ldr r0, VPBDIV_ADR mov r1, #0x01 /* VPB clock is same as process clock */ str r1, [r0] +#elif defined(CONFIG_LPC2468) + ldr r0, =0x40008000 /*0x40000000 is internal SRAM, 0x4000FFFF is end of SRAM*/ + mov sp,r0 + sub sl,sp,#0x2000 #else #error No cpu_init_crit() defined for current CPU type #endif @@ -383,7 +387,7 @@ lock_loop: str r1, [r0] #endif
-#ifndef CONFIG_LPC2292 +#if !defined(CONFIG_LPC2292) && !defined(CONFIG_LPC2468) mov ip, lr /* * before relocating, we have to setup RAM timing @@ -601,7 +605,7 @@ reset_cpu: * on external peripherals such as watchdog timers, etc. */ #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No specific reset actions for IntegratorAP/CM720T as yet */ -#elif defined(CONFIG_LPC2292) +#elif defined(CONFIG_LPC2292) || defined(CONFIG_LPC2468) .align 5 .globl reset_cpu reset_cpu: diff -upNr u-boot-orig/include/asm-arm/arch-lpc24xx/hardware.h u-boot-cleanup/include/asm-arm/arch-lpc24xx/hardware.h --- u-boot-orig/include/asm-arm/arch-lpc24xx/hardware.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-cleanup/include/asm-arm/arch-lpc24xx/hardware.h 2009-03-24 11:54:44.000000000 +0100 @@ -0,0 +1,32 @@ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +/* + * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) + * Curt Brune curt@cucy.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#if defined(CONFIG_LPC2468) +#else +#error No hardware file defined for this configuration +#endif + +#endif /* __ASM_ARCH_HARDWARE_H */ diff -upNr u-boot-orig/include/asm-arm/arch-lpc24xx/immap.h u-boot-cleanup/include/asm-arm/arch-lpc24xx/immap.h --- u-boot-orig/include/asm-arm/arch-lpc24xx/immap.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-cleanup/include/asm-arm/arch-lpc24xx/immap.h 2009-03-24 11:54:10.000000000 +0100 @@ -0,0 +1,362 @@ +/* + * (C) Copyright 2009 Duran Audio B.V. + * + * LPC2468 Internal Memory Map + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __LPC24XX_IMMAP_H +#define __LPC24XX_IMMAP_H + +#include <asm/types.h> +#include <config.h> + +/* Macros for reading/writing registers */ +#define PUT8(reg, value) (*(volatile unsigned char*)(reg) = (value)) +#define PUT16(reg, value) (*(volatile unsigned short*)(reg) = (value)) +#define PUT32(reg, value) (*(volatile unsigned int*)(reg) = (value)) +#define GET8(reg) (*(volatile unsigned char*)(reg)) +#define GET16(reg) (*(volatile unsigned short*)(reg)) +#define GET32(reg) (*(volatile unsigned int*)(reg)) + +#define BFS32(reg,value) (*(volatile unsigned int*)(reg) |= (value)) +#define BFC32(reg, value) (*(volatile unsigned int*)(reg) &= (~value)) + +typedef struct watchdog_2468 { + u8 fixme[0x4000]; +} watchdog2468_t; + +typedef struct timer_2468 { + u32 ir; + u32 tcr; + u32 tc; + u32 pr; + u32 pc; + u32 mcr; + u32 mr0; + u32 mr1; + u32 mr2; + u32 mr3; + u32 ccr; + u32 cr0; + u32 cr1; + u32 cr2; + u32 cr3; + u32 emr; + u32 ctcr; + u8 notused[0x3fbc]; +} timer_2468_t; + +/*These two UART structs can probably be combined*/ +typedef struct uart_2468 { + u32 rbr_thr_dll; + u32 ier_dlm; + u32 iir_fcr; + u32 lcr; + u32 notused1; + u32 lsr; + u32 notused2; + u32 scr; + u32 acr; + u32 icr; + u32 fdr; + u32 notused3; + u32 ter; + u8 notused[0x3fcc]; +} uart_2468_t; + +typedef struct uart1_2468 { + u8 fixme[0x4000]; +} uart1_2468_t; + +typedef struct pwm0_2468 { + u8 fixme[0x4000]; +} pwm0_2468_t; + +typedef struct pwm1_2468 { + u8 fixme[0x4000]; +} pwm1_2468_t; + +typedef struct i2c0_2468 { + u8 fixme[0x4000]; +} i2c0_2468_t; + +typedef struct spi_2468 { + u8 fixme[0x4000]; +} spi_2468_t; + +typedef struct rtc_2468 { + u8 fixme[0x4000]; +} rtc_2468_t; + +typedef struct gpio_2468 { + u8 fixme[0x4000]; +} gpio_2468_t; + +typedef struct pin_connect_2468 { + u32 pinsel0; + u32 pinsel1; + u32 pinsel2; + u32 pinsel3; + u32 pinsel4; + u32 pinsel5; + u32 pinsel6; + u32 pinsel7; + u32 pinsel8; + u32 pinsel9; + u32 pinsel10; + u32 pinsel11; + u32 pinmode0; + u32 pinmode1; + u32 pinmode2; + u32 pinmode3; + u32 pinmode4; + u32 pinmode5; + u32 pinmode6; + u32 pinmode7; + u32 pinmode8; + u32 pinmode9; + u8 fixme[0x3fa8]; +} pin_connect_2468_t; + +typedef struct ssp1_2468 { + u8 fixme[0x4000]; +} ssp1_2468_t; + +typedef struct adc_2468 { + u8 fixme[0x4000]; +} adc_2468_t; + +typedef struct can_accept_ram_2468 { + u8 fixme[0x4000]; +} can_accept_ram_2468_t; + +typedef struct can_accept_filter_2468 { + u8 fixme[0x4000]; +} can_accept_filter_2468_t; + +typedef struct can_common_2468 { + u8 fixme[0x4000]; +} can_common_2468_t; + +typedef struct can1_2468 { + u8 fixme[0x4000]; +} can1_2468_t; + +typedef struct can2_2468 { + u8 fixme[0x4000]; +} can2_2468_t; + +typedef struct i2c1_2468 { + u8 fixme[0x4000]; +} i2c1_2468_t; + +typedef struct ssp0_2468 { + u8 fixme[0x4000]; +} ssp0_2468_t; + +typedef struct dac_2468 { + u8 fixme[0x4000]; +} dac_2468_t; + +typedef struct i2c2_2468 { + u8 fixme[0x4000]; +} i2c2_2468_t; + +typedef struct batt_ram_2468 { + u8 fixme[0x4000]; +} batt_ram_2468_t; + +typedef struct i2s_2468 { + u8 fixme[0x4000]; +} i2s_2468_t; + +typedef struct mmc_2468 { + u8 fixme[0x4000]; +} mmc_2468_t; + +typedef struct sys_con_2468 { + u8 notused1[0x40]; + u32 memmap; + u8 notused2[0xfb]; + u32 extint; + u32 extmode; + u32 extpolar; + u8 notused3[0x34]; + u32 rsid; + u32 cspr; + u32 scs; + u8 notused4[0x3e71]; +} sys_con_2468_t; + + +typedef struct mac_2468 { + u8 fixme[0x4000]; +} mac_2468_t; + +typedef struct gpdma__2468 { + u8 fixme[0x4000]; +} gpdma_2468_t; + +typedef struct ext_mem_2468 { + u8 fixme[0x4000]; +} ext_mem_2468_t; + +typedef struct usb_2468 { + u8 fixme[0x4000]; +} usb_2468_t; + +typedef struct lcd_2468 { + u8 fixme[0x4000]; +} lcd_2468_t; + +typedef struct vic_2468 { + u32 vicirqstat; + u32 vicfiqstat; + u32 vicrawintr; + u32 vicintselect; + u32 vicintenable; + u32 vicinenclr; + u32 vicsoftint; + u32 vicsoftintclr; + u32 vicprotect; + u32 vicswpriomask; + u8 notused1[0xd8]; + u32 vicvectaddr0; + u32 vicvectaddr1; + u32 vicvectaddr2; + u32 vicvectaddr3; + u32 vicvectaddr4; + u32 vicvectaddr5; + u32 vicvectaddr6; + u32 vicvectaddr7; + u32 vicvectaddr8; + u32 vicvectaddr9; + u32 vicvectaddr10; + u32 vicvectaddr11; + u32 vicvectaddr12; + u32 vicvectaddr13; + u32 vicvectaddr14; + u32 vicvectaddr15; + u32 vicvectaddr16; + u32 vicvectaddr17; + u32 vicvectaddr18; + u32 vicvectaddr19; + u32 vicvectaddr20; + u32 vicvectaddr21; + u32 vicvectaddr22; + u32 vicvectaddr23; + u32 vicvectaddr24; + u32 vicvectaddr25; + u32 vicvectaddr26; + u32 vicvectaddr27; + u32 vicvectaddr28; + u32 vicvectaddr29; + u32 vicvectaddr30; + u32 vicvectaddr31; + u8 notused2[0x7f]; + u32 vicvectprio0; + u32 vicvectprio1; + u32 vicvectprio2; + u32 vicvectprio3; + u32 vicvectprio4; + u32 vicvectprio5; + u32 vicvectprio6; + u32 vicvectprio7; + u32 vicvectprio8; + u32 vicvectprio9; + u32 vicvectprio10; + u32 vicvectprio11; + u32 vicvectprio12; + u32 vicvectprio13; + u32 vicvectprio14; + u32 vicvectprio15; + u32 vicvectprio16; + u32 vicvectprio17; + u32 vicvectprio18; + u32 vicvectprio19; + u32 vicvectprio20; + u32 vicvectprio21; + u32 vicvectprio22; + u32 vicvectprio23; + u32 vicvectprio24; + u32 vicvectprio25; + u32 vicvectprio26; + u32 vicvectprio27; + u32 vicvectprio28; + u32 vicvectprio29; + u32 vicvectprio30; + u32 vicvectprio31; + u8 notused3[0xc7f]; + u32 vicaddr; +} vic_2468_t; + +typedef struct apb_2468 { + watchdog2468_t watchdog; + timer_2468_t timer0; + timer_2468_t timer1; + uart_2468_t uart0; + uart1_2468_t uart1; + pwm0_2468_t pwm0; + pwm1_2468_t pwm1; + i2c0_2468_t i2c0; + spi_2468_t spi; + rtc_2468_t rtc; + gpio_2468_t gpio; + pin_connect_2468_t pin_connect; + ssp1_2468_t ssp1; + adc_2468_t adc; + can_accept_ram_2468_t can_accept_ram; + can_accept_filter_2468_t can_accept_filter; + can_common_2468_t can_comon; + can1_2468_t can1; + can2_2468_t can2; + u8 not_used1[0x10000]; + i2c1_2468_t i2c1; + u8 notused2[0x8000]; + ssp0_2468_t ssp0; + dac_2468_t dac; + timer_2468_t timer2; + timer_2468_t timer3; + uart_2468_t uart2; + uart_2468_t uart3; + i2c2_2468_t i2c2; + batt_ram_2468_t batt_ram; + i2s_2468_t i2s; + mmc_2468_t mmc; + u8 not_used3[0x16c000]; + sys_con_2468_t sys_con; +} apb_2468_t; + +typedef struct ahb_2468 { + mac_2468_t mac; + gpdma_2468_t gpdma; + ext_mem_2468_t ext_mem; + usb_2468_t usb; + lcd_2468_t lcd; + u8 notused1[0x1eb000]; + vic_2468_t vic; +} ahb_2468_t; + +typedef struct immap { + apb_2468_t apb; + u8 res1[0x1fc00000]; + ahb_2468_t ahb; +} immap_t; + +#endif diff -upNr u-boot-orig/include/flash.h u-boot-cleanup/include/flash.h --- u-boot-orig/include/flash.h 2009-03-18 00:42:12.000000000 +0100 +++ u-boot-cleanup/include/flash.h 2009-03-24 11:56:34.000000000 +0100 @@ -339,7 +339,7 @@ extern flash_info_t *flash_get_info(ulon #define TOSH_ID_FVT160 0xC2 /* TC58FVT160 ID (16 M, top ) */ #define TOSH_ID_FVB160 0x43 /* TC58FVT160 ID (16 M, bottom ) */ #define PHILIPS_LPC2292 0x0401FF13 /* LPC2292 internal FLASH */ - +#define PHILIPS_LPC2468 0x0603FF35 /* LPC2468 internal FLASH */ /*----------------------------------------------------------------------- * Internal FLASH identification codes *
Dear Remco Poelstra,
In message 49C8BE7A.10504@duran-audio.com you wrote:
This patch includes support for the LPC2468 processor from NXP.
The example board will follow when this patch is OK.
Such a comment does not belong into the commit message. Please mode it below the "---" line.
Signed-off-by: Remco Poelstra remco.poelstra+u-boot@duran-audio.com
diff -upNr u-boot-orig/cpu/arm720t/interrupts.c u-boot-cleanup/cpu/arm720t/interrupts.c --- u-boot-orig/cpu/arm720t/interrupts.c 2009-03-18 00:42:12.000000000 +0100 +++ u-boot-cleanup/cpu/arm720t/interrupts.c 2009-03-24 11:48:50.000000000 +0100 @@ -29,7 +29,11 @@ #include <common.h> #include <clps7111.h> #include <asm/proc-armv/ptrace.h> +#if defined(CONFIG_LPC2468) +#include <asm/arch/immap.h> +#else #include <asm/hardware.h> +#endif
Is there no way we can do without such a #ifdef here?
#ifndef CONFIG_NETARM /* we always count down the max. */ @@ -40,6 +44,11 @@ #ifdef CONFIG_LPC2292 #undef READ_TIMER #define READ_TIMER (0xFFFFFFFF - GET32(T0TC)) +#elif defined(CONFIG_LPC2468) +#undef TIMER_LOAD_VAL +#define TIMER_LOAD_VAL 0 +#undef READ_TIMER +#define READ_TIMER (0xFFFFFFFF - 0xE0004008)
NAK. When you have to #unifdef existing variable definitions, then ther eis something fundamentally wrong. Please fix this problem at the cause, i. e. where the wroing values are defined.
#endif
#else @@ -80,6 +89,14 @@ void do_irq (struct pt_regs *pt_regs) pfnct = (void (*)(void))VICVectAddr;
(*pfnct)();+#elif defined(CONFIG_LPC2468)
- void (*pfnct) (void);
- vic_2468_t *vic = &(((immap_t *)CONFIG_SYS_IMMAP)->ahb.vic);
- pfnct = (void (*)(void))(&(vic->vicaddr));
- (*pfnct) ();
Is there no way to combine this code with the one for the LPC2292? It doesn't look that different to me...
#else #error do_irq() not defined for this CPU type #endif @@ -112,6 +129,9 @@ static ulong lastdec;
int interrupt_init (void) { +#if defined(CONFIG_LPC2468)
- timer_2468_t *timer0=&(((immap_t *)CONFIG_SYS_IMMAP)->apb.timer0);
+#endif
#if defined(CONFIG_NETARM) /* disable all interrupts */ @@ -185,6 +205,13 @@ int interrupt_init (void) PUT32(T0MCR, 0); PUT32(T0TC, 0); PUT32(T0TCR, 1); /* enable timer0 */ +#elif defined(CONFIG_LPC2468)
- PUT32 (&(timer0->ir), 0); /*disable all timer0 interupts */
- PUT32 (&(timer0->tcr), 0); /*disable timer0 */
- PUT32 (&(timer0->pr), CFG_SYS_CLK_FREQ / CONFIG_SYS_HZ - 1);
- PUT32 (&(timer0->mcr), 0);
- PUT32 (&(timer0->tc), 0);
- PUT32 (&(timer0->tcr), 1);
Again: Is there no way to combine this code with the one for the LPC2292? It doesn't look that different to me...
...
--- u-boot-orig/cpu/arm720t/lpc24xx/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-cleanup/cpu/arm720t/lpc24xx/Makefile 2009-03-19 10:56:53.000000000 +0100
...
+$(SOBJS):
- $(CC) $(AFLAGS) -march=armv4t -c -o $(SOBJS) iap_entry.S
Such compile options hsould probably be set globally, not just for this single source file?
...
+int serial_tstc (void) +{
- uart_2468_t *uart0=&(((immap_t *)CONFIG_SYS_IMMAP)->apb.uart0);
- return (GET8 (&(uart0->lsr)) & 1);
+}
- #endif
Get rid of all these empty lines, please.
diff -upNr u-boot-orig/cpu/arm720t/start.S u-boot-cleanup/cpu/arm720t/start.S --- u-boot-orig/cpu/arm720t/start.S 2009-03-18 00:42:12.000000000 +0100 +++ u-boot-cleanup/cpu/arm720t/start.S 2009-03-24 11:52:35.000000000 +0100 @@ -127,7 +127,7 @@ reset: bl cpu_init_crit #endif
-#ifdef CONFIG_LPC2292 +#if defined(CONFIG_LPC2292) || defined(CONFIG_LPC2468)
Is there no way to combine this code with the one for the LPC2292?
bl lowlevel_init #endif
@@ -368,6 +368,10 @@ lock_loop: ldr r0, VPBDIV_ADR mov r1, #0x01 /* VPB clock is same as process clock */ str r1, [r0] +#elif defined(CONFIG_LPC2468)
- ldr r0, =0x40008000 /*0x40000000 is internal SRAM, 0x4000FFFF is end of SRAM*/
Line too long.
- mov sp,r0
- sub sl,sp,#0x2000
Indentation by TAB, please.
#else #error No cpu_init_crit() defined for current CPU type #endif @@ -383,7 +387,7 @@ lock_loop: str r1, [r0] #endif
-#ifndef CONFIG_LPC2292 +#if !defined(CONFIG_LPC2292) && !defined(CONFIG_LPC2468)
Is there no way to combine this code with the one for the LPC2292?
mov ip, lr /* * before relocating, we have to setup RAM timing @@ -601,7 +605,7 @@ reset_cpu:
- on external peripherals such as watchdog timers, etc. */
#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No specific reset actions for IntegratorAP/CM720T as yet */ -#elif defined(CONFIG_LPC2292) +#elif defined(CONFIG_LPC2292) || defined(CONFIG_LPC2468)
Is there no way to combine this code with the one for the LPC2292?
.align 5 .globl reset_cpu reset_cpu: diff -upNr u-boot-orig/include/asm-arm/arch-lpc24xx/hardware.h u-boot-cleanup/include/asm-arm/arch-lpc24xx/hardware.h --- u-boot-orig/include/asm-arm/arch-lpc24xx/hardware.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-cleanup/include/asm-arm/arch-lpc24xx/hardware.h 2009-03-24 11:54:44.000000000 +0100 @@ -0,0 +1,32 @@ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H
+/*
- Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
- Curt Brune curt@cucy.com
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#if defined(CONFIG_LPC2468) +#else +#error No hardware file defined for this configuration +#endif
+#endif /* __ASM_ARCH_HARDWARE_H */
Ummm... What exactly is this file needed for?
diff -upNr u-boot-orig/include/asm-arm/arch-lpc24xx/immap.h u-boot-cleanup/include/asm-arm/arch-lpc24xx/immap.h --- u-boot-orig/include/asm-arm/arch-lpc24xx/immap.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-cleanup/include/asm-arm/arch-lpc24xx/immap.h 2009-03-24 11:54:10.000000000 +0100 @@ -0,0 +1,362 @@ +/*
- (C) Copyright 2009 Duran Audio B.V.
- LPC2468 Internal Memory Map
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#ifndef __LPC24XX_IMMAP_H +#define __LPC24XX_IMMAP_H
+#include <asm/types.h> +#include <config.h>
+/* Macros for reading/writing registers */ +#define PUT8(reg, value) (*(volatile unsigned char*)(reg) = (value)) +#define PUT16(reg, value) (*(volatile unsigned short*)(reg) = (value)) +#define PUT32(reg, value) (*(volatile unsigned int*)(reg) = (value)) +#define GET8(reg) (*(volatile unsigned char*)(reg)) +#define GET16(reg) (*(volatile unsigned short*)(reg)) +#define GET32(reg) (*(volatile unsigned int*)(reg))
Do you clain these are proper accessor functions for your processor?
+#define BFS32(reg,value) (*(volatile unsigned int*)(reg) |= (value)) +#define BFC32(reg, value) (*(volatile unsigned int*)(reg) &= (~value))
+typedef struct watchdog_2468 {
- u8 fixme[0x4000];
+} watchdog2468_t;
Indentation by TAB, please - here and everywhere else.
diff -upNr u-boot-orig/include/flash.h u-boot-cleanup/include/flash.h --- u-boot-orig/include/flash.h 2009-03-18 00:42:12.000000000 +0100 +++ u-boot-cleanup/include/flash.h 2009-03-24 11:56:34.000000000 +0100 @@ -339,7 +339,7 @@ extern flash_info_t *flash_get_info(ulon #define TOSH_ID_FVT160 0xC2 /* TC58FVT160 ID (16 M, top ) */ #define TOSH_ID_FVB160 0x43 /* TC58FVT160 ID (16 M, bottom ) */ #define PHILIPS_LPC2292 0x0401FF13 /* LPC2292 internal FLASH */
+#define PHILIPS_LPC2468 0x0603FF35 /* LPC2468 internal FLASH */ /*-----------------------------------------------------------------------
- Internal FLASH identification codes
Please keep the empty line here.
Best regards,
Wolfgang Denk
Wolfgang Denk schreef:
Dear Remco Poelstra,
In message 49C8BE7A.10504@duran-audio.com you wrote:
This patch includes support for the LPC2468 processor from NXP.
The example board will follow when this patch is OK.
Such a comment does not belong into the commit message. Please mode it below the "---" line.
I see, I thought nothing else was allowed below the "---"
Signed-off-by: Remco Poelstra remco.poelstra+u-boot@duran-audio.com
diff -upNr u-boot-orig/cpu/arm720t/interrupts.c u-boot-cleanup/cpu/arm720t/interrupts.c --- u-boot-orig/cpu/arm720t/interrupts.c 2009-03-18 00:42:12.000000000 +0100 +++ u-boot-cleanup/cpu/arm720t/interrupts.c 2009-03-24 11:48:50.000000000 +0100 @@ -29,7 +29,11 @@ #include <common.h> #include <clps7111.h> #include <asm/proc-armv/ptrace.h> +#if defined(CONFIG_LPC2468) +#include <asm/arch/immap.h> +#else #include <asm/hardware.h> +#endif
Is there no way we can do without such a #ifdef here?
The problem is that start.S needs hardware.h, but the code in immap.h should not be included in start.S, so I can not merge hardware.h and immap.h
#ifndef CONFIG_NETARM /* we always count down the max. */ @@ -40,6 +44,11 @@ #ifdef CONFIG_LPC2292 #undef READ_TIMER #define READ_TIMER (0xFFFFFFFF - GET32(T0TC)) +#elif defined(CONFIG_LPC2468) +#undef TIMER_LOAD_VAL +#define TIMER_LOAD_VAL 0 +#undef READ_TIMER +#define READ_TIMER (0xFFFFFFFF - 0xE0004008)
NAK. When you have to #unifdef existing variable definitions, then ther eis something fundamentally wrong. Please fix this problem at the cause, i. e. where the wroing values are defined.
I'll look into this.
#endif
#else @@ -80,6 +89,14 @@ void do_irq (struct pt_regs *pt_regs) pfnct = (void (*)(void))VICVectAddr;
(*pfnct)();+#elif defined(CONFIG_LPC2468)
- void (*pfnct) (void);
- vic_2468_t *vic = &(((immap_t *)CONFIG_SYS_IMMAP)->ahb.vic);
- pfnct = (void (*)(void))(&(vic->vicaddr));
- (*pfnct) ();
Is there no way to combine this code with the one for the LPC2292? It doesn't look that different to me...
Interesting point. I was wondering the same. The problem lies in the fact that you want this patch to use C data structures, while the LPC2292 code uses offset lists. I can not convert the LPC2292 code to C structures, since a) I can not test the code b) I get paid to design hardware, not getting my ports published. I'm doing this to give something back to the community, since I really appreciate the work done by other OSS developers. But I can not spend time on converting complete other architectures. I leave that to other (the original LPC2292?) developers.
--- u-boot-orig/cpu/arm720t/lpc24xx/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-cleanup/cpu/arm720t/lpc24xx/Makefile 2009-03-19 10:56:53.000000000 +0100
...
+$(SOBJS):
- $(CC) $(AFLAGS) -march=armv4t -c -o $(SOBJS) iap_entry.S
Such compile options hsould probably be set globally, not just for this single source file?
No, thumb code is less efficient in terms of performance, but this single file needs thumb code. See LPC2292.
diff -upNr u-boot-orig/cpu/arm720t/start.S u-boot-cleanup/cpu/arm720t/start.S --- u-boot-orig/cpu/arm720t/start.S 2009-03-18 00:42:12.000000000 +0100 +++ u-boot-cleanup/cpu/arm720t/start.S 2009-03-24 11:52:35.000000000 +0100 @@ -127,7 +127,7 @@ reset: bl cpu_init_crit #endif
-#ifdef CONFIG_LPC2292 +#if defined(CONFIG_LPC2292) || defined(CONFIG_LPC2468)
Is there no way to combine this code with the one for the LPC2292?
I'm sorry, it is combined in this case, no?
#else #error No cpu_init_crit() defined for current CPU type #endif @@ -383,7 +387,7 @@ lock_loop: str r1, [r0] #endif
-#ifndef CONFIG_LPC2292 +#if !defined(CONFIG_LPC2292) && !defined(CONFIG_LPC2468)
Is there no way to combine this code with the one for the LPC2292?
Same here.
mov ip, lr /* * before relocating, we have to setup RAM timing @@ -601,7 +605,7 @@ reset_cpu:
- on external peripherals such as watchdog timers, etc. */
#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No specific reset actions for IntegratorAP/CM720T as yet */ -#elif defined(CONFIG_LPC2292) +#elif defined(CONFIG_LPC2292) || defined(CONFIG_LPC2468)
Is there no way to combine this code with the one for the LPC2292?
Same here.
.align 5 .globl reset_cpu reset_cpu: diff -upNr u-boot-orig/include/asm-arm/arch-lpc24xx/hardware.h u-boot-cleanup/include/asm-arm/arch-lpc24xx/hardware.h --- u-boot-orig/include/asm-arm/arch-lpc24xx/hardware.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-cleanup/include/asm-arm/arch-lpc24xx/hardware.h 2009-03-24 11:54:44.000000000 +0100 @@ -0,0 +1,32 @@ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H
+/*
- Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
- Curt Brune curt@cucy.com
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#if defined(CONFIG_LPC2468) +#else +#error No hardware file defined for this configuration +#endif
+#endif /* __ASM_ARCH_HARDWARE_H */
Ummm... What exactly is this file needed for?
I don't need it, but start.S wants to include it. See my comment about the #ifdef's. Other architectures left it empty too, so it seemed the best option to me.
+/* Macros for reading/writing registers */ +#define PUT8(reg, value) (*(volatile unsigned char*)(reg) = (value)) +#define PUT16(reg, value) (*(volatile unsigned short*)(reg) = (value)) +#define PUT32(reg, value) (*(volatile unsigned int*)(reg) = (value)) +#define GET8(reg) (*(volatile unsigned char*)(reg)) +#define GET16(reg) (*(volatile unsigned short*)(reg)) +#define GET32(reg) (*(volatile unsigned int*)(reg))
Do you clain these are proper accessor functions for your processor?
Yes I do. They are straight from the LPC2292 code, so once they were considered OK. I checked out the the write{s,l,b} functions in asm/io.h, but although they look similar, for some reason they simply don't work. Given the similarities between the write{s,l,b} and the PUT* functions, what is the problem with those? Furthermore, the ARM architecture doesn't use any kind of special instructions for accessing registers, everything is memory mapped.
I do understand that you want the best code for U-boot, but I do not entirely agree on all points. Certainly when I look at the code already in place in U-boot. Please tell me what you really want to see changed/whether you expect me to convert the LPC2292 code. Depending on the amount of work left I'll reconsider submitting a patch.
Kind regards,
Remco Poelstra
Dear Remco Poelstra,
In message 49C9EB4D.5050503@duran-audio.com you wrote:
--- u-boot-orig/cpu/arm720t/interrupts.c 2009-03-18 00:42:12.000000000 +0100 +++ u-boot-cleanup/cpu/arm720t/interrupts.c 2009-03-24 11:48:50.000000000 +0100 @@ -29,7 +29,11 @@ #include <common.h> #include <clps7111.h> #include <asm/proc-armv/ptrace.h> +#if defined(CONFIG_LPC2468) +#include <asm/arch/immap.h> +#else #include <asm/hardware.h> +#endif
Is there no way we can do without such a #ifdef here?
The problem is that start.S needs hardware.h, but the code in immap.h should not be included in start.S, so I can not merge hardware.h and immap.h
Why not? I'm not aware of such a restriction?
diff -upNr u-boot-orig/cpu/arm720t/start.S u-boot-cleanup/cpu/arm720t/start.S --- u-boot-orig/cpu/arm720t/start.S 2009-03-18 00:42:12.000000000 +0100 +++ u-boot-cleanup/cpu/arm720t/start.S 2009-03-24 11:52:35.000000000 +0100 @@ -127,7 +127,7 @@ reset: bl cpu_init_crit #endif
-#ifdef CONFIG_LPC2292 +#if defined(CONFIG_LPC2292) || defined(CONFIG_LPC2468)
Is there no way to combine this code with the one for the LPC2292?
I'm sorry, it is combined in this case, no?
I would like to avoid the ever growing list of
#if defined(this) || defined(that) || defined(...) || ...
Maybe we can have a common #define that covers the common case?
diff -upNr u-boot-orig/include/asm-arm/arch-lpc24xx/hardware.h u-boot-cleanup/include/asm-arm/arch-lpc24xx/hardware.h --- u-boot-orig/include/asm-arm/arch-lpc24xx/hardware.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-cleanup/include/asm-arm/arch-lpc24xx/hardware.h 2009-03-24 11:54:44.000000000 +0100 @@ -0,0 +1,32 @@ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H
+/*
...
- */
+#if defined(CONFIG_LPC2468) +#else +#error No hardware file defined for this configuration +#endif
+#endif /* __ASM_ARCH_HARDWARE_H */
Ummm... What exactly is this file needed for?
I don't need it, but start.S wants to include it. See my comment about the #ifdef's. Other architectures left it empty too, so it seemed the best option to me.
Hm... that doesn't really make sense to me. Also, the error checking in this file makes little sense to me.
+/* Macros for reading/writing registers */ +#define PUT8(reg, value) (*(volatile unsigned char*)(reg) = (value)) +#define PUT16(reg, value) (*(volatile unsigned short*)(reg) = (value)) +#define PUT32(reg, value) (*(volatile unsigned int*)(reg) = (value)) +#define GET8(reg) (*(volatile unsigned char*)(reg)) +#define GET16(reg) (*(volatile unsigned short*)(reg)) +#define GET32(reg) (*(volatile unsigned int*)(reg))
Do you clain these are proper accessor functions for your processor?
Yes I do. They are straight from the LPC2292 code, so once they were considered OK. I checked out the the write{s,l,b} functions in asm/io.h, but although they look similar, for some reason they simply don't work. Given the similarities between the write{s,l,b} and the PUT* functions, what is the problem with those? Furthermore, the ARM architecture doesn't use any kind of special instructions for accessing registers, everything is memory mapped.
I'm not an expert for this processor, but I wonder it there might be some form of sync instruction (or memory barrier or similar) needed?
Best regards,
Wolfgang Denk
Wolfgang Denk schreef:
Dear Remco Poelstra,
Is there no way we can do without such a #ifdef here?
The problem is that start.S needs hardware.h, but the code in immap.h should not be included in start.S, so I can not merge hardware.h and immap.h
Why not? I'm not aware of such a restriction?
I'm not an expert in assembly, but at first I had immap.h included in start.S and it complained about invalid instructions, so if I combine hardware.h and immap.h, then there must be some way of making sure that the assembler ignores the C code in immap.h. Do you know of any such thing?
I would like to avoid the ever growing list of
#if defined(this) || defined(that) || defined(...) || ...
Maybe we can have a common #define that covers the common case?
I could add something like #if defined(CONFIG_LPC2922) || defined(CONFIG_LPC2468) #define (CONFIG_LPC2000) #endif
in a general place and then use CONFIG_LPC2000 at the common places.
The problem I then have is: What would be the best place to put such define? Preferably it is automatically included also for the LPC2292 code. If that's not possible, it can be defined in the board config, but I think that leads to confusion. What's your opinion?
Ummm... What exactly is this file needed for?
I don't need it, but start.S wants to include it. See my comment about the #ifdef's. Other architectures left it empty too, so it seemed the best option to me.
Hm... that doesn't really make sense to me. Also, the error checking in this file makes little sense to me.
I can remove the file, but than I need to put an #ifdef construct in start.S to only exclude it in the lpc2468 case. The file is used by the other ARM ports. I can also simply empty it, but in this way it is more similar to the other ports. What would you like?
I'm not an expert for this processor, but I wonder it there might be some form of sync instruction (or memory barrier or similar) needed?
No, none at all. There is only a single linear memory region for the processor and a write to a location has immediate effect, whether it be a register or just RAM.
I suppose leaving parts of the 2468 and 2292 code separated is OK for the time being (considering offset lists and data structures), in the hope someone will upgrade the 2292 code?
I'm willing to look into the PUT32() vs. writel() problem in about half a year or so. That will at least cleanup part of the code.
Kind regards,
Remco Poelstra
On 11:06 Wed 25 Mar , Remco Poelstra wrote:
Wolfgang Denk schreef:
Dear Remco Poelstra,
Is there no way we can do without such a #ifdef here?
The problem is that start.S needs hardware.h, but the code in immap.h should not be included in start.S, so I can not merge hardware.h and immap.h
Why not? I'm not aware of such a restriction?
I'm not an expert in assembly, but at first I had immap.h included in start.S and it complained about invalid instructions, so if I combine hardware.h and immap.h, then there must be some way of making sure that the assembler ignores the C code in immap.h. Do you know of any such thing?
immap.h?
I would like to avoid the ever growing list of
#if defined(this) || defined(that) || defined(...) || ...
Maybe we can have a common #define that covers the common case?
I could add something like #if defined(CONFIG_LPC2922) || defined(CONFIG_LPC2468) #define (CONFIG_LPC2000) #endif
in a general place and then use CONFIG_LPC2000 at the common places.
The problem I then have is: What would be the best place to put such define? Preferably it is automatically included also for the LPC2292 code. If that's not possible, it can be defined in the board config, but I think that leads to confusion. What's your opinion?
Maybe in include/asm-arm/config.h
Ummm... What exactly is this file needed for?
I don't need it, but start.S wants to include it. See my comment about the #ifdef's. Other architectures left it empty too, so it seemed the best option to me.
Hm... that doesn't really make sense to me. Also, the error checking in this file makes little sense to me.
I can remove the file, but than I need to put an #ifdef construct in start.S to only exclude it in the lpc2468 case. The file is used by the other ARM ports. I can also simply empty it, but in this way it is more similar to the other ports. What would you like?
no please do not I'll prefer to separate arch file
Best Regards; J.
Jean-Christophe PLAGNIOL-VILLARD schreef:
I'm not an expert in assembly, but at first I had immap.h included in start.S and it complained about invalid instructions, so if I combine hardware.h and immap.h, then there must be some way of making sure that the assembler ignores the C code in immap.h. Do you know of any such thing?
immap.h?
immap.h is like hardware.h for the LPC2292, but it contains C structures to define the registers instead of #defines. I based it on the ppc code. See the patch for an explanation.
I can remove the file, but than I need to put an #ifdef construct in start.S to only exclude it in the lpc2468 case. The file is used by the other ARM ports. I can also simply empty it, but in this way it is more similar to the other ports. What would you like?
no please do not I'll prefer to separate arch file
I do not understand what you mean with the last part of your comment.
Kind regards,
Remco Poelstra
This patch includes support for the LPC2468 processor from NXP.
Signed-off-by: Remco Poelstra remco.poelstra+u-boot@duran-audio.com --- A working board example will be submitted when this patch is found to be OK. This patch is against latest git. The previous problem with PUTx vs. writex is solved.
From 75361079ed78fb40c2840b3bd74687153e486620 Mon Sep 17 00:00:00 2001 From: Remco Poelstra remco.poelstra+u-boot@duran-audio.com Date: Fri, 24 Apr 2009 12:18:21 +0200 Subject: [PATCH] Support for LPC2468 processor from NXP
--- Makefile | 3 + cpu/arm720t/cpu.c | 2 +- cpu/arm720t/interrupts.c | 37 +++- cpu/arm720t/lpc24xx/Makefile | 50 +++++ cpu/arm720t/lpc24xx/flash.c | 233 ++++++++++++++++++++ cpu/arm720t/lpc24xx/iap_entry.S | 7 + cpu/arm720t/start.S | 11 +- drivers/serial/Makefile | 1 + drivers/serial/serial_lpc2468.c | 119 +++++++++++ include/asm-arm/arch-lpc24xx/hardware.h | 32 +++ include/asm-arm/arch-lpc24xx/immap.h | 351 +++++++++++++++++++++++++++++++ include/asm-arm/config.h | 4 + include/flash.h | 1 + 13 files changed, 842 insertions(+), 9 deletions(-) create mode 100644 cpu/arm720t/lpc24xx/Makefile create mode 100644 cpu/arm720t/lpc24xx/flash.c create mode 100644 cpu/arm720t/lpc24xx/iap_entry.S create mode 100644 drivers/serial/serial_lpc2468.c create mode 100644 include/asm-arm/arch-lpc24xx/hardware.h create mode 100644 include/asm-arm/arch-lpc24xx/immap.h
diff --git a/Makefile b/Makefile index e91c051..fb23ee6 100644 --- a/Makefile +++ b/Makefile @@ -2940,6 +2940,9 @@ B2_config : unconfig ## ARM720T Systems #########################################################################
+LPC2468_config: unconfig + @$(MKCONFIG) $(@:_config=) arm arm720t LPC2468 NULL lpc24xx + armadillo_config: unconfig @$(MKCONFIG) $(@:_config=) arm arm720t armadillo
diff --git a/cpu/arm720t/cpu.c b/cpu/arm720t/cpu.c index 6c40903..b3a2853 100644 --- a/cpu/arm720t/cpu.c +++ b/cpu/arm720t/cpu.c @@ -75,7 +75,7 @@ int cleanup_before_linux (void) /* go to high speed */ IO_SYSCON3 = (IO_SYSCON3 & ~CLKCTL) | CLKCTL_73; #endif -#elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) || defined(CONFIG_LPC2292) +#elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) || defined(CONFIG_LPC2000) disable_interrupts (); /* Nothing more needed */ #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) diff --git a/cpu/arm720t/interrupts.c b/cpu/arm720t/interrupts.c index 39ed345..d7aec27 100644 --- a/cpu/arm720t/interrupts.c +++ b/cpu/arm720t/interrupts.c @@ -29,17 +29,26 @@ #include <common.h> #include <clps7111.h> #include <asm/proc-armv/ptrace.h> +#include <asm/io.h> +#if defined(CONFIG_LPC2468) +#include <asm/arch/immap.h> +#else #include <asm/hardware.h> +#endif
#ifndef CONFIG_NETARM + +#if defined(CONFIG_LPC2292) +#define TIMER_LOAD_VAL 0xffff +#define READ_TIMER (0xFFFFFFFF - GET32(T0TC)) +#elif defined(CONFIG_LPC2468) +#define TIMER_LOAD_VAL 0 +#define READ_TIMER (0xFFFFFFFF - 0xE0004008) +#else /* we always count down the max. */ #define TIMER_LOAD_VAL 0xffff /* macro to read the 16 bit timer */ #define READ_TIMER (IO_TC1D & 0xffff) - -#ifdef CONFIG_LPC2292 -#undef READ_TIMER -#define READ_TIMER (0xFFFFFFFF - GET32(T0TC)) #endif
#else @@ -80,6 +89,14 @@ void do_irq (struct pt_regs *pt_regs) pfnct = (void (*)(void))VICVectAddr;
(*pfnct)(); +#elif defined(CONFIG_LPC2468) + void (*pfnct) (void); + vic_2468_t *vic = &(((immap_t *)CONFIG_SYS_IMMAP)->ahb.vic); + + pfnct = (void (*)(void))(&(vic->vicaddr)); + + (*pfnct) (); + #else #error do_irq() not defined for this CPU type #endif @@ -112,6 +129,9 @@ static ulong lastdec;
int interrupt_init (void) { +#if defined(CONFIG_LPC2468) + timer_2468_t *timer0=&(((immap_t *)CONFIG_SYS_IMMAP)->apb.timer0); +#endif
#if defined(CONFIG_NETARM) /* disable all interrupts */ @@ -185,6 +205,13 @@ int interrupt_init (void) PUT32(T0MCR, 0); PUT32(T0TC, 0); PUT32(T0TCR, 1); /* enable timer0 */ +#elif defined(CONFIG_LPC2468) + writel (0, &(timer0->ir)); /*disable all timer0 interupts */ + writel (0, &(timer0->tcr)); /*disable timer0 */ + writel (CFG_SYS_CLK_FREQ / CONFIG_SYS_HZ - 1, &(timer0->pr)); + writel (0, &(timer0->mcr)); + writel (0, &(timer0->tc)); + writel (1, &(timer0->tcr));
#else #error No interrupt_init() defined for this CPU type @@ -201,7 +228,7 @@ int interrupt_init (void) */
-#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO) || defined(CONFIG_LPC2292) +#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO) || defined(CONFIG_LPC2000)
void reset_timer (void) { diff --git a/cpu/arm720t/lpc24xx/Makefile b/cpu/arm720t/lpc24xx/Makefile new file mode 100644 index 0000000..f091502 --- /dev/null +++ b/cpu/arm720t/lpc24xx/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2000-2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = flash.o +SOBJS = $(obj)iap_entry.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +# this MUST be compiled as thumb code! +$(SOBJS): + $(CC) $(AFLAGS) -march=armv4t -c -o $(SOBJS) iap_entry.S + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm720t/lpc24xx/flash.c b/cpu/arm720t/lpc24xx/flash.c new file mode 100644 index 0000000..46a1a56 --- /dev/null +++ b/cpu/arm720t/lpc24xx/flash.c @@ -0,0 +1,233 @@ +/* + * (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/immap.h> +/* IAP commands use 32 bytes at the top of CPU internal sram, we + use 512 bytes below that */ +#define COPY_BUFFER_LOCATION 0x4000fde0 + +#define IAP_LOCATION 0x7ffffff1 +#define IAP_CMD_PREPARE 50 +#define IAP_CMD_COPY 51 +#define IAP_CMD_ERASE 52 +#define IAP_CMD_CHECK 53 +#define IAP_CMD_ID 54 +#define IAP_CMD_VERSION 55 +#define IAP_CMD_COMPARE 56 + +#define IAP_RET_CMD_SUCCESS 0 + +static unsigned long command[5]; +static unsigned long result[2]; + +extern void iap_entry (unsigned long *command, unsigned long *result); + +/*----------------------------------------------------------------------- + * + */ +int get_flash_sector (flash_info_t * info, ulong flash_addr) +{ + int i; + + for (i = 1; i < (info->sector_count); i++) { + if (flash_addr < (info->start[i])) + break; + } + + return (i - 1); +} + +/*----------------------------------------------------------------------- + * This function assumes that flash_addr is aligned on 512 bytes boundary + * in flash. This function also assumes that prepare have been called + * for the sector in question. + */ +int lpc24xx_copy_buffer_to_flash (flash_info_t * info, ulong flash_addr) +{ + int first_sector; + int last_sector; + + first_sector = get_flash_sector (info, flash_addr); + last_sector = get_flash_sector (info, flash_addr + 512 - 1); + + /* prepare sectors for write */ + command[0] = IAP_CMD_PREPARE; + command[1] = first_sector; + command[2] = last_sector; + iap_entry (command, result); + if (result[0] != IAP_RET_CMD_SUCCESS) { + printf ("IAP prepare failed\n"); + return ERR_PROG_ERROR; + } + + command[0] = IAP_CMD_COPY; + command[1] = flash_addr; + command[2] = COPY_BUFFER_LOCATION; + command[3] = 512; + command[4] = CFG_SYS_CLK_FREQ >> 10; + iap_entry (command, result); + if (result[0] != IAP_RET_CMD_SUCCESS) { + printf ("IAP copy failed\n"); + return 1; + } + + return 0; +} + +int lpc24xx_flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag; + int prot; + int sect; + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) + return ERR_PROTECTED; + + flag = disable_interrupts (); + + printf ("Erasing %d sectors starting at sector %2d.\n" + "This make take some time ... ", s_last - s_first + 1, s_first); + + command[0] = IAP_CMD_PREPARE; + command[1] = s_first; + command[2] = s_last; + iap_entry (command, result); + if (result[0] != IAP_RET_CMD_SUCCESS) { + printf ("IAP prepare failed\n"); + return ERR_PROTECTED; + } + + command[0] = IAP_CMD_ERASE; + command[1] = s_first; + command[2] = s_last; + command[3] = CFG_SYS_CLK_FREQ >> 10; + iap_entry (command, result); + if (result[0] != IAP_RET_CMD_SUCCESS) { + printf ("IAP erase failed\n"); + return ERR_PROTECTED; + } + + if (flag) + enable_interrupts (); + + return ERR_OK; +} + +int lpc24xx_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + int first_copy_size; + int last_copy_size; + int first_block; + int last_block; + int nbr_mid_blocks; + sys_con_2468_t *sys_con=&(((immap_t *)CONFIG_SYS_IMMAP)->apb.sys_con); + uchar memmap_value; + ulong i; + uchar *src_org; + uchar *dst_org; + int ret = ERR_OK; + + src_org = src; + dst_org = (uchar *) addr; + + first_block = addr / 512; + last_block = (addr + cnt) / 512; + nbr_mid_blocks = last_block - first_block - 1; + + first_copy_size = 512 - (addr % 512); + last_copy_size = (addr + cnt) % 512; + + debug ("\ncopy first block: (1) %lX -> %lX 0x200 bytes, " + "(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX 0x200 bytes\n", + (ulong) (first_block * 512), + (ulong) COPY_BUFFER_LOCATION, + (ulong) src, + (ulong) (COPY_BUFFER_LOCATION + 512 - first_copy_size), + first_copy_size, + (ulong) COPY_BUFFER_LOCATION, (ulong) (first_block * 512)); + + /* copy first block */ + memcpy ((void *)COPY_BUFFER_LOCATION, (void *)(first_block * 512), 512); + memcpy ((void *)(COPY_BUFFER_LOCATION + 512 - first_copy_size), + src, first_copy_size); + lpc24xx_copy_buffer_to_flash (info, first_block * 512); + src += first_copy_size; + addr += first_copy_size; + + /* copy middle blocks */ + for (i = 0; i < nbr_mid_blocks; i++) { + debug ("copy middle block: %lX -> %lX 512 bytes, " + "%lX -> %lX 512 bytes\n", + (ulong) src, + (ulong) COPY_BUFFER_LOCATION, + (ulong) COPY_BUFFER_LOCATION, (ulong) addr); + memcpy ((void *)COPY_BUFFER_LOCATION, src, 512); + lpc24xx_copy_buffer_to_flash (info, addr); + src += 512; + addr += 512; + } + + if (last_copy_size > 0) { + debug ("copy last block: (1) %lX -> %lX 0x200 bytes, " + "(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX x200 bytes\n", + (ulong) (last_block * 512), + (ulong) COPY_BUFFER_LOCATION, + (ulong) src, + (ulong) (COPY_BUFFER_LOCATION), + last_copy_size, + (ulong) COPY_BUFFER_LOCATION, (ulong) addr); + /* copy last block */ + memcpy ((void *)COPY_BUFFER_LOCATION, + (void *)(last_block * 512), 512); + memcpy ((void *)COPY_BUFFER_LOCATION, src, last_copy_size); + lpc24xx_copy_buffer_to_flash (info, addr); + } + + /* verify write */ + memmap_value = readl(&(sys_con->memmap)); + + disable_interrupts (); + + writel(01, &(sys_con->memmap)); /* we must make sure that initial 64 + bytes are taken from flash when we + do the compare */ + + for (i = 0; i < cnt; i++) { + if (*dst_org != *src_org) { + printf ("Write failed. Byte %lX differs\n", i); + ret = ERR_PROG_ERROR; + break; + } + dst_org++; + src_org++; + } + + writel(memmap_value, &(sys_con->memmap)); + enable_interrupts (); + + return ret; +} diff --git a/cpu/arm720t/lpc24xx/iap_entry.S b/cpu/arm720t/lpc24xx/iap_entry.S new file mode 100644 index 0000000..c31d519 --- /dev/null +++ b/cpu/arm720t/lpc24xx/iap_entry.S @@ -0,0 +1,7 @@ +IAP_ADDRESS: .word 0x7FFFFFF1 + +.globl iap_entry +iap_entry: + ldr r2, IAP_ADDRESS + bx r2 + mov pc, lr diff --git a/cpu/arm720t/start.S b/cpu/arm720t/start.S index 022b873..eca4d9f 100644 --- a/cpu/arm720t/start.S +++ b/cpu/arm720t/start.S @@ -127,7 +127,7 @@ reset: bl cpu_init_crit #endif
-#ifdef CONFIG_LPC2292 +#if defined(CONFIG_LPC2000) bl lowlevel_init #endif
@@ -368,6 +368,11 @@ lock_loop: ldr r0, VPBDIV_ADR mov r1, #0x01 /* VPB clock is same as process clock */ str r1, [r0] +#elif defined(CONFIG_LPC2468) + ldr r0, =0x40008000 /*0x40000000 is internal SRAM, + 0x4000FFFF is end of SRAM*/ + mov sp,r0 + sub sl,sp,#0x2000 #else #error No cpu_init_crit() defined for current CPU type #endif @@ -383,7 +388,7 @@ lock_loop: str r1, [r0] #endif
-#ifndef CONFIG_LPC2292 +#if !defined(CONFIG_LPC2000) mov ip, lr /* * before relocating, we have to setup RAM timing @@ -601,7 +606,7 @@ reset_cpu: * on external peripherals such as watchdog timers, etc. */ #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No specific reset actions for IntegratorAP/CM720T as yet */ -#elif defined(CONFIG_LPC2292) +#elif defined(CONFIG_LPC2000) .align 5 .globl reset_cpu reset_cpu: diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index bb99a34..929fb5a 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -39,6 +39,7 @@ COBJS-$(CONFIG_IMX_SERIAL) += serial_imx.o COBJS-$(CONFIG_IXP_SERIAL) += serial_ixp.o COBJS-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o COBJS-$(CONFIG_LPC2292_SERIAL) += serial_lpc2292.o +COBJS-$(CONFIG_LPC2468_SERIAL) += serial_lpc2468.o COBJS-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o COBJS-$(CONFIG_MX31_UART) += serial_mx31.o COBJS-$(CONFIG_NETARM_SERIAL) += serial_netarm.o diff --git a/drivers/serial/serial_lpc2468.c b/drivers/serial/serial_lpc2468.c new file mode 100644 index 0000000..4b8f241 --- /dev/null +++ b/drivers/serial/serial_lpc2468.c @@ -0,0 +1,119 @@ +/* + * (C) Copyright 2002-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger mgroeger@sysgo.de + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke azu@sysgo.de + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include <common.h> +#include <asm/arch/immap.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +void serial_setbrg (void) +{ + unsigned short divisor; + uart_2468_t *uart0=&(((immap_t *)CONFIG_SYS_IMMAP)->apb.uart0); + + switch (gd->baudrate) { + case 1200: + case 9600: + case 19200: + case 38400: + case 57600: + case 115200: + divisor = CFG_SYS_CLK_FREQ / (gd->baudrate * 16); + break; + default: + hang (); + break; + } + + /* init serial UART0 */ + writeb (0, &(uart0->iir_fcr)); /* Disable RX and TX FIFOs */ + writeb (0, &(uart0->lcr)); + writeb (0, &(uart0->ier_dlm)); + writeb (0x80, &(uart0->lcr)); /* DLAB=1 */ + writeb ((unsigned char)(divisor & 0x00FF), &(uart0->rbr_thr_dll)); + writeb ((unsigned char)(divisor >> 8),&(uart0->ier_dlm)); + writeb (0x03, &(uart0->lcr)); /* 8N1, DLAB=0 */ + writeb (0x7, &(uart0->iir_fcr)); /* Enable RX and TX FIFOs */ +} + +int serial_init (void) +{ + unsigned long pinsel0; + pin_connect_2468_t *pin_connect= + &(((immap_t *)CONFIG_SYS_IMMAP)->apb.pin_connect); + + /*enable uart #0 pins in GPIO (P0.2 = TxD0, P0.3 = RxD0) */ + pinsel0 = readl (&(pin_connect->pinsel0)); + pinsel0 &= ~(0x000000f0); + pinsel0 |= 0x00000050; + writel (pinsel0, &(pin_connect->pinsel0)); + + serial_setbrg (); + + return (0); +} + +void serial_putc (const char c) +{ + uart_2468_t *uart0=&(((immap_t *)CONFIG_SYS_IMMAP)->apb.uart0); + + if (c == '\n') { + /* Wait for empty U0THR */ + while ((readb (&(uart0->lsr)) & (1 << 5)) == 0) ; + writeb ('\r', &(uart0->rbr_thr_dll)); + } + /* Wait for empty U0THR */ + while ((readb (&(uart0->lsr)) & (1 << 5)) == 0) ; + writeb (c, &(uart0->rbr_thr_dll)); +} + +int serial_getc (void) +{ + uart_2468_t *uart0=&(((immap_t *)CONFIG_SYS_IMMAP)->apb.uart0); + + while ((readb (&(uart0->lsr)) & 1) == 0) ; + return readb (&(uart0->rbr_thr_dll)); +} + +void serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +/* Test if there is a byte to read */ +int serial_tstc (void) +{ + uart_2468_t *uart0=&(((immap_t *)CONFIG_SYS_IMMAP)->apb.uart0); + + return (readb (&(uart0->lsr)) & 1); +} diff --git a/include/asm-arm/arch-lpc24xx/hardware.h b/include/asm-arm/arch-lpc24xx/hardware.h new file mode 100644 index 0000000..b42746e --- /dev/null +++ b/include/asm-arm/arch-lpc24xx/hardware.h @@ -0,0 +1,32 @@ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +/* + * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) + * Curt Brune curt@cucy.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#if defined(CONFIG_LPC2468) +#else +#error No hardware file defined for this configuration +#endif + +#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-lpc24xx/immap.h b/include/asm-arm/arch-lpc24xx/immap.h new file mode 100644 index 0000000..d37e4f1 --- /dev/null +++ b/include/asm-arm/arch-lpc24xx/immap.h @@ -0,0 +1,351 @@ +/* + * (C) Copyright 2009 Duran Audio B.V. + * + * LPC2468 Internal Memory Map + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __LPC24XX_IMMAP_H +#define __LPC24XX_IMMAP_H + +#include <asm/types.h> +#include <config.h> + +typedef struct watchdog_2468 { + u8 fixme[0x4000]; +} watchdog2468_t; + +typedef struct timer_2468 { + u32 ir; + u32 tcr; + u32 tc; + u32 pr; + u32 pc; + u32 mcr; + u32 mr0; + u32 mr1; + u32 mr2; + u32 mr3; + u32 ccr; + u32 cr0; + u32 cr1; + u32 cr2; + u32 cr3; + u32 emr; + u32 ctcr; + u8 notused[0x3fbc]; +} timer_2468_t; + +/*These two UART structs can probably be combined*/ +typedef struct uart_2468 { + u32 rbr_thr_dll; + u32 ier_dlm; + u32 iir_fcr; + u32 lcr; + u32 notused1; + u32 lsr; + u32 notused2; + u32 scr; + u32 acr; + u32 icr; + u32 fdr; + u32 notused3; + u32 ter; + u8 notused[0x3fcc]; +} uart_2468_t; + +typedef struct uart1_2468 { + u8 fixme[0x4000]; +} uart1_2468_t; + +typedef struct pwm0_2468 { + u8 fixme[0x4000]; +} pwm0_2468_t; + +typedef struct pwm1_2468 { + u8 fixme[0x4000]; +} pwm1_2468_t; + +typedef struct i2c0_2468 { + u8 fixme[0x4000]; +} i2c0_2468_t; + +typedef struct spi_2468 { + u8 fixme[0x4000]; +} spi_2468_t; + +typedef struct rtc_2468 { + u8 fixme[0x4000]; +} rtc_2468_t; + +typedef struct gpio_2468 { + u8 fixme[0x4000]; +} gpio_2468_t; + +typedef struct pin_connect_2468 { + u32 pinsel0; + u32 pinsel1; + u32 pinsel2; + u32 pinsel3; + u32 pinsel4; + u32 pinsel5; + u32 pinsel6; + u32 pinsel7; + u32 pinsel8; + u32 pinsel9; + u32 pinsel10; + u32 pinsel11; + u32 pinmode0; + u32 pinmode1; + u32 pinmode2; + u32 pinmode3; + u32 pinmode4; + u32 pinmode5; + u32 pinmode6; + u32 pinmode7; + u32 pinmode8; + u32 pinmode9; + u8 fixme[0x3fa8]; +} pin_connect_2468_t; + +typedef struct ssp1_2468 { + u8 fixme[0x4000]; +} ssp1_2468_t; + +typedef struct adc_2468 { + u8 fixme[0x4000]; +} adc_2468_t; + +typedef struct can_accept_ram_2468 { + u8 fixme[0x4000]; +} can_accept_ram_2468_t; + +typedef struct can_accept_filter_2468 { + u8 fixme[0x4000]; +} can_accept_filter_2468_t; + +typedef struct can_common_2468 { + u8 fixme[0x4000]; +} can_common_2468_t; + +typedef struct can1_2468 { + u8 fixme[0x4000]; +} can1_2468_t; + +typedef struct can2_2468 { + u8 fixme[0x4000]; +} can2_2468_t; + +typedef struct i2c1_2468 { + u8 fixme[0x4000]; +} i2c1_2468_t; + +typedef struct ssp0_2468 { + u8 fixme[0x4000]; +} ssp0_2468_t; + +typedef struct dac_2468 { + u8 fixme[0x4000]; +} dac_2468_t; + +typedef struct i2c2_2468 { + u8 fixme[0x4000]; +} i2c2_2468_t; + +typedef struct batt_ram_2468 { + u8 fixme[0x4000]; +} batt_ram_2468_t; + +typedef struct i2s_2468 { + u8 fixme[0x4000]; +} i2s_2468_t; + +typedef struct mmc_2468 { + u8 fixme[0x4000]; +} mmc_2468_t; + +typedef struct sys_con_2468 { + u8 notused1[0x40]; + u32 memmap; + u8 notused2[0xfb]; + u32 extint; + u32 extmode; + u32 extpolar; + u8 notused3[0x34]; + u32 rsid; + u32 cspr; + u32 scs; + u8 notused4[0x3e71]; +} sys_con_2468_t; + + +typedef struct mac_2468 { + u8 fixme[0x4000]; +} mac_2468_t; + +typedef struct gpdma__2468 { + u8 fixme[0x4000]; +} gpdma_2468_t; + +typedef struct ext_mem_2468 { + u8 fixme[0x4000]; +} ext_mem_2468_t; + +typedef struct usb_2468 { + u8 fixme[0x4000]; +} usb_2468_t; + +typedef struct lcd_2468 { + u8 fixme[0x4000]; +} lcd_2468_t; + +typedef struct vic_2468 { + u32 vicirqstat; + u32 vicfiqstat; + u32 vicrawintr; + u32 vicintselect; + u32 vicintenable; + u32 vicinenclr; + u32 vicsoftint; + u32 vicsoftintclr; + u32 vicprotect; + u32 vicswpriomask; + u8 notused1[0xd8]; + u32 vicvectaddr0; + u32 vicvectaddr1; + u32 vicvectaddr2; + u32 vicvectaddr3; + u32 vicvectaddr4; + u32 vicvectaddr5; + u32 vicvectaddr6; + u32 vicvectaddr7; + u32 vicvectaddr8; + u32 vicvectaddr9; + u32 vicvectaddr10; + u32 vicvectaddr11; + u32 vicvectaddr12; + u32 vicvectaddr13; + u32 vicvectaddr14; + u32 vicvectaddr15; + u32 vicvectaddr16; + u32 vicvectaddr17; + u32 vicvectaddr18; + u32 vicvectaddr19; + u32 vicvectaddr20; + u32 vicvectaddr21; + u32 vicvectaddr22; + u32 vicvectaddr23; + u32 vicvectaddr24; + u32 vicvectaddr25; + u32 vicvectaddr26; + u32 vicvectaddr27; + u32 vicvectaddr28; + u32 vicvectaddr29; + u32 vicvectaddr30; + u32 vicvectaddr31; + u8 notused2[0x7f]; + u32 vicvectprio0; + u32 vicvectprio1; + u32 vicvectprio2; + u32 vicvectprio3; + u32 vicvectprio4; + u32 vicvectprio5; + u32 vicvectprio6; + u32 vicvectprio7; + u32 vicvectprio8; + u32 vicvectprio9; + u32 vicvectprio10; + u32 vicvectprio11; + u32 vicvectprio12; + u32 vicvectprio13; + u32 vicvectprio14; + u32 vicvectprio15; + u32 vicvectprio16; + u32 vicvectprio17; + u32 vicvectprio18; + u32 vicvectprio19; + u32 vicvectprio20; + u32 vicvectprio21; + u32 vicvectprio22; + u32 vicvectprio23; + u32 vicvectprio24; + u32 vicvectprio25; + u32 vicvectprio26; + u32 vicvectprio27; + u32 vicvectprio28; + u32 vicvectprio29; + u32 vicvectprio30; + u32 vicvectprio31; + u8 notused3[0xc7f]; + u32 vicaddr; +} vic_2468_t; + +typedef struct apb_2468 { + watchdog2468_t watchdog; + timer_2468_t timer0; + timer_2468_t timer1; + uart_2468_t uart0; + uart1_2468_t uart1; + pwm0_2468_t pwm0; + pwm1_2468_t pwm1; + i2c0_2468_t i2c0; + spi_2468_t spi; + rtc_2468_t rtc; + gpio_2468_t gpio; + pin_connect_2468_t pin_connect; + ssp1_2468_t ssp1; + adc_2468_t adc; + can_accept_ram_2468_t can_accept_ram; + can_accept_filter_2468_t can_accept_filter; + can_common_2468_t can_comon; + can1_2468_t can1; + can2_2468_t can2; + u8 not_used1[0x10000]; + i2c1_2468_t i2c1; + u8 notused2[0x8000]; + ssp0_2468_t ssp0; + dac_2468_t dac; + timer_2468_t timer2; + timer_2468_t timer3; + uart_2468_t uart2; + uart_2468_t uart3; + i2c2_2468_t i2c2; + batt_ram_2468_t batt_ram; + i2s_2468_t i2s; + mmc_2468_t mmc; + u8 not_used3[0x16c000]; + sys_con_2468_t sys_con; +} apb_2468_t; + +typedef struct ahb_2468 { + mac_2468_t mac; + gpdma_2468_t gpdma; + ext_mem_2468_t ext_mem; + usb_2468_t usb; + lcd_2468_t lcd; + u8 notused1[0x1eb000]; + vic_2468_t vic; +} ahb_2468_t; + +typedef struct immap { + apb_2468_t apb; + u8 res1[0x1fc00000]; + ahb_2468_t ahb; +} immap_t; + +#endif diff --git a/include/asm-arm/config.h b/include/asm-arm/config.h index 049c44e..2d46a34 100644 --- a/include/asm-arm/config.h +++ b/include/asm-arm/config.h @@ -21,4 +21,8 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_
+#if defined(CONFIG_LPC2292) || defined(CONFIG_LPC2468) +#define CONFIG_LPC2000 +#endif + #endif diff --git a/include/flash.h b/include/flash.h index b016162..ac4a705 100644 --- a/include/flash.h +++ b/include/flash.h @@ -337,6 +337,7 @@ extern flash_info_t *flash_get_info(ulong base); #define TOSH_ID_FVT160 0xC2 /* TC58FVT160 ID (16 M, top ) */ #define TOSH_ID_FVB160 0x43 /* TC58FVT160 ID (16 M, bottom ) */ #define PHILIPS_LPC2292 0x0401FF13 /* LPC2292 internal FLASH */ +#define PHILIPS_LPC2468 0x0603FF35 /* LPC2468 internal FLASH */
/*----------------------------------------------------------------------- * Internal FLASH identification codes
Dear Remco Poelstra,
In message 49F1A92F.9070804@duran-audio.com you wrote:
This patch includes support for the LPC2468 processor from NXP.
Thanks.
Here a few comments:
--- a/cpu/arm720t/cpu.c +++ b/cpu/arm720t/cpu.c @@ -75,7 +75,7 @@ int cleanup_before_linux (void) /* go to high speed */ IO_SYSCON3 = (IO_SYSCON3 & ~CLKCTL) | CLKCTL_73; #endif -#elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) || defined(CONFIG_LPC2292) +#elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) || defined(CONFIG_LPC2000)
Line too long.
diff --git a/cpu/arm720t/interrupts.c b/cpu/arm720t/interrupts.c index 39ed345..d7aec27 100644 --- a/cpu/arm720t/interrupts.c +++ b/cpu/arm720t/interrupts.c @@ -29,17 +29,26 @@ #include <common.h> #include <clps7111.h> #include <asm/proc-armv/ptrace.h> +#include <asm/io.h> +#if defined(CONFIG_LPC2468) +#include <asm/arch/immap.h> +#else #include <asm/hardware.h> +#endif
Would it be possible to keep a generic ``#include <asm/hardware.h>'' here and add the processor specific stuff there?
#ifndef CONFIG_NETARM
+#if defined(CONFIG_LPC2292) +#define TIMER_LOAD_VAL 0xffff +#define READ_TIMER (0xFFFFFFFF - GET32(T0TC)) +#elif defined(CONFIG_LPC2468) +#define TIMER_LOAD_VAL 0 +#define READ_TIMER (0xFFFFFFFF - 0xE0004008) +#else
Can we please move this out of a common source file?
-#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO) || defined(CONFIG_LPC2292) +#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO) || defined(CONFIG_LPC2000)
Line too long.
--- a/cpu/arm720t/start.S +++ b/cpu/arm720t/start.S
...
@@ -368,6 +368,11 @@ lock_loop: ldr r0, VPBDIV_ADR mov r1, #0x01 /* VPB clock is same as process clock */ str r1, [r0] +#elif defined(CONFIG_LPC2468)
- ldr r0, =0x40008000 /*0x40000000 is internal SRAM,
0x4000FFFF is end of SRAM*/- mov sp,r0
- sub sl,sp,#0x2000
Indentation not by TAB
diff --git a/drivers/serial/serial_lpc2468.c b/drivers/serial/serial_lpc2468.c new file mode 100644 index 0000000..4b8f241 --- /dev/null +++ b/drivers/serial/serial_lpc2468.c @@ -0,0 +1,119 @@
Do we really need a new file here?
diff --git a/include/asm-arm/arch-lpc24xx/immap.h b/include/asm-arm/arch-lpc24xx/immap.h new file mode 100644 index 0000000..d37e4f1 --- /dev/null +++ b/include/asm-arm/arch-lpc24xx/immap.h @@ -0,0 +1,351 @@ +/*
- (C) Copyright 2009 Duran Audio B.V.
- LPC2468 Internal Memory Map
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#ifndef __LPC24XX_IMMAP_H +#define __LPC24XX_IMMAP_H
+#include <asm/types.h> +#include <config.h>
+typedef struct watchdog_2468 {
- u8 fixme[0x4000];
+} watchdog2468_t;
+typedef struct timer_2468 {
- u32 ir;
- u32 tcr;
- u32 tc;
- u32 pr;
- u32 pc;
- u32 mcr;
- u32 mr0;
- u32 mr1;
- u32 mr2;
- u32 mr3;
- u32 ccr;
- u32 cr0;
- u32 cr1;
- u32 cr2;
- u32 cr3;
- u32 emr;
- u32 ctcr;
- u8 notused[0x3fbc];
+} timer_2468_t;
Indentation not by TAB (whole file!).
How about adding some comments to explain what all these fields mean? (whole file!)
Best regards,
Wolfgang Denk
This patch includes support for the LPC2468 processor from NXP.
Signed-off-by: Remco Poelstra remco.poelstra+u-boot@duran-audio.com --- It now also includes support for the ethernet interface. It does not include any changes to flash related code, until it's known where to put it. Stefan was right that the unreferenced function are needed by the board code. Neither does it contain any significant changes to the interrupt code, waiting for the patch to clean it up. I would be gratefull if the patch can be applied before then, I can then help clean up the code, instead of staying behind. Concerning thumb code: As explained earlier, it is needed to call the internal IAP functions. These are seldom used, so there is no performance penalty.
From 10ae52e03e99a2567f4b74434ba346b45c24ac02 Mon Sep 17 00:00:00 2001 From: Remco Poelstra remco.poelstra+u-boot@duran-audio.com Date: Fri, 24 Apr 2009 12:18:21 +0200 Subject: [PATCH] Support for LPC2468 processor from NXP
--- Makefile | 3 + cpu/arm720t/cpu.c | 4 +- cpu/arm720t/interrupts.c | 38 ++- cpu/arm720t/lpc24xx/Makefile | 50 +++ cpu/arm720t/lpc24xx/flash.c | 236 +++++++++++++++ cpu/arm720t/lpc24xx/iap_entry.S | 7 + cpu/arm720t/start.S | 12 +- drivers/net/Makefile | 1 + drivers/net/lpc2468_eth.c | 494 +++++++++++++++++++++++++++++++ drivers/net/lpc2468_eth.h | 159 ++++++++++ drivers/serial/Makefile | 1 + drivers/serial/serial_lpc2468.c | 119 ++++++++ include/asm-arm/arch-lpc24xx/hardware.h | 32 ++ include/asm-arm/arch-lpc24xx/immap.h | 406 +++++++++++++++++++++++++ include/asm-arm/config.h | 4 + include/flash.h | 1 + 16 files changed, 1558 insertions(+), 9 deletions(-) create mode 100644 cpu/arm720t/lpc24xx/Makefile create mode 100644 cpu/arm720t/lpc24xx/flash.c create mode 100644 cpu/arm720t/lpc24xx/iap_entry.S create mode 100644 drivers/net/lpc2468_eth.c create mode 100644 drivers/net/lpc2468_eth.h create mode 100644 drivers/serial/serial_lpc2468.c create mode 100644 include/asm-arm/arch-lpc24xx/hardware.h create mode 100644 include/asm-arm/arch-lpc24xx/immap.h
diff --git a/Makefile b/Makefile index e91c051..fb23ee6 100644 --- a/Makefile +++ b/Makefile @@ -2940,6 +2940,9 @@ B2_config : unconfig ## ARM720T Systems #########################################################################
+LPC2468_config: unconfig + @$(MKCONFIG) $(@:_config=) arm arm720t LPC2468 NULL lpc24xx + armadillo_config: unconfig @$(MKCONFIG) $(@:_config=) arm arm720t armadillo
diff --git a/cpu/arm720t/cpu.c b/cpu/arm720t/cpu.c index 6c40903..29e13d0 100644 --- a/cpu/arm720t/cpu.c +++ b/cpu/arm720t/cpu.c @@ -75,7 +75,9 @@ int cleanup_before_linux (void) /* go to high speed */ IO_SYSCON3 = (IO_SYSCON3 & ~CLKCTL) | CLKCTL_73; #endif -#elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) || defined(CONFIG_LPC2292) +#elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) ||\ + defined(CONFIG_LPC2000) + disable_interrupts (); /* Nothing more needed */ #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) diff --git a/cpu/arm720t/interrupts.c b/cpu/arm720t/interrupts.c index 39ed345..8671b63 100644 --- a/cpu/arm720t/interrupts.c +++ b/cpu/arm720t/interrupts.c @@ -29,17 +29,26 @@ #include <common.h> #include <clps7111.h> #include <asm/proc-armv/ptrace.h> +#include <asm/io.h> +#if defined(CONFIG_LPC2468) +#include <asm/arch/immap.h> +#else #include <asm/hardware.h> +#endif
#ifndef CONFIG_NETARM + +#if defined(CONFIG_LPC2292) +#define TIMER_LOAD_VAL 0xffff +#define READ_TIMER (0xFFFFFFFF - GET32(T0TC)) +#elif defined(CONFIG_LPC2468) +#define TIMER_LOAD_VAL 0 +#define READ_TIMER (0xFFFFFFFF - 0xE0004008) +#else /* we always count down the max. */ #define TIMER_LOAD_VAL 0xffff /* macro to read the 16 bit timer */ #define READ_TIMER (IO_TC1D & 0xffff) - -#ifdef CONFIG_LPC2292 -#undef READ_TIMER -#define READ_TIMER (0xFFFFFFFF - GET32(T0TC)) #endif
#else @@ -80,6 +89,14 @@ void do_irq (struct pt_regs *pt_regs) pfnct = (void (*)(void))VICVectAddr;
(*pfnct)(); +#elif defined(CONFIG_LPC2468) + void (*pfnct) (void); + vic_2468_t *vic = &(((immap_t *)CONFIG_SYS_IMMAP)->ahb.vic); + + pfnct = (void (*)(void))(&(vic->vicaddr)); + + (*pfnct) (); + #else #error do_irq() not defined for this CPU type #endif @@ -112,6 +129,9 @@ static ulong lastdec;
int interrupt_init (void) { +#if defined(CONFIG_LPC2468) + timer_2468_t *timer0=&(((immap_t *)CONFIG_SYS_IMMAP)->apb.timer0); +#endif
#if defined(CONFIG_NETARM) /* disable all interrupts */ @@ -185,6 +205,13 @@ int interrupt_init (void) PUT32(T0MCR, 0); PUT32(T0TC, 0); PUT32(T0TCR, 1); /* enable timer0 */ +#elif defined(CONFIG_LPC2468) + writel (0, &(timer0->ir)); /*disable all timer0 interupts */ + writel (0, &(timer0->tcr)); /*disable timer0 */ + writel (CFG_SYS_CLK_FREQ / CONFIG_SYS_HZ - 1, &(timer0->pr)); + writel (0, &(timer0->mcr)); + writel (0, &(timer0->tc)); + writel (1, &(timer0->tcr));
#else #error No interrupt_init() defined for this CPU type @@ -201,7 +228,8 @@ int interrupt_init (void) */
-#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO) || defined(CONFIG_LPC2292) +#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) ||\ + defined(CONFIG_ARMADILLO) || defined(CONFIG_LPC2000)
void reset_timer (void) { diff --git a/cpu/arm720t/lpc24xx/Makefile b/cpu/arm720t/lpc24xx/Makefile new file mode 100644 index 0000000..f091502 --- /dev/null +++ b/cpu/arm720t/lpc24xx/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2000-2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = flash.o +SOBJS = $(obj)iap_entry.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +# this MUST be compiled as thumb code! +$(SOBJS): + $(CC) $(AFLAGS) -march=armv4t -c -o $(SOBJS) iap_entry.S + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm720t/lpc24xx/flash.c b/cpu/arm720t/lpc24xx/flash.c new file mode 100644 index 0000000..963bf6e --- /dev/null +++ b/cpu/arm720t/lpc24xx/flash.c @@ -0,0 +1,236 @@ +/* + * (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/immap.h> + +/* IAP commands use 32 bytes at the top of CPU internal sram, we + * use 512 bytes below that + */ + +#define COPY_BUFFER_LOCATION 0x4000fde0 + +#define IAP_LOCATION 0x7ffffff1 +#define IAP_CMD_PREPARE 50 +#define IAP_CMD_COPY 51 +#define IAP_CMD_ERASE 52 +#define IAP_CMD_CHECK 53 +#define IAP_CMD_ID 54 +#define IAP_CMD_VERSION 55 +#define IAP_CMD_COMPARE 56 + +#define IAP_RET_CMD_SUCCESS 0 + +static unsigned long command[5]; +static unsigned long result[2]; + +extern void iap_entry (unsigned long *command, unsigned long *result); + +/*----------------------------------------------------------------------- + * + */ +int get_flash_sector (flash_info_t * info, ulong flash_addr) +{ + int i; + + for (i = 1; i < (info->sector_count); i++) { + if (flash_addr < (info->start[i])) + break; + } + + return (i - 1); +} + +/*----------------------------------------------------------------------- + * This function assumes that flash_addr is aligned on 512 bytes boundary + * in flash. This function also assumes that prepare have been called + * for the sector in question. + */ +int lpc24xx_copy_buffer_to_flash (flash_info_t * info, ulong flash_addr) +{ + int first_sector; + int last_sector; + + first_sector = get_flash_sector (info, flash_addr); + last_sector = get_flash_sector (info, flash_addr + 512 - 1); + + /* prepare sectors for write */ + command[0] = IAP_CMD_PREPARE; + command[1] = first_sector; + command[2] = last_sector; + iap_entry (command, result); + if (result[0] != IAP_RET_CMD_SUCCESS) { + printf ("IAP prepare failed\n"); + return ERR_PROG_ERROR; + } + + command[0] = IAP_CMD_COPY; + command[1] = flash_addr; + command[2] = COPY_BUFFER_LOCATION; + command[3] = 512; + command[4] = CFG_SYS_CLK_FREQ >> 10; + iap_entry (command, result); + if (result[0] != IAP_RET_CMD_SUCCESS) { + printf ("IAP copy failed\n"); + return 1; + } + + return 0; +} + +int lpc24xx_flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag; + int prot; + int sect; + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) + return ERR_PROTECTED; + + flag = disable_interrupts (); + + printf ("Erasing %d sectors starting at sector %2d.\n" + "This make take some time ... ", s_last - s_first + 1, s_first); + + command[0] = IAP_CMD_PREPARE; + command[1] = s_first; + command[2] = s_last; + iap_entry (command, result); + if (result[0] != IAP_RET_CMD_SUCCESS) { + printf ("IAP prepare failed\n"); + return ERR_PROTECTED; + } + + command[0] = IAP_CMD_ERASE; + command[1] = s_first; + command[2] = s_last; + command[3] = CFG_SYS_CLK_FREQ >> 10; + iap_entry (command, result); + if (result[0] != IAP_RET_CMD_SUCCESS) { + printf ("IAP erase failed\n"); + return ERR_PROTECTED; + } + + if (flag) + enable_interrupts (); + + return ERR_OK; +} + +int lpc24xx_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + int first_copy_size; + int last_copy_size; + int first_block; + int last_block; + int nbr_mid_blocks; + sys_con_2468_t *sys_con=&(((immap_t *)CONFIG_SYS_IMMAP)->apb.sys_con); + uchar memmap_value; + ulong i; + uchar *src_org; + uchar *dst_org; + int ret = ERR_OK; + + src_org = src; + dst_org = (uchar *) addr; + + first_block = addr / 512; + last_block = (addr + cnt) / 512; + nbr_mid_blocks = last_block - first_block - 1; + + first_copy_size = 512 - (addr % 512); + last_copy_size = (addr + cnt) % 512; + + debug ("\ncopy first block: (1) %lX -> %lX 0x200 bytes, " + "(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX 0x200 bytes\n", + (ulong) (first_block * 512), + (ulong) COPY_BUFFER_LOCATION, + (ulong) src, + (ulong) (COPY_BUFFER_LOCATION + 512 - first_copy_size), + first_copy_size, + (ulong) COPY_BUFFER_LOCATION, (ulong) (first_block * 512)); + + /* copy first block */ + memcpy ((void *)COPY_BUFFER_LOCATION, (void *)(first_block * 512), 512); + memcpy ((void *)(COPY_BUFFER_LOCATION + 512 - first_copy_size), + src, first_copy_size); + lpc24xx_copy_buffer_to_flash (info, first_block * 512); + src += first_copy_size; + addr += first_copy_size; + + /* copy middle blocks */ + for (i = 0; i < nbr_mid_blocks; i++) { + debug ("copy middle block: %lX -> %lX 512 bytes, " + "%lX -> %lX 512 bytes\n", + (ulong) src, + (ulong) COPY_BUFFER_LOCATION, + (ulong) COPY_BUFFER_LOCATION, (ulong) addr); + memcpy ((void *)COPY_BUFFER_LOCATION, src, 512); + lpc24xx_copy_buffer_to_flash (info, addr); + src += 512; + addr += 512; + } + + if (last_copy_size > 0) { + debug ("copy last block: (1) %lX -> %lX 0x200 bytes, " + "(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX x200 bytes\n", + (ulong) (last_block * 512), + (ulong) COPY_BUFFER_LOCATION, + (ulong) src, + (ulong) (COPY_BUFFER_LOCATION), + last_copy_size, + (ulong) COPY_BUFFER_LOCATION, (ulong) addr); + /* copy last block */ + memcpy ((void *)COPY_BUFFER_LOCATION, + (void *)(last_block * 512), 512); + memcpy ((void *)COPY_BUFFER_LOCATION, src, last_copy_size); + lpc24xx_copy_buffer_to_flash (info, addr); + } + + /* verify write */ + memmap_value = readl(&(sys_con->memmap)); + + disable_interrupts (); + + writel(01, &(sys_con->memmap)); /* we must make sure that initial 64 + bytes are taken from flash when we + do the compare */ + + for (i = 0; i < cnt; i++) { + if (*dst_org != *src_org) { + printf ("Write failed. Byte %lX differs\n", i); + ret = ERR_PROG_ERROR; + break; + } + dst_org++; + src_org++; + } + + writel(memmap_value, &(sys_con->memmap)); + enable_interrupts (); + + return ret; +} diff --git a/cpu/arm720t/lpc24xx/iap_entry.S b/cpu/arm720t/lpc24xx/iap_entry.S new file mode 100644 index 0000000..c31d519 --- /dev/null +++ b/cpu/arm720t/lpc24xx/iap_entry.S @@ -0,0 +1,7 @@ +IAP_ADDRESS: .word 0x7FFFFFF1 + +.globl iap_entry +iap_entry: + ldr r2, IAP_ADDRESS + bx r2 + mov pc, lr diff --git a/cpu/arm720t/start.S b/cpu/arm720t/start.S index 022b873..1b2e4bf 100644 --- a/cpu/arm720t/start.S +++ b/cpu/arm720t/start.S @@ -127,7 +127,7 @@ reset: bl cpu_init_crit #endif
-#ifdef CONFIG_LPC2292 +#if defined(CONFIG_LPC2000) bl lowlevel_init #endif
@@ -368,6 +368,12 @@ lock_loop: ldr r0, VPBDIV_ADR mov r1, #0x01 /* VPB clock is same as process clock */ str r1, [r0] +#elif defined(CONFIG_LPC2468) + ldr r0, =0x40008000 /* 0x40000000 is internal SRAM, + * 0x4000FFFF is end of SRAM + */ + mov sp,r0 + sub sl,sp,#0x2000 #else #error No cpu_init_crit() defined for current CPU type #endif @@ -383,7 +389,7 @@ lock_loop: str r1, [r0] #endif
-#ifndef CONFIG_LPC2292 +#if !defined(CONFIG_LPC2000) mov ip, lr /* * before relocating, we have to setup RAM timing @@ -601,7 +607,7 @@ reset_cpu: * on external peripherals such as watchdog timers, etc. */ #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No specific reset actions for IntegratorAP/CM720T as yet */ -#elif defined(CONFIG_LPC2292) +#elif defined(CONFIG_LPC2000) .align 5 .globl reset_cpu reset_cpu: diff --git a/drivers/net/Makefile b/drivers/net/Makefile index a360a50..83a1401 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -42,6 +42,7 @@ COBJS-$(CONFIG_GRETH) += greth.o COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o COBJS-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o COBJS-$(CONFIG_DRIVER_LAN91C96) += lan91c96.o +COBJS-$(CONFIG_LPC2468_ETH) += lpc2468_eth.o COBJS-$(CONFIG_MACB) += macb.o COBJS-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o COBJS-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o diff --git a/drivers/net/lpc2468_eth.c b/drivers/net/lpc2468_eth.c new file mode 100644 index 0000000..b16e404 --- /dev/null +++ b/drivers/net/lpc2468_eth.c @@ -0,0 +1,494 @@ +/* + * (C) Copyright 2009 Duran Audio B.V. <www.duran-audio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * 18-03-2009 Updated for U-boot 2009.3 + * by Remco Poelstra remco.poelstra+u-boot@duran-audio.com + * Based on sample code from NXP + */ + +#include <config.h> +#include <common.h> +#include <net.h> +#include <asm/io.h> +#include <asm/arch/immap.h> +#include "lpc2468_eth.h" + +/****************************************************************************** + * Local variables + *****************************************************************************/ + +static unsigned char macAddr[6]; +static volatile int phyAddr = 0x1000; +static int eth_initialized = 0; +mac_2468_t *mac=&(((immap_t *)CONFIG_SYS_IMMAP)->ahb.mac); + +/****************************************************************************** + * Local functions + *****************************************************************************/ + +static void writePhy (u32 phyReg, u32 phyData) +{ + + /* write command */ + writel (0x0, &(mac->mcmd)); + + /* [12:8] == PHY addr, [4:0]=0x00(BMCR) register addr */ + writel ((phyAddr | phyReg), &(mac->madr)); + writel (phyData, &(mac->mwtd)); + while (readl (&(mac->mind)) != 0) ; +} + +static u32 readPhy (u32 phyReg) +{ + + /* read command */ + writel (0x1, &(mac->mcmd)); + + /* [12:8] == PHY addr, [4:0]=0x00(BMCR) register addr */ + writel ((phyAddr | phyReg), &(mac->madr)); + + while (readl (&(mac->mind)) != 0); + + writel (0x0, &(mac->mcmd)); + + return readl (&(mac->mrdd)); +} + +static int emac_start_xmit (volatile void *buf, int length) +{ + + u32 txProduceIndex = 0; + u32 txConsumeIndex = 0; + u8 *pData = 0; + u32 len = length; + u32 sendLen = 0; + u32 *tx_desc_addr = NULL; + + txProduceIndex = readl (&(mac->txproduceindex)); + txConsumeIndex = readl (&(mac->txconsumeindex)); + + if (txConsumeIndex != txProduceIndex) { + /* TODO why return here? This just means that the transmit array isn't empty */ + printf ("emac: emac_tx transmit array isn't empty\n"); + return -1; + } + + if (txProduceIndex == EMAC_TX_DESCRIPTOR_COUNT) { + /* should never happen */ + printf ("emac: emac_tx produce index == count\n"); + } + + if (len > 0) { + pData = (u8 *) EMAC_TX_BUFFER_ADDR; + memcpy (pData, (void *)buf, length); + + do { + tx_desc_addr = + (u32 *) (TX_DESCRIPTOR_ADDR + txProduceIndex * 8); + + sendLen = len; + if (sendLen > EMAC_BLOCK_SIZE) { + sendLen = EMAC_BLOCK_SIZE; + } else { + /* last fragment */ + sendLen |= EMAC_TX_DESC_LAST; + } + + writel ((unsigned long) pData, tx_desc_addr); + tx_desc_addr++; + writel ((u32) (EMAC_TX_DESC_INT | (sendLen - 1)), + tx_desc_addr); + + txProduceIndex++; + if (txProduceIndex == EMAC_TX_DESCRIPTOR_COUNT) { + txProduceIndex = 0; + } + + writel (txProduceIndex, &(mac->txproduceindex)); + + len -= (sendLen & ~EMAC_TX_DESC_LAST); + pData += (sendLen & ~EMAC_TX_DESC_LAST); + } while (len > 0); + } + + return 0; +} + +static void emac_rx (void) +{ + u32 rxProduceIndex = 0; + u32 rxConsumeIndex = 0; + u32 *rxStatusAddr = 0; + u32 recvSize = 0; + u32 *recvAddr = 0; + + /* the input parameter, EMCBuf, needs to be word aligned */ + + rxProduceIndex = readl (&(mac->rxproduceindex)); + rxConsumeIndex = readl (&(mac->rxconsumeindex)); + + /* consume the received packets */ + while (rxConsumeIndex != rxProduceIndex) { + + rxStatusAddr = (u32 *) (RX_STATUS_ADDR + rxConsumeIndex * 8); + + recvSize = readl (rxStatusAddr); + + if ((recvSize & RX_DESC_STATUS_LAST) == 0) { + /* TODO: could this occur when EMAC_BLOCK_SIZE == 0x0600? */ + printf ("emac_rx: NOT LAST fragment\n"); + } + + recvSize = (recvSize & DESC_SIZE_MASK) + 1; + + recvAddr = (u32 *) (RX_DESCRIPTOR_ADDR + rxConsumeIndex * 8); + + /* TODO: allocate buffer? */ + NetReceive ((uchar *) (readl (recvAddr) /*inBuf */ ), + recvSize); + + rxConsumeIndex++; + if (rxConsumeIndex == EMAC_RX_DESCRIPTOR_COUNT) { + rxConsumeIndex = 0; + } + + writel (rxConsumeIndex, &(mac->rxconsumeindex)); + + } + +} + +static void emac_interrupt (void) +{ + volatile u32 regValue = 0; + + regValue = readl (&(mac->intstatus)); + + do { + if (regValue == 0) { + break; + } + + if (regValue & EMAC_INT_RXOVERRUN) { + writel (EMAC_INT_RXOVERRUN, &(mac->intclear)); + printf ("rxOverrun\n"); + break; + } + + if (regValue & EMAC_INT_RXERROR) { + writel (EMAC_INT_RXERROR, &(mac->intclear)); + } + + if (regValue & EMAC_INT_RXFINISHED) { + writel (EMAC_INT_RXFINISHED, &(mac->intclear)); + } + + if (regValue & EMAC_INT_RXDONE) { + writel (EMAC_INT_RXDONE, &(mac->intclear)); + emac_rx (); + } + + if (regValue & EMAC_INT_TXUNDERRUN) { + printf ("TX underrun\n"); + writel (EMAC_INT_TXUNDERRUN, &(mac->intclear)); + break; + } + + if (regValue & EMAC_INT_TXERROR) { + printf ("TX err\n"); + writel (EMAC_INT_TXERROR, &(mac->intclear)); + break; + } + + if (regValue & EMAC_INT_TXFINISHED) { + writel (EMAC_INT_TXFINISHED, &(mac->intclear)); + } + + if (regValue & EMAC_INT_TXDONE) { + writel (EMAC_INT_TXDONE, &(mac->intclear)); + } + + } while (0); +} + +static int emac_open (void) +{ + /* enable Rx & Tx */ + BFS32 (&(mac->command), CMD_RX_ENABLE); + BFS32 (&(mac->command), CMD_TX_ENABLE); + BFS32 (&(mac->command), CMD_PASS_RX_FILTER); + BFS32 (&(mac->mac1), 0x01); + + return 0; +} + +static void emac_close (void) +{ + /* disable Rx6 Tx */ + BFC32 (&(mac->command), CMD_RX_ENABLE); + BFC32 (&(mac->command), CMD_TX_ENABLE); + BFC32 (&(mac->mac1), 0x01); +} + +static int phyInit (void) +{ + int i = 0; + u32 regValue = 0; + u32 timeout = 0; + + writel (0x801C, &(mac->mcfg)); /* host clock divided by 28, + no suppress preamble, + no scan increment */ + + for (i = 0; i < 0x40; i++) + asm volatile (" nop"); + + /* MII Mgmt. Divided by 28. */ + writel (0x001C, &(mac->mcfg)); + writel (0x0, &(mac->mcmd)); + + for (i = 0; i < 0x100; i++) + asm volatile (" nop"); + + /*Reset the PHY */ + writePhy (PHY_BMCR, BMCR_RESET); + udelay (100); + + timeout = MII_BMSR_TIMEOUT * 4; + while (timeout != 0) { + regValue = readPhy (PHY_BMCR); + if ((regValue & BMCR_RESET) == 0x0000) { + /* reset bit has been cleared */ + break; + } + timeout--; + } + + if (timeout == 0) { + printf (" Error: phyInit failed to reset PHY\n"); + return -1; + } + + return 0; +} + +static void emacTxDescriptorInit (void) +{ + int i = 0; + u32 *txDescAddr = NULL; + u32 *txStatusAddr = NULL; + + /* base address of tx descriptor array */ + writel (TX_DESCRIPTOR_ADDR, &(mac->txdescriptor)); + + /* base address of tx status */ + writel (TX_STATUS_ADDR, &(mac->txstatus)); + + /* number of tx descriptors */ + writel (EMAC_TX_DESCRIPTOR_COUNT - 1, &(mac->txdescriptornumber)); + + for (i = 0; i < EMAC_TX_DESCRIPTOR_COUNT; i++) { + txDescAddr = (u32 *) (TX_DESCRIPTOR_ADDR + i * 8); + writel ((EMAC_TX_BUFFER_ADDR + i * EMAC_BLOCK_SIZE), + (unsigned long)txDescAddr); + + /* control field in descriptor */ + txDescAddr++; + writel ((EMAC_TX_DESC_INT | (EMAC_BLOCK_SIZE - 1)), + (unsigned long)txDescAddr); + } + + for (i = 0; i < EMAC_TX_DESCRIPTOR_COUNT; i++) { + + txStatusAddr = (u32 *) (TX_STATUS_ADDR + i * 4); + + /* set status info to 0 */ + writel (0x0, (unsigned long)txStatusAddr); + } + + writel (0x0, &(mac->txproduceindex)); +} + +static void emacRxDescriptorInit (void) +{ + int i; + u32 *rxDescAddr = NULL; + u32 *rxStatusAddr = NULL; + + /* base address of rx descriptor array */ + writel (RX_DESCRIPTOR_ADDR, &(mac->rxdescriptor)); + + /* base address of rx status */ + writel (RX_STATUS_ADDR, &(mac->rxstatus)); + + /* number of rx descriptors */ + writel (EMAC_RX_DESCRIPTOR_COUNT - 1, &(mac->rxdescriptornumber)); + + for (i = 0; i < EMAC_RX_DESCRIPTOR_COUNT; i++) { + rxDescAddr = (u32 *) (RX_DESCRIPTOR_ADDR + i * 8); + + writel ((EMAC_RX_BUFFER_ADDR + i * EMAC_BLOCK_SIZE), + (unsigned long)rxDescAddr); + + rxDescAddr++; + + writel ((EMAC_RX_DESC_INT | + ((EMAC_BLOCK_SIZE - 1) & DESC_SIZE_MASK)), + (unsigned long)rxDescAddr); + } + + for (i = 0; i < EMAC_RX_DESCRIPTOR_COUNT; i++) { + /* RX status, two words, status info. and status hash CRC. */ + rxStatusAddr = (u32 *) (RX_STATUS_ADDR + i * 8); + writel (0x0, (unsigned long)rxStatusAddr); + rxStatusAddr++; + writel (0x0, (unsigned long)rxStatusAddr); + } + + writel (0x0, &(mac->rxconsumeindex)); +} + +static int emacInit (void) +{ + int i = 0; + pin_connect_2468_t *pin_connect=&(((immap_t *)CONFIG_SYS_IMMAP)->apb.pin_connect); + + /* turn on the ethernet MAC clock in PCONP, bit 30 */ + BFS32 (&(((immap_t *)CONFIG_SYS_IMMAP)->apb.sys_con.pconp), PCONP_EMAC_CLOCK); + /*----------------------------------------------------------------------- + * write to PINSEL2/3 to select the PHY functions on P1[17:0] + *-----------------------------------------------------------------------*/ + + /* documentation needs to be updated */ + writel (0x55555555, &(pin_connect->pinsel2)); /* selects P1[0,1,4,8,9,10,14,15] */ + writel (0x00000005, &(pin_connect->pinsel3)); /* selects P1[17:16] */ + + /*reset MAC modules, tx, mcs_tx, rx, mcs_rx, simulation and soft reset*/ + writel (0xCF00, &(mac->mac1)); + + /* reset datapaths and host registers */ + writel (0x0038, &(mac->command)); + + /* short delay after reset */ + for (i = 0; i < 0x40; i++) + asm volatile (" nop"); + + /*Remove reset conditions*/ + writel (0x0, &(mac->mac1)); + + /*disable Tx*/ + BFC32 (&(mac->command), CMD_TX_ENABLE); + + /*disable Rx*/ + BFC32 (&(mac->command), CMD_RX_ENABLE); + + /*initialize MAC2 to default value + TODO don't thinkt this is necessary?? m_nic_write(EMAC_MAC2, 0x0);*/ + writel (0x030, &(mac->mac2)); + + /*non back-to-back Inter-Packet-Gap register + The manual recommends the value 0x12 */ + writel (0x12, &(mac->ipgr)); + + /*collision window/retry register. Using recommended value from manual*/ + writel (0x370F, &(mac->clrt)); + + /* intialize PHY. */ + if (phyInit () < 0) + return -1; + + /* write the mac address */ + writel ((macAddr[5] << 8 | macAddr[4]), &(mac->sa0)); + writel ((macAddr[3] << 8 | macAddr[2]), &(mac->sa1)); + writel ((macAddr[1] << 8 | macAddr[0]), &(mac->sa2)); + + printf ("emac: MAC address = %2x:%2x:%2x:%2x:%2x:%2x\n", + macAddr[0], + macAddr[1], macAddr[2], macAddr[3], macAddr[4], macAddr[5]); + + emacTxDescriptorInit (); + emacRxDescriptorInit (); + + /* pass all receive frames */ + BFS32 (&(mac->mac1), 0x002); + + /* set up the Rx filter + [0]-AllUnicast, [1]-AllBroadCast, [2]-AllMulticast, [3]-UnicastHash + [4]-MulticastHash, [5]-Perfect, [12]-MagicPacketEnWoL, + [13]-RxFilterEnWoL + PUT32(MAC_RXFILTERCTRL, 0x0022); */ + writel (0x003F, &(mac->rxfilterctrl)); /*Pass everything */ + + /* clear all interrupts */ + writel (0xFFFF, &(mac->intclear)); + + /* enable interrupts (not SoftInt and WoL) */ + writel (0x00FF, &(mac->intenable)); + + return 0; +} + +/* ############################## + * u-boot interface + * ############################## + */ + +/* + * Returns 0 when failes otherwise 1 + */ +int eth_init (bd_t * bis) +{ + int ret; + if (!eth_initialized) { + if (!eth_getenv_enetaddr ("ethaddr", macAddr)) { + printf ("Failed to get MAC address from environment\n"); + return 1; + } + + ret = emacInit (); + if (ret != 0) { + return ret; + } + + eth_initialized = 1; + } + + emac_open (); + return 0; +} + +int eth_send (volatile void *packet, int length) +{ + emac_start_xmit (packet, length); + return 0; +} + +/*----------------------------------------------------------------------------- + * Check for received packets. Call NetReceive for each packet. The return + * value is ignored by the caller. + */ +int eth_rx (void) +{ + emac_interrupt (); + return 0; +} + +void eth_halt (void) +{ + emac_close (); +} diff --git a/drivers/net/lpc2468_eth.h b/drivers/net/lpc2468_eth.h new file mode 100644 index 0000000..b1c4671 --- /dev/null +++ b/drivers/net/lpc2468_eth.h @@ -0,0 +1,159 @@ +#ifndef LPC2468_ETH_H +#define LPC2468_ETH_H + +/****************************************************************************** + * Typedefs and defines + *****************************************************************************/ +#define MAX_PHY_INIT_RETRY 10 + +/* EMAC MODULE ID */ +#define OLD_EMAC_MODULE_ID ((0x3902 << 16) | 0x2000) + +/* MAC registers and parameters */ +#define PCONP_EMAC_CLOCK 0x40000000 + +#define SPEED_100 1 +#define SPEED_10 0 +#define FULL_DUPLEX 1 +#define HALF_DUPLEX 0 + +#define EMAC_RAM_ADDR 0x7FE00000 +#define EMAC_RAM_SIZE 0x00004000 + +#define EMAC_TX_DESCRIPTOR_COUNT 5 +#define EMAC_RX_DESCRIPTOR_COUNT 4 + +/* + * (Rx|Tx)Descriptor :: + * [4] packet - base address of the buffer containing the data + * [4] control - control information + */ +#define TX_DESCRIPTOR_SIZE (EMAC_TX_DESCRIPTOR_COUNT * 8) +#define RX_DESCRIPTOR_SIZE (EMAC_RX_DESCRIPTOR_COUNT * 8) + +/* + * TxStatus :: + * [4] status + */ +#define TX_STATUS_SIZE (EMAC_TX_DESCRIPTOR_COUNT * 4) + +/* + * RxStatus :: + * [4] status - receive status flags + * [4] statusHashCRC - concat of dest addr hash CRC and src addr CRC + */ +#define RX_STATUS_SIZE (EMAC_RX_DESCRIPTOR_COUNT * 8) + +#define TOTAL_DESCRIPTOR_SIZE (TX_DESCRIPTOR_SIZE + RX_DESCRIPTOR_SIZE + TX_STATUS_SIZE + RX_STATUS_SIZE) + +/* descriptors are placed at the end of the emac address space */ +#define EMAC_DESCRIPTOR_ADDR (EMAC_RAM_ADDR + EMAC_RAM_SIZE - TOTAL_DESCRIPTOR_SIZE) + +#define TX_DESCRIPTOR_ADDR EMAC_DESCRIPTOR_ADDR +#define TX_STATUS_ADDR (EMAC_DESCRIPTOR_ADDR + TX_DESCRIPTOR_SIZE) +#define RX_DESCRIPTOR_ADDR (TX_STATUS_ADDR + TX_STATUS_SIZE) +#define RX_STATUS_ADDR (RX_DESCRIPTOR_ADDR + RX_DESCRIPTOR_SIZE) + +#define EMAC_DMA_ADDR EMAC_RAM_ADDR +#define EMAC_DMA_SIZE EMAC_RAM_ADDR + EMAC_RAM_END - TOTAL_DESCRIPTOR_SIZE + +#define EMAC_BLOCK_SIZE 0x600 +#define EMAC_TX_BLOCK_NUM 5 +#define EMAC_RX_BLOCK_NUM 5 +#define TOTAL_EMAC_BLOCK_NUM 10 + +#define EMAC_BUFFER_SIZE (EMAC_BLOCK_SIZE * (EMAC_TX_BLOCK_NUM + EMAC_RX_BLOCK_NUM )) +#define EMAC_TX_BUFFER_ADDR EMAC_RAM_ADDR +#define EMAC_RX_BUFFER_ADDR (EMAC_RAM_ADDR + EMAC_BLOCK_SIZE * EMAC_TX_BLOCK_NUM) + +/* EMAC Descriptor TX and RX Control fields */ +#define EMAC_TX_DESC_INT 0x80000000 +#define EMAC_TX_DESC_LAST 0x40000000 +#define EMAC_TX_DESC_CRC 0x20000000 +#define EMAC_TX_DESC_PAD 0x10000000 +#define EMAC_TX_DESC_HUGE 0x08000000 +#define EMAC_TX_DESC_OVERRIDE 0x04000000 + +#define EMAC_RX_DESC_INT 0x80000000 + +/* EMAC Descriptor status related definition */ +#define TX_DESC_STATUS_ERR 0x80000000 +#define TX_DESC_STATUS_NODESC 0x40000000 +#define TX_DESC_STATUS_UNDERRUN 0x20000000 +#define TX_DESC_STATUS_LCOL 0x10000000 +#define TX_DESC_STATUS_ECOL 0x08000000 +#define TX_DESC_STATUS_EDEFER 0x04000000 +#define TX_DESC_STATUS_DEFER 0x02000000 +#define TX_DESC_STATUS_COLCNT 0x01E00000 /* four bits, it's a mask, not exact count */ + +#define RX_DESC_STATUS_ERR 0x80000000 +#define RX_DESC_STATUS_LAST 0x40000000 +#define RX_DESC_STATUS_NODESC 0x20000000 +#define RX_DESC_STATUS_OVERRUN 0x10000000 +#define RX_DESC_STATUS_ALGNERR 0x08000000 +#define RX_DESC_STATUS_RNGERR 0x04000000 +#define RX_DESC_STATUS_LENERR 0x02000000 +#define RX_DESC_STATUS_SYMERR 0x01000000 +#define RX_DESC_STATUS_CRCERR 0x00800000 +#define RX_DESC_STATUS_BCAST 0x00400000 +#define RX_DESC_STATUS_MCAST 0x00200000 +#define RX_DESC_STATUS_FAILFLT 0x00100000 +#define RX_DESC_STATUS_VLAN 0x00080000 +#define RX_DESC_STATUS_CTLFRAM 0x00040000 + +#define DESC_SIZE_MASK 0x000007FF /* 11 bits for both TX and RX */ + +/* EMAC interrupt controller related definition */ +#define EMAC_INT_RXOVERRUN 0x01 << 0 +#define EMAC_INT_RXERROR 0x01 << 1 +#define EMAC_INT_RXFINISHED 0x01 << 2 +#define EMAC_INT_RXDONE 0x01 << 3 +#define EMAC_INT_TXUNDERRUN 0x01 << 4 +#define EMAC_INT_TXERROR 0x01 << 5 +#define EMAC_INT_TXFINISHED 0x01 << 6 +#define EMAC_INT_TXDONE 0x01 << 7 +#define EMAC_INT_SOFTINT 0x01 << 12 +#define EMAC_INT_WOL 0x01 << 13 + +#define PHY_BMCR 0x0000 +#define PHY_BMSR 0x0001 +#define PHY_PHYIDR1 0x0002 +#define PHY_PHYIDR2 0x0003 +#define PHY_ANAR 0x0004 +#define PHY_ANLPAR 0x0005 +#define PHY_ANLPARNP 0x0005 +#define PHY_ANER 0x0006 +#define PHY_ANNPTR 0x0007 + +/* BMCR setting */ +#define BMCR_RESET 0x8000 +#define BMCR_LOOPBACK 0x4000 +#define BMCR_SPEED_100 0x2000 +#define BMCR_AN 0x1000 +#define BMCR_POWERDOWN 0x0800 +#define BMCR_ISOLATE 0x0400 +#define BMCR_RE_AN 0x0200 +#define BMCR_DUPLEX 0x0100 + +/* BMSR setting */ +#define BMSR_100BE_T4 0x8000 +#define BMSR_100TX_FULL 0x4000 +#define BMSR_100TX_HALF 0x2000 +#define BMSR_10BE_FULL 0x1000 +#define BMSR_10BE_HALF 0x0800 +#define BMSR_AUTO_DONE 0x0020 +#define BMSR_REMOTE_FAULT 0x0010 +#define BMSR_NO_AUTO 0x0008 +#define BMSR_LINK_ESTABLISHED 0x0004 + +#define MII_BMSR_TIMEOUT 0x1000000 + +#define CMD_RX_ENABLE 0x01 +#define CMD_TX_ENABLE 0x02 +#define CMD_PASS_RX_FILTER 0x80 + +/* Helper macros */ +#define BFS32(reg,value) writel( (readl(reg)|=(value)) ,reg) +#define BFC32(reg,value) writel( (readl(reg)&=(~value)) ,reg) + +#endif diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index bb99a34..929fb5a 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -39,6 +39,7 @@ COBJS-$(CONFIG_IMX_SERIAL) += serial_imx.o COBJS-$(CONFIG_IXP_SERIAL) += serial_ixp.o COBJS-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o COBJS-$(CONFIG_LPC2292_SERIAL) += serial_lpc2292.o +COBJS-$(CONFIG_LPC2468_SERIAL) += serial_lpc2468.o COBJS-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o COBJS-$(CONFIG_MX31_UART) += serial_mx31.o COBJS-$(CONFIG_NETARM_SERIAL) += serial_netarm.o diff --git a/drivers/serial/serial_lpc2468.c b/drivers/serial/serial_lpc2468.c new file mode 100644 index 0000000..4b8f241 --- /dev/null +++ b/drivers/serial/serial_lpc2468.c @@ -0,0 +1,119 @@ +/* + * (C) Copyright 2002-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger mgroeger@sysgo.de + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke azu@sysgo.de + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include <common.h> +#include <asm/arch/immap.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +void serial_setbrg (void) +{ + unsigned short divisor; + uart_2468_t *uart0=&(((immap_t *)CONFIG_SYS_IMMAP)->apb.uart0); + + switch (gd->baudrate) { + case 1200: + case 9600: + case 19200: + case 38400: + case 57600: + case 115200: + divisor = CFG_SYS_CLK_FREQ / (gd->baudrate * 16); + break; + default: + hang (); + break; + } + + /* init serial UART0 */ + writeb (0, &(uart0->iir_fcr)); /* Disable RX and TX FIFOs */ + writeb (0, &(uart0->lcr)); + writeb (0, &(uart0->ier_dlm)); + writeb (0x80, &(uart0->lcr)); /* DLAB=1 */ + writeb ((unsigned char)(divisor & 0x00FF), &(uart0->rbr_thr_dll)); + writeb ((unsigned char)(divisor >> 8),&(uart0->ier_dlm)); + writeb (0x03, &(uart0->lcr)); /* 8N1, DLAB=0 */ + writeb (0x7, &(uart0->iir_fcr)); /* Enable RX and TX FIFOs */ +} + +int serial_init (void) +{ + unsigned long pinsel0; + pin_connect_2468_t *pin_connect= + &(((immap_t *)CONFIG_SYS_IMMAP)->apb.pin_connect); + + /*enable uart #0 pins in GPIO (P0.2 = TxD0, P0.3 = RxD0) */ + pinsel0 = readl (&(pin_connect->pinsel0)); + pinsel0 &= ~(0x000000f0); + pinsel0 |= 0x00000050; + writel (pinsel0, &(pin_connect->pinsel0)); + + serial_setbrg (); + + return (0); +} + +void serial_putc (const char c) +{ + uart_2468_t *uart0=&(((immap_t *)CONFIG_SYS_IMMAP)->apb.uart0); + + if (c == '\n') { + /* Wait for empty U0THR */ + while ((readb (&(uart0->lsr)) & (1 << 5)) == 0) ; + writeb ('\r', &(uart0->rbr_thr_dll)); + } + /* Wait for empty U0THR */ + while ((readb (&(uart0->lsr)) & (1 << 5)) == 0) ; + writeb (c, &(uart0->rbr_thr_dll)); +} + +int serial_getc (void) +{ + uart_2468_t *uart0=&(((immap_t *)CONFIG_SYS_IMMAP)->apb.uart0); + + while ((readb (&(uart0->lsr)) & 1) == 0) ; + return readb (&(uart0->rbr_thr_dll)); +} + +void serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +/* Test if there is a byte to read */ +int serial_tstc (void) +{ + uart_2468_t *uart0=&(((immap_t *)CONFIG_SYS_IMMAP)->apb.uart0); + + return (readb (&(uart0->lsr)) & 1); +} diff --git a/include/asm-arm/arch-lpc24xx/hardware.h b/include/asm-arm/arch-lpc24xx/hardware.h new file mode 100644 index 0000000..b42746e --- /dev/null +++ b/include/asm-arm/arch-lpc24xx/hardware.h @@ -0,0 +1,32 @@ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +/* + * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) + * Curt Brune curt@cucy.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#if defined(CONFIG_LPC2468) +#else +#error No hardware file defined for this configuration +#endif + +#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-lpc24xx/immap.h b/include/asm-arm/arch-lpc24xx/immap.h new file mode 100644 index 0000000..ab25dd5 --- /dev/null +++ b/include/asm-arm/arch-lpc24xx/immap.h @@ -0,0 +1,406 @@ +/* + * (C) Copyright 2009 Duran Audio B.V. + * + * LPC2468 Internal Memory Map + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __LPC24XX_IMMAP_H +#define __LPC24XX_IMMAP_H + +#include <asm/types.h> +#include <config.h> + +typedef struct watchdog_2468 { + u8 fixme[0x4000]; +} watchdog2468_t; + +typedef struct timer_2468 { + u32 ir; /* Interrupt register */ + u32 tcr; /* Timer control register */ + u32 tc; /* Timer counter */ + u32 pr; /* Prescale register */ + u32 pc; /* Prescale counter */ + u32 mcr; /* Match control register */ + u32 mr0; /* Match register 0 */ + u32 mr1; /* Match register 1 */ + u32 mr2; /* Match register 2 */ + u32 mr3; /* Match register 3 */ + u32 ccr; /* Capture control register */ + u32 cr0; /* Capture register 0 */ + u32 cr1; /* Capture register 1 */ + u32 cr2; /* Capture register 2 */ + u32 cr3; /* Capture register 3 */ + u32 emr; /* External match register */ + u32 ctcr; /* Count control register */ + u8 notused[0x3fbc]; +} timer_2468_t; + +/*These two UART structs can probably be combined*/ +typedef struct uart_2468 { + u32 rbr_thr_dll; /*Receive buffer/transmit holding/divisor latch lsb register */ + u32 ier_dlm; /*Interrupt enable/divisor latch msb register */ + u32 iir_fcr; /*Interrupt ID/FIFO control register */ + u32 lcr; /* Line control register */ + u32 notused1; + u32 lsr; /*Line status register */ + u32 notused2; + u32 scr; /*Scratch pad register */ + u32 acr; /*Auto-baud control register */ + u32 icr; /*IrDA control register */ + u32 fdr; /*Fractional division register */ + u32 notused3; + u32 ter; /* Transmit enable register */ + u8 notused[0x3fcc]; +} uart_2468_t; + +typedef struct uart1_2468 { + u8 fixme[0x4000]; +} uart1_2468_t; + +typedef struct pwm0_2468 { + u8 fixme[0x4000]; +} pwm0_2468_t; + +typedef struct pwm1_2468 { + u8 fixme[0x4000]; +} pwm1_2468_t; + +typedef struct i2c0_2468 { + u8 fixme[0x4000]; +} i2c0_2468_t; + +typedef struct spi_2468 { + u8 fixme[0x4000]; +} spi_2468_t; + +typedef struct rtc_2468 { + u8 fixme[0x4000]; +} rtc_2468_t; + +typedef struct gpio_2468 { + u8 fixme[0x4000]; +} gpio_2468_t; + +typedef struct pin_connect_2468 { + u32 pinsel0; /*Pin function select register*/ + u32 pinsel1; + u32 pinsel2; + u32 pinsel3; + u32 pinsel4; + u32 pinsel5; + u32 pinsel6; + u32 pinsel7; + u32 pinsel8; + u32 pinsel9; + u32 pinsel10; + u32 pinsel11; + u32 pinmode0; /*Pin mode select register*/ + u32 pinmode1; + u32 pinmode2; + u32 pinmode3; + u32 pinmode4; + u32 pinmode5; + u32 pinmode6; + u32 pinmode7; + u32 pinmode8; + u32 pinmode9; + u8 fixme[0x3fa8]; +} pin_connect_2468_t; + +typedef struct ssp1_2468 { + u8 fixme[0x4000]; +} ssp1_2468_t; + +typedef struct adc_2468 { + u8 fixme[0x4000]; +} adc_2468_t; + +typedef struct can_accept_ram_2468 { + u8 fixme[0x4000]; +} can_accept_ram_2468_t; + +typedef struct can_accept_filter_2468 { + u8 fixme[0x4000]; +} can_accept_filter_2468_t; + +typedef struct can_common_2468 { + u8 fixme[0x4000]; +} can_common_2468_t; + +typedef struct can1_2468 { + u8 fixme[0x4000]; +} can1_2468_t; + +typedef struct can2_2468 { + u8 fixme[0x4000]; +} can2_2468_t; + +typedef struct i2c1_2468 { + u8 fixme[0x4000]; +} i2c1_2468_t; + +typedef struct ssp0_2468 { + u8 fixme[0x4000]; +} ssp0_2468_t; + +typedef struct dac_2468 { + u8 fixme[0x4000]; +} dac_2468_t; + +typedef struct i2c2_2468 { + u8 fixme[0x4000]; +} i2c2_2468_t; + +typedef struct batt_ram_2468 { + u8 fixme[0x4000]; +} batt_ram_2468_t; + +typedef struct i2s_2468 { + u8 fixme[0x4000]; +} i2s_2468_t; + +typedef struct mmc_2468 { + u8 fixme[0x4000]; +} mmc_2468_t; + +typedef struct sys_con_2468 { + u8 notused1[0x40]; + u32 memmap; /*Memory mapping control register c040*/ + u8 notused2[0x80]; + u32 pconp; /*Power control for peripherals register c0c4*/ + u8 notused3[0x7c]; + u32 extint; /*External interrupt flag register c140*/ + u32 extmode; /*External interrupt mode resgister c148*/ + u32 extpolar; /*External interrupt polarity register c14c*/ + u8 notused4[0x30]; + u32 rsid; /*Reset source identification register c180*/ + u32 cspr; /*Code security protection register c184*/ + u8 notused5[0x18]; + u32 scs; /*System control and status register c1a0*/ + u8 notused6[0x3e5c]; +} sys_con_2468_t; + + +typedef struct mac_2468 { + u32 mac1; /* MAC configuration register 1 */ + u32 mac2; /* MAC configuration register 2 */ + u32 ipgt; /* Back-to-back Inter-Packet-Gap register */ + u32 ipgr; /* Non Back-to-back Inter-Packet-Gap register */ + u32 clrt; /* Collision window/Retry register */ + u32 maxf; /* Maximum frame register */ + u32 supp; /* PHY support register */ + u32 test; /* Test register */ + u32 mcfg; /* MII mgmt Configuration register */ + u32 mcmd; /* MII mgmt Command register */ + u32 madr; /* MII mgmt Address register */ + u32 mwtd; /* MII mgmt Write data register */ + u32 mrdd; /* MII mgmt Read data register */ + u32 mind; /* MII mgmt Indicators register */ + u8 reserved1[0x8]; + u32 sa0; /* Station Address 0 register */ + u32 sa1; /* Station Address 1 register */ + u32 sa2; /* Station Address 2 register */ + u8 reserved2[0xb4]; + u32 command; /* Command register */ + u32 status; /* Status register */ + u32 rxdescriptor; /* Receive descriptor base address register */ + u32 rxstatus; /* Receive status base address register */ + u32 rxdescriptornumber; /* Receive number of descriptors register */ + u32 rxproduceindex; /* Receive produce index register */ + u32 rxconsumeindex; /* Receive consume index register */ + u32 txdescriptor; /* Transmit descriptor base address register */ + u32 txstatus; /* Transmit status base address register */ + u32 txdescriptornumber; /* Transmit number of descriptors register */ + u32 txproduceindex; /* Transmit produce index register */ + u32 txconsumeindex; /* Transmite consume index register */ + u8 reserved3[0x28]; + u32 tsv0; /* Transmit status vector 0 register */ + u32 tsv1; /* Transmit status vector 1 register */ + u32 rsv; /* Receive status vector register */ + u8 reserved4[0xc]; + u32 flowcontrolcounter; /*Flow control counter register */ + u32 flowcontrolstatus; /* Flow control status register */ + u8 reserved5[0x88]; + u32 rxfilterctrl; /* Receive filter control register */ + u32 rxfilterwolstatus; /* Receive filter WoL status register */ + u32 rxfilterwolclear; /* Receive filter WoL clear register */ + u8 reserved6[0x4]; + u32 hashfilterL; /* Hash filter LSBs register */ + u32 hashfilterH; /* Hash filter MSBs register */ + u8 reserved7[0xdc8]; + u32 intstatus; /* Interrupt status register */ + u32 intenable; /* Interrupt enable register */ + u32 intclear; /* Interrupt clear register */ + u32 intset; /* Interrupt set register */ + u8 reserved8[0x4]; + u32 powerdown; /* Powerdown register */ + u8 notused[0x3008]; +} mac_2468_t; + +typedef struct gpdma__2468 { + u8 fixme[0x4000]; +} gpdma_2468_t; + +typedef struct ext_mem_2468 { + u8 fixme[0x4000]; +} ext_mem_2468_t; + +typedef struct usb_2468 { + u8 fixme[0x4000]; +} usb_2468_t; + +typedef struct lcd_2468 { + u8 fixme[0x4000]; +} lcd_2468_t; + +typedef struct vic_2468 { + u32 vicirqstat; /*IRQ status register */ + u32 vicfiqstat; /*FIQ status register */ + u32 vicrawintr; /*Raw interrupt status register */ + u32 vicintselect; /*Interrupt select register */ + u32 vicintenable; /*Interrupt enable register */ + u32 vicinenclr; /*Interrupt enable clear register */ + u32 vicsoftint; /*Software interrupt register */ + u32 vicsoftintclr; /*Software interrupt clear register */ + u32 vicprotect; /*Protection enable register */ + u32 vicswpriomask; /*Software Priority Mask Register */ + u8 notused1[0xd8]; + u32 vicvectaddr0; /*Vector address register */ + u32 vicvectaddr1; + u32 vicvectaddr2; + u32 vicvectaddr3; + u32 vicvectaddr4; + u32 vicvectaddr5; + u32 vicvectaddr6; + u32 vicvectaddr7; + u32 vicvectaddr8; + u32 vicvectaddr9; + u32 vicvectaddr10; + u32 vicvectaddr11; + u32 vicvectaddr12; + u32 vicvectaddr13; + u32 vicvectaddr14; + u32 vicvectaddr15; + u32 vicvectaddr16; + u32 vicvectaddr17; + u32 vicvectaddr18; + u32 vicvectaddr19; + u32 vicvectaddr20; + u32 vicvectaddr21; + u32 vicvectaddr22; + u32 vicvectaddr23; + u32 vicvectaddr24; + u32 vicvectaddr25; + u32 vicvectaddr26; + u32 vicvectaddr27; + u32 vicvectaddr28; + u32 vicvectaddr29; + u32 vicvectaddr30; + u32 vicvectaddr31; + u8 notused2[0x7f]; + u32 vicvectprio0; /*Vector priority register */ + u32 vicvectprio1; + u32 vicvectprio2; + u32 vicvectprio3; + u32 vicvectprio4; + u32 vicvectprio5; + u32 vicvectprio6; + u32 vicvectprio7; + u32 vicvectprio8; + u32 vicvectprio9; + u32 vicvectprio10; + u32 vicvectprio11; + u32 vicvectprio12; + u32 vicvectprio13; + u32 vicvectprio14; + u32 vicvectprio15; + u32 vicvectprio16; + u32 vicvectprio17; + u32 vicvectprio18; + u32 vicvectprio19; + u32 vicvectprio20; + u32 vicvectprio21; + u32 vicvectprio22; + u32 vicvectprio23; + u32 vicvectprio24; + u32 vicvectprio25; + u32 vicvectprio26; + u32 vicvectprio27; + u32 vicvectprio28; + u32 vicvectprio29; + u32 vicvectprio30; + u32 vicvectprio31; + u8 notused3[0xc7f]; + u32 vicaddr; /*Vector address register for active interrupt*/ +} vic_2468_t; + +typedef struct apb_2468 { /*Peripheral bus memory layout*/ + watchdog2468_t watchdog; + timer_2468_t timer0; + timer_2468_t timer1; + uart_2468_t uart0; + uart1_2468_t uart1; + pwm0_2468_t pwm0; + pwm1_2468_t pwm1; + i2c0_2468_t i2c0; + spi_2468_t spi; + rtc_2468_t rtc; + gpio_2468_t gpio; + pin_connect_2468_t pin_connect; + ssp1_2468_t ssp1; + adc_2468_t adc; + can_accept_ram_2468_t can_accept_ram; + can_accept_filter_2468_t can_accept_filter; + can_common_2468_t can_comon; + can1_2468_t can1; + can2_2468_t can2; + u8 not_used1[0x10000]; + i2c1_2468_t i2c1; + u8 notused2[0x8000]; + ssp0_2468_t ssp0; + dac_2468_t dac; + timer_2468_t timer2; + timer_2468_t timer3; + uart_2468_t uart2; + uart_2468_t uart3; + i2c2_2468_t i2c2; + batt_ram_2468_t batt_ram; + i2s_2468_t i2s; + mmc_2468_t mmc; + u8 not_used3[0x16c000]; + sys_con_2468_t sys_con; +} apb_2468_t; + +typedef struct ahb_2468 { /*High-speed bus memory layout*/ + mac_2468_t mac; + gpdma_2468_t gpdma; + ext_mem_2468_t ext_mem; + usb_2468_t usb; + lcd_2468_t lcd; + u8 notused1[0x1eb000]; + vic_2468_t vic; +} ahb_2468_t; + +typedef struct immap { /*LPC24xx memory layout*/ + apb_2468_t apb; /*Peripheral bus*/ + u8 res1[0x1fc00000]; + ahb_2468_t ahb; /*High-speed bus*/ +} immap_t; + +#endif diff --git a/include/asm-arm/config.h b/include/asm-arm/config.h index 049c44e..2d46a34 100644 --- a/include/asm-arm/config.h +++ b/include/asm-arm/config.h @@ -21,4 +21,8 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_
+#if defined(CONFIG_LPC2292) || defined(CONFIG_LPC2468) +#define CONFIG_LPC2000 +#endif + #endif diff --git a/include/flash.h b/include/flash.h index b016162..ac4a705 100644 --- a/include/flash.h +++ b/include/flash.h @@ -337,6 +337,7 @@ extern flash_info_t *flash_get_info(ulong base); #define TOSH_ID_FVT160 0xC2 /* TC58FVT160 ID (16 M, top ) */ #define TOSH_ID_FVB160 0x43 /* TC58FVT160 ID (16 M, bottom ) */ #define PHILIPS_LPC2292 0x0401FF13 /* LPC2292 internal FLASH */ +#define PHILIPS_LPC2468 0x0603FF35 /* LPC2468 internal FLASH */
/*----------------------------------------------------------------------- * Internal FLASH identification codes
Hi Remco,
Remco Poelstra wrote:
This patch includes support for the LPC2468 processor from NXP.
Signed-off-by: Remco Poelstra remco.poelstra+u-boot@duran-audio.com
It now also includes support for the ethernet interface. It does not include any changes to flash related code, until it's known where to put it. Stefan was right that the unreferenced function are needed by the board code. Neither does it contain any significant changes to the interrupt code, waiting for the patch to clean it up. I would be gratefull if the patch can be applied before then, I can then help clean up the code, instead of staying behind. Concerning thumb code: As explained earlier, it is needed to call the internal IAP functions. These are seldom used, so there is no performance penalty.
Please break this up into orthogonal patches by functionality. I'll comment on the net driver here, but will likely have more comments once the major issues are taken care of :) : <snip>
diff --git a/drivers/net/lpc2468_eth.c b/drivers/net/lpc2468_eth.c new file mode 100644 index 0000000..b16e404 --- /dev/null +++ b/drivers/net/lpc2468_eth.c @@ -0,0 +1,494 @@ +/*
- (C) Copyright 2009 Duran Audio B.V. <www.duran-audio.com>
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- 18-03-2009 Updated for U-boot 2009.3
- by Remco Poelstra remco.poelstra+u-boot@duran-audio.com
- Based on sample code from NXP
- */
+#include <config.h> +#include <common.h> +#include <net.h> +#include <asm/io.h> +#include <asm/arch/immap.h> +#include "lpc2468_eth.h"
+/******************************************************************************
- Local variables
- *****************************************************************************/
+static unsigned char macAddr[6]; +static volatile int phyAddr = 0x1000; +static int eth_initialized = 0; +mac_2468_t *mac=&(((immap_t *)CONFIG_SYS_IMMAP)->ahb.mac);
Please encapsulate these in a 'priv' data structure. More on that later...
+/******************************************************************************
- Local functions
- *****************************************************************************/
+static void writePhy (u32 phyReg, u32 phyData) +{
- /* write command */
- writel (0x0, &(mac->mcmd));
- /* [12:8] == PHY addr, [4:0]=0x00(BMCR) register addr */
- writel ((phyAddr | phyReg), &(mac->madr));
- writel (phyData, &(mac->mwtd));
I don't know if 'writel' and 'readl' are the correct accessors for ARM. Hopefully somebody'll chime in on that.
- while (readl (&(mac->mind)) != 0) ;
+}
+static u32 readPhy (u32 phyReg) +{
- /* read command */
- writel (0x1, &(mac->mcmd));
- /* [12:8] == PHY addr, [4:0]=0x00(BMCR) register addr */
- writel ((phyAddr | phyReg), &(mac->madr));
- while (readl (&(mac->mind)) != 0);
- writel (0x0, &(mac->mcmd));
- return readl (&(mac->mrdd));
+}
+static int emac_start_xmit (volatile void *buf, int length) +{
- u32 txProduceIndex = 0;
- u32 txConsumeIndex = 0;
- u8 *pData = 0;
- u32 len = length;
- u32 sendLen = 0;
- u32 *tx_desc_addr = NULL;
- txProduceIndex = readl (&(mac->txproduceindex));
- txConsumeIndex = readl (&(mac->txconsumeindex));
- if (txConsumeIndex != txProduceIndex) {
/* TODO why return here? This just means that the transmit array isn't empty */
Good question... Please resolve before submitting.
printf ("emac: emac_tx transmit array isn't empty\n");return -1;- }
- if (txProduceIndex == EMAC_TX_DESCRIPTOR_COUNT) {
/* should never happen */printf ("emac: emac_tx produce index == count\n");- }
- if (len > 0) {
pData = (u8 *) EMAC_TX_BUFFER_ADDR;memcpy (pData, (void *)buf, length);do {tx_desc_addr =(u32 *) (TX_DESCRIPTOR_ADDR + txProduceIndex * 8);sendLen = len;if (sendLen > EMAC_BLOCK_SIZE) {sendLen = EMAC_BLOCK_SIZE;} else {/* last fragment */sendLen |= EMAC_TX_DESC_LAST;}writel ((unsigned long) pData, tx_desc_addr);tx_desc_addr++;writel ((u32) (EMAC_TX_DESC_INT | (sendLen - 1)),tx_desc_addr);txProduceIndex++;if (txProduceIndex == EMAC_TX_DESCRIPTOR_COUNT) {txProduceIndex = 0;}writel (txProduceIndex, &(mac->txproduceindex));len -= (sendLen & ~EMAC_TX_DESC_LAST);pData += (sendLen & ~EMAC_TX_DESC_LAST);} while (len > 0);- }
- return 0;
+}
+static void emac_rx (void) +{
- u32 rxProduceIndex = 0;
- u32 rxConsumeIndex = 0;
- u32 *rxStatusAddr = 0;
- u32 recvSize = 0;
- u32 *recvAddr = 0;
- /* the input parameter, EMCBuf, needs to be word aligned */
- rxProduceIndex = readl (&(mac->rxproduceindex));
- rxConsumeIndex = readl (&(mac->rxconsumeindex));
- /* consume the received packets */
- while (rxConsumeIndex != rxProduceIndex) {
rxStatusAddr = (u32 *) (RX_STATUS_ADDR + rxConsumeIndex * 8);recvSize = readl (rxStatusAddr);if ((recvSize & RX_DESC_STATUS_LAST) == 0) {/* TODO: could this occur when EMAC_BLOCK_SIZE == 0x0600? */printf ("emac_rx: NOT LAST fragment\n");}recvSize = (recvSize & DESC_SIZE_MASK) + 1;recvAddr = (u32 *) (RX_DESCRIPTOR_ADDR + rxConsumeIndex * 8);/* TODO: allocate buffer? */NetReceive ((uchar *) (readl (recvAddr) /*inBuf */ ),recvSize);rxConsumeIndex++;if (rxConsumeIndex == EMAC_RX_DESCRIPTOR_COUNT) {rxConsumeIndex = 0;}writel (rxConsumeIndex, &(mac->rxconsumeindex));- }
+}
+static void emac_interrupt (void) +{
Do you really intend to use interrupts? If this is dead code, please remove it.
- volatile u32 regValue = 0;
- regValue = readl (&(mac->intstatus));
- do {
if (regValue == 0) {break;}if (regValue & EMAC_INT_RXOVERRUN) {writel (EMAC_INT_RXOVERRUN, &(mac->intclear));printf ("rxOverrun\n");break;}if (regValue & EMAC_INT_RXERROR) {writel (EMAC_INT_RXERROR, &(mac->intclear));}if (regValue & EMAC_INT_RXFINISHED) {writel (EMAC_INT_RXFINISHED, &(mac->intclear));}if (regValue & EMAC_INT_RXDONE) {writel (EMAC_INT_RXDONE, &(mac->intclear));emac_rx ();}if (regValue & EMAC_INT_TXUNDERRUN) {printf ("TX underrun\n");writel (EMAC_INT_TXUNDERRUN, &(mac->intclear));break;}if (regValue & EMAC_INT_TXERROR) {printf ("TX err\n");writel (EMAC_INT_TXERROR, &(mac->intclear));break;}if (regValue & EMAC_INT_TXFINISHED) {writel (EMAC_INT_TXFINISHED, &(mac->intclear));}if (regValue & EMAC_INT_TXDONE) {writel (EMAC_INT_TXDONE, &(mac->intclear));}- } while (0);
+}
+static int emac_open (void) +{
- /* enable Rx & Tx */
- BFS32 (&(mac->command), CMD_RX_ENABLE);
- BFS32 (&(mac->command), CMD_TX_ENABLE);
- BFS32 (&(mac->command), CMD_PASS_RX_FILTER);
- BFS32 (&(mac->mac1), 0x01);
- return 0;
+}
+static void emac_close (void) +{
- /* disable Rx6 Tx */
- BFC32 (&(mac->command), CMD_RX_ENABLE);
- BFC32 (&(mac->command), CMD_TX_ENABLE);
- BFC32 (&(mac->mac1), 0x01);
+}
+static int phyInit (void) +{
- int i = 0;
- u32 regValue = 0;
- u32 timeout = 0;
- writel (0x801C, &(mac->mcfg)); /* host clock divided by 28,
no suppress preamble,no scan increment */- for (i = 0; i < 0x40; i++)
asm volatile (" nop");- /* MII Mgmt. Divided by 28. */
- writel (0x001C, &(mac->mcfg));
- writel (0x0, &(mac->mcmd));
- for (i = 0; i < 0x100; i++)
asm volatile (" nop");- /*Reset the PHY */
- writePhy (PHY_BMCR, BMCR_RESET);
- udelay (100);
- timeout = MII_BMSR_TIMEOUT * 4;
- while (timeout != 0) {
regValue = readPhy (PHY_BMCR);if ((regValue & BMCR_RESET) == 0x0000) {/* reset bit has been cleared */break;}timeout--;- }
- if (timeout == 0) {
printf (" Error: phyInit failed to reset PHY\n");return -1;- }
- return 0;
+}
+static void emacTxDescriptorInit (void) +{
- int i = 0;
- u32 *txDescAddr = NULL;
- u32 *txStatusAddr = NULL;
- /* base address of tx descriptor array */
- writel (TX_DESCRIPTOR_ADDR, &(mac->txdescriptor));
- /* base address of tx status */
- writel (TX_STATUS_ADDR, &(mac->txstatus));
- /* number of tx descriptors */
- writel (EMAC_TX_DESCRIPTOR_COUNT - 1, &(mac->txdescriptornumber));
- for (i = 0; i < EMAC_TX_DESCRIPTOR_COUNT; i++) {
txDescAddr = (u32 *) (TX_DESCRIPTOR_ADDR + i * 8);writel ((EMAC_TX_BUFFER_ADDR + i * EMAC_BLOCK_SIZE),(unsigned long)txDescAddr);/* control field in descriptor */txDescAddr++;writel ((EMAC_TX_DESC_INT | (EMAC_BLOCK_SIZE - 1)),(unsigned long)txDescAddr);- }
- for (i = 0; i < EMAC_TX_DESCRIPTOR_COUNT; i++) {
txStatusAddr = (u32 *) (TX_STATUS_ADDR + i * 4);/* set status info to 0 */writel (0x0, (unsigned long)txStatusAddr);- }
- writel (0x0, &(mac->txproduceindex));
+}
+static void emacRxDescriptorInit (void) +{
- int i;
- u32 *rxDescAddr = NULL;
- u32 *rxStatusAddr = NULL;
- /* base address of rx descriptor array */
- writel (RX_DESCRIPTOR_ADDR, &(mac->rxdescriptor));
- /* base address of rx status */
- writel (RX_STATUS_ADDR, &(mac->rxstatus));
- /* number of rx descriptors */
- writel (EMAC_RX_DESCRIPTOR_COUNT - 1, &(mac->rxdescriptornumber));
- for (i = 0; i < EMAC_RX_DESCRIPTOR_COUNT; i++) {
rxDescAddr = (u32 *) (RX_DESCRIPTOR_ADDR + i * 8);writel ((EMAC_RX_BUFFER_ADDR + i * EMAC_BLOCK_SIZE),(unsigned long)rxDescAddr);rxDescAddr++;writel ((EMAC_RX_DESC_INT |((EMAC_BLOCK_SIZE - 1) & DESC_SIZE_MASK)),(unsigned long)rxDescAddr);- }
- for (i = 0; i < EMAC_RX_DESCRIPTOR_COUNT; i++) {
/* RX status, two words, status info. and status hash CRC. */rxStatusAddr = (u32 *) (RX_STATUS_ADDR + i * 8);writel (0x0, (unsigned long)rxStatusAddr);rxStatusAddr++;writel (0x0, (unsigned long)rxStatusAddr);- }
- writel (0x0, &(mac->rxconsumeindex));
+}
+static int emacInit (void) +{
- int i = 0;
- pin_connect_2468_t *pin_connect=&(((immap_t *)CONFIG_SYS_IMMAP)->apb.pin_connect);
- /* turn on the ethernet MAC clock in PCONP, bit 30 */
- BFS32 (&(((immap_t *)CONFIG_SYS_IMMAP)->apb.sys_con.pconp), PCONP_EMAC_CLOCK);
- /*-----------------------------------------------------------------------
- write to PINSEL2/3 to select the PHY functions on P1[17:0]
- *-----------------------------------------------------------------------*/
- /* documentation needs to be updated */
- writel (0x55555555, &(pin_connect->pinsel2)); /* selects P1[0,1,4,8,9,10,14,15] */
- writel (0x00000005, &(pin_connect->pinsel3)); /* selects P1[17:16] */
This looks to me like board code. If it is, it doesn't belong in this driver.
- /*reset MAC modules, tx, mcs_tx, rx, mcs_rx, simulation and soft reset*/
- writel (0xCF00, &(mac->mac1));
- /* reset datapaths and host registers */
- writel (0x0038, &(mac->command));
- /* short delay after reset */
- for (i = 0; i < 0x40; i++)
asm volatile (" nop");- /*Remove reset conditions*/
- writel (0x0, &(mac->mac1));
- /*disable Tx*/
- BFC32 (&(mac->command), CMD_TX_ENABLE);
- /*disable Rx*/
- BFC32 (&(mac->command), CMD_RX_ENABLE);
- /*initialize MAC2 to default value
TODO don't thinkt this is necessary?? m_nic_write(EMAC_MAC2, 0x0);*/- writel (0x030, &(mac->mac2));
- /*non back-to-back Inter-Packet-Gap register
The manual recommends the value 0x12 */- writel (0x12, &(mac->ipgr));
- /*collision window/retry register. Using recommended value from manual*/
- writel (0x370F, &(mac->clrt));
- /* intialize PHY. */
- if (phyInit () < 0)
return -1;- /* write the mac address */
- writel ((macAddr[5] << 8 | macAddr[4]), &(mac->sa0));
- writel ((macAddr[3] << 8 | macAddr[2]), &(mac->sa1));
- writel ((macAddr[1] << 8 | macAddr[0]), &(mac->sa2));
- printf ("emac: MAC address = %2x:%2x:%2x:%2x:%2x:%2x\n",
macAddr[0],macAddr[1], macAddr[2], macAddr[3], macAddr[4], macAddr[5]);- emacTxDescriptorInit ();
- emacRxDescriptorInit ();
- /* pass all receive frames */
- BFS32 (&(mac->mac1), 0x002);
- /* set up the Rx filter
[0]-AllUnicast, [1]-AllBroadCast, [2]-AllMulticast, [3]-UnicastHash[4]-MulticastHash, [5]-Perfect, [12]-MagicPacketEnWoL,[13]-RxFilterEnWoLPUT32(MAC_RXFILTERCTRL, 0x0022); */- writel (0x003F, &(mac->rxfilterctrl)); /*Pass everything */
- /* clear all interrupts */
- writel (0xFFFF, &(mac->intclear));
- /* enable interrupts (not SoftInt and WoL) */
- writel (0x00FF, &(mac->intenable));
- return 0;
+}
+/* ##############################
- u-boot interface
- ##############################
- */
Please don't use this old API. Instead, use the CONFIG_NET_MULTI API where a 'struct eth_device' is allocated, initialized and filled. This struct contains a 'priv' field that you can use to store the static variables that were defined at the top of the driver. The API you've used is on its way out. You'll find plenty of examples in drivers/net.
+/*
- Returns 0 when failes otherwise 1
- */
+int eth_init (bd_t * bis) +{
- int ret;
- if (!eth_initialized) {
if (!eth_getenv_enetaddr ("ethaddr", macAddr)) {printf ("Failed to get MAC address from environment\n");return 1;}ret = emacInit ();if (ret != 0) {return ret;}eth_initialized = 1;- }
- emac_open ();
- return 0;
+}
+int eth_send (volatile void *packet, int length) +{
- emac_start_xmit (packet, length);
- return 0;
+}
+/*-----------------------------------------------------------------------------
- Check for received packets. Call NetReceive for each packet. The return
- value is ignored by the caller.
- */
+int eth_rx (void) +{
- emac_interrupt ();
- return 0;
+}
+void eth_halt (void) +{
- emac_close ();
+} diff --git a/drivers/net/lpc2468_eth.h b/drivers/net/lpc2468_eth.h new file mode 100644 index 0000000..b1c4671 --- /dev/null +++ b/drivers/net/lpc2468_eth.h @@ -0,0 +1,159 @@ +#ifndef LPC2468_ETH_H +#define LPC2468_ETH_H
+/******************************************************************************
- Typedefs and defines
- *****************************************************************************/
+#define MAX_PHY_INIT_RETRY 10
+/* EMAC MODULE ID */ +#define OLD_EMAC_MODULE_ID ((0x3902 << 16) | 0x2000)
+/* MAC registers and parameters */ +#define PCONP_EMAC_CLOCK 0x40000000
+#define SPEED_100 1 +#define SPEED_10 0 +#define FULL_DUPLEX 1 +#define HALF_DUPLEX 0
+#define EMAC_RAM_ADDR 0x7FE00000 +#define EMAC_RAM_SIZE 0x00004000
+#define EMAC_TX_DESCRIPTOR_COUNT 5 +#define EMAC_RX_DESCRIPTOR_COUNT 4
+/*
- (Rx|Tx)Descriptor ::
- [4] packet - base address of the buffer containing the data
- [4] control - control information
- */
+#define TX_DESCRIPTOR_SIZE (EMAC_TX_DESCRIPTOR_COUNT * 8) +#define RX_DESCRIPTOR_SIZE (EMAC_RX_DESCRIPTOR_COUNT * 8)
+/*
- TxStatus ::
- [4] status
- */
+#define TX_STATUS_SIZE (EMAC_TX_DESCRIPTOR_COUNT * 4)
+/*
- RxStatus ::
- [4] status - receive status flags
- [4] statusHashCRC - concat of dest addr hash CRC and src addr CRC
- */
+#define RX_STATUS_SIZE (EMAC_RX_DESCRIPTOR_COUNT * 8)
+#define TOTAL_DESCRIPTOR_SIZE (TX_DESCRIPTOR_SIZE + RX_DESCRIPTOR_SIZE + TX_STATUS_SIZE + RX_STATUS_SIZE)
+/* descriptors are placed at the end of the emac address space */ +#define EMAC_DESCRIPTOR_ADDR (EMAC_RAM_ADDR + EMAC_RAM_SIZE - TOTAL_DESCRIPTOR_SIZE)
+#define TX_DESCRIPTOR_ADDR EMAC_DESCRIPTOR_ADDR +#define TX_STATUS_ADDR (EMAC_DESCRIPTOR_ADDR + TX_DESCRIPTOR_SIZE) +#define RX_DESCRIPTOR_ADDR (TX_STATUS_ADDR + TX_STATUS_SIZE) +#define RX_STATUS_ADDR (RX_DESCRIPTOR_ADDR + RX_DESCRIPTOR_SIZE)
+#define EMAC_DMA_ADDR EMAC_RAM_ADDR +#define EMAC_DMA_SIZE EMAC_RAM_ADDR + EMAC_RAM_END - TOTAL_DESCRIPTOR_SIZE
+#define EMAC_BLOCK_SIZE 0x600 +#define EMAC_TX_BLOCK_NUM 5 +#define EMAC_RX_BLOCK_NUM 5 +#define TOTAL_EMAC_BLOCK_NUM 10
+#define EMAC_BUFFER_SIZE (EMAC_BLOCK_SIZE * (EMAC_TX_BLOCK_NUM + EMAC_RX_BLOCK_NUM )) +#define EMAC_TX_BUFFER_ADDR EMAC_RAM_ADDR +#define EMAC_RX_BUFFER_ADDR (EMAC_RAM_ADDR + EMAC_BLOCK_SIZE * EMAC_TX_BLOCK_NUM)
+/* EMAC Descriptor TX and RX Control fields */ +#define EMAC_TX_DESC_INT 0x80000000 +#define EMAC_TX_DESC_LAST 0x40000000 +#define EMAC_TX_DESC_CRC 0x20000000 +#define EMAC_TX_DESC_PAD 0x10000000 +#define EMAC_TX_DESC_HUGE 0x08000000 +#define EMAC_TX_DESC_OVERRIDE 0x04000000
+#define EMAC_RX_DESC_INT 0x80000000
+/* EMAC Descriptor status related definition */ +#define TX_DESC_STATUS_ERR 0x80000000 +#define TX_DESC_STATUS_NODESC 0x40000000 +#define TX_DESC_STATUS_UNDERRUN 0x20000000 +#define TX_DESC_STATUS_LCOL 0x10000000 +#define TX_DESC_STATUS_ECOL 0x08000000 +#define TX_DESC_STATUS_EDEFER 0x04000000 +#define TX_DESC_STATUS_DEFER 0x02000000 +#define TX_DESC_STATUS_COLCNT 0x01E00000 /* four bits, it's a mask, not exact count */
+#define RX_DESC_STATUS_ERR 0x80000000 +#define RX_DESC_STATUS_LAST 0x40000000 +#define RX_DESC_STATUS_NODESC 0x20000000 +#define RX_DESC_STATUS_OVERRUN 0x10000000 +#define RX_DESC_STATUS_ALGNERR 0x08000000 +#define RX_DESC_STATUS_RNGERR 0x04000000 +#define RX_DESC_STATUS_LENERR 0x02000000 +#define RX_DESC_STATUS_SYMERR 0x01000000 +#define RX_DESC_STATUS_CRCERR 0x00800000 +#define RX_DESC_STATUS_BCAST 0x00400000 +#define RX_DESC_STATUS_MCAST 0x00200000 +#define RX_DESC_STATUS_FAILFLT 0x00100000 +#define RX_DESC_STATUS_VLAN 0x00080000 +#define RX_DESC_STATUS_CTLFRAM 0x00040000
+#define DESC_SIZE_MASK 0x000007FF /* 11 bits for both TX and RX */
+/* EMAC interrupt controller related definition */ +#define EMAC_INT_RXOVERRUN 0x01 << 0 +#define EMAC_INT_RXERROR 0x01 << 1 +#define EMAC_INT_RXFINISHED 0x01 << 2 +#define EMAC_INT_RXDONE 0x01 << 3 +#define EMAC_INT_TXUNDERRUN 0x01 << 4 +#define EMAC_INT_TXERROR 0x01 << 5 +#define EMAC_INT_TXFINISHED 0x01 << 6 +#define EMAC_INT_TXDONE 0x01 << 7 +#define EMAC_INT_SOFTINT 0x01 << 12 +#define EMAC_INT_WOL 0x01 << 13
+#define PHY_BMCR 0x0000 +#define PHY_BMSR 0x0001 +#define PHY_PHYIDR1 0x0002 +#define PHY_PHYIDR2 0x0003 +#define PHY_ANAR 0x0004 +#define PHY_ANLPAR 0x0005 +#define PHY_ANLPARNP 0x0005 +#define PHY_ANER 0x0006 +#define PHY_ANNPTR 0x0007
Please use the definitions in include/miiphy.h for all these standard IEEE802.3 registers.
+/* BMCR setting */ +#define BMCR_RESET 0x8000 +#define BMCR_LOOPBACK 0x4000 +#define BMCR_SPEED_100 0x2000 +#define BMCR_AN 0x1000 +#define BMCR_POWERDOWN 0x0800 +#define BMCR_ISOLATE 0x0400 +#define BMCR_RE_AN 0x0200 +#define BMCR_DUPLEX 0x0100
+/* BMSR setting */ +#define BMSR_100BE_T4 0x8000 +#define BMSR_100TX_FULL 0x4000 +#define BMSR_100TX_HALF 0x2000 +#define BMSR_10BE_FULL 0x1000 +#define BMSR_10BE_HALF 0x0800 +#define BMSR_AUTO_DONE 0x0020 +#define BMSR_REMOTE_FAULT 0x0010 +#define BMSR_NO_AUTO 0x0008 +#define BMSR_LINK_ESTABLISHED 0x0004
+#define MII_BMSR_TIMEOUT 0x1000000
+#define CMD_RX_ENABLE 0x01 +#define CMD_TX_ENABLE 0x02 +#define CMD_PASS_RX_FILTER 0x80
+/* Helper macros */ +#define BFS32(reg,value) writel( (readl(reg)|=(value)) ,reg) +#define BFC32(reg,value) writel( (readl(reg)&=(~value)) ,reg)
Could you make these macro names a bit more descriptive please?
Thanks a lot! This is a very good start.
regards, Ben
On 13:57 Fri 24 Apr , Remco Poelstra wrote:
This patch includes support for the LPC2468 processor from NXP.
Signed-off-by: Remco Poelstra remco.poelstra+u-boot@duran-audio.com
A working board example will be submitted when this patch is found to be OK. This patch is against latest git. The previous problem with PUTx vs. writex is solved.
two general news
I'm preparing some patch to cleanup the arm720t include LPC irq support
I'll send it asap
please take a look and test it
From 75361079ed78fb40c2840b3bd74687153e486620 Mon Sep 17 00:00:00 2001 From: Remco Poelstra remco.poelstra+u-boot@duran-audio.com Date: Fri, 24 Apr 2009 12:18:21 +0200 Subject: [PATCH] Support for LPC2468 processor from NXP
Makefile | 3 + cpu/arm720t/cpu.c | 2 +- cpu/arm720t/interrupts.c | 37 +++- cpu/arm720t/lpc24xx/Makefile | 50 +++++ cpu/arm720t/lpc24xx/flash.c | 233 ++++++++++++++++++++ cpu/arm720t/lpc24xx/iap_entry.S | 7 + cpu/arm720t/start.S | 11 +- drivers/serial/Makefile | 1 + drivers/serial/serial_lpc2468.c | 119 +++++++++++ include/asm-arm/arch-lpc24xx/hardware.h | 32 +++ include/asm-arm/arch-lpc24xx/immap.h | 351 +++++++++++++++++++++++++++++++ include/asm-arm/config.h | 4 + include/flash.h | 1 + 13 files changed, 842 insertions(+), 9 deletions(-) create mode 100644 cpu/arm720t/lpc24xx/Makefile create mode 100644 cpu/arm720t/lpc24xx/flash.c create mode 100644 cpu/arm720t/lpc24xx/iap_entry.S create mode 100644 drivers/serial/serial_lpc2468.c create mode 100644 include/asm-arm/arch-lpc24xx/hardware.h create mode 100644 include/asm-arm/arch-lpc24xx/immap.h
diff --git a/Makefile b/Makefile index e91c051..fb23ee6 100644 --- a/Makefile +++ b/Makefile @@ -2940,6 +2940,9 @@ B2_config : unconfig ## ARM720T Systems #########################################################################
+LPC2468_config: unconfig
- @$(MKCONFIG) $(@:_config=) arm arm720t LPC2468 NULL lpc24xx
- armadillo_config: unconfig @$(MKCONFIG) $(@:_config=) arm arm720t armadillo
diff --git a/cpu/arm720t/cpu.c b/cpu/arm720t/cpu.c index 6c40903..b3a2853 100644 --- a/cpu/arm720t/cpu.c +++ b/cpu/arm720t/cpu.c @@ -75,7 +75,7 @@ int cleanup_before_linux (void) /* go to high speed */ IO_SYSCON3 = (IO_SYSCON3 & ~CLKCTL) | CLKCTL_73; #endif -#elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) || defined(CONFIG_LPC2292) +#elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) || defined(CONFIG_LPC2000) disable_interrupts (); /* Nothing more needed */ #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) diff --git a/cpu/arm720t/interrupts.c b/cpu/arm720t/interrupts.c index 39ed345..d7aec27 100644 --- a/cpu/arm720t/interrupts.c +++ b/cpu/arm720t/interrupts.c @@ -29,17 +29,26 @@ #include <common.h> #include <clps7111.h> #include <asm/proc-armv/ptrace.h> +#include <asm/io.h> +#if defined(CONFIG_LPC2468) +#include <asm/arch/immap.h> +#else #include <asm/hardware.h> +#endif
#ifndef CONFIG_NETARM
+#if defined(CONFIG_LPC2292) +#define TIMER_LOAD_VAL 0xffff +#define READ_TIMER (0xFFFFFFFF - GET32(T0TC)) +#elif defined(CONFIG_LPC2468) +#define TIMER_LOAD_VAL 0 +#define READ_TIMER (0xFFFFFFFF - 0xE0004008) +#else /* we always count down the max. */ #define TIMER_LOAD_VAL 0xffff /* macro to read the 16 bit timer */ #define READ_TIMER (IO_TC1D & 0xffff)
-#ifdef CONFIG_LPC2292 -#undef READ_TIMER -#define READ_TIMER (0xFFFFFFFF - GET32(T0TC)) #endif
#else @@ -80,6 +89,14 @@ void do_irq (struct pt_regs *pt_regs) pfnct = (void (*)(void))VICVectAddr;
(*pfnct)();+#elif defined(CONFIG_LPC2468)
- void (*pfnct) (void);
- vic_2468_t *vic = &(((immap_t *)CONFIG_SYS_IMMAP)->ahb.vic);
- pfnct = (void (*)(void))(&(vic->vicaddr));
- (*pfnct) ();
- #else #error do_irq() not defined for this CPU type #endif
@@ -112,6 +129,9 @@ static ulong lastdec;
int interrupt_init (void) { +#if defined(CONFIG_LPC2468)
- timer_2468_t *timer0=&(((immap_t *)CONFIG_SYS_IMMAP)->apb.timer0);
+#endif
#if defined(CONFIG_NETARM) /* disable all interrupts */ @@ -185,6 +205,13 @@ int interrupt_init (void) PUT32(T0MCR, 0); PUT32(T0TC, 0); PUT32(T0TCR, 1); /* enable timer0 */ +#elif defined(CONFIG_LPC2468)
writel (0, &(timer0->ir)); /*disable all timer0 interupts */
writel (0, &(timer0->tcr)); /*disable timer0 */
writel (CFG_SYS_CLK_FREQ / CONFIG_SYS_HZ - 1, &(timer0->pr));
writel (0, &(timer0->mcr));
writel (0, &(timer0->tc));
writel (1, &(timer0->tcr));
#else #error No interrupt_init() defined for this CPU type
@@ -201,7 +228,7 @@ int interrupt_init (void) */
-#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO) || defined(CONFIG_LPC2292) +#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO) || defined(CONFIG_LPC2000)
void reset_timer (void) { diff --git a/cpu/arm720t/lpc24xx/Makefile b/cpu/arm720t/lpc24xx/Makefile new file mode 100644 index 0000000..f091502 --- /dev/null +++ b/cpu/arm720t/lpc24xx/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2000-2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +#
+include $(TOPDIR)/config.mk
+LIB = $(obj)lib$(SOC).a
+COBJS = flash.o +SOBJS = $(obj)iap_entry.o
+SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS))
+all: $(obj).depend $(LIB)
+$(LIB): $(OBJS) $(SOBJS)
- $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+# this MUST be compiled as thumb code!
why? no thumb will be accpeted without a clear explination
+$(SOBJS):
- $(CC) $(AFLAGS) -march=armv4t -c -o $(SOBJS) iap_entry.S
+#########################################################################
+# defines $(obj).depend target +include $(SRCTREE)/rules.mk
+sinclude $(obj).depend
+######################################################################### diff --git a/cpu/arm720t/lpc24xx/flash.c b/cpu/arm720t/lpc24xx/flash.c new file mode 100644 index 0000000..46a1a56 --- /dev/null +++ b/cpu/arm720t/lpc24xx/flash.c @@ -0,0 +1,233 @@ +/*
- (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com>
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#include <common.h> +#include <asm/io.h> +#include <asm/arch/immap.h> +/* IAP commands use 32 bytes at the top of CPU internal sram, we
- use 512 bytes below that */
please use this style of comment /* * */
+#define COPY_BUFFER_LOCATION 0x4000fde0
evenif it's soc specific flash support I think they need to be store with the other flash and need to have the ack of Stefan
+#define IAP_LOCATION 0x7ffffff1 +#define IAP_CMD_PREPARE 50 +#define IAP_CMD_COPY 51 +#define IAP_CMD_ERASE 52 +#define IAP_CMD_CHECK 53 +#define IAP_CMD_ID 54 +#define IAP_CMD_VERSION 55 +#define IAP_CMD_COMPARE 56
diff --git a/cpu/arm720t/start.S b/cpu/arm720t/start.S index 022b873..eca4d9f 100644 --- a/cpu/arm720t/start.S +++ b/cpu/arm720t/start.S @@ -127,7 +127,7 @@ reset: bl cpu_init_crit #endif
-#ifdef CONFIG_LPC2292 +#if defined(CONFIG_LPC2000) bl lowlevel_init #endif
I'm not really happy with this we need to extract the soc specific from the arch init
@@ -368,6 +368,11 @@ lock_loop: ldr r0, VPBDIV_ADR mov r1, #0x01 /* VPB clock is same as process clock */ str r1, [r0] +#elif defined(CONFIG_LPC2468)
- ldr r0, =0x40008000 /*0x40000000 is internal SRAM,
0x4000FFFF is end of SRAM*/- mov sp,r0
- sub sl,sp,#0x2000 #else #error No cpu_init_crit() defined for current CPU type #endif
@@ -383,7 +388,7 @@ lock_loop: str r1, [r0] #endif
-#ifndef CONFIG_LPC2292 +#if !defined(CONFIG_LPC2000) mov ip, lr /* * before relocating, we have to setup RAM timing @@ -601,7 +606,7 @@ reset_cpu:
- on external peripherals such as watchdog timers, etc. */
#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No specific reset actions for IntegratorAP/CM720T as yet */ -#elif defined(CONFIG_LPC2292) +#elif defined(CONFIG_LPC2000) .align 5 .globl reset_cpu reset_cpu: diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index bb99a34..929fb5a 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -39,6 +39,7 @@ COBJS-$(CONFIG_IMX_SERIAL) += serial_imx.o COBJS-$(CONFIG_IXP_SERIAL) += serial_ixp.o COBJS-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o COBJS-$(CONFIG_LPC2292_SERIAL) += serial_lpc2292.o +COBJS-$(CONFIG_LPC2468_SERIAL) += serial_lpc2468.o COBJS-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o COBJS-$(CONFIG_MX31_UART) += serial_mx31.o COBJS-$(CONFIG_NETARM_SERIAL) += serial_netarm.o
Best Regards, J.
Dear Jean-Christophe PLAGNIOL-VILLARD,
In message 20090424215804.GC10032@game.jcrosoft.org you wrote:
...
+#define COPY_BUFFER_LOCATION 0x4000fde0
evenif it's soc specific flash support I think they need to be store with the other flash and need to have the ack of Stefan
No, not really. Stefan cares only about the CFI driver, and this is clearly not a CFI conformant flash type.
Best regards,
Wolfgang Denk
On 00:14 Sat 25 Apr , Wolfgang Denk wrote:
Dear Jean-Christophe PLAGNIOL-VILLARD,
In message 20090424215804.GC10032@game.jcrosoft.org you wrote:
...
+#define COPY_BUFFER_LOCATION 0x4000fde0
evenif it's soc specific flash support I think they need to be store with the other flash and need to have the ack of Stefan
No, not really. Stefan cares only about the CFI driver, and this is clearly not a CFI conformant flash type.
ok but I steel wish to have Stefan opinion
Best Regards, J.
On Saturday 25 April 2009, Jean-Christophe PLAGNIOL-VILLARD wrote:
In message 20090424215804.GC10032@game.jcrosoft.org you wrote:
...
+#define COPY_BUFFER_LOCATION 0x4000fde0
evenif it's soc specific flash support I think they need to be store with the other flash and need to have the ack of Stefan
No, not really. Stefan cares only about the CFI driver, and this is clearly not a CFI conformant flash type.
ok but I steel wish to have Stefan opinion
I took a quick look at the flash "driver". The main functions lpc24xx_flash_erase() and lpc24xx_write_buff() are not even referenced somewhere in this patch. They seem to be used in the 2nd patch (2/2) though. It's hard to really understand what's going on here. So this flash driver part really needs some sort of documentation how it's supposed to work.
And I also think this driver (as all FLASH related drivers) should be moved into drivers/mtd instead.
Best regards, Stefan
===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office@denx.de =====================================================================
Dear Stefan Roese,
In message 200904270927.29232.sr@denx.de you wrote:
I took a quick look at the flash "driver". The main functions lpc24xx_flash_erase() and lpc24xx_write_buff() are not even referenced somewhere in this patch. They seem to be used in the 2nd patch (2/2) though. It's hard to really understand what's going on here. So this flash driver part really needs some sort of documentation how it's supposed to work.
And I also think this driver (as all FLASH related drivers) should be moved into drivers/mtd instead.
Into drivers/mtd? Even if it's not a MTD driver? This doesn't make mnuch sense to me.
Best regards,
Wolfgang Denk
Hi Wolfgang,
On Tuesday 28 April 2009, Wolfgang Denk wrote:
I took a quick look at the flash "driver". The main functions lpc24xx_flash_erase() and lpc24xx_write_buff() are not even referenced somewhere in this patch. They seem to be used in the 2nd patch (2/2) though. It's hard to really understand what's going on here. So this flash driver part really needs some sort of documentation how it's supposed to work.
And I also think this driver (as all FLASH related drivers) should be moved into drivers/mtd instead.
Into drivers/mtd? Even if it's not a MTD driver? This doesn't make mnuch sense to me.
In the end this driver will be used by the common FLASH user interface (cmd_flash.c, cmd_mem.c). So I prefer to have the "driver" for this interface in a common place for a better overview. And the only common place I can think of is drivers/mtd right now. We should probably add a subdirectory for NOR flash drivers: drivers/mtd/nor (or drivers/mtd/maps as done in Linux).
BTW: This common place will prevent those multiple platform/board specific flash drivers we have right now as well.
Best regards, Stefan
===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office@denx.de =====================================================================
Dear Stefan Roese,
In message 200904280827.45894.sr@denx.de you wrote:
Into drivers/mtd? Even if it's not a MTD driver? This doesn't make mnuch sense to me.
In the end this driver will be used by the common FLASH user interface (cmd_flash.c, cmd_mem.c). So I prefer to have the "driver" for this interface
Yes. But MTD is a description of a specific interface. Even now we have two versions of the CFI driver: drivers/mtd/cfi_flash.c and drivers/mtd/cfi_mtd.c, and if we look closer at it only cfi_mtd.c makes sense in this directory. cfi_flash.c is *not* MTD conformant and should be somewhere else.
in a common place for a better overview. And the only common place I can think of is drivers/mtd right now. We should probably add a subdirectory for
Maybe we should create drivers/flash for those non-MTD flash drivers? Then we should also move cfi_flash.c there.
NOR flash drivers: drivers/mtd/nor (or drivers/mtd/maps as done in Linux).
Um... this is something different - in Linux all flash drivers (at least all in mainline) are handled through the MTD layer.
BTW: This common place will prevent those multiple platform/board specific flash drivers we have right now as well.
We agree on that.
Best regards,
Wolfgang Denk
Hi Wolfgang,
On Tuesday 28 April 2009, Wolfgang Denk wrote:
Into drivers/mtd? Even if it's not a MTD driver? This doesn't make mnuch sense to me.
In the end this driver will be used by the common FLASH user interface (cmd_flash.c, cmd_mem.c). So I prefer to have the "driver" for this interface
Yes. But MTD is a description of a specific interface. Even now we have two versions of the CFI driver: drivers/mtd/cfi_flash.c and drivers/mtd/cfi_mtd.c,
No, we don't have "two versions of the CFI driver". cfi_mtd.c is not really a driver but "only" a wrapper implementing the MTD infrastructure on top of the U-Boot NOR driver (cfi_flash or others).
and if we look closer at it only cfi_mtd.c makes sense in this directory. cfi_flash.c is *not* MTD conformant and should be somewhere else.
in a common place for a better overview. And the only common place I can think of is drivers/mtd right now. We should probably add a subdirectory for
Maybe we should create drivers/flash for those non-MTD flash drivers? Then we should also move cfi_flash.c there.
Yes, this could be done.
Best regards, Stefan
===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office@denx.de =====================================================================
--- u-boot-orig/cpu/arm720t/lpc24xx/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-cleanup/cpu/arm720t/lpc24xx/Makefile 2009-03-19 10:56:53.000000000 +0100
...
+$(SOBJS):
- $(CC) $(AFLAGS) -march=armv4t -c -o $(SOBJS) iap_entry.S
Such compile options hsould probably be set globally, not just for this single source file?
No, thumb code is less efficient in terms of performance, but this single file needs thumb code. See LPC2292.
what is the Difference?
until a real big gap please do not use thumb
diff -upNr u-boot-orig/cpu/arm720t/start.S u-boot-cleanup/cpu/arm720t/start.S --- u-boot-orig/cpu/arm720t/start.S 2009-03-18 00:42:12.000000000 +0100 +++ u-boot-cleanup/cpu/arm720t/start.S 2009-03-24 11:52:35.000000000 +0100 @@ -127,7 +127,7 @@ reset: bl cpu_init_crit #endif
-#ifdef CONFIG_LPC2292 +#if defined(CONFIG_LPC2292) || defined(CONFIG_LPC2468)
Is there no way to combine this code with the one for the LPC2292?
I'm sorry, it is combined in this case, no?
#else #error No cpu_init_crit() defined for current CPU type #endif @@ -383,7 +387,7 @@ lock_loop: str r1, [r0] #endif
-#ifndef CONFIG_LPC2292 +#if !defined(CONFIG_LPC2292) && !defined(CONFIG_LPC2468)
Is there no way to combine this code with the one for the LPC2292?
Same here.
mov ip, lr /* * before relocating, we have to setup RAM timing @@ -601,7 +605,7 @@ reset_cpu:
- on external peripherals such as watchdog timers, etc. */
#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No specific reset actions for IntegratorAP/CM720T as yet */ -#elif defined(CONFIG_LPC2292) +#elif defined(CONFIG_LPC2292) || defined(CONFIG_LPC2468)
Is there no way to combine this code with the one for the LPC2292?
Same here.
.align 5 .globl reset_cpu reset_cpu: diff -upNr u-boot-orig/include/asm-arm/arch-lpc24xx/hardware.h u-boot-cleanup/include/asm-arm/arch-lpc24xx/hardware.h --- u-boot-orig/include/asm-arm/arch-lpc24xx/hardware.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-cleanup/include/asm-arm/arch-lpc24xx/hardware.h 2009-03-24 11:54:44.000000000 +0100 @@ -0,0 +1,32 @@ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H
+/*
- Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
- Curt Brune curt@cucy.com
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#if defined(CONFIG_LPC2468) +#else +#error No hardware file defined for this configuration +#endif
+#endif /* __ASM_ARCH_HARDWARE_H */
Ummm... What exactly is this file needed for?
I don't need it, but start.S wants to include it. See my comment about the #ifdef's. Other architectures left it empty too, so it seemed the best option to me.
+/* Macros for reading/writing registers */ +#define PUT8(reg, value) (*(volatile unsigned char*)(reg) = (value)) +#define PUT16(reg, value) (*(volatile unsigned short*)(reg) = (value)) +#define PUT32(reg, value) (*(volatile unsigned int*)(reg) = (value)) +#define GET8(reg) (*(volatile unsigned char*)(reg)) +#define GET16(reg) (*(volatile unsigned short*)(reg)) +#define GET32(reg) (*(volatile unsigned int*)(reg))
Do you clain these are proper accessor functions for your processor?
Yes I do. They are straight from the LPC2292 code, so once they were considered OK. I checked out the the write{s,l,b} functions in asm/io.h, but although they look similar, for some reason they simply don't work. Given the similarities between the write{s,l,b} and the PUT* functions, what is the problem with those? Furthermore, the ARM architecture doesn't use any kind of special instructions for accessing registers, everything is memory mapped.
please use readx/writex
I do understand that you want the best code for U-boot, but I do not entirely agree on all points. Certainly when I look at the code already in place in U-boot.
I'm preparing a patch series to clean the arm720t to seprate it as arch and avoid this borring #ifdef
Best Regards, J.
Jean-Christophe PLAGNIOL-VILLARD schreef:
No, thumb code is less efficient in terms of performance, but this single file needs thumb code. See LPC2292.
what is the Difference?
until a real big gap please do not use thumb
IAP entries need thumb code. This is not a problem, they are only used for programming the internal flash of the processor, so there is no performance penalty for normal operation.
Yes I do. They are straight from the LPC2292 code, so once they were considered OK. I checked out the the write{s,l,b} functions in asm/io.h, but although they look similar, for some reason they simply don't work. Given the similarities between the write{s,l,b} and the PUT* functions, what is the problem with those? Furthermore, the ARM architecture doesn't use any kind of special instructions for accessing registers, everything is memory mapped.
please use readx/writex
Thanks for the pointer, I'll look into those.
I do understand that you want the best code for U-boot, but I do not entirely agree on all points. Certainly when I look at the code already in place in U-boot.
I'm preparing a patch series to clean the arm720t to seprate it as arch and avoid this borring #ifdef
Can you explain what you mean here?
Kind regards,
Remco Poelstra
Remco Poelstra schreef:
Yes I do. They are straight from the LPC2292 code, so once they were considered OK. I checked out the the write{s,l,b} functions in asm/io.h, but although they look similar, for some reason they simply don't work. Given the similarities between the write{s,l,b} and the PUT* functions, what is the problem with those? Furthermore, the ARM architecture doesn't use any kind of special instructions for accessing registers, everything is memory mapped.
please use readx/writex
Thanks for the pointer, I'll look into those.
I can't find these functions/macros, but I think you mean the write{b,s,l} macros. As I already indicated in a previous e-mail, they do not work in my code. If I replace, e.g. the PUT32 with writel than the code doesn't run. I will look into that problem after I've finished another project at work.
Kind regards,
Remco Poelstra
Example board for LPC2468 support
Signed-off-by: Remco Poelstra remco.poelstra+u-boot@duran-audio.com --- diff -upNr u-boot-orig/board/LPC2468/config.mk u-boot/board/LPC2468/config.mk --- u-boot-orig/board/LPC2468/config.mk 1970-01-01 01:00:00.000000000 +0100 +++ u-boot/board/LPC2468/config.mk 2009-03-18 09:30:20.000000000 +0100 @@ -0,0 +1,29 @@ +# +# (C) Copyright 2000 +# Sysgo Real-Time Solutions, GmbH <www.elinos.com> +# Marius Groeger mgroeger@sysgo.de +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +#address where u-boot will be relocated +TEXT_BASE = 0xA1f80000 diff -upNr u-boot-orig/board/LPC2468/eth.c u-boot/board/LPC2468/eth.c --- u-boot-orig/board/LPC2468/eth.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot/board/LPC2468/eth.c 2009-03-18 15:33:31.000000000 +0100 @@ -0,0 +1,694 @@ +/* + * (C) Copyright 2009 Duran Audio B.V. <www.duran-audio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * 18-03-2009 Updated for U-boot 2009.3 by Remco Poelstra remco.poelstra+u-boot@duran-audio.com + * Based on sample code from NXP + */ + +#include <config.h> +#include <common.h> +#include <net.h> +#include <asm/arch/hardware.h> + +/****************************************************************************** + * Typedefs and defines + *****************************************************************************/ +#define MAX_PHY_INIT_RETRY 10 + +/* EMAC MODULE ID */ +#define OLD_EMAC_MODULE_ID ((0x3902 << 16) | 0x2000) + +/* MAC registers and parameters */ +#define PCONP_EMAC_CLOCK 0x40000000 + +#define SPEED_100 1 +#define SPEED_10 0 +#define FULL_DUPLEX 1 +#define HALF_DUPLEX 0 + +#define EMAC_RAM_ADDR 0x7FE00000 +#define EMAC_RAM_SIZE 0x00004000 + +//#define EMAC_TX_DESCRIPTOR_COUNT 0x0010 +//#define EMAC_RX_DESCRIPTOR_COUNT 0x0010 + +#define EMAC_TX_DESCRIPTOR_COUNT 5 +#define EMAC_RX_DESCRIPTOR_COUNT 4 + +/* + * (Rx|Tx)Descriptor :: + * [4] packet - base address of the buffer containing the data + * [4] control - control information + */ +#define TX_DESCRIPTOR_SIZE (EMAC_TX_DESCRIPTOR_COUNT * 8) +#define RX_DESCRIPTOR_SIZE (EMAC_RX_DESCRIPTOR_COUNT * 8) + +/* + * TxStatus :: + * [4] status + */ +#define TX_STATUS_SIZE (EMAC_TX_DESCRIPTOR_COUNT * 4) + +/* + * RxStatus :: + * [4] status - receive status flags + * [4] statusHashCRC - concat of dest addr hash CRC and src addr CRC + */ +#define RX_STATUS_SIZE (EMAC_RX_DESCRIPTOR_COUNT * 8) + +#define TOTAL_DESCRIPTOR_SIZE (TX_DESCRIPTOR_SIZE + RX_DESCRIPTOR_SIZE + TX_STATUS_SIZE + RX_STATUS_SIZE) + +/* descriptors are placed at the end of the emac address space */ +#define EMAC_DESCRIPTOR_ADDR (EMAC_RAM_ADDR + EMAC_RAM_SIZE - TOTAL_DESCRIPTOR_SIZE) + +#define TX_DESCRIPTOR_ADDR EMAC_DESCRIPTOR_ADDR +#define TX_STATUS_ADDR (EMAC_DESCRIPTOR_ADDR + TX_DESCRIPTOR_SIZE) +#define RX_DESCRIPTOR_ADDR (TX_STATUS_ADDR + TX_STATUS_SIZE) +#define RX_STATUS_ADDR (RX_DESCRIPTOR_ADDR + RX_DESCRIPTOR_SIZE) + +#define EMAC_DMA_ADDR EMAC_RAM_ADDR +#define EMAC_DMA_SIZE EMAC_RAM_ADDR + EMAC_RAM_END - TOTAL_DESCRIPTOR_SIZE + +#define EMAC_BLOCK_SIZE 0x600 +#define EMAC_TX_BLOCK_NUM 5 +#define EMAC_RX_BLOCK_NUM 5 +#define TOTAL_EMAC_BLOCK_NUM 10 + +#define EMAC_BUFFER_SIZE (EMAC_BLOCK_SIZE * (EMAC_TX_BLOCK_NUM + EMAC_RX_BLOCK_NUM )) +#define EMAC_TX_BUFFER_ADDR EMAC_RAM_ADDR +#define EMAC_RX_BUFFER_ADDR (EMAC_RAM_ADDR + EMAC_BLOCK_SIZE * EMAC_TX_BLOCK_NUM) + +/* EMAC Descriptor TX and RX Control fields */ +#define EMAC_TX_DESC_INT 0x80000000 +#define EMAC_TX_DESC_LAST 0x40000000 +#define EMAC_TX_DESC_CRC 0x20000000 +#define EMAC_TX_DESC_PAD 0x10000000 +#define EMAC_TX_DESC_HUGE 0x08000000 +#define EMAC_TX_DESC_OVERRIDE 0x04000000 + +#define EMAC_RX_DESC_INT 0x80000000 + +/* EMAC Descriptor status related definition */ +#define TX_DESC_STATUS_ERR 0x80000000 +#define TX_DESC_STATUS_NODESC 0x40000000 +#define TX_DESC_STATUS_UNDERRUN 0x20000000 +#define TX_DESC_STATUS_LCOL 0x10000000 +#define TX_DESC_STATUS_ECOL 0x08000000 +#define TX_DESC_STATUS_EDEFER 0x04000000 +#define TX_DESC_STATUS_DEFER 0x02000000 +#define TX_DESC_STATUS_COLCNT 0x01E00000 /* four bits, it's a mask, not exact count */ + +#define RX_DESC_STATUS_ERR 0x80000000 +#define RX_DESC_STATUS_LAST 0x40000000 +#define RX_DESC_STATUS_NODESC 0x20000000 +#define RX_DESC_STATUS_OVERRUN 0x10000000 +#define RX_DESC_STATUS_ALGNERR 0x08000000 +#define RX_DESC_STATUS_RNGERR 0x04000000 +#define RX_DESC_STATUS_LENERR 0x02000000 +#define RX_DESC_STATUS_SYMERR 0x01000000 +#define RX_DESC_STATUS_CRCERR 0x00800000 +#define RX_DESC_STATUS_BCAST 0x00400000 +#define RX_DESC_STATUS_MCAST 0x00200000 +#define RX_DESC_STATUS_FAILFLT 0x00100000 +#define RX_DESC_STATUS_VLAN 0x00080000 +#define RX_DESC_STATUS_CTLFRAM 0x00040000 + +#define DESC_SIZE_MASK 0x000007FF /* 11 bits for both TX and RX */ + +/* EMAC interrupt controller related definition */ +#define EMAC_INT_RXOVERRUN 0x01 << 0 +#define EMAC_INT_RXERROR 0x01 << 1 +#define EMAC_INT_RXFINISHED 0x01 << 2 +#define EMAC_INT_RXDONE 0x01 << 3 +#define EMAC_INT_TXUNDERRUN 0x01 << 4 +#define EMAC_INT_TXERROR 0x01 << 5 +#define EMAC_INT_TXFINISHED 0x01 << 6 +#define EMAC_INT_TXDONE 0x01 << 7 +#define EMAC_INT_SOFTINT 0x01 << 12 +#define EMAC_INT_WOL 0x01 << 13 + +/* Micrel KSZ8001 PHY related registers */ + +/* PHY_ADDR, by default, AD0 has pull-up, AD1~4 have pull-downs, +so, the default address is 0x0001 */ +//#define PHY_ADDR (0x0000 << 8) /* in MAC_MADR, bit 8~12 */ + +static volatile int phyAddr = 0x1000; +#define NATIONAL_PHY 0 +#define MICREL_PHY 1 +static volatile int phyType = MICREL_PHY; + +#define PHY_BMCR 0x0000 +#define PHY_BMSR 0x0001 +#define PHY_PHYIDR1 0x0002 +#define PHY_PHYIDR2 0x0003 +#define PHY_ANAR 0x0004 +#define PHY_ANLPAR 0x0005 +#define PHY_ANLPARNP 0x0005 +#define PHY_ANER 0x0006 +#define PHY_ANNPTR 0x0007 + +/* BMCR setting */ +#define BMCR_RESET 0x8000 +#define BMCR_LOOPBACK 0x4000 +#define BMCR_SPEED_100 0x2000 +#define BMCR_AN 0x1000 +#define BMCR_POWERDOWN 0x0800 +#define BMCR_ISOLATE 0x0400 +#define BMCR_RE_AN 0x0200 +#define BMCR_DUPLEX 0x0100 + +/* BMSR setting */ +#define BMSR_100BE_T4 0x8000 +#define BMSR_100TX_FULL 0x4000 +#define BMSR_100TX_HALF 0x2000 +#define BMSR_10BE_FULL 0x1000 +#define BMSR_10BE_HALF 0x0800 +#define BMSR_AUTO_DONE 0x0020 +#define BMSR_REMOTE_FAULT 0x0010 +#define BMSR_NO_AUTO 0x0008 +#define BMSR_LINK_ESTABLISHED 0x0004 + +#define MII_BMSR_TIMEOUT 0x1000000 + +#define CMD_RX_ENABLE 0x01 +#define CMD_TX_ENABLE 0x02 +#define CMD_PASS_RX_FILTER 0x80 + +#ifndef IRQ_EXT3 +#define IRQ_EXT3 LPC2294_INTERRUPT_EINT3 +#endif + +#define m_nic_bfs(reg, data) reg |= (data) +#define m_nic_bfc(reg, data) reg &= ~(data) + +#define printk printf + +#define m_nic_read(reg) (*(volatile unsigned long *)(reg)) +#define m_nic_write(reg, data) ((*(volatile unsigned long *)(reg)) = (volatile unsigned long)(data)) + +/****************************************************************************** + * Local variables + *****************************************************************************/ + +//static struct eth_device _dev_emac; +static volatile u32 emacDuplex; +static volatile u32 emacSpeed; +static unsigned char macAddr[6]; +static int opened = 0; + +/****************************************************************************** + * Local functions + *****************************************************************************/ + +static void writePhy(u32 phyReg, u32 phyData) +{ + + // write command + MAC_MCMD = 0x0000; + + // [12:8] == PHY addr, [4:0]=0x00(BMCR) register addr + MAC_MADR = (phyAddr | phyReg); + MAC_MWTD = phyData; + while (MAC_MIND != 0) ; +} + +static u32 readPhy(u32 phyReg) +{ + + // read command + MAC_MCMD = 0x0001; + + // [12:8] == PHY addr, [4:0]=0x00(BMCR) register addr + MAC_MADR = (phyAddr | phyReg); + + while (MAC_MIND != 0) ; + + MAC_MCMD = 0x0000; + + return MAC_MRDD; +} + +static int emac_start_xmit(volatile void *buf, int length) +{ + + u32 txProduceIndex = 0; + u32 txConsumeIndex = 0; + u8 *pData = 0; + u32 len = length; //skb->len; + u32 sendLen = 0; + u32 *tx_desc_addr = NULL; + + txProduceIndex = MAC_TXPRODUCEINDEX; + txConsumeIndex = MAC_TXCONSUMEINDEX; + +// printf("emac_start_xmit: pIdx = %d, cIdx=%d\n", +// txProduceIndex, txConsumeIndex); + + if (txConsumeIndex != txProduceIndex) { + // TODO why return here? This just means that the transmit array isn't empty + printk("emac: emac_tx transmit array isn't empty\n"); + return -1; + } + + if (txProduceIndex == EMAC_TX_DESCRIPTOR_COUNT) { + // should never happen + // TODO remove + printk("emac: emac_tx produce index == count\n"); + } + + if (len > 0) { + pData = (u8 *) EMAC_TX_BUFFER_ADDR; + memcpy(pData, (void *)buf, length); + + do { + tx_desc_addr = + (u32 *) (TX_DESCRIPTOR_ADDR + txProduceIndex * 8); + + sendLen = len; + if (sendLen > EMAC_BLOCK_SIZE) { + sendLen = EMAC_BLOCK_SIZE; + } else { + // last fragment + sendLen |= EMAC_TX_DESC_LAST; + } + + m_nic_write(tx_desc_addr, (u32) pData); + tx_desc_addr++; + m_nic_write(tx_desc_addr, + (u32) (EMAC_TX_DESC_INT | (sendLen - 1))); + + txProduceIndex++; + if (txProduceIndex == EMAC_TX_DESCRIPTOR_COUNT) { + txProduceIndex = 0; + } + + MAC_TXPRODUCEINDEX = txProduceIndex; + + len -= (sendLen & ~EMAC_TX_DESC_LAST); + pData += (sendLen & ~EMAC_TX_DESC_LAST); + } while (len > 0); + } + + return 0; +} + +static void emac_rx(void) +{ + u32 rxProduceIndex = 0; + u32 rxConsumeIndex = 0; + u32 *rxStatusAddr = 0; + u32 recvSize = 0; + u32 *recvAddr = 0; + + /* the input parameter, EMCBuf, needs to be word aligned */ + + rxProduceIndex = MAC_RXPRODUCEINDEX; + rxConsumeIndex = MAC_RXCONSUMEINDEX; + + // consume the received packets + while (rxConsumeIndex != rxProduceIndex) { + + rxStatusAddr = (u32 *) (RX_STATUS_ADDR + rxConsumeIndex * 8); + + recvSize = m_nic_read(rxStatusAddr); + + if ((recvSize & RX_DESC_STATUS_LAST) == 0) { + // TODO: could this occur when EMAC_BLOCK_SIZE == 0x0600? + printk("emac_rx: NOT LAST fragment\n"); + } + + recvSize = (recvSize & DESC_SIZE_MASK) + 1; + + recvAddr = (u32 *) (RX_DESCRIPTOR_ADDR + rxConsumeIndex * 8); + + // TODO: allocate buffer? + NetReceive((uchar *) (m_nic_read(recvAddr) /*inBuf */ ), + recvSize); + + rxConsumeIndex++; + if (rxConsumeIndex == EMAC_RX_DESCRIPTOR_COUNT) { + rxConsumeIndex = 0; + } + + MAC_RXCONSUMEINDEX = rxConsumeIndex; + + } + +} + +static void emac_interrupt(void) +{ + //struct net_device *dev = dev_id; +// struct eth_device* dev = &_dev_emac; + + volatile u32 regValue = 0; + + regValue = MAC_INTSTATUS; + + do { + if (regValue == 0) { + break; + } + + if (regValue & EMAC_INT_RXOVERRUN) { + MAC_INTCLEAR = EMAC_INT_RXOVERRUN; + printk("rxOverrun\n"); + break; + } + + if (regValue & EMAC_INT_RXERROR) { + MAC_INTCLEAR = EMAC_INT_RXERROR; + +/* + { + u32 rxConsumeIndex = m_nic_read(EMAC_RXCONSUMEINDEX); + u32* rxStatusAddr = (tU32*)(RX_STATUS_ADDR + rxConsumeIndex * 8); + u32 val = m_nic_read(rxStatusAddr); + + printf("val = %x\n", val); + } +*/ + + //break; + } + + if (regValue & EMAC_INT_RXFINISHED) { + MAC_INTCLEAR = EMAC_INT_RXFINISHED; + } + + if (regValue & EMAC_INT_RXDONE) { + MAC_INTCLEAR = EMAC_INT_RXDONE; + emac_rx(); + } + + if (regValue & EMAC_INT_TXUNDERRUN) { + printf("TX underrun\n"); + MAC_INTCLEAR = EMAC_INT_TXUNDERRUN; + break; + } + + if (regValue & EMAC_INT_TXERROR) { + printf("TX err\n"); + MAC_INTCLEAR = EMAC_INT_TXERROR; + + break; + } + + if (regValue & EMAC_INT_TXFINISHED) { + MAC_INTCLEAR = EMAC_INT_TXFINISHED; + } + + if (regValue & EMAC_INT_TXDONE) { + MAC_INTCLEAR = EMAC_INT_TXDONE; + } + + } while (0); +} + +static int emac_open(void) +{ + + opened = 1; + + // enable Rx & Tx + m_nic_bfs(MAC_COMMAND, CMD_RX_ENABLE); + m_nic_bfs(MAC_COMMAND, CMD_TX_ENABLE); + m_nic_bfs(MAC_COMMAND, CMD_PASS_RX_FILTER); + m_nic_bfs(MAC_MAC1, 0x01); + + return 0; +} + +//static int emac_close(struct net_device *dev) +static void emac_close(void) +{ + opened = 0; + + // disable Rx6 Tx + m_nic_bfc(MAC_COMMAND, CMD_RX_ENABLE); + m_nic_bfc(MAC_COMMAND, CMD_TX_ENABLE); + m_nic_bfc(MAC_MAC1, 0x01); +} + +static int phyInit(void) +{ + int i = 0; + u32 regValue = 0; + u32 timeout = 0; + + MAC_MCFG = 0x801C; /* host clock divided by 28, no suppress preamble, no scan increment */ + for (i = 0; i < 0x40; i++) + asm volatile (" nop"); + + // MII Mgmt. Divided by 28. + MAC_MCFG = 0x001C; + MAC_MCMD = 0; + + for (i = 0; i < 0x100; i++) + asm volatile (" nop"); + + /*Reset the PHY */ + writePhy(PHY_BMCR, BMCR_RESET); + udelay(100); + + timeout = MII_BMSR_TIMEOUT * 4; + while (timeout != 0) { + regValue = readPhy(PHY_BMCR); + if ((regValue & BMCR_RESET) == 0x0000) { + // reset bit has been cleared + break; + } + timeout--; + } + + if (timeout == 0) { + printk(" Error: phyInit failed to reset PHY\n"); + return -1; + } + // check PHY IDs. + phyAddr = 0x1000; + +// writePhy(PHY_BMCR,BMCR_POWERDOWN); +// printf("BMCR: %x\n",readPhy(PHY_BMCR)); + return 0; +} + +static void emacTxDescriptorInit(void) +{ + int i = 0; + u32 *txDescAddr = NULL; + u32 *txStatusAddr = NULL; + + // base address of tx descriptor array + MAC_TXDESCRIPTOR = TX_DESCRIPTOR_ADDR; + + // base address of tx status + MAC_TXSTATUS = TX_STATUS_ADDR; + + // number of tx descriptors + MAC_TXDESCRIPTORNUM = EMAC_TX_DESCRIPTOR_COUNT - 1; + + for (i = 0; i < EMAC_TX_DESCRIPTOR_COUNT; i++) { + txDescAddr = (u32 *) (TX_DESCRIPTOR_ADDR + i * 8); + m_nic_write(txDescAddr, + (EMAC_TX_BUFFER_ADDR + i * EMAC_BLOCK_SIZE)); + + // control field in descriptor + txDescAddr++; + m_nic_write(txDescAddr, + (EMAC_TX_DESC_INT | (EMAC_BLOCK_SIZE - 1))); + } + + for (i = 0; i < EMAC_TX_DESCRIPTOR_COUNT; i++) { + + txStatusAddr = (u32 *) (TX_STATUS_ADDR + i * 4); + + // set status info to 0 + m_nic_write(txStatusAddr, 0); + } + + MAC_TXPRODUCEINDEX = 0; +} + +static void emacRxDescriptorInit(void) +{ + int i; + u32 *rxDescAddr = NULL; + u32 *rxStatusAddr = NULL; + + // base address of rx descriptor array + MAC_RXDESCRIPTOR = RX_DESCRIPTOR_ADDR; + + // base address of rx status + MAC_RXSTATUS = RX_STATUS_ADDR; + + // number of rx descriptors + MAC_RXDESCRIPTORNUM = EMAC_RX_DESCRIPTOR_COUNT - 1; + + for (i = 0; i < EMAC_RX_DESCRIPTOR_COUNT; i++) { + rxDescAddr = (u32 *) (RX_DESCRIPTOR_ADDR + i * 8); + m_nic_write(rxDescAddr, + (EMAC_RX_BUFFER_ADDR + i * EMAC_BLOCK_SIZE)); + rxDescAddr++; + m_nic_write(rxDescAddr, + (EMAC_RX_DESC_INT | + ((EMAC_BLOCK_SIZE - 1) & DESC_SIZE_MASK))); + } + + for (i = 0; i < EMAC_RX_DESCRIPTOR_COUNT; i++) { + // RX status, two words, status info. and status hash CRC. + rxStatusAddr = (u32 *) (RX_STATUS_ADDR + i * 8); + m_nic_write(rxStatusAddr, 0); + rxStatusAddr++; + m_nic_write(rxStatusAddr, 0); + } + + MAC_RXCONSUMEINDEX = 0; +} + +static int emacInit(void) +{ + int i = 0; + + // turn on the ethernet MAC clock in PCONP, bit 30 + m_nic_bfs(PCONP, PCONP_EMAC_CLOCK); + + /*------------------------------------------------------------------------------ + * write to PINSEL2/3 to select the PHY functions on P1[17:0] + *-----------------------------------------------------------------------------*/ + /* documentation needs to be updated */ + PINSEL2 = 0x55555555; /* selects P1[0,1,4,8,9,10,14,15] */ + PINSEL3 = 0x00000005; /* selects P1[17:16] */ + + // reset MAC modules, tx, mcs_tx, rx, mcs_rx, simulation and soft reset + MAC_MAC1 = 0xCF00; + + // reset datapaths and host registers + MAC_COMMAND = 0x0038; + + // short delay after reset + for (i = 0; i < 0x40; i++) + asm volatile (" nop"); + + //Remove reset conditions + MAC_MAC1 = 0x0; + + // disable Tx + m_nic_bfc(MAC_COMMAND, CMD_TX_ENABLE); + // disable Rx + m_nic_bfc(MAC_COMMAND, CMD_RX_ENABLE); + + // initialize MAC2 to default value + // TODO don't thinkt this is necessary?? m_nic_write(EMAC_MAC2, 0x0); + MAC_MAC2 = 0x030; + // non back-to-back Inter-Packet-Gap register + // The manual recommends the value 0x12 + MAC_IPGR = 0x12; + + // collision window/retry register. Using recommended value from manual. + MAC_CLRT = 0x370F; + + // intialize PHY. emacSpeed and emacDuplex will be set in phyInit + if (phyInit() < 0) + return -1; + + // write the mac address + MAC_SA0 = (macAddr[5] << 8 | macAddr[4]); + MAC_SA1 = (macAddr[3] << 8 | macAddr[2]); + MAC_SA2 = (macAddr[1] << 8 | macAddr[0]); + + printk("emac: MAC address = %2x:%2x:%2x:%2x:%2x:%2x\n", macAddr[0], + macAddr[1], macAddr[2], macAddr[3], macAddr[4], macAddr[5]); + + emacTxDescriptorInit(); + emacRxDescriptorInit(); + + // pass all receive frames + m_nic_bfs(MAC_MAC1, 0x002); + + // set up the Rx filter + // [0]-AllUnicast, [1]-AllBroadCast, [2]-AllMulticast, [3]-UnicastHash + // [4]-MulticastHash, [5]-Perfect, [12]-MagicPacketEnWoL, [13]-RxFilterEnWoL +// MAC_RXFILTERCTRL=0x0022; + MAC_RXFILTERCTRL = 0x003F; //Pass everything + + // clear all interrupts + MAC_INTCLEAR = 0xFFFF; + + // TODO the irq is installed here in sample code !! + + // enable interrupts (not SoftInt and WoL) + MAC_INTENABLE = 0x00FF; + + return 0; +} + +/* ############################## + * u-boot interface + * ############################## + */ +static int eth_initialized = 0; +/*----------------------------------------------------------------------------- + * Returns 0 when failes otherwise 1 + */ +int eth_init(bd_t * bis) +{ + int ret; + + if (!eth_initialized) { + if (!eth_getenv_enetaddr("ethaddr", macAddr)) { + printf("Failed to get MAC address from environment\n"); + return 1; + } + + ret = emacInit(); + if (ret != 0) { + return ret; + } + + eth_initialized = 1; + } + + emac_open(); + + return 0; +} + +int eth_send(volatile void *packet, int length) +{ + emac_start_xmit(packet, length); + + return 0; +} + +/*----------------------------------------------------------------------------- + * Check for received packets. Call NetReceive for each packet. The return + * value is ignored by the caller. + */ +int eth_rx(void) +{ + emac_interrupt(); + + return 0; +} + +void eth_halt(void) +{ + emac_close(); +} diff -upNr u-boot-orig/board/LPC2468/flash.c u-boot/board/LPC2468/flash.c --- u-boot-orig/board/LPC2468/flash.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot/board/LPC2468/flash.c 2009-03-18 15:32:37.000000000 +0100 @@ -0,0 +1,253 @@ +/* + * (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com> + * + * (C) Copyright 2009 Duran Audio B.V. <www.duran-audio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * 18-03-2009 Updated for U-boot 2009.3 by Remco Poelstra remco.poelstra+u-boot@duran-audio.com + */ + +#include <common.h> +#include <asm/arch/hardware.h> + +#define SST_BASEADDR 0x80000000 +#define SST_ADDR1 ((volatile ushort*)(SST_BASEADDR + (0x5555<<1))) +#define SST_ADDR2 ((volatile ushort*)(SST_BASEADDR + (0x2AAA<<1))) + +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; + +extern void iap_entry(unsigned long *command, unsigned long *result); + +extern int lpc24xx_copy_buffer_to_flash(flash_info_t *, ulong); +extern int lpc24xx_flash_erase(flash_info_t *, int, int); +extern int lpc24xx_write_buff(flash_info_t *, uchar *, ulong, ulong); + +/*----------------------------------------------------------------------- + * + */ + +void write_word_sst(ulong addr, ushort data) +{ + ushort tmp; + + *SST_ADDR1 = 0x00AA; + *SST_ADDR2 = 0x0055; + *SST_ADDR1 = 0x00A0; + *((volatile ushort *)addr) = data; + /* do data polling */ + do { + tmp = *((volatile ushort *)addr); + } while (tmp != data); +} + +/*----------------------------------------------------------------------- + */ + +ulong flash_init(void) +{ + int j, k; + ulong size = 0; + ulong flashbase = 0; + + flash_info[0].flash_id = (PHILIPS_LPC2468 & FLASH_VENDMASK); + flash_info[0].size = 0x007D000; /* 512 - 12 KB */ + flash_info[0].sector_count = 27; + memset(flash_info[0].protect, 0, 27); + flashbase = 0x00000000; + for (j = 0, k = 0; j < 8; j++, k++) { + flash_info[0].start[k] = flashbase; + flashbase += 0x00001000; + } + for (j = 0; j < 14; j++, k++) { + flash_info[0].start[k] = flashbase; + flashbase += 0x00008000; + } + for (j = 0; j < 5; j++, k++) { + flash_info[0].start[k] = flashbase; + flashbase += 0x00001000; + } + size += flash_info[0].size; + + flash_info[1].flash_id = (SST_MANUFACT & FLASH_VENDMASK); + flash_info[1].size = 0x00400000; /* 4 MB */ + flash_info[1].sector_count = 1024; + memset(flash_info[1].protect, 0, 1024); + flashbase = SST_BASEADDR; + for (j = 0; j < 1024; j++) { + flash_info[1].start[j] = flashbase; + flashbase += 0x1000; /* 4 KB sectors */ + } + size += flash_info[1].size; + + /* Protect monitor and environment sectors */ + flash_protect(FLAG_PROTECT_SET, + 0x0, 0x0 + monitor_flash_len - 1, &flash_info[0]); + +#ifdef CFG_ENV_IS_IN_FLASH + flash_protect(FLAG_PROTECT_SET, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); +#endif + + return size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info(flash_info_t * info) +{ + int i; + int erased = 0; + unsigned long j; + unsigned long count; + unsigned char *p; + + switch (info->flash_id & FLASH_VENDMASK) { + case (SST_MANUFACT & FLASH_VENDMASK): + printf("SST: "); + break; + case (PHILIPS_LPC2468 & FLASH_VENDMASK): + printf("Philips: "); + break; + default: + printf("Unknown Vendor "); + break; + } + + printf(" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) { + printf("\n "); + } + if (i < (info->sector_count - 1)) { + count = info->start[i + 1] - info->start[i]; + } else { + count = info->start[0] + info->size - info->start[i]; + } + p = (unsigned char *)(info->start[i]); + erased = 1; + for (j = 0; j < count; j++) { + if (*p != 0xFF) { + erased = 0; + break; + } + p++; + } + printf(" %08lX%s%s", info->start[i], + info->protect[i] ? " RO" : " ", erased ? " E" : " "); + } + printf("\n"); +} + +int flash_erase_sst(flash_info_t * info, int s_first, int s_last) +{ + int i; + + for (i = s_first; i <= s_last; i++) { + *SST_ADDR1 = 0x00AA; + *SST_ADDR2 = 0x0055; + *SST_ADDR1 = 0x0080; + *SST_ADDR1 = 0x00AA; + *SST_ADDR2 = 0x0055; + *((volatile ushort *)(info->start[i])) = 0x0030; + /* wait for erase to finish */ + udelay(25000); + } + + return ERR_OK; +} + +int flash_erase(flash_info_t * info, int s_first, int s_last) +{ + switch (info->flash_id & FLASH_VENDMASK) { + case (SST_MANUFACT & FLASH_VENDMASK): + return flash_erase_sst(info, s_first, s_last); + case (PHILIPS_LPC2468 & FLASH_VENDMASK): + return lpc24xx_flash_erase(info, s_first, s_last); + default: + return ERR_PROTECTED; + } + return ERR_PROTECTED; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash. + * + * cnt is in bytes + */ + +int write_buff_sst(flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ushort tmp; + ulong i; + uchar *src_org; + uchar *dst_org; + ulong cnt_org = cnt; + int ret = ERR_OK; + + src_org = src; + dst_org = (uchar *) addr; + + if (addr & 1) { /* if odd address */ + tmp = *((uchar *) (addr - 1)); /* little endian */ + tmp |= (*src << 8); + write_word_sst(addr - 1, tmp); + addr += 1; + cnt -= 1; + src++; + } + while (cnt > 1) { + tmp = ((*(src + 1)) << 8) + (*src); /* little endian */ + write_word_sst(addr, tmp); + addr += 2; + src += 2; + cnt -= 2; + } + if (cnt > 0) { + tmp = (*((uchar *) (addr + 1))) << 8; + tmp |= *src; + write_word_sst(addr, tmp); + } + + for (i = 0; i < cnt_org; i++) { + if (*dst_org != *src_org) { + printf("Write failed. Byte %lX differs\n", i); + ret = ERR_PROG_ERROR; + break; + } + dst_org++; + src_org++; + } + + return ret; +} + +int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + switch (info->flash_id & FLASH_VENDMASK) { + case (SST_MANUFACT & FLASH_VENDMASK): + return write_buff_sst(info, src, addr, cnt); + case (PHILIPS_LPC2468 & FLASH_VENDMASK): + return lpc24xx_write_buff(info, src, addr, cnt); + default: + return ERR_PROG_ERROR; + } + return ERR_PROG_ERROR; +} diff -upNr u-boot-orig/board/LPC2468/lowlevel_init.c u-boot/board/LPC2468/lowlevel_init.c --- u-boot-orig/board/LPC2468/lowlevel_init.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot/board/LPC2468/lowlevel_init.c 2009-03-18 15:35:21.000000000 +0100 @@ -0,0 +1,436 @@ +/* + * (C) Copyright 2006-2007 Embedded Artists AB <www.embeddedartists.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <exports.h> +#include <asm/arch/hardware.h> +#include <asm/hardware.h> + +/****************************************************************************** + * Defines, macros, and typedefs + *****************************************************************************/ + +#define USE_USB 1 + +#define PLL_MValue (CONFIG_PLL_MVALUE-1) +#define PLL_NValue (CONFIG_PLL_NVALUE-1) +#define CCLKDivValue (CONFIG_PLL_CLKDIV-1) +#define USBCLKDivValue (CONFIG_PLL_USBCLKDIV-1) + +#define Fcco ((2*CONFIG_PLL_MVALUE*CONFIG_FOSC) / CONFIG_PLL_NVALUE) +#define Fcclk (Fcco / CONFIG_PLL_CLKDIV) +#define Fpclk (Fcclk / CONFIG_FPCLK_DIV) +#define MAM_SETTING 1 /* 0=disabled, + 1=partly enabled (enabled for code prefetch, but not for data), + 2=fully enabled */ +#define MEM_MAP 2 /* When executing from RAM, MAM_MAP should always be 2 */ +#define SDRAM_BASE_ADDR 0xA0000000 +#define m_reg_write(reg,data) ((*(volatile unsigned long *)(reg)) = (volatile unsigned long)(data)) +/***************************************************************************** + * + * Description: + * Delay execution by a specified number of milliseconds by using + * timer #1. A polled implementation. + * + * Params: + * [in] delayInMs - the number of milliseconds to delay. + * + ****************************************************************************/ +void delayMs(unsigned short delayInMs) +{ + /* + * setup timer #1 for delay + */ + T1TCR = 0x02; //stop and reset timer + T1PR = 0x00; //set prescaler to zero + T1MR0 = delayInMs * (Fpclk / 1000); + + T1IR = 0xff; //reset all interrrupt flags + T1MCR = 0x04; //stop timer on match + T1TCR = 0x01; //start timer + + //wait until delay time has elapsed + while (T1TCR & 0x01) + ; + +} + +/****************************************************************************** +** Function name: GPIOinit +** +** Descriptions: Sets all GPIO ports to a known state +** parameters: None +** Returned value: None +** +******************************************************************************/ +static void GPIOinit(void) +{ + PINSEL0 = 0; + PINSEL1 = 0; + PINSEL2 = 0; + PINSEL3 = 0; + PINSEL4 = 0; + PINSEL5 = 0; + PINSEL6 = 0; + PINSEL7 = 0; + PINSEL8 = 0; + PINSEL9 = 0; + PINSEL10 = 0; + + IODIR0 = 0; + IODIR1 = 0; + IOSET0 = 0xffffffff; + IOSET1 = 0xffffffff; + + FIO0DIR = 0; + FIO1DIR = 0; + FIO2DIR = 0; + FIO3DIR = 0; + FIO4DIR = 0; + + FIO0SET = 0xffffffff; + FIO1SET = 0xffffffff; + FIO2SET = 0xffffffff; + FIO3SET = 0x0; + FIO4SET = 0xffffffff; +} + +/****************************************************************************** +** Function name: VICinit +** +** Descriptions: Initialize the VIC to a known state +** parameters: None +** Returned value: None +** +******************************************************************************/ +static void VICinit(void) +{ + //initialize VIC + VICIntEnClr = 0xFFFFFFFF; /* Disable ALL interrupts */ + + VICProtection = 0; /* Setup interrupt controller */ + VICVectAddr = 0; + VICIntSelect = 0; + + VICVectAddr0 = (unsigned int)0; /* Set the vector address */ + VICVectAddr1 = (unsigned int)0; /* Set the vector address */ + VICVectAddr2 = (unsigned int)0; /* Set the vector address */ + VICVectAddr3 = (unsigned int)0; /* Set the vector address */ + VICVectAddr4 = (unsigned int)0; /* Set the vector address */ + VICVectAddr5 = (unsigned int)0; /* Set the vector address */ + VICVectAddr6 = (unsigned int)0; /* Set the vector address */ + VICVectAddr7 = (unsigned int)0; /* Set the vector address */ + VICVectAddr8 = (unsigned int)0; /* Set the vector address */ + VICVectAddr9 = (unsigned int)0; /* Set the vector address */ + VICVectAddr10 = (unsigned int)0; /* Set the vector address */ + VICVectAddr11 = (unsigned int)0; /* Set the vector address */ + VICVectAddr12 = (unsigned int)0; /* Set the vector address */ + VICVectAddr13 = (unsigned int)0; /* Set the vector address */ + VICVectAddr14 = (unsigned int)0; /* Set the vector address */ + VICVectAddr15 = (unsigned int)0; /* Set the vector address */ + VICVectAddr16 = (unsigned int)0; /* Set the vector address */ + VICVectAddr17 = (unsigned int)0; /* Set the vector address */ + VICVectAddr18 = (unsigned int)0; /* Set the vector address */ + VICVectAddr19 = (unsigned int)0; /* Set the vector address */ + VICVectAddr20 = (unsigned int)0; /* Set the vector address */ + VICVectAddr21 = (unsigned int)0; /* Set the vector address */ + VICVectAddr22 = (unsigned int)0; /* Set the vector address */ + VICVectAddr23 = (unsigned int)0; /* Set the vector address */ + VICVectAddr24 = (unsigned int)0; /* Set the vector address */ + VICVectAddr25 = (unsigned int)0; /* Set the vector address */ + VICVectAddr26 = (unsigned int)0; /* Set the vector address */ + VICVectAddr27 = (unsigned int)0; /* Set the vector address */ + VICVectAddr28 = (unsigned int)0; /* Set the vector address */ + VICVectAddr29 = (unsigned int)0; /* Set the vector address */ + VICVectAddr30 = (unsigned int)0; /* Set the vector address */ + VICVectAddr31 = (unsigned int)0; /* Set the vector address */ + + VICVectCntl0 = (unsigned int)0xf; + VICVectCntl1 = (unsigned int)0xf; + VICVectCntl2 = (unsigned int)0xf; + VICVectCntl3 = (unsigned int)0xf; + VICVectCntl4 = (unsigned int)0xf; + VICVectCntl5 = (unsigned int)0xf; + VICVectCntl6 = (unsigned int)0xf; + VICVectCntl7 = (unsigned int)0xf; + VICVectCntl8 = (unsigned int)0xf; + VICVectCntl9 = (unsigned int)0xf; + VICVectCntl10 = (unsigned int)0xf; + VICVectCntl11 = (unsigned int)0xf; + VICVectCntl12 = (unsigned int)0xf; + VICVectCntl13 = (unsigned int)0xf; + VICVectCntl14 = (unsigned int)0xf; + VICVectCntl15 = (unsigned int)0xf; + VICVectCntl16 = (unsigned int)0xf; + VICVectCntl17 = (unsigned int)0xf; + VICVectCntl18 = (unsigned int)0xf; + VICVectCntl19 = (unsigned int)0xf; + VICVectCntl20 = (unsigned int)0xf; + VICVectCntl21 = (unsigned int)0xf; + VICVectCntl22 = (unsigned int)0xf; + VICVectCntl23 = (unsigned int)0xf; + VICVectCntl24 = (unsigned int)0xf; + VICVectCntl25 = (unsigned int)0xf; + VICVectCntl26 = (unsigned int)0xf; + VICVectCntl27 = (unsigned int)0xf; + VICVectCntl28 = (unsigned int)0xf; + VICVectCntl29 = (unsigned int)0xf; + VICVectCntl30 = (unsigned int)0xf; + VICVectCntl31 = (unsigned int)0xf; +} + +/****************************************************************************** +** Function name: ConfigurePLL +** +** Descriptions: Configure the PLL +** parameters: None +** Returned value: None +** +******************************************************************************/ +void ConfigurePLL(void) +{ + + volatile unsigned long MValue; + volatile unsigned long NValue; + + if (PLLSTAT & (1 << 25)) + { + + PLLCON = 1; /* Enable PLL, disconnected */ + + PLLFEED = 0xaa; + + PLLFEED = 0x55; + + } + + PLLCON = 0; /* Disable PLL, disconnected */ + PLLFEED = 0xaa; + PLLFEED = 0x55; + SCS |= 0x20; /* Enable main OSC */ + + while (!(SCS & 0x40)) ; /* Wait until main OSC is usable */ + + CLKSRCSEL = 0x1; /* select main OSC, 12MHz, as the PLL clock source */ + PLLCFG = PLL_MValue | (PLL_NValue << 16); + PLLFEED = 0xaa; + PLLFEED = 0x55; + PLLCON = 1; /* Enable PLL, disconnected */ + PLLFEED = 0xaa; + PLLFEED = 0x55; + CCLKCFG = CCLKDivValue; /* Set clock divider */ + +#if USE_USB + USBCLKCFG = USBCLKDivValue; /* usbclk = 288 MHz/6 = 48 MHz */ + +#endif /* + */ + + while (((PLLSTAT & (1 << 26)) == 0)) ; /* Check lock bit status */ + + MValue = PLLSTAT & 0x00007FFF; + NValue = (PLLSTAT & 0x00FF0000) >> 16; + + while ((MValue != PLL_MValue) && (NValue != PLL_NValue)) ; + + PLLCON = 3; /* enable and connect */ + PLLFEED = 0xaa; + PLLFEED = 0x55; + + while (((PLLSTAT & (1 << 25)) == 0)) ; /* Check connect bit status */ + +} + +/****************************************************************************** +** Function name: ConfigureEMC +** +** Descriptions: Configure EMC for external SDRAM, NAND and NOR FLASH +** parameters: None +** Returned value: None +** +******************************************************************************/ +void ConfigureEMC(void) +{ + + volatile unsigned int i, dummy = dummy; + + EMC_CTRL = 0x00000001; + PCONP |= 0x00000800; /* Turn on EMC PCLK */ + + // CS2 & CS3 not used PINSEL4 = 0x50000000; + PINSEL5 = 0x05050555; + PINSEL6 = 0x55555555; + PINSEL8 = 0x55555555; + PINSEL9 = 0x50555555; + + //all registers... + EMC_DYN_RP = 2; //>20ns = 2 clk + EMC_DYN_RAS = 3; //>45ns = 3 clk + EMC_DYN_SREX = 7; //>80-100ns = 6 clk + EMC_DYN_APR = 2; // + EMC_DYN_DAL = 5; //2 clk + EMC_DYN_WR = 1; //2 clk + EMC_DYN_RC = 5; //>65ns = 4 clk + EMC_DYN_RFC = 5; //>80-100ns = 6 clk + EMC_DYN_XSR = 7; //>80-100ns = 6 clk + EMC_DYN_RRD = 1; //>15ns = 1-2 clk + EMC_DYN_MRD = 2; //2 clk + EMC_DYN_RD_CFG = 1; //or 1,2,3 + + // + EMC_DYN_RASCAS0 = 0x00000303; + + // + EMC_DYN_CFG0 = 0x00000680; + + //wait 100mS + delayMs(100); + + //Send command: NOP + EMC_DYN_CTRL = 0x00000183; + + //wait 200mS + delayMs(200); + + //Send command: PRECHARGE-ALL, shortest possible refresh period + EMC_DYN_CTRL = 0x00000103; + + EMC_DYN_RFSH = 0x00000002; + + //wait 128 ABH clock cycles + for (i = 0; i < 0x40; i++) + asm volatile (" nop"); + + //Set correct refresh period + EMC_DYN_RFSH = 28; + + //Send command: MODE + EMC_DYN_CTRL = 0x00000083; + + //Set mode register in SDRAM + dummy = *((volatile unsigned int *)(SDRAM_BASE_ADDR | (0x33 << 12))); + + //Send command: NORMAL + EMC_DYN_CTRL = 0x00000000; + + //Enable buffer + EMC_DYN_CFG0 |= 0x00080000; + + //initial system delay + delayMs(1); + + EMC_STA_WAITWEN0 = 0x2; + EMC_STA_WAITOEN0 = 0x2; + EMC_STA_WAITRD0 = 0x1f; + EMC_STA_WAITPAGE0 = 0x1f; + EMC_STA_WAITWR0 = 0x1f; + EMC_STA_WAITTURN0 = 0xf; + EMC_STA_CFG0 = 0x00000081; + EMC_STA_WAITWEN1 = 0x2; + EMC_STA_WAITOEN1 = 0x2; + EMC_STA_WAITRD1 = 0x8; + EMC_STA_WAITPAGE1 = 0x1f; + EMC_STA_WAITWR1 = 0x8; + EMC_STA_WAITTURN1 = 0xf; + EMC_STA_CFG1 = 0x00000080; +} + +/***************************************************************************** + * + * Description: + * Initialize system functions and GPIO + * + ****************************************************************************/ +void lowlevel_init(void) +{ + + /******************************************************************************************** + * Remap vectors for RAM execution + ********************************************************************************************/ + MEMMAP = 1; + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + /* move vectors to beginning of SRAM */ + asm volatile (" mov r2, #0x40000000 \n" + " mov r0, #0x00000000 \n" + " ldmneia r0!, {r3-r10} \n" + " stmneia r2!, {r3-r10} \n" + " ldmneia r0, {r3-r9} \n" + " stmneia r2, {r3-r9} \n"::: + "r0", "r2", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10"); +#else + /* move vectors to beginning of SRAM */ + asm volatile (" mov r2, #0x40000000 \n" + " mov r0, #0xa1000000 \n" + " ldmneia r0!, {r3-r10} \n" + " stmneia r2!, {r3-r10} \n" + " ldmneia r0, {r3-r9} \n" + " stmneia r2, {r3-r9} \n"::: + "r0", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", + "r10"); +#endif + + //initialize the exception vector mapping + MEMMAP = MEM_MAP; + +#if USE_USB + PCONP |= 0x80000000; /* Turn On USB PCLK */ + +#endif + ConfigurePLL(); + + /* Set system timers for each component */ +#if (Fpclk / (Fcclk / 4)) == 1 + PCLKSEL0 = 0x00000000; /* PCLK is 1/4 CCLK */ + PCLKSEL1 = 0x00000000; +#endif +#if (Fpclk / (Fcclk / 4)) == 2 + PCLKSEL0 = 0xAAAAAAAA; /* PCLK is 1/2 CCLK */ + PCLKSEL1 = 0xAAAAAAAA; + +#endif +#if (Fpclk / (Fcclk / 4)) == 4 + PCLKSEL0 = 0x55555555; /* PCLK is the same as CCLK */ + PCLKSEL1 = 0x55555555; +#endif + /* Set memory accelerater module */ + MAMCR = 0; + + MAMTIM = 4; + +// MAMCR = 2; + //Init GPIO + GPIOinit(); + + //initialize VIC + VICinit(); + + //short delay + delayMs(10); + + /******************************************************************************************** + * Initialize external memory interface (EMC) + ********************************************************************************************/ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + ConfigureEMC(); +#endif /* + */ +} diff -upNr u-boot-orig/board/LPC2468/LPC2468.c u-boot/board/LPC2468/LPC2468.c --- u-boot-orig/board/LPC2468/LPC2468.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot/board/LPC2468/LPC2468.c 2009-03-18 13:25:15.000000000 +0100 @@ -0,0 +1,66 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger mgroeger@sysgo.de + * + * (C) Copyright 2005 Rowel Atienza rowel@diwalabs.com + * Armadillo board HT1070 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <clps7111.h> + +/* ------------------------------------------------------------------------- */ + + +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* arch number MACH_TYPE_ARMADILLO - not official*/ + gd->bd->bi_arch_number = 1339; + + /* location of boot parameters */ + gd->bd->bi_boot_params = 0xA0000100; + + return 0; +} + +int print_cpuinfo(void) +{ + printf("CPU: LPC2468 (ARM7tdmi-s from NXP)\n" + " running at 57.6 MHz (12 MHz crystal)\n"); + return 0; +} + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return (0); +} diff -upNr u-boot-orig/board/LPC2468/Makefile u-boot/board/LPC2468/Makefile --- u-boot-orig/board/LPC2468/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ u-boot/board/LPC2468/Makefile 2009-03-18 09:30:20.000000000 +0100 @@ -0,0 +1,55 @@ + +####################################################################### +# +# Copyright (C) 2000, 2001, 2002, 2003 +# The LEOX team team@leox.org, http://www.leox.org +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# LEOX.org is about the development of free hardware and software resources +# for system on chip. +# +# Description: U-Boot port on the LEOX's ELPT860 CPU board +# ~~~~~~~~~~~ +# +####################################################################### +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +####################################################################### + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o eth.o nand.o flash.o lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff -upNr u-boot-orig/board/LPC2468/nand.c u-boot/board/LPC2468/nand.c --- u-boot-orig/board/LPC2468/nand.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot/board/LPC2468/nand.c 2009-03-18 13:38:15.000000000 +0100 @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2009 Duran Audio B.V. <www.duran-audio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * 18-03-2009 Updated for U-boot 2009.3 by Remco Poelstra remco.poelstra+u-boot@duran-audio.com + */ + +#include <common.h> +#include <nand.h> +#include <asm/io.h> + +/* + * CLE at A20 + * ALE at A19 + */ +#define MASK_CLE (1l<<20) +#define MASK_ALE (1l<<19) + +static void cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + + ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; + + if (ctrl & NAND_CTRL_CHANGE) { + IO_ADDR_W &= ~(MASK_ALE | MASK_CLE); + if (ctrl & NAND_CLE) + IO_ADDR_W |= MASK_CLE; + if (ctrl & NAND_ALE) + IO_ADDR_W |= MASK_ALE; + this->IO_ADDR_W = (void *)IO_ADDR_W; + } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); +} + +int board_nand_init(struct nand_chip *nand) +{ + /* IO_ADDR_R and IO_ADDR_W set by nand-driver using CFG_NAND_BASE */ + nand->dev_ready = 0; + nand->cmd_ctrl = cmd_ctrl; + nand->ecc.mode = NAND_ECC_SOFT; + nand->chip_delay = 25; /* us */ + nand->options = NAND_SAMSUNG_LP_OPTIONS; + + return 0; +} diff -upNr u-boot-orig/board/LPC2468/u-boot.lds u-boot/board/LPC2468/u-boot.lds --- u-boot-orig/board/LPC2468/u-boot.lds 1970-01-01 01:00:00.000000000 +0100 +++ u-boot/board/LPC2468/u-boot.lds 2009-03-18 09:30:20.000000000 +0100 @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm720t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff -upNr u-boot-orig/include/configs/LPC2468.h u-boot/include/configs/LPC2468.h --- u-boot-orig/include/configs/LPC2468.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot/include/configs/LPC2468.h 2009-03-18 10:34:25.000000000 +0100 @@ -0,0 +1,213 @@ +/* + * (C) Copyright 2008 + * Embedded Artists AB, Sweden <www.EmbeddedArtists.com> + * + * Configuation settings for the LPC2468 OEM Board, 16 bit databus. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_LPC2468 + +/* + * If we are developing, we might want to start armboot from ram + * so we MUST NOT initialize critical regs like mem-timing ... + */ +#if 0 +#define CONFIG_INIT_CRITICAL /* undef for developing */ +#endif + +#undef CONFIG_SKIP_LOWLEVEL_INIT + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM7 1 /* This is a ARM7 CPU */ +#define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */ +#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ + +/* Clock settings */ + +/* Crystal frequency */ +#define CONFIG_FOSC 12000000 + +/* + * Fcco = 2*M*Fosc / N + * + * Fcco = 288000000 -> M = 12, N = 1 + * + * PLLCFG (MSEL) = (M-1) + * PLLCFG (NSEL) = (N-1) + */ +#define CONFIG_PLL_MVALUE 12 +#define CONFIG_PLL_NVALUE 1 + +/* + * Fcclk = Fcco / CLKDIV + * CLKDIV must be an even number + * + * CCLKCFG = CLKDIV-1 (odd number must be written to register) + * CLKDIV = 4 -> Fcclk = 72 MHz (if Fcco = 288 MHz) + * CLKDIV = 6 -> Fcclk = 48 MHz (if Fcco = 288 MHz) + */ +#define CONFIG_PLL_CLKDIV 4 + +/* + * The USB clock must be 48 MHz + * Fusb = Fcco / USBCLKDIV + * USBCLKCFG = (USBCLKDIV-1) + */ +#define CONFIG_PLL_USBCLKDIV 6 + +/* + * Periperhal clock divider, i.e. Fpclk = Fcclk / divider + * Valid values are 1, 2, or 4 + */ +#define CONFIG_FPCLK_DIV 1 + +#define CONFIG_USE_IRQ /* use irq for mci interface */ + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* we use Serial line 1 */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) + +#include <config_cmd_default.h> +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_BOOTD +#define CONFIG_CMD_NAND + +#define CONFIG_BOOTARGS "root=/dev/ram initrd=0xa1800000,4000k console=ttyS0,115200N8" + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0xA0000000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0xA1F80000 /* 31.5 MB in DRAM, U-boot is relocated after this location */ +#define CONFIG_SYS_ALT_MEMTEST + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR 0xA0008000 /* default load address for kernel img is here*/ + + +#define CLK_FCCO ((2*CONFIG_PLL_MVALUE*CONFIG_FOSC) / CONFIG_PLL_NVALUE) + +#define CFG_SYS_CLK_FREQ (CLK_FCCO / CONFIG_PLL_CLKDIV)/* Hz */ +#define CONFIG_SYS_HZ 200000 /* decrementer freq in Hz */ + + /* valid baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (8*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0xA0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB SDRAM */ + +#define PHYS_FLASH_1 0x80000000 /* Flash Bank #1 */ +#define PHYS_FLASH_SIZE 0x00400000 /* 4 MB */ + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ + +/* + * Linux tags + */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +/* + * NAND Flash + */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_NAND_BASE 0x81000000 + + +/* + * Default environment settings + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "ipaddr=192.168.3.2" \ + "netmask=255.255.255.0" \ + "serverip=192.168.3.1" \ + "ethaddr=00:1a:f1:00:00:00" + +/* + * Control where environment is stored + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR (0x0 + 0x7C000) /* Addr of Environment Sector */ +#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector(4k) */ + +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT "LPC2468 # " + +#endif /* __CONFIG_H */ diff -upNr u-boot-orig/MAKEALL u-boot/MAKEALL --- u-boot-orig/MAKEALL 2009-03-18 00:42:12.000000000 +0100 +++ u-boot/MAKEALL 2009-03-18 13:51:02.000000000 +0100 @@ -481,6 +481,7 @@ LIST_ARM7=" \ impa7 \ integratorap \ lpc2292sodimm \ + LPC2468 \ modnet50 \ SMN42 \ " diff -upNr u-boot-orig/Makefile u-boot/Makefile --- u-boot-orig/Makefile 2009-03-18 00:42:12.000000000 +0100 +++ u-boot/Makefile 2009-03-18 09:29:58.000000000 +0100 @@ -2899,6 +2899,9 @@ B2_config : unconfig ## ARM720T Systems #########################################################################
+LPC2468_config: unconfig + @$(MKCONFIG) $(@:_config=) arm arm720t LPC2468 NULL lpc24xx + armadillo_config: unconfig @$(MKCONFIG) $(@:_config=) arm arm720t armadillo
On 15:56 Wed 18 Mar , Remco Poelstra wrote:
Example board for LPC2468 support
Signed-off-by: Remco Poelstra remco.poelstra+u-boot@duran-audio.com
diff -upNr u-boot-orig/board/LPC2468/config.mk u-boot/board/LPC2468/config.mk --- u-boot-orig/board/LPC2468/config.mk 1970-01-01 01:00:00.000000000 +0100 +++ u-boot/board/LPC2468/config.mk 2009-03-18 09:30:20.000000000 +0100 @@ -0,0 +1,29 @@ +# +# (C) Copyright 2000 +# Sysgo Real-Time Solutions, GmbH <www.elinos.com> +# Marius Groeger mgroeger@sysgo.de +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +#
+#address where u-boot will be relocated +TEXT_BASE = 0xA1f80000
please move the eth to drivers/net
diff -upNr u-boot-orig/board/LPC2468/eth.c u-boot/board/LPC2468/eth.c --- u-boot-orig/board/LPC2468/eth.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot/board/LPC2468/eth.c 2009-03-18 15:33:31.000000000 +0100 @@ -0,0 +1,694 @@ +/*
- (C) Copyright 2009 Duran Audio B.V. <www.duran-audio.com>
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- 18-03-2009 Updated for U-boot 2009.3 by Remco Poelstra remco.poelstra+u-boot@duran-audio.com
- Based on sample code from NXP
- */
+#include <config.h> +#include <common.h> +#include <net.h> +#include <asm/arch/hardware.h>
please move define to a header please fix the whitespace please remove dead code please use proper access why do you need your own flash driver? please use the generic cfi drivers please check the coding style
+/******************************************************************************
- Typedefs and defines
- *****************************************************************************/
+#define MAX_PHY_INIT_RETRY 10
+/* EMAC MODULE ID */ +#define OLD_EMAC_MODULE_ID ((0x3902 << 16) | 0x2000)
+/* MAC registers and parameters */ +#define PCONP_EMAC_CLOCK 0x40000000
+#define SPEED_100 1 +#define SPEED_10 0 +#define FULL_DUPLEX 1 +#define HALF_DUPLEX 0
+#define EMAC_RAM_ADDR 0x7FE00000 +#define EMAC_RAM_SIZE 0x00004000
+//#define EMAC_TX_DESCRIPTOR_COUNT 0x0010 +//#define EMAC_RX_DESCRIPTOR_COUNT 0x0010
diff -upNr u-boot-orig/board/LPC2468/lowlevel_init.c u-boot/board/LPC2468/lowlevel_init.c --- u-boot-orig/board/LPC2468/lowlevel_init.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot/board/LPC2468/lowlevel_init.c 2009-03-18 15:35:21.000000000 +0100 @@ -0,0 +1,436 @@ +/*
- (C) Copyright 2006-2007 Embedded Artists AB <www.embeddedartists.com>
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#include <config.h> +#include <version.h> +#include <exports.h> +#include <asm/arch/hardware.h> +#include <asm/hardware.h>
+/******************************************************************************
- Defines, macros, and typedefs
- *****************************************************************************/
+#define USE_USB 1
+#define PLL_MValue (CONFIG_PLL_MVALUE-1) +#define PLL_NValue (CONFIG_PLL_NVALUE-1) +#define CCLKDivValue (CONFIG_PLL_CLKDIV-1) +#define USBCLKDivValue (CONFIG_PLL_USBCLKDIV-1)
+#define Fcco ((2*CONFIG_PLL_MVALUE*CONFIG_FOSC) / CONFIG_PLL_NVALUE) +#define Fcclk (Fcco / CONFIG_PLL_CLKDIV) +#define Fpclk (Fcclk / CONFIG_FPCLK_DIV) +#define MAM_SETTING 1 /* 0=disabled,
1=partly enabled (enabled for code prefetch, but not for data),2=fully enabled */+#define MEM_MAP 2 /* When executing from RAM, MAM_MAP should always be 2 */ +#define SDRAM_BASE_ADDR 0xA0000000 +#define m_reg_write(reg,data) ((*(volatile unsigned long *)(reg)) = (volatile unsigned long)(data)) +/*****************************************************************************
- Description:
- Delay execution by a specified number of milliseconds by using
- timer #1. A polled implementation.
- Params:
- [in] delayInMs - the number of milliseconds to delay.
- ****************************************************************************/
+void delayMs(unsigned short delayInMs) +{
- /*
* setup timer #1 for delay*/- T1TCR = 0x02; //stop and reset timer
- T1PR = 0x00; //set prescaler to zero
- T1MR0 = delayInMs * (Fpclk / 1000);
- T1IR = 0xff; //reset all interrrupt flags
- T1MCR = 0x04; //stop timer on match
- T1TCR = 0x01; //start timer
- //wait until delay time has elapsed
- while (T1TCR & 0x01)
;+}
please implemet and use timer
+/****************************************************************************** +** Function name: GPIOinit +** +** Descriptions: Sets all GPIO ports to a known state +** parameters: None +** Returned value: None +** +******************************************************************************/ +static void GPIOinit(void) +{
- PINSEL0 = 0;
- PINSEL1 = 0;
- PINSEL2 = 0;
- PINSEL3 = 0;
- PINSEL4 = 0;
- PINSEL5 = 0;
- PINSEL6 = 0;
- PINSEL7 = 0;
- PINSEL8 = 0;
- PINSEL9 = 0;
- PINSEL10 = 0;
- IODIR0 = 0;
- IODIR1 = 0;
- IOSET0 = 0xffffffff;
- IOSET1 = 0xffffffff;
- FIO0DIR = 0;
- FIO1DIR = 0;
- FIO2DIR = 0;
- FIO3DIR = 0;
- FIO4DIR = 0;
- FIO0SET = 0xffffffff;
- FIO1SET = 0xffffffff;
- FIO2SET = 0xffffffff;
- FIO3SET = 0x0;
- FIO4SET = 0xffffffff;
+}
??? please explain what do you do? please try use access as at91 or other mach
+/****************************************************************************** +** Function name: VICinit +** +** Descriptions: Initialize the VIC to a known state +** parameters: None +** Returned value: None +** +******************************************************************************/ +static void VICinit(void) +{
- //initialize VIC
- VICIntEnClr = 0xFFFFFFFF; /* Disable ALL interrupts */
- VICProtection = 0; /* Setup interrupt controller */
- VICVectAddr = 0;
- VICIntSelect = 0;
- VICVectAddr0 = (unsigned int)0; /* Set the vector address */
- VICVectAddr1 = (unsigned int)0; /* Set the vector address */
- VICVectAddr2 = (unsigned int)0; /* Set the vector address */
- VICVectAddr3 = (unsigned int)0; /* Set the vector address */
- VICVectAddr4 = (unsigned int)0; /* Set the vector address */
- VICVectAddr5 = (unsigned int)0; /* Set the vector address */
- VICVectAddr6 = (unsigned int)0; /* Set the vector address */
- VICVectAddr7 = (unsigned int)0; /* Set the vector address */
- VICVectAddr8 = (unsigned int)0; /* Set the vector address */
- VICVectAddr9 = (unsigned int)0; /* Set the vector address */
- VICVectAddr10 = (unsigned int)0; /* Set the vector address */
- VICVectAddr11 = (unsigned int)0; /* Set the vector address */
- VICVectAddr12 = (unsigned int)0; /* Set the vector address */
- VICVectAddr13 = (unsigned int)0; /* Set the vector address */
- VICVectAddr14 = (unsigned int)0; /* Set the vector address */
- VICVectAddr15 = (unsigned int)0; /* Set the vector address */
- VICVectAddr16 = (unsigned int)0; /* Set the vector address */
- VICVectAddr17 = (unsigned int)0; /* Set the vector address */
- VICVectAddr18 = (unsigned int)0; /* Set the vector address */
- VICVectAddr19 = (unsigned int)0; /* Set the vector address */
- VICVectAddr20 = (unsigned int)0; /* Set the vector address */
- VICVectAddr21 = (unsigned int)0; /* Set the vector address */
- VICVectAddr22 = (unsigned int)0; /* Set the vector address */
- VICVectAddr23 = (unsigned int)0; /* Set the vector address */
- VICVectAddr24 = (unsigned int)0; /* Set the vector address */
- VICVectAddr25 = (unsigned int)0; /* Set the vector address */
- VICVectAddr26 = (unsigned int)0; /* Set the vector address */
- VICVectAddr27 = (unsigned int)0; /* Set the vector address */
- VICVectAddr28 = (unsigned int)0; /* Set the vector address */
- VICVectAddr29 = (unsigned int)0; /* Set the vector address */
- VICVectAddr30 = (unsigned int)0; /* Set the vector address */
- VICVectAddr31 = (unsigned int)0; /* Set the vector address */
- VICVectCntl0 = (unsigned int)0xf;
- VICVectCntl1 = (unsigned int)0xf;
- VICVectCntl2 = (unsigned int)0xf;
- VICVectCntl3 = (unsigned int)0xf;
- VICVectCntl4 = (unsigned int)0xf;
- VICVectCntl5 = (unsigned int)0xf;
- VICVectCntl6 = (unsigned int)0xf;
- VICVectCntl7 = (unsigned int)0xf;
- VICVectCntl8 = (unsigned int)0xf;
- VICVectCntl9 = (unsigned int)0xf;
- VICVectCntl10 = (unsigned int)0xf;
- VICVectCntl11 = (unsigned int)0xf;
- VICVectCntl12 = (unsigned int)0xf;
- VICVectCntl13 = (unsigned int)0xf;
- VICVectCntl14 = (unsigned int)0xf;
- VICVectCntl15 = (unsigned int)0xf;
- VICVectCntl16 = (unsigned int)0xf;
- VICVectCntl17 = (unsigned int)0xf;
- VICVectCntl18 = (unsigned int)0xf;
- VICVectCntl19 = (unsigned int)0xf;
- VICVectCntl20 = (unsigned int)0xf;
- VICVectCntl21 = (unsigned int)0xf;
- VICVectCntl22 = (unsigned int)0xf;
- VICVectCntl23 = (unsigned int)0xf;
- VICVectCntl24 = (unsigned int)0xf;
- VICVectCntl25 = (unsigned int)0xf;
- VICVectCntl26 = (unsigned int)0xf;
- VICVectCntl27 = (unsigned int)0xf;
- VICVectCntl28 = (unsigned int)0xf;
- VICVectCntl29 = (unsigned int)0xf;
- VICVectCntl30 = (unsigned int)0xf;
- VICVectCntl31 = (unsigned int)0xf;
+}
please try to use loop
+/****************************************************************************** +** Function name: ConfigurePLL +** +** Descriptions: Configure the PLL +** parameters: None +** Returned value: None +** +******************************************************************************/ +void ConfigurePLL(void) +{
- volatile unsigned long MValue;
- volatile unsigned long NValue;
- if (PLLSTAT & (1 << 25))
- {
PLLCON = 1; /* Enable PLL, disconnected */PLLFEED = 0xaa;PLLFEED = 0x55;- }
- PLLCON = 0; /* Disable PLL, disconnected */
- PLLFEED = 0xaa;
- PLLFEED = 0x55;
- SCS |= 0x20; /* Enable main OSC */
- while (!(SCS & 0x40)) ; /* Wait until main OSC is usable */
- CLKSRCSEL = 0x1; /* select main OSC, 12MHz, as the PLL clock source */
- PLLCFG = PLL_MValue | (PLL_NValue << 16);
- PLLFEED = 0xaa;
- PLLFEED = 0x55;
- PLLCON = 1; /* Enable PLL, disconnected */
- PLLFEED = 0xaa;
- PLLFEED = 0x55;
- CCLKCFG = CCLKDivValue; /* Set clock divider */
+#if USE_USB
- USBCLKCFG = USBCLKDivValue; /* usbclk = 288 MHz/6 = 48 MHz */
+#endif /*
*/- while (((PLLSTAT & (1 << 26)) == 0)) ; /* Check lock bit status */
- MValue = PLLSTAT & 0x00007FFF;
- NValue = (PLLSTAT & 0x00FF0000) >> 16;
- while ((MValue != PLL_MValue) && (NValue != PLL_NValue)) ;
- PLLCON = 3; /* enable and connect */
- PLLFEED = 0xaa;
- PLLFEED = 0x55;
- while (((PLLSTAT & (1 << 25)) == 0)) ; /* Check connect bit status */
+}
+/****************************************************************************** +** Function name: ConfigureEMC +** +** Descriptions: Configure EMC for external SDRAM, NAND and NOR FLASH +** parameters: None +** Returned value: None +** +******************************************************************************/ +void ConfigureEMC(void) +{
- volatile unsigned int i, dummy = dummy;
- EMC_CTRL = 0x00000001;
- PCONP |= 0x00000800; /* Turn on EMC PCLK */
- // CS2 & CS3 not used PINSEL4 = 0x50000000;
- PINSEL5 = 0x05050555;
- PINSEL6 = 0x55555555;
- PINSEL8 = 0x55555555;
- PINSEL9 = 0x50555555;
- //all registers...
- EMC_DYN_RP = 2; //>20ns = 2 clk
- EMC_DYN_RAS = 3; //>45ns = 3 clk
- EMC_DYN_SREX = 7; //>80-100ns = 6 clk
- EMC_DYN_APR = 2; //
- EMC_DYN_DAL = 5; //2 clk
- EMC_DYN_WR = 1; //2 clk
- EMC_DYN_RC = 5; //>65ns = 4 clk
- EMC_DYN_RFC = 5; //>80-100ns = 6 clk
- EMC_DYN_XSR = 7; //>80-100ns = 6 clk
- EMC_DYN_RRD = 1; //>15ns = 1-2 clk
- EMC_DYN_MRD = 2; //2 clk
- EMC_DYN_RD_CFG = 1; //or 1,2,3
- //
- EMC_DYN_RASCAS0 = 0x00000303;
- //
- EMC_DYN_CFG0 = 0x00000680;
- //wait 100mS
- delayMs(100);
- //Send command: NOP
- EMC_DYN_CTRL = 0x00000183;
- //wait 200mS
- delayMs(200);
- //Send command: PRECHARGE-ALL, shortest possible refresh period
- EMC_DYN_CTRL = 0x00000103;
- EMC_DYN_RFSH = 0x00000002;
- //wait 128 ABH clock cycles
- for (i = 0; i < 0x40; i++)
asm volatile (" nop");- //Set correct refresh period
- EMC_DYN_RFSH = 28;
- //Send command: MODE
- EMC_DYN_CTRL = 0x00000083;
- //Set mode register in SDRAM
- dummy = *((volatile unsigned int *)(SDRAM_BASE_ADDR | (0x33 << 12)));
- //Send command: NORMAL
- EMC_DYN_CTRL = 0x00000000;
- //Enable buffer
- EMC_DYN_CFG0 |= 0x00080000;
- //initial system delay
- delayMs(1);
- EMC_STA_WAITWEN0 = 0x2;
- EMC_STA_WAITOEN0 = 0x2;
- EMC_STA_WAITRD0 = 0x1f;
- EMC_STA_WAITPAGE0 = 0x1f;
- EMC_STA_WAITWR0 = 0x1f;
- EMC_STA_WAITTURN0 = 0xf;
- EMC_STA_CFG0 = 0x00000081;
- EMC_STA_WAITWEN1 = 0x2;
- EMC_STA_WAITOEN1 = 0x2;
- EMC_STA_WAITRD1 = 0x8;
- EMC_STA_WAITPAGE1 = 0x1f;
- EMC_STA_WAITWR1 = 0x8;
- EMC_STA_WAITTURN1 = 0xf;
- EMC_STA_CFG1 = 0x00000080;
+}
+/*****************************************************************************
- Description:
- Initialize system functions and GPIO
- ****************************************************************************/
+void lowlevel_init(void) +{
- /********************************************************************************************
- Remap vectors for RAM execution
- ********************************************************************************************/
- MEMMAP = 1;
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- /* move vectors to beginning of SRAM */
- asm volatile (" mov r2, #0x40000000 \n"
" mov r0, #0x00000000 \n"" ldmneia r0!, {r3-r10} \n"" stmneia r2!, {r3-r10} \n"" ldmneia r0, {r3-r9} \n"" stmneia r2, {r3-r9} \n":::"r0", "r2", "r3", "r4", "r5", "r6", "r7","r8", "r9", "r10");+#else
- /* move vectors to beginning of SRAM */
- asm volatile (" mov r2, #0x40000000 \n"
" mov r0, #0xa1000000 \n"" ldmneia r0!, {r3-r10} \n"" stmneia r2!, {r3-r10} \n"" ldmneia r0, {r3-r9} \n"" stmneia r2, {r3-r9} \n":::"r0", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9","r10");+#endif
- //initialize the exception vector mapping
- MEMMAP = MEM_MAP;
+#if USE_USB
- PCONP |= 0x80000000; /* Turn On USB PCLK */
+#endif
- ConfigurePLL();
- /* Set system timers for each component */
+#if (Fpclk / (Fcclk / 4)) == 1
- PCLKSEL0 = 0x00000000; /* PCLK is 1/4 CCLK */
- PCLKSEL1 = 0x00000000;
+#endif +#if (Fpclk / (Fcclk / 4)) == 2
- PCLKSEL0 = 0xAAAAAAAA; /* PCLK is 1/2 CCLK */
- PCLKSEL1 = 0xAAAAAAAA;
+#endif +#if (Fpclk / (Fcclk / 4)) == 4
- PCLKSEL0 = 0x55555555; /* PCLK is the same as CCLK */
- PCLKSEL1 = 0x55555555;
+#endif
- /* Set memory accelerater module */
- MAMCR = 0;
- MAMTIM = 4;
+// MAMCR = 2;
- //Init GPIO
- GPIOinit();
- //initialize VIC
- VICinit();
- //short delay
- delayMs(10);
- /********************************************************************************************
- Initialize external memory interface (EMC)
- ********************************************************************************************/
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- ConfigureEMC();
+#endif /*
*/+} diff -upNr u-boot-orig/board/LPC2468/LPC2468.c u-boot/board/LPC2468/LPC2468.c --- u-boot-orig/board/LPC2468/LPC2468.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot/board/LPC2468/LPC2468.c 2009-03-18 13:25:15.000000000 +0100 @@ -0,0 +1,66 @@ +/*
- (C) Copyright 2002
- Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- Marius Groeger mgroeger@sysgo.de
- (C) Copyright 2005 Rowel Atienza rowel@diwalabs.com
- Armadillo board HT1070
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#include <common.h> +#include <clps7111.h>
+/* ------------------------------------------------------------------------- */
+/*
- Miscelaneous platform dependent initialisations
- */
+int board_init (void) +{
- DECLARE_GLOBAL_DATA_PTR;
- /* arch number MACH_TYPE_ARMADILLO - not official*/
- gd->bd->bi_arch_number = 1339;
please a valid ARCH NUMBER macro (mandatory)
- /* location of boot parameters */
- gd->bd->bi_boot_params = 0xA0000100;
- return 0;
+}
+int print_cpuinfo(void) +{
- printf("CPU: LPC2468 (ARM7tdmi-s from NXP)\n"
" running at 57.6 MHz (12 MHz crystal)\n");- return 0;
+}
+int dram_init (void) +{
- DECLARE_GLOBAL_DATA_PTR;
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- return (0);
+}
please clean up first before a full review
Best Regards, J.
Jean-Christophe PLAGNIOL-VILLARD schreef:
please clean up first before a full review
Hi,
This patch is outdated. After the part 1 patch is OK, I'll work on this part. I'll include your comments then.
Kind regards,
Remco Poelstra
Added example board for LPC2468 processor
Signed-off-by: Remco Poelstra <remco.poelstra+u-boot@duran-audio.com --- From ab9ef1e9c2bd8f04612429461baa5c24dbc52266 Mon Sep 17 00:00:00 2001 From: Remco Poelstra remco.poelstra@duran-audio.com Date: Tue, 28 Apr 2009 15:04:33 +0200 Subject: [PATCH] Added example board for LPC2468 processor
--- board/LPC2468/LPC2468.c | 65 +++++ board/LPC2468/Makefile | 55 +++++ board/LPC2468/config.mk | 29 +++ board/LPC2468/flash.c | 255 +++++++++++++++++++ board/LPC2468/lowlevel_init.c | 445 ++++++++++++++++++++++++++++++++++ board/LPC2468/nand.c | 63 +++++ board/LPC2468/u-boot.lds | 55 +++++ include/asm-arm/arch-lpc24xx/immap.h | 142 ++++++++++- include/configs/LPC2468.h | 220 +++++++++++++++++ 9 files changed, 1319 insertions(+), 10 deletions(-) create mode 100644 board/LPC2468/LPC2468.c create mode 100755 board/LPC2468/Makefile create mode 100755 board/LPC2468/config.mk create mode 100644 board/LPC2468/flash.c create mode 100644 board/LPC2468/lowlevel_init.c create mode 100755 board/LPC2468/nand.c create mode 100755 board/LPC2468/u-boot.lds create mode 100644 include/configs/LPC2468.h
diff --git a/board/LPC2468/LPC2468.c b/board/LPC2468/LPC2468.c new file mode 100644 index 0000000..498885f --- /dev/null +++ b/board/LPC2468/LPC2468.c @@ -0,0 +1,65 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger mgroeger@sysgo.de + * + * (C) Copyright 2005 Rowel Atienza rowel@diwalabs.com + * Armadillo board HT1070 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <clps7111.h> + +/* ------------------------------------------------------------------------- */ + +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* arch number MACH_TYPE_ARMADILLO - not official */ + gd->bd->bi_arch_number = 1339; + + /* location of boot parameters */ + gd->bd->bi_boot_params = 0xA0000100; + + return 0; +} + +int print_cpuinfo (void) +{ + printf ("CPU: LPC2468 (ARM7tdmi-s from NXP)\n" + " running at 57.6 MHz (12 MHz crystal)\n"); + return 0; +} + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return (0); +} diff --git a/board/LPC2468/Makefile b/board/LPC2468/Makefile new file mode 100755 index 0000000..19a2cd7 --- /dev/null +++ b/board/LPC2468/Makefile @@ -0,0 +1,55 @@ + +####################################################################### +# +# Copyright (C) 2000, 2001, 2002, 2003 +# The LEOX team team@leox.org, http://www.leox.org +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# LEOX.org is about the development of free hardware and software resources +# for system on chip. +# +# Description: U-Boot port on the LEOX's ELPT860 CPU board +# ~~~~~~~~~~~ +# +####################################################################### +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +####################################################################### + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o nand.o flash.o lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/LPC2468/config.mk b/board/LPC2468/config.mk new file mode 100755 index 0000000..6dc9e0b --- /dev/null +++ b/board/LPC2468/config.mk @@ -0,0 +1,29 @@ +# +# (C) Copyright 2000 +# Sysgo Real-Time Solutions, GmbH <www.elinos.com> +# Marius Groeger mgroeger@sysgo.de +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +#address where u-boot will be relocated +TEXT_BASE = 0xA1f80000 diff --git a/board/LPC2468/flash.c b/board/LPC2468/flash.c new file mode 100644 index 0000000..9d61b43 --- /dev/null +++ b/board/LPC2468/flash.c @@ -0,0 +1,255 @@ +/* + * (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com> + * + * (C) Copyright 2009 Duran Audio B.V. <www.duran-audio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * 18-03-2009 Updated for U-boot 2009.3 + * by Remco Poelstra remco.poelstra+u-boot@duran-audio.com + */ + +#include <common.h> +#include <asm/io.h> + +#define SST_BASEADDR 0x80000000 +#define SST_ADDR1 SST_BASEADDR + (0x5555<<1) +#define SST_ADDR2 SST_BASEADDR + (0x2AAA<<1) + +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; + +extern void iap_entry (unsigned long *command, unsigned long *result); + +extern int lpc24xx_copy_buffer_to_flash (flash_info_t *, ulong); +extern int lpc24xx_flash_erase (flash_info_t *, int, int); +extern int lpc24xx_write_buff (flash_info_t *, uchar *, ulong, ulong); + +/*----------------------------------------------------------------------- + * + */ + +void write_word_sst (ulong addr, ushort data) +{ + ushort tmp; + + writew (0x00AA, SST_ADDR1); + writew (0x0055, SST_ADDR2); + writew (0x00A0, SST_ADDR1); + writew (data, addr); + /* do data polling */ + do { + tmp = readw (addr); + } while (tmp != data); +} + +/*----------------------------------------------------------------------- + */ + +ulong flash_init (void) +{ + int j, k; + ulong size = 0; + ulong flashbase = 0; + + flash_info[0].flash_id = (PHILIPS_LPC2468 & FLASH_VENDMASK); + flash_info[0].size = 0x007D000; /* 512 - 12 KB */ + flash_info[0].sector_count = 27; + memset (flash_info[0].protect, 0, 27); + flashbase = 0x00000000; + for (j = 0, k = 0; j < 8; j++, k++) { + flash_info[0].start[k] = flashbase; + flashbase += 0x00001000; + } + for (j = 0; j < 14; j++, k++) { + flash_info[0].start[k] = flashbase; + flashbase += 0x00008000; + } + for (j = 0; j < 5; j++, k++) { + flash_info[0].start[k] = flashbase; + flashbase += 0x00001000; + } + size += flash_info[0].size; + + flash_info[1].flash_id = (SST_MANUFACT & FLASH_VENDMASK); + flash_info[1].size = 0x00400000; /* 4 MB */ + flash_info[1].sector_count = 1024; + memset (flash_info[1].protect, 0, 1024); + flashbase = SST_BASEADDR; + for (j = 0; j < 1024; j++) { + flash_info[1].start[j] = flashbase; + flashbase += 0x1000; /* 4 KB sectors */ + } + size += flash_info[1].size; + + /* Protect monitor and environment sectors */ + flash_protect (FLAG_PROTECT_SET, + 0x0, 0x0 + monitor_flash_len - 1, &flash_info[0]); + +#ifdef CFG_ENV_IS_IN_FLASH + flash_protect (FLAG_PROTECT_SET, + CONFIG_ENV_ADDR, + CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); +#endif + + return size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + int erased = 0; + unsigned long j; + unsigned long count; + unsigned char *p; + + switch (info->flash_id & FLASH_VENDMASK) { + case (SST_MANUFACT & FLASH_VENDMASK): + printf ("SST: "); + break; + case (PHILIPS_LPC2468 & FLASH_VENDMASK): + printf ("Philips: "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + printf (" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) { + printf ("\n "); + } + if (i < (info->sector_count - 1)) { + count = info->start[i + 1] - info->start[i]; + } else { + count = info->start[0] + info->size - info->start[i]; + } + p = (unsigned char *)(info->start[i]); + erased = 1; + for (j = 0; j < count; j++) { + if (*p != 0xFF) { + erased = 0; + break; + } + p++; + } + printf (" %08lX%s%s", info->start[i], + info->protect[i] ? " RO" : " ", + erased ? " E" : " "); + } + printf ("\n"); +} + +int flash_erase_sst (flash_info_t * info, int s_first, int s_last) +{ + int i; + + for (i = s_first; i <= s_last; i++) { + writel (0x00AA, SST_ADDR1); + writel (0x0055, SST_ADDR2); + writel (0x0080, SST_ADDR1); + writel (0x00AA, SST_ADDR1); + writel (0x0055, SST_ADDR2); + writel (0x0030, info->start[i]); + /* wait for erase to finish */ + udelay (25000); + } + + return ERR_OK; +} + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + switch (info->flash_id & FLASH_VENDMASK) { + case (SST_MANUFACT & FLASH_VENDMASK): + return flash_erase_sst (info, s_first, s_last); + case (PHILIPS_LPC2468 & FLASH_VENDMASK): + return lpc24xx_flash_erase (info, s_first, s_last); + default: + return ERR_PROTECTED; + } + return ERR_PROTECTED; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash. + * + * cnt is in bytes + */ + +int write_buff_sst (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ushort tmp; + ulong i; + uchar *src_org; + uchar *dst_org; + ulong cnt_org = cnt; + int ret = ERR_OK; + + src_org = src; + dst_org = (uchar *) addr; + + if (addr & 1) { /* if odd address */ + tmp = *((uchar *) (addr - 1)); /* little endian */ + tmp |= (*src << 8); + write_word_sst (addr - 1, tmp); + addr += 1; + cnt -= 1; + src++; + } + while (cnt > 1) { + tmp = ((*(src + 1)) << 8) + (*src); /* little endian */ + write_word_sst (addr, tmp); + addr += 2; + src += 2; + cnt -= 2; + } + if (cnt > 0) { + tmp = (*((uchar *) (addr + 1))) << 8; + tmp |= *src; + write_word_sst (addr, tmp); + } + + for (i = 0; i < cnt_org; i++) { + if (*dst_org != *src_org) { + printf ("Write failed. Byte %lX differs\n", i); + ret = ERR_PROG_ERROR; + break; + } + dst_org++; + src_org++; + } + + return ret; +} + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + switch (info->flash_id & FLASH_VENDMASK) { + case (SST_MANUFACT & FLASH_VENDMASK): + return write_buff_sst (info, src, addr, cnt); + case (PHILIPS_LPC2468 & FLASH_VENDMASK): + return lpc24xx_write_buff (info, src, addr, cnt); + default: + return ERR_PROG_ERROR; + } + return ERR_PROG_ERROR; +} diff --git a/board/LPC2468/lowlevel_init.c b/board/LPC2468/lowlevel_init.c new file mode 100644 index 0000000..f7d7698 --- /dev/null +++ b/board/LPC2468/lowlevel_init.c @@ -0,0 +1,445 @@ +/* + * (C) Copyright 2006-2007 Embedded Artists AB <www.embeddedartists.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <exports.h> +#include <asm/arch/immap.h> +#include <asm/io.h> + +/****************************************************************************** + * Defines, macros, and typedefs + *****************************************************************************/ + +#define USE_USB 1 + +#define PLL_MValue (CONFIG_PLL_MVALUE-1) +#define PLL_NValue (CONFIG_PLL_NVALUE-1) +#define CCLKDivValue (CONFIG_PLL_CLKDIV-1) +#define USBCLKDivValue (CONFIG_PLL_USBCLKDIV-1) + +#define Fcco ((2*CONFIG_PLL_MVALUE*CONFIG_FOSC) / CONFIG_PLL_NVALUE) +#define Fcclk (Fcco / CONFIG_PLL_CLKDIV) +#define Fpclk (Fcclk / CONFIG_FPCLK_DIV) +#define MAM_SETTING 1 /* 0=disabled, + 1=partly enabled (enabled for code prefetch, + but not for data), + 2=fully enabled */ +#define MEM_MAP 2 /*When executing from RAM, MAM_MAP should always be 2*/ +#define SDRAM_BASE_ADDR 0xA0000000 +#define FASTIO_BASE_ADDR 0x3FFF8000 + +/* Helper macros */ +#define BFS32(reg,value) writel( (readl(reg)|=(value)) ,reg) +#define BFC32(reg,value) writel( (readl(reg)&=(~value)) ,reg) + +/***************************************************************************** + * + * Description: + * Delay execution by a specified number of milliseconds by using + * timer #1. A polled implementation. + * + * Params: + * [in] delayInMs - the number of milliseconds to delay. + * + ****************************************************************************/ +void delayMs (unsigned short delayInMs) +{ + timer_2468_t *timer=&(((immap_t *)CONFIG_SYS_IMMAP)->apb.timer1); + /* + * setup timer #1 for delay + */ + writel (0x02, &(timer->tcr)); /*stop and reset timer */ + writel (0x00, &(timer->pr)); /*set prescaler to zero */ + writel (delayInMs * (Fpclk / 1000), &(timer->mr0)); + + writel (0xff, &(timer->ir)); /*reset all interrrupt flags */ + writel (0x04, &(timer->mcr)); /*stop timer on match */ + writel (0x01, &(timer->tcr)); /*start timer */ + + /*wait until delay time has elapsed */ + while (readl (&(timer->tcr)) & 0x01) ; + +} + +/****************************************************************************** +** Function name: GPIOinit +** +** Descriptions: Sets all GPIO ports to a known state +** parameters: None +** Returned value: None +** +******************************************************************************/ +static void GPIOinit (void) +{ + pin_connect_2468_t *pin_connect= + &(((immap_t *)CONFIG_SYS_IMMAP)->apb.pin_connect); + gpio_2468_t *gpio= + &(((immap_t *)CONFIG_SYS_IMMAP)->apb.gpio); + fastio_2468_t *fio=(fastio_2468_t *)FASTIO_BASE_ADDR; + + writel (0, &(pin_connect->pinsel0)); + writel (0, &(pin_connect->pinsel1)); + writel (0, &(pin_connect->pinsel2)); + writel (0, &(pin_connect->pinsel3)); + writel (0, &(pin_connect->pinsel4)); + writel (0, &(pin_connect->pinsel5)); + writel (0, &(pin_connect->pinsel6)); + writel (0, &(pin_connect->pinsel7)); + writel (0, &(pin_connect->pinsel8)); + writel (0, &(pin_connect->pinsel9)); + writel (0, &(pin_connect->pinsel10)); + + writel (0, &(gpio->iodir0)); + writel (0, &(gpio->iodir1)); + writel (0xffffffff, &(gpio->ioset0)); + writel (0xffffffff, &(gpio->ioset1)); + + writel (0, &(fio->fio0dir)); + writel (0, &(fio->fio1dir)); + writel (0, &(fio->fio2dir)); + writel (0, &(fio->fio3dir)); + writel (0, &(fio->fio4dir)); + + writel (0xffffffff, &(fio->fio0set)); + writel (0xffffffff, &(fio->fio1set)); + writel (0xffffffff, &(fio->fio2set)); + writel (0, &(fio->fio3set)); + writel (0xffffffff, &(fio->fio4set)); +} + +/****************************************************************************** +** Function name: VICinit +** +** Descriptions: Initialize the VIC to a known state +** parameters: None +** Returned value: None +** +******************************************************************************/ +static void VICinit (void) +{ + vic_2468_t *vic=&(((immap_t *)CONFIG_SYS_IMMAP)->ahb.vic); + /*initialize VIC */ + writel (0xffffffff, &(vic->vicinenclr)); /* Disable ALL interrupts */ + writel (0, &(vic->vicprotect)); /* Setup interrupt controller */ + writel (0, &(vic->vicaddr)); + writel (0, &(vic->vicintselect)); + writel (0, &(vic->vicvectaddr0)); /* Set the vector address */ + writel (0, &(vic->vicvectaddr1)); + writel (0, &(vic->vicvectaddr2)); + writel (0, &(vic->vicvectaddr3)); + writel (0, &(vic->vicvectaddr4)); + writel (0, &(vic->vicvectaddr5)); + writel (0, &(vic->vicvectaddr6)); + writel (0, &(vic->vicvectaddr7)); + writel (0, &(vic->vicvectaddr8)); + writel (0, &(vic->vicvectaddr9)); + writel (0, &(vic->vicvectaddr10)); + writel (0, &(vic->vicvectaddr11)); + writel (0, &(vic->vicvectaddr12)); + writel (0, &(vic->vicvectaddr13)); + writel (0, &(vic->vicvectaddr14)); + writel (0, &(vic->vicvectaddr15)); + writel (0, &(vic->vicvectaddr16)); + writel (0, &(vic->vicvectaddr17)); + writel (0, &(vic->vicvectaddr18)); + writel (0, &(vic->vicvectaddr19)); + writel (0, &(vic->vicvectaddr20)); + writel (0, &(vic->vicvectaddr21)); + writel (0, &(vic->vicvectaddr22)); + writel (0, &(vic->vicvectaddr23)); + writel (0, &(vic->vicvectaddr24)); + writel (0, &(vic->vicvectaddr25)); + writel (0, &(vic->vicvectaddr26)); + writel (0, &(vic->vicvectaddr27)); + writel (0, &(vic->vicvectaddr28)); + writel (0, &(vic->vicvectaddr29)); + writel (0, &(vic->vicvectaddr30)); + writel (0, &(vic->vicvectaddr31)); + writel (0xf, &(vic->vicvectprio0)); + writel (0xf, &(vic->vicvectprio1)); + writel (0xf, &(vic->vicvectprio2)); + writel (0xf, &(vic->vicvectprio3)); + writel (0xf, &(vic->vicvectprio4)); + writel (0xf, &(vic->vicvectprio5)); + writel (0xf, &(vic->vicvectprio6)); + writel (0xf, &(vic->vicvectprio7)); + writel (0xf, &(vic->vicvectprio8)); + writel (0xf, &(vic->vicvectprio9)); + writel (0xf, &(vic->vicvectprio10)); + writel (0xf, &(vic->vicvectprio11)); + writel (0xf, &(vic->vicvectprio12)); + writel (0xf, &(vic->vicvectprio13)); + writel (0xf, &(vic->vicvectprio14)); + writel (0xf, &(vic->vicvectprio15)); + writel (0xf, &(vic->vicvectprio16)); + writel (0xf, &(vic->vicvectprio17)); + writel (0xf, &(vic->vicvectprio18)); + writel (0xf, &(vic->vicvectprio19)); + writel (0xf, &(vic->vicvectprio20)); + writel (0xf, &(vic->vicvectprio21)); + writel (0xf, &(vic->vicvectprio22)); + writel (0xf, &(vic->vicvectprio23)); + writel (0xf, &(vic->vicvectprio24)); + writel (0xf, &(vic->vicvectprio25)); + writel (0xf, &(vic->vicvectprio26)); + writel (0xf, &(vic->vicvectprio27)); + writel (0xf, &(vic->vicvectprio28)); + writel (0xf, &(vic->vicvectprio29)); + writel (0xf, &(vic->vicvectprio30)); + writel (0xf, &(vic->vicvectprio31)); +} + +/***************************************************************************** +** Function name: ConfigurePLL +** +** Descriptions: Configure the PLL +** parameters: None +** Returned value: None +** +*****************************************************************************/ +void ConfigurePLL (void) +{ + sys_con_2468_t *sys_con=&(((immap_t *)CONFIG_SYS_IMMAP)->apb.sys_con); + + volatile unsigned long MValue; + volatile unsigned long NValue; + if (readl (&(sys_con->pllstat)) & (1 << 25)) { + + writel (1, &(sys_con->pllcon)); /* Enable PLL, disconnected */ + writel (0xaa, &(sys_con->pllfeed)); + writel (0x55, &(sys_con->pllfeed)); + } + + writel (0, &(sys_con->pllcon)); /* Disable PLL, disconnected */ + writel (0xaa, &(sys_con->pllfeed)); + writel (0x55, &(sys_con->pllfeed)); + BFS32 (&(sys_con->scs), 0x20); /* Enable main OSC */ + + /* Wait until main OSC is usable */ + while (!(readl (&(sys_con->scs)) & 0x40)); + + /* select main OSC, 12MHz, as the PLL clock source */ + writel (0x1, &(sys_con->clksrcsel)); + writel (PLL_MValue | (PLL_NValue << 16), &(sys_con->pllcfg)); + writel (0xaa, &(sys_con->pllfeed)); + writel (0x55, &(sys_con->pllfeed)); + writel (1, &(sys_con->pllcon)); /* Enable PLL, disconnected */ + writel (0xaa, &(sys_con->pllfeed)); + writel (0x55, &(sys_con->pllfeed)); + writel (CCLKDivValue, &(sys_con->cclkcfg)); /*Set clock divider*/ + +#if USE_USB + /* usbclk = 288 MHz/6 = 48 MHz */ + writel (USBCLKDivValue, &(sys_con->usbclkcfg)); +#endif + + /* Check lock bit status */ + while (((readl (&(sys_con->pllstat)) & (1 << 26)) == 0)); + + MValue = readl (&(sys_con->pllstat)) & 0x00007FFF; + NValue = (readl (&(sys_con->pllstat)) & 0x00FF0000) >> 16; + + while ((MValue != PLL_MValue) && (NValue != PLL_NValue)) ; + + writel (3, &(sys_con->pllcon)); /* enable and connect */ + writel (0xaa, &(sys_con->pllfeed)); + writel (0x55, &(sys_con->pllfeed)); + /* Check connect bit status */ + while (((readl (&(sys_con->pllstat)) & (1 << 25)) == 0)); +} + +/**************************************************************************** +** Function name: ConfigureEMC +** +** Descriptions: Configure EMC for external SDRAM, NAND and NOR FLASH +** parameters: None +** Returned value: None +** +****************************************************************************/ +void ConfigureEMC (void) +{ + ext_mem_2468_t *emc=&(((immap_t *)CONFIG_SYS_IMMAP)->ahb.ext_mem); + pin_connect_2468_t *pin_connect= + &(((immap_t *)CONFIG_SYS_IMMAP)->apb.pin_connect); + sys_con_2468_t *sys_con=&(((immap_t *)CONFIG_SYS_IMMAP)->apb.sys_con); + + volatile unsigned int i, dummy = dummy; + + writel (0x00000001, &(emc->control)); + BFS32 (&(sys_con->pconp), 0x00000800); /* Turn on EMC PCLK */ + + /* CS2 & CS3 not used PINSEL4 = 0x50000000; */ + writel (0x05050555, &(pin_connect->pinsel5)); + writel (0x55555555, &(pin_connect->pinsel6)); + writel (0x55555555, &(pin_connect->pinsel8)); + writel (0x50555555, &(pin_connect->pinsel9)); + + /*all registers... */ + writel (2, &(emc->dynrp)); /*>20ns = 2 clk */ + writel (3, &(emc->dynras)); /*>45ns = 3 clk */ + writel (7, &(emc->dynsrex)); /*>80-100ns = 6 clk */ + writel (2, &(emc->dynapr)); + writel (5, &(emc->dyndal)); /*2 clk */ + writel (1, &(emc->dynwr)); /*2 clk */ + writel (5, &(emc->dynrc)); /*>65ns = 4 clk */ + writel (5, &(emc->dynrfc)); /*>80-100ns = 6 clk */ + writel (7, &(emc->dynxsr)); /*>80-100ns = 6 clk */ + writel (1, &(emc->dynrrd)); /*>15ns = 1-2 clk */ + writel (2, &(emc->dynmrd)); /*2 clk */ + writel (1, &(emc->dynreadconfig)); /*or 1,2,3 */ + writel (0x00000303, &(emc->dynrascas0)); + writel (0x00000680, &(emc->dynconfig0)); + + /*wait 100mS */ + delayMs (100); + + /*Send command: NOP */ + writel (0x00000183, &(emc->dyncontrol)); + + /*wait 200mS */ + delayMs (200); + + /*Send command: PRECHARGE-ALL, shortest possible refresh period */ + writel (0x00000103, &(emc->dyncontrol)); + writel (0x00000002, &(emc->dynrefresh)); + + /*wait 128 ABH clock cycles */ + for (i = 0; i < 0x40; i++) + asm volatile (" nop"); + + /*Set correct refresh period */ + writel (28, &(emc->dynrefresh)); + + /*Send command: MODE */ + writel (0x00000083, &(emc->dyncontrol)); + + /*Set mode register in SDRAM */ + dummy = *((volatile unsigned int *)(SDRAM_BASE_ADDR | (0x33 << 12))); + + /*Send command: NORMAL */ + writel (0x00000000, &(emc->dyncontrol)); + + /*Enable buffer */ + BFS32 (&(emc->dynconfig0), 0x00080000); + + /*initial system delay */ + delayMs (1); + + writel (0x2, &(emc->statwaitwen0)); + writel (0x2, &(emc->statwaitoen0)); + writel (0x1f, &(emc->statwaitrd0)); + writel (0x1f, &(emc->statwaitpage0)); + writel (0x1f, &(emc->statwaitwr0)); + writel (0xf, &(emc->statwaitturn0)); + writel (0x00000081, &(emc->statconfig0)); + writel (0x2, &(emc->statwaitwen1)); + writel (0x2, &(emc->statwaitoen1)); + writel (0x8, &(emc->statwaitrd1)); + writel (0x1f, &(emc->statwaitpage1)); + writel (0x8, &(emc->statwaitwr1)); + writel (0xf, &(emc->statwaitturn1)); + writel (0x00000080, &(emc->statconfig1)); +} + +/***************************************************************************** + * + * Description: + * Initialize system functions and GPIO + * + ****************************************************************************/ +void lowlevel_init (void) +{ + sys_con_2468_t *sys_con=&(((immap_t *)CONFIG_SYS_IMMAP)->apb.sys_con); + + /************************************************************************** + * Remap vectors for RAM execution + **************************************************************************/ + + writel (1, &(sys_con->memmap)); + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + /* move vectors to beginning of SRAM */ + asm volatile + (" mov r2, #0x40000000 \n" + " mov r0, #0x00000000 \n" + " ldmneia r0!, {r3-r10} \n" + " stmneia r2!, {r3-r10} \n" + " ldmneia r0, {r3-r9} \n" + " stmneia r2, {r3-r9} \n":::"r0", + "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10"); +#else + /* move vectors to beginning of SRAM */ + asm volatile + (" mov r2, #0x40000000 \n" + " mov r0, #0xa1000000 \n" + " ldmneia r0!, {r3-r10} \n" + " stmneia r2!, {r3-r10} \n" + " ldmneia r0, {r3-r9} \n" + " stmneia r2, {r3-r9} \n":::"r0", + "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10"); +#endif + + /*initialize the exception vector mapping */ + writel (MEM_MAP, (&sys_con->memmap)); + +#if USE_USB + BFS32 (&(sys_con->pconp), 0x80000000); /* Turn On USB PCLK */ +#endif + + ConfigurePLL (); + + /* Set system timers for each component */ + +#if (Fpclk / (Fcclk / 4)) == 1 + writel (0x00000000, &(sys_con->pclksel0)); /* PCLK is 1/4 CCLK */ + writel (0x00000000, &(sys_con->pclksel1)); +#endif + +#if (Fpclk / (Fcclk / 4)) == 2 + writel (0xAAAAAAAA, &(sys_con->pclksel0)); /* PCLK is 1/2 CCLK */ + writel (0xAAAAAAAA, &(sys_con->pclksel1)); +#endif + +#if (Fpclk / (Fcclk / 4)) == 4 + writel (0x55555555, &(sys_con->pclksel0)); /*PCLK is the same as CCLK*/ + writel (0x55555555, &(sys_con->pclksel1)); +#endif + + /* Set memory accelerater module */ + writel (0, &(sys_con->mamcr)); + writel (4, &(sys_con->mamtim)); + + /*Init GPIO */ + GPIOinit (); + + /*initialize VIC */ + VICinit (); + + /*short delay */ + delayMs (10); + + /************************************************************************* + * Initialize external memory interface (EMC) + ************************************************************************/ + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + ConfigureEMC (); +#endif +} diff --git a/board/LPC2468/nand.c b/board/LPC2468/nand.c new file mode 100755 index 0000000..dbbfe36 --- /dev/null +++ b/board/LPC2468/nand.c @@ -0,0 +1,63 @@ +/* + * (C) Copyright 2009 Duran Audio B.V. <www.duran-audio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * 18-03-2009 Updated for U-boot 2009.3 + * by Remco Poelstra remco.poelstra+u-boot@duran-audio.com + */ + +#include <common.h> +#include <nand.h> +#include <asm/io.h> + +/* + * CLE at A20 + * ALE at A19 + */ +#define MASK_CLE (1l<<20) +#define MASK_ALE (1l<<19) + +static void cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + + ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; + + if (ctrl & NAND_CTRL_CHANGE) { + IO_ADDR_W &= ~(MASK_ALE | MASK_CLE); + if (ctrl & NAND_CLE) + IO_ADDR_W |= MASK_CLE; + if (ctrl & NAND_ALE) + IO_ADDR_W |= MASK_ALE; + this->IO_ADDR_W = (void *)IO_ADDR_W; + } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); +} + +int board_nand_init(struct nand_chip *nand) +{ + /* IO_ADDR_R and IO_ADDR_W set by nand-driver using CFG_NAND_BASE */ + nand->dev_ready = 0; + nand->cmd_ctrl = cmd_ctrl; + nand->ecc.mode = NAND_ECC_SOFT; + nand->chip_delay = 25; /* us */ + nand->options = NAND_SAMSUNG_LP_OPTIONS; + + return 0; +} diff --git a/board/LPC2468/u-boot.lds b/board/LPC2468/u-boot.lds new file mode 100755 index 0000000..64d946c --- /dev/null +++ b/board/LPC2468/u-boot.lds @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm720t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/include/asm-arm/arch-lpc24xx/immap.h b/include/asm-arm/arch-lpc24xx/immap.h index ab25dd5..0841230 100644 --- a/include/asm-arm/arch-lpc24xx/immap.h +++ b/include/asm-arm/arch-lpc24xx/immap.h @@ -94,7 +94,15 @@ typedef struct rtc_2468 { } rtc_2468_t;
typedef struct gpio_2468 { - u8 fixme[0x4000]; + u32 iopin0; + u32 ioset0; + u32 iodir0; + u32 ioclr0; + u32 iopin1; + u32 ioset1; + u32 iodir1; + u32 ioclr1; + u8 notused[0x3fe0]; } gpio_2468_t;
typedef struct pin_connect_2468 { @@ -120,7 +128,7 @@ typedef struct pin_connect_2468 { u32 pinmode7; u32 pinmode8; u32 pinmode9; - u8 fixme[0x3fa8]; + u8 notused[0x3fa8]; } pin_connect_2468_t;
typedef struct ssp1_2468 { @@ -179,21 +187,37 @@ typedef struct mmc_2468 { u8 fixme[0x4000]; } mmc_2468_t;
-typedef struct sys_con_2468 { - u8 notused1[0x40]; +typedef struct sys_con_2468 { // c000 + u32 mamcr; /*Memory Accelerator configuration register*/ + u32 mamtim; /*Memory Accelerator timing register*/ + u8 notused1[0x38]; u32 memmap; /*Memory mapping control register c040*/ - u8 notused2[0x80]; + u8 notused2[0x3c]; + u32 pllcon; /*PLL control register c080*/ + u32 pllcfg; /*PLL configuration register c084*/ + u32 pllstat; /*PLL status register c088*/ + u32 pllfeed; /*PLL feed register c08c*/ + u8 notused3[0x30]; + u32 pcon; /*Power control register c0c0*/ u32 pconp; /*Power control for peripherals register c0c4*/ - u8 notused3[0x7c]; + u8 notused4[0x3c]; + u32 cclkcfg; /*CPU clock configuration register c104*/ + u32 usbclkcfg; /*USB clock configuration register c108*/ + u32 clksrcsel; /*Clock source select register c10c*/ + u8 notused5[0x30]; u32 extint; /*External interrupt flag register c140*/ + u32 intwake; /*Interrupt wakeup register c144*/ u32 extmode; /*External interrupt mode resgister c148*/ u32 extpolar; /*External interrupt polarity register c14c*/ - u8 notused4[0x30]; + u8 notused6[0x30]; u32 rsid; /*Reset source identification register c180*/ u32 cspr; /*Code security protection register c184*/ - u8 notused5[0x18]; + u8 notused7[0x18]; u32 scs; /*System control and status register c1a0*/ - u8 notused6[0x3e5c]; + u32 irctrim; /*IRC trim register c1a4*/ + u32 pclksel0; /*Peripheral clock selection register 0 c1a8*/ + u32 pclksel1; /*Peripheral clock selection register 1 c1ac*/ + u8 notused8[0x3e50]; } sys_con_2468_t;
@@ -258,7 +282,72 @@ typedef struct gpdma__2468 { } gpdma_2468_t;
typedef struct ext_mem_2468 { - u8 fixme[0x4000]; + u32 control; /*Controls operation of the memory controller*/ + u32 status; /*Provides EMC status*/ + u32 config; /*Configures operation of the memorycontroller*/ + u8 notused1[0x14]; + u32 dyncontrol; /*Controls dynamic memory operation*/ + u32 dynrefresh; /*Configures dynamic refresh operation*/ + u32 dynreadconfig; /*Configures the dynamic memory read strategy*/ + u32 notused2; + u32 dynrp; /*Selects the precharge command period*/ + u32 dynras; /*Selects the active to precharge command period*/ + u32 dynsrex; /*Selects the self-refresh time*/ + u32 dynapr; /*Selects the last-data-out to active command time*/ + u32 dyndal; /*Selects the data-in to active command time*/ + u32 dynwr; /*Selects the write recovery time*/ + u32 dynrc; /*Selects the active to active command period*/ + u32 dynrfc; /*Selects the auto-refresh period*/ + u32 dynxsr; /*Selects the exit self-refresh to active command time*/ + u32 dynrrd; /*Selects the active ank A to active bank B latency*/ + u32 dynmrd; /*Selects the load mode register to active command time*/ + u8 notused3[0xa4]; + u32 dynconfig0; /*Configuration information for dyn memory CS 0*/ + u32 dynrascas0; /*Selects the RAs and CAS latency fos CS 0*/ + u8 notused4[0x18]; + u32 dynconfig1; /*Configuration information for dyn memory CS 1*/ + u32 dynrascas1; /*Selects the RAs and CAS latency fos CS 1*/ + u8 notused5[0x18]; + u32 dynconfig2; /*Configuration information for dyn memory CS 2*/ + u32 dynrascas2; /*Selects the RAs and CAS latency fos CS 2*/ + u8 notused6[0x18]; + u32 dynconfig3; /*Configuration information for dyn memory CS 3*/ + u32 dynrascas3; /*Selects the RAs and CAS latency fos CS 3*/ + u8 notused7[0x98]; + u32 statconfig0; /*Memory configuration for static CS 0*/ + u32 statwaitwen0; /*Selects the delay from CS 0 to WE*/ + u32 statwaitoen0; /*Selects the delay from CS 0 OE*/ + u32 statwaitrd0; /*Selects the delay from CS 0 to a read access*/ + u32 statwaitpage0; /*Selects the delay for async page mode for CS 0*/ + u32 statwaitwr0; /*Selects the delay from CS 0 to a write access*/ + u32 statwaitturn0; /*Selects the # of bus turnaround cycles for CS 0*/ + u8 notused8[0x4]; + u32 statconfig1; /*Memory configuration for static CS 1*/ + u32 statwaitwen1; /*Selects the delay from CS 1 to WE*/ + u32 statwaitoen1; /*Selects the delay from CS 1 OE*/ + u32 statwaitrd1; /*Selects the delay from CS 1 to a read access*/ + u32 statwaitpage1; /*Selects the delay for async page mode for CS 1*/ + u32 statwaitwr1; /*Selects the delay from CS 1 to a write access*/ + u32 statwaitturn1; /*Selects the # of bus turnaround cycles for CS 1*/ + u8 notused9[0x4]; + u32 statconfig2; /*Memory configuration for static CS 2*/ + u32 statwaitwen2; /*Selects the delay from CS 2 to WE*/ + u32 statwaitoen2; /*Selects the delay from CS 2 OE*/ + u32 statwaitrd2; /*Selects the delay from CS 2 to a read access*/ + u32 statwaitpage2; /*Selects the delay for async page mode for CS 2*/ + u32 statwaitwr2; /*Selects the delay from CS 2 to a write access*/ + u32 statwaitturn2; /*Selects the # of bus turnaround cycles for CS 2*/ + u8 notused10[0x4]; + u32 statconfig3; /*Memory configuration for static CS 3*/ + u32 satwaitwen3; /*Selects the delay from CS 3 to WE*/ + u32 statwaitoen3; /*Selects the delay from CS 3 OE*/ + u32 statwaitrd3; /*Selects the delay from CS 3 to a read access*/ + u32 statwaitpage3; /*Selects the delay for async page mode for CS 3*/ + u32 statwaitwr3; /*Selects the delay from CS 3 to a write access*/ + u32 statwaitturn3; /*Selects the # of bus turnaround cycles for CS 3*/ + u8 notused11[0x604]; + u32 extwait; + u8 notused12[0x377c]; } ext_mem_2468_t;
typedef struct usb_2468 { @@ -350,6 +439,39 @@ typedef struct vic_2468 { u32 vicaddr; /*Vector address register for active interrupt*/ } vic_2468_t;
+typedef struct fastio_2468 { + u32 fio0dir; /*Fast IO 0 port direction register*/ + u8 notused1[0xc]; + u32 fio0mask; /*Fast IO 0 mask register*/ + u32 fio0pin; /*Fast IO 0 pin value register*/ + u32 fio0set; /*Fast IO 0 output set register*/ + u32 fio0clr; /*Fast IO 0 output clear register*/ + u32 fio1dir; /*Fast IO 1 port direction register*/ + u8 notused2[0xc]; + u32 fio1mask; /*Fast IO 1 mask register*/ + u32 fio1pin; /*Fast IO 1 pin value register*/ + u32 fio1set; /*Fast IO 1 output set register*/ + u32 fio1clr; /*Fast IO 1 output clear register*/ + u32 fio2dir; /*Fast IO 2 port direction register*/ + u8 notused3[0xc]; + u32 fio2mask; /*Fast IO 2 mask register*/ + u32 fio2pin; /*Fast IO 2 pin value register*/ + u32 fio2set; /*Fast IO 2 output set register*/ + u32 fio2clr; /*Fast IO 2 output clear register*/ + u32 fio3dir; /*Fast IO 3 port direction register*/ + u8 notused4[0xc]; + u32 fio3mask; /*Fast IO 3 mask register*/ + u32 fio3pin; /*Fast IO 3 pin value register*/ + u32 fio3set; /*Fast IO 3 output set register*/ + u32 fio3clr; /*Fast IO 3 output clear register*/ + u32 fio4dir; /*Fast IO 4 port direction register*/ + u8 notused5[0xc]; + u32 fio4mask; /*Fast IO 4 mask register*/ + u32 fio4pin; /*Fast IO 4 pin value register*/ + u32 fio4set; /*Fast IO 4 output set register*/ + u32 fio4clr; /*Fast IO 4 output clear register*/ +} fastio_2468_t; + typedef struct apb_2468 { /*Peripheral bus memory layout*/ watchdog2468_t watchdog; timer_2468_t timer0; diff --git a/include/configs/LPC2468.h b/include/configs/LPC2468.h new file mode 100644 index 0000000..67680ca --- /dev/null +++ b/include/configs/LPC2468.h @@ -0,0 +1,220 @@ +/* + * (C) Copyright 2008 + * Embedded Artists AB, Sweden <www.EmbeddedArtists.com> + * + * Configuation settings for the LPC2468 OEM Board, 16 bit databus. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_LPC2468 + +/* + * If we are developing, we might want to start armboot from ram + * so we MUST NOT initialize critical regs like mem-timing ... + */ +#if 0 +#define CONFIG_INIT_CRITICAL /* undef for developing */ +#endif + +#undef CONFIG_SKIP_LOWLEVEL_INIT + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM7 1 /* This is a ARM7 CPU */ +#define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */ +#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ + +/* Clock settings */ + +/* Crystal frequency */ +#define CONFIG_FOSC 12000000 + +/* + * Fcco = 2*M*Fosc / N + * + * Fcco = 288000000 -> M = 12, N = 1 + * + * PLLCFG (MSEL) = (M-1) + * PLLCFG (NSEL) = (N-1) + */ +#define CONFIG_PLL_MVALUE 12 +#define CONFIG_PLL_NVALUE 1 + +/* + * Fcclk = Fcco / CLKDIV + * CLKDIV must be an even number + * + * CCLKCFG = CLKDIV-1 (odd number must be written to register) + * CLKDIV = 4 -> Fcclk = 72 MHz (if Fcco = 288 MHz) + * CLKDIV = 6 -> Fcclk = 48 MHz (if Fcco = 288 MHz) + */ +#define CONFIG_PLL_CLKDIV 4 + +/* + * The USB clock must be 48 MHz + * Fusb = Fcco / USBCLKDIV + * USBCLKCFG = (USBCLKDIV-1) + */ +#define CONFIG_PLL_USBCLKDIV 6 + +/* + * Periperhal clock divider, i.e. Fpclk = Fcclk / divider + * Valid values are 1, 2, or 4 + */ +#define CONFIG_FPCLK_DIV 1 + +#define CONFIG_USE_IRQ /* use irq for mci interface */ + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Hardware drivers + */ + +/* + * select serial console configuration + */ +#define CONFIG_LPC2468_SERIAL +#define CONFIG_SERIAL 1 /* we use Serial line 1 */ + +#define CONFIG_LPC2468_ETH + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) + +#include <config_cmd_default.h> +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_BOOTD +#define CONFIG_CMD_NAND + +#define CONFIG_BOOTARGS\ + "root=/dev/ram initrd=0xa1800000,4000k console=ttyS0,115200N8" + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /*undef to save memory*/ +#define CONFIG_SYS_CBSIZE 256 /*Console I/O Buffer Size*/ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /*max number of command args*/ +#define CFG_BARGSIZE CFG_CBSIZE /*Boot Argument Buffer Size*/ + +#define CONFIG_SYS_MEMTEST_START 0xA0000000 /* memtest works on */ +/* 31.5 MB in DRAM, U-boot is relocated after this location*/ +#define CONFIG_SYS_MEMTEST_END 0xA1F80000 +#define CONFIG_SYS_ALT_MEMTEST + +#define CONFIG_SYS_IMMAP 0xE0000000 +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ +/* default load address for kernel img is here*/ +#define CONFIG_SYS_LOAD_ADDR 0xA0008000 + +#define CLK_FCCO ((2*CONFIG_PLL_MVALUE*CONFIG_FOSC) / CONFIG_PLL_NVALUE) + +#define CFG_SYS_CLK_FREQ (CLK_FCCO / CONFIG_PLL_CLKDIV)/* Hz */ +#define ODCONFIG_SYS_HZ 200000 /* decrementer freq in Hz */ + +/* valid baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (8*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0xA0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB SDRAM */ + +#define PHYS_FLASH_1 0x80000000 /* Flash Bank #1 */ +#define PHYS_FLASH_SIZE 0x00400000 /* 4 MB */ + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks*/ +#define CONFIG_SYS_MAX_FLASH_SECT1024 /* max number of sectors on one chip*/ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ + +/* + * Linux tags + */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +/* + * NAND Flash + */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_NAND_BASE 0x81000000 + + +/* + * Default environment settings + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "ipaddr=192.168.3.2" \ + "netmask=255.255.255.0" \ + "serverip=192.168.3.1" \ + "ethaddr=00:1a:f1:00:00:00" + +/* + * Control where environment is stored + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR (0x0 + 0x7C000) /*Addr of Environment Sector*/ +#define CONFIG_ENV_SIZE 0x1000 /*Total Size of Environment Sector(4k)*/ + +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT "LPC2468 # " + +#endif /* __CONFIG_H */
Dear Jean-Christophe,
In message 49F70A9D.5000704@duran-audio.com Remco Poelstra wrote:
Added example board for LPC2468 processor
Signed-off-by: Remco Poelstra <remco.poelstra+u-boot@duran-audio.com
From ab9ef1e9c2bd8f04612429461baa5c24dbc52266 Mon Sep 17 00:00:00 2001 From: Remco Poelstra remco.poelstra@duran-audio.com Date: Tue, 28 Apr 2009 15:04:33 +0200 Subject: [PATCH] Added example board for LPC2468 processor
board/LPC2468/LPC2468.c | 65 +++++ board/LPC2468/Makefile | 55 +++++ board/LPC2468/config.mk | 29 +++ board/LPC2468/flash.c | 255 +++++++++++++++++++ board/LPC2468/lowlevel_init.c | 445 ++++++++++++++++++++++++++++++++++ board/LPC2468/nand.c | 63 +++++ board/LPC2468/u-boot.lds | 55 +++++ include/asm-arm/arch-lpc24xx/immap.h | 142 ++++++++++- include/configs/LPC2468.h | 220 +++++++++++++++++ 9 files changed, 1319 insertions(+), 10 deletions(-) create mode 100644 board/LPC2468/LPC2468.c create mode 100755 board/LPC2468/Makefile create mode 100755 board/LPC2468/config.mk create mode 100644 board/LPC2468/flash.c create mode 100644 board/LPC2468/lowlevel_init.c create mode 100755 board/LPC2468/nand.c create mode 100755 board/LPC2468/u-boot.lds create mode 100644 include/configs/LPC2468.h
AFAICT this has neither been applied nor rejected yet. Please check.
Best regards,
Wolfgang Denk
On 15:54 Tue 28 Apr , Remco Poelstra wrote:
Added example board for LPC2468 processor
Signed-off-by: Remco Poelstra <remco.poelstra+u-boot@duran-audio.com
please split your patch
From ab9ef1e9c2bd8f04612429461baa5c24dbc52266 Mon Sep 17 00:00:00 2001 From: Remco Poelstra remco.poelstra@duran-audio.com Date: Tue, 28 Apr 2009 15:04:33 +0200 Subject: [PATCH] Added example board for LPC2468 processor
board/LPC2468/LPC2468.c | 65 +++++ board/LPC2468/Makefile | 55 +++++ board/LPC2468/config.mk | 29 +++ board/LPC2468/flash.c | 255 +++++++++++++++++++ board/LPC2468/lowlevel_init.c | 445 ++++++++++++++++++++++++++++++++++ board/LPC2468/nand.c | 63 +++++
please add it in an other patch and please store it in drivers/mtd/nand/
board/LPC2468/u-boot.lds | 55 +++++ include/asm-arm/arch-lpc24xx/immap.h | 142 ++++++++++- include/configs/LPC2468.h | 220 +++++++++++++++++ 9 files changed, 1319 insertions(+), 10 deletions(-) create mode 100644 board/LPC2468/LPC2468.c create mode 100755 board/LPC2468/Makefile create mode 100755 board/LPC2468/config.mk create mode 100644 board/LPC2468/flash.c create mode 100644 board/LPC2468/lowlevel_init.c create mode 100755 board/LPC2468/nand.c create mode 100755 board/LPC2468/u-boot.lds create mode 100644 include/configs/LPC2468.h
diff --git a/board/LPC2468/LPC2468.c b/board/LPC2468/LPC2468.c new file mode 100644 index 0000000..498885f --- /dev/null +++ b/board/LPC2468/LPC2468.c @@ -0,0 +1,65 @@ +/*
- (C) Copyright 2002
- Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- Marius Groeger mgroeger@sysgo.de
- (C) Copyright 2005 Rowel Atienza rowel@diwalabs.com
- Armadillo board HT1070
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#include <common.h> +#include <clps7111.h>
+/* ------------------------------------------------------------------------- */
+/*
- Miscelaneous platform dependent initialisations
- */
+int board_init (void) +{
- DECLARE_GLOBAL_DATA_PTR;
- /* arch number MACH_TYPE_ARMADILLO - not official */
- gd->bd->bi_arch_number = 1339;
please use proper CONFIG
- /* location of boot parameters */
- gd->bd->bi_boot_params = 0xA0000100;
please use this style CONFIG_RAM_BASE + 0x100
- return 0;
+}
+int print_cpuinfo (void) +{
- printf ("CPU: LPC2468 (ARM7tdmi-s from NXP)\n"
" running at 57.6 MHz (12 MHz crystal)\n");
is it possible to detect it?
- return 0;
+}
+int dram_init (void) +{
- DECLARE_GLOBAL_DATA_PTR;
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- return (0);
+} diff --git a/board/LPC2468/Makefile b/board/LPC2468/Makefile new file mode 100755 index 0000000..19a2cd7 --- /dev/null
<snip>
+TEXT_BASE = 0xA1f80000 diff --git a/board/LPC2468/flash.c b/board/LPC2468/flash.c new file mode 100644 index 0000000..9d61b43 --- /dev/null +++ b/board/LPC2468/flash.c
Is your flash cfi compatible? Stefan what do you think?
@@ -0,0 +1,255 @@ +/*
- (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com>
- (C) Copyright 2009 Duran Audio B.V. <www.duran-audio.com>
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- 18-03-2009 Updated for U-boot 2009.3
- by Remco Poelstra remco.poelstra+u-boot@duran-audio.com
- */
diff --git a/board/LPC2468/lowlevel_init.c b/board/LPC2468/lowlevel_init.c new file mode 100644 index 0000000..f7d7698 --- /dev/null +++ b/board/LPC2468/lowlevel_init.c @@ -0,0 +1,445 @@ +/*
- (C) Copyright 2006-2007 Embedded Artists AB <www.embeddedartists.com>
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+#include <config.h> +#include <version.h> +#include <exports.h> +#include <asm/arch/immap.h> +#include <asm/io.h>
I think a lot's of the inits done here are soc specific and not board specific
+/******************************************************************************
- Defines, macros, and typedefs
- *****************************************************************************/
+#define USE_USB 1
+#define PLL_MValue (CONFIG_PLL_MVALUE-1) +#define PLL_NValue (CONFIG_PLL_NVALUE-1) +#define CCLKDivValue (CONFIG_PLL_CLKDIV-1) +#define USBCLKDivValue (CONFIG_PLL_USBCLKDIV-1)
+#define Fcco ((2*CONFIG_PLL_MVALUE*CONFIG_FOSC) / CONFIG_PLL_NVALUE) +#define Fcclk (Fcco / CONFIG_PLL_CLKDIV) +#define Fpclk (Fcclk / CONFIG_FPCLK_DIV) +#define MAM_SETTING 1 /* 0=disabled,
1=partly enabled (enabled for code prefetch,but not for data),2=fully enabled */+#define MEM_MAP 2 /*When executing from RAM, MAM_MAP should always be 2*/ +#define SDRAM_BASE_ADDR 0xA0000000 +#define FASTIO_BASE_ADDR 0x3FFF8000
please move thise configs to beter place
+/* Helper macros */ +#define BFS32(reg,value) writel( (readl(reg)|=(value)) ,reg) +#define BFC32(reg,value) writel( (readl(reg)&=(~value)) ,reg)
+/*****************************************************************************
- Description:
- Delay execution by a specified number of milliseconds by using
- timer #1. A polled implementation.
- Params:
- [in] delayInMs - the number of milliseconds to delay.
- ****************************************************************************/
+void delayMs (unsigned short delayInMs) +{
- timer_2468_t *timer=&(((immap_t *)CONFIG_SYS_IMMAP)->apb.timer1);
- /*
* setup timer #1 for delay*/- writel (0x02, &(timer->tcr)); /*stop and reset timer */
- writel (0x00, &(timer->pr)); /*set prescaler to zero */
- writel (delayInMs * (Fpclk / 1000), &(timer->mr0));
- writel (0xff, &(timer->ir)); /*reset all interrrupt flags */
- writel (0x04, &(timer->mcr)); /*stop timer on match */
- writel (0x01, &(timer->tcr)); /*start timer */
- /*wait until delay time has elapsed */
- while (readl (&(timer->tcr)) & 0x01) ;
+}
why do you need this and do not use the general timer implementation?
+/****************************************************************************** +** Function name: GPIOinit +** +** Descriptions: Sets all GPIO ports to a known state +** parameters: None +** Returned value: None
could you describe what you do here? maybe use gpio api to be more generic and understandable
+** +******************************************************************************/ +static void GPIOinit (void) +{
- pin_connect_2468_t *pin_connect=
&(((immap_t *)CONFIG_SYS_IMMAP)->apb.pin_connect);- gpio_2468_t *gpio=
&(((immap_t *)CONFIG_SYS_IMMAP)->apb.gpio);- fastio_2468_t *fio=(fastio_2468_t *)FASTIO_BASE_ADDR;
- writel (0, &(pin_connect->pinsel0));
- writel (0, &(pin_connect->pinsel1));
- writel (0, &(pin_connect->pinsel2));
- writel (0, &(pin_connect->pinsel3));
- writel (0, &(pin_connect->pinsel4));
- writel (0, &(pin_connect->pinsel5));
- writel (0, &(pin_connect->pinsel6));
- writel (0, &(pin_connect->pinsel7));
- writel (0, &(pin_connect->pinsel8));
- writel (0, &(pin_connect->pinsel9));
- writel (0, &(pin_connect->pinsel10));
- writel (0, &(gpio->iodir0));
- writel (0, &(gpio->iodir1));
- writel (0xffffffff, &(gpio->ioset0));
- writel (0xffffffff, &(gpio->ioset1));
- writel (0, &(fio->fio0dir));
- writel (0, &(fio->fio1dir));
- writel (0, &(fio->fio2dir));
- writel (0, &(fio->fio3dir));
- writel (0, &(fio->fio4dir));
- writel (0xffffffff, &(fio->fio0set));
- writel (0xffffffff, &(fio->fio1set));
- writel (0xffffffff, &(fio->fio2set));
- writel (0, &(fio->fio3set));
- writel (0xffffffff, &(fio->fio4set));
+}
+/****************************************************************************** +** Function name: VICinit +** +** Descriptions: Initialize the VIC to a known state +** parameters: None +** Returned value: None
why do you need this? do you use the interrupt in update?
+** +******************************************************************************/ +static void VICinit (void)
please uppercase for macro and lowercase for the rest
+{
- vic_2468_t *vic=&(((immap_t *)CONFIG_SYS_IMMAP)->ahb.vic);
- /*initialize VIC */
- writel (0xffffffff, &(vic->vicinenclr)); /* Disable ALL interrupts */
- writel (0, &(vic->vicprotect)); /* Setup interrupt controller */
- writel (0, &(vic->vicaddr));
- writel (0, &(vic->vicintselect));
- writel (0, &(vic->vicvectaddr0)); /* Set the vector address */
try to use array to simplify it
- writel (0, &(vic->vicvectaddr1));
- writel (0, &(vic->vicvectaddr2));
- writel (0, &(vic->vicvectaddr3));
- writel (0, &(vic->vicvectaddr4));
<snip>
+void ConfigurePLL (void) +{
- sys_con_2468_t *sys_con=&(((immap_t *)CONFIG_SYS_IMMAP)->apb.sys_con);
- volatile unsigned long MValue;
- volatile unsigned long NValue;
please add an empty line
- if (readl (&(sys_con->pllstat)) & (1 << 25)) {
writel (1, &(sys_con->pllcon)); /* Enable PLL, disconnected */writel (0xaa, &(sys_con->pllfeed));writel (0x55, &(sys_con->pllfeed));- }
- writel (0, &(sys_con->pllcon)); /* Disable PLL, disconnected */
- writel (0xaa, &(sys_con->pllfeed));
- writel (0x55, &(sys_con->pllfeed));
- BFS32 (&(sys_con->scs), 0x20); /* Enable main OSC */
- /* Wait until main OSC is usable */
- while (!(readl (&(sys_con->scs)) & 0x40));
- /* select main OSC, 12MHz, as the PLL clock source */
- writel (0x1, &(sys_con->clksrcsel));
- writel (PLL_MValue | (PLL_NValue << 16), &(sys_con->pllcfg));
- writel (0xaa, &(sys_con->pllfeed));
- writel (0x55, &(sys_con->pllfeed));
- writel (1, &(sys_con->pllcon)); /* Enable PLL, disconnected */
- writel (0xaa, &(sys_con->pllfeed));
- writel (0x55, &(sys_con->pllfeed));
- writel (CCLKDivValue, &(sys_con->cclkcfg)); /*Set clock divider*/
+#if USE_USB
please use a CONFIG_CMD_USB or other related CONFIG
- /* usbclk = 288 MHz/6 = 48 MHz */
- writel (USBCLKDivValue, &(sys_con->usbclkcfg));
+#endif
- /* Check lock bit status */
- while (((readl (&(sys_con->pllstat)) & (1 << 26)) == 0));
- MValue = readl (&(sys_con->pllstat)) & 0x00007FFF;
- NValue = (readl (&(sys_con->pllstat)) & 0x00FF0000) >> 16;
- while ((MValue != PLL_MValue) && (NValue != PLL_NValue)) ;
- writel (3, &(sys_con->pllcon)); /* enable and connect */
- writel (0xaa, &(sys_con->pllfeed));
- writel (0x55, &(sys_con->pllfeed));
- /* Check connect bit status */
- while (((readl (&(sys_con->pllstat)) & (1 << 25)) == 0));
+}
+/**************************************************************************** +** Function name: ConfigureEMC +** +** Descriptions: Configure EMC for external SDRAM, NAND and NOR FLASH +** parameters: None +** Returned value: None +** +****************************************************************************/ +void ConfigureEMC (void) +{
- ext_mem_2468_t *emc=&(((immap_t *)CONFIG_SYS_IMMAP)->ahb.ext_mem);
- pin_connect_2468_t *pin_connect=
&(((immap_t *)CONFIG_SYS_IMMAP)->apb.pin_connect);- sys_con_2468_t *sys_con=&(((immap_t *)CONFIG_SYS_IMMAP)->apb.sys_con);
- volatile unsigned int i, dummy = dummy;
- writel (0x00000001, &(emc->control));
- BFS32 (&(sys_con->pconp), 0x00000800); /* Turn on EMC PCLK */
- /* CS2 & CS3 not used PINSEL4 = 0x50000000; */
- writel (0x05050555, &(pin_connect->pinsel5));
- writel (0x55555555, &(pin_connect->pinsel6));
- writel (0x55555555, &(pin_connect->pinsel8));
- writel (0x50555555, &(pin_connect->pinsel9));
- /*all registers... */
- writel (2, &(emc->dynrp)); /*>20ns = 2 clk */
- writel (3, &(emc->dynras)); /*>45ns = 3 clk */
- writel (7, &(emc->dynsrex)); /*>80-100ns = 6 clk */
- writel (2, &(emc->dynapr));
- writel (5, &(emc->dyndal)); /*2 clk */
- writel (1, &(emc->dynwr)); /*2 clk */
- writel (5, &(emc->dynrc)); /*>65ns = 4 clk */
- writel (5, &(emc->dynrfc)); /*>80-100ns = 6 clk */
- writel (7, &(emc->dynxsr)); /*>80-100ns = 6 clk */
- writel (1, &(emc->dynrrd)); /*>15ns = 1-2 clk */
- writel (2, &(emc->dynmrd)); /*2 clk */
- writel (1, &(emc->dynreadconfig)); /*or 1,2,3 */
- writel (0x00000303, &(emc->dynrascas0));
- writel (0x00000680, &(emc->dynconfig0));
- /*wait 100mS */
- delayMs (100);
- /*Send command: NOP */
- writel (0x00000183, &(emc->dyncontrol));
- /*wait 200mS */
- delayMs (200);
- /*Send command: PRECHARGE-ALL, shortest possible refresh period */
- writel (0x00000103, &(emc->dyncontrol));
- writel (0x00000002, &(emc->dynrefresh));
- /*wait 128 ABH clock cycles */
- for (i = 0; i < 0x40; i++)
asm volatile (" nop");- /*Set correct refresh period */
- writel (28, &(emc->dynrefresh));
- /*Send command: MODE */
- writel (0x00000083, &(emc->dyncontrol));
- /*Set mode register in SDRAM */
- dummy = *((volatile unsigned int *)(SDRAM_BASE_ADDR | (0x33 << 12)));
- /*Send command: NORMAL */
- writel (0x00000000, &(emc->dyncontrol));
- /*Enable buffer */
- BFS32 (&(emc->dynconfig0), 0x00080000);
- /*initial system delay */
- delayMs (1);
- writel (0x2, &(emc->statwaitwen0));
- writel (0x2, &(emc->statwaitoen0));
- writel (0x1f, &(emc->statwaitrd0));
- writel (0x1f, &(emc->statwaitpage0));
- writel (0x1f, &(emc->statwaitwr0));
- writel (0xf, &(emc->statwaitturn0));
- writel (0x00000081, &(emc->statconfig0));
- writel (0x2, &(emc->statwaitwen1));
- writel (0x2, &(emc->statwaitoen1));
- writel (0x8, &(emc->statwaitrd1));
- writel (0x1f, &(emc->statwaitpage1));
- writel (0x8, &(emc->statwaitwr1));
- writel (0xf, &(emc->statwaitturn1));
- writel (0x00000080, &(emc->statconfig1));
+}
+/*****************************************************************************
- Description:
- Initialize system functions and GPIO
- ****************************************************************************/
--- /dev/null +++ b/board/LPC2468/u-boot.lds
no need please remove
@@ -0,0 +1,55 @@ +/*
- (C) Copyright 2000
- Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
<snip>
+#ifndef __CONFIG_H +#define __CONFIG_H
+#define CONFIG_LPC2468
+/*
- If we are developing, we might want to start armboot from ram
- so we MUST NOT initialize critical regs like mem-timing ...
- */
+#if 0 +#define CONFIG_INIT_CRITICAL /* undef for developing */ +#endif
please remove
+#undef CONFIG_SKIP_LOWLEVEL_INIT
+/*
- High Level Configuration Options
- (easy to change)
- */
+#define CONFIG_ARM7 1 /* This is a ARM7 CPU */ +#define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */ +#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */
+/* Clock settings */
+/* Crystal frequency */ +#define CONFIG_FOSC 12000000
+/*
- Fcco = 2*M*Fosc / N
- Fcco = 288000000 -> M = 12, N = 1
- PLLCFG (MSEL) = (M-1)
- PLLCFG (NSEL) = (N-1)
- */
+#define CONFIG_PLL_MVALUE 12 +#define CONFIG_PLL_NVALUE 1
+/*
- Fcclk = Fcco / CLKDIV
- CLKDIV must be an even number
- CCLKCFG = CLKDIV-1 (odd number must be written to register)
- CLKDIV = 4 -> Fcclk = 72 MHz (if Fcco = 288 MHz)
- CLKDIV = 6 -> Fcclk = 48 MHz (if Fcco = 288 MHz)
- */
+#define CONFIG_PLL_CLKDIV 4
+/*
- The USB clock must be 48 MHz
- Fusb = Fcco / USBCLKDIV
- USBCLKCFG = (USBCLKDIV-1)
- */
+#define CONFIG_PLL_USBCLKDIV 6
+/*
- Periperhal clock divider, i.e. Fpclk = Fcclk / divider
- Valid values are 1, 2, or 4
- */
+#define CONFIG_FPCLK_DIV 1
+#define CONFIG_USE_IRQ /* use irq for mci interface */
+/*
- Size of malloc() pool
- */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128
+/*
- Hardware drivers
- */
+/*
- select serial console configuration
- */
+#define CONFIG_LPC2468_SERIAL +#define CONFIG_SERIAL 1 /* we use Serial line 1 */
+#define CONFIG_LPC2468_ETH
+/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+#include <config_cmd_default.h> +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_BOOTD +#define CONFIG_CMD_NAND
+#define CONFIG_BOOTARGS\
- "root=/dev/ram initrd=0xa1800000,4000k console=ttyS0,115200N8"
+/*
- Miscellaneous configurable options
- */
+#define CFG_LONGHELP /*undef to save memory*/
it's not anymore CFG_ but CONFIG_SYS_ please rebase your patch against the Mainline
Best Regards, J.
participants (5)
-
Ben Warren -
Jean-Christophe PLAGNIOL-VILLARD -
Remco Poelstra -
Stefan Roese -
Wolfgang Denk