[U-Boot] [PATCH 0/2] ARM: AMx3xx: Enable DDR IO dynamic power down
This patch series enables the DDR IO dynamic power down on boards using DDR3.
This is applied on top of u-boot-ti: git://git.denx.de/u-boot-ti.git
Lokesh Vutla (1): ARM: AM43xx: Enable DDR dynamic IO power down for DDR3
Satyanarayana, Sandhya (1): ARM: AM335x: Enable DDR dynamic IO power down
arch/arm/include/asm/arch-am33xx/ddr_defs.h | 8 ++++---- board/ti/am43xx/board.c | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-)
This patch enables dynamically powering down the IO receiver when not performing a read on DDR3 board. This optimizes both active and standby power consumption. This is derived from a patch that is done on AM335x[1]
[1] http://arago-project.org/git/projects/?p=u-boot-am33x.git;a=commit;h=6a9ee4b...
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- board/ti/am43xx/board.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index ed87cd9..4e6846a 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -188,7 +188,7 @@ const struct ctrl_ioregs ioregs_ddr3 = { .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE, .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE, .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE, - .emif_sdram_config_ext = 0x0043, + .emif_sdram_config_ext = 0x0143, };
const struct emif_regs ddr3_emif_regs_400Mhz = {
On Thu, Dec 19, 2013 at 10:00:28AM +0530, Lokesh Vutla wrote:
This patch enables dynamically powering down the IO receiver when not performing a read on DDR3 board. This optimizes both active and standby power consumption. This is derived from a patch that is done on AM335x[1]
[1] http://arago-project.org/git/projects/?p=u-boot-am33x.git;a=commit;h=6a9ee4b...
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
Applied to u-boot-ti/master, thanks!
From: "Satyanarayana, Sandhya" sandhya.satyanarayana@ti.com
This patch enables dynamically powering down the IO receiver when not performing a read on boards using DDR3. This optimizes both active and standby power consumption. This bit is not set on EVM SK and EVM 1.5 and later boards. Setting the same.
This has been tested on PG2.0 EVM1.5, EVM1.2, EVM-SK, BBB.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Signed-off-by: Satyanarayana, Sandhya sandhya.satyanarayana@ti.com --- arch/arm/include/asm/arch-am33xx/ddr_defs.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index c1777df..fbe599d 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -43,7 +43,7 @@ #define MT47H128M16RT25E_IOCTRL_VALUE 0x18B
/* Micron MT41J128M16JT-125 */ -#define MT41J128MJT125_EMIF_READ_LATENCY 0x06 +#define MT41J128MJT125_EMIF_READ_LATENCY 0x100006 #define MT41J128MJT125_EMIF_TIM1 0x0888A39B #define MT41J128MJT125_EMIF_TIM2 0x26337FDA #define MT41J128MJT125_EMIF_TIM3 0x501F830F @@ -65,7 +65,7 @@ #define MT41J256MJT125_EMIF_SDCFG 0x61C04B32
/* Micron MT41J256M8HX-15E */ -#define MT41J256M8HX15E_EMIF_READ_LATENCY 0x06 +#define MT41J256M8HX15E_EMIF_READ_LATENCY 0x100006 #define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B #define MT41J256M8HX15E_EMIF_TIM2 0x26337FDA #define MT41J256M8HX15E_EMIF_TIM3 0x501F830F @@ -97,7 +97,7 @@ #define MT41K256M16HA125E_IOCTRL_VALUE 0x18B
/* Micron MT41J512M8RH-125 on EVM v1.5 */ -#define MT41J512M8RH125_EMIF_READ_LATENCY 0x06 +#define MT41J512M8RH125_EMIF_READ_LATENCY 0x100006 #define MT41J512M8RH125_EMIF_TIM1 0x0888A39B #define MT41J512M8RH125_EMIF_TIM2 0x26517FDA #define MT41J512M8RH125_EMIF_TIM3 0x501F84EF @@ -113,7 +113,7 @@ #define MT41J512M8RH125_IOCTRL_VALUE 0x18B
/* Samsung K4B2G1646E-BIH9 */ -#define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x07 +#define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x100007 #define K4B2G1646EBIH9_EMIF_TIM1 0x0AAAE51B #define K4B2G1646EBIH9_EMIF_TIM2 0x2A1D7FDA #define K4B2G1646EBIH9_EMIF_TIM3 0x501F83FF
On Thu, Dec 19, 2013 at 10:00:29AM +0530, Lokesh Vutla wrote:
From: "Satyanarayana, Sandhya" sandhya.satyanarayana@ti.com
This patch enables dynamically powering down the IO receiver when not performing a read on boards using DDR3. This optimizes both active and standby power consumption. This bit is not set on EVM SK and EVM 1.5 and later boards. Setting the same.
This has been tested on PG2.0 EVM1.5, EVM1.2, EVM-SK, BBB.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Signed-off-by: Satyanarayana, Sandhya sandhya.satyanarayana@ti.com
Applied to u-boot-ti/master, thanks!
participants (2)
-
Lokesh Vutla -
Tom Rini