[PATCH 0/5] riscv: mbv: Enhance MB-V support with also enabling SPL
Hi,
enhance MB-V support with SPL configuration to support OpenSBI. All of that changes are out of generic Risc-V support that's why happy to take it via my tree. Please let me know if you want this to take via riscv subtree.
Thanks, Michal
Michal Simek (5): riscv: mbv: Align addresses with default DT riscv: mbv: Enable REMAKE_ELF by default riscv: mbv: Switch to OF_SEPARATE with fixed address riscv: mbv: Moving little_endian variable to data section riscv: mbv: Enable SPL and binman
arch/riscv/dts/xilinx-mbv32.dts | 3 +++ board/xilinx/Kconfig | 1 + board/xilinx/common/board.c | 8 ++++++++ board/xilinx/mbv/Kconfig | 14 ++++++++++++-- board/xilinx/mbv/board.c | 10 ++++++++++ configs/xilinx_mbv32_defconfig | 23 ++++++++++++++++++----- configs/xilinx_mbv32_smode_defconfig | 25 ++++++++++++++++++++----- drivers/serial/serial_xuartlite.c | 2 +- 8 files changed, 73 insertions(+), 13 deletions(-)
Better to align everything with memory map described in DT to avoid mistakes. Execute both modes form the same address to make address map more understandable.
Signed-off-by: Michal Simek michal.simek@amd.com ---
board/xilinx/mbv/Kconfig | 3 +-- configs/xilinx_mbv32_defconfig | 3 +-- configs/xilinx_mbv32_smode_defconfig | 3 +-- 3 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/board/xilinx/mbv/Kconfig b/board/xilinx/mbv/Kconfig index 4bc9f72c541b..553c2320697d 100644 --- a/board/xilinx/mbv/Kconfig +++ b/board/xilinx/mbv/Kconfig @@ -13,8 +13,7 @@ config SYS_CONFIG_NAME default "xilinx_mbv"
config TEXT_BASE - default 0x80000000 if !RISCV_SMODE - default 0x80400000 if RISCV_SMODE && ARCH_RV32I + default 0x21200000
config BOARD_SPECIFIC_OPTIONS def_bool y diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig index 2689495057b0..912355f42911 100644 --- a/configs/xilinx_mbv32_defconfig +++ b/configs/xilinx_mbv32_defconfig @@ -1,5 +1,4 @@ CONFIG_RISCV=y -CONFIG_TEXT_BASE=0x21200000 CONFIG_SYS_MALLOC_LEN=0x800000 CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y @@ -10,7 +9,7 @@ CONFIG_DEBUG_UART_BASE=0x40600000 CONFIG_DEBUG_UART_CLOCK=1000000 CONFIG_SYS_CLK_FREQ=100000000 CONFIG_BOOT_SCRIPT_OFFSET=0x0 -CONFIG_SYS_LOAD_ADDR=0x80200000 +CONFIG_SYS_LOAD_ADDR=0x20200000 CONFIG_DEBUG_UART=y CONFIG_TARGET_XILINX_MBV=y CONFIG_FIT=y diff --git a/configs/xilinx_mbv32_smode_defconfig b/configs/xilinx_mbv32_smode_defconfig index c724d1bad742..3c911607a8d9 100644 --- a/configs/xilinx_mbv32_smode_defconfig +++ b/configs/xilinx_mbv32_smode_defconfig @@ -1,5 +1,4 @@ CONFIG_RISCV=y -CONFIG_TEXT_BASE=0x21200000 CONFIG_SYS_MALLOC_LEN=0x800000 CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y @@ -10,7 +9,7 @@ CONFIG_DEBUG_UART_BASE=0x40600000 CONFIG_DEBUG_UART_CLOCK=1000000 CONFIG_SYS_CLK_FREQ=100000000 CONFIG_BOOT_SCRIPT_OFFSET=0x0 -CONFIG_SYS_LOAD_ADDR=0x80200000 +CONFIG_SYS_LOAD_ADDR=0x20200000 CONFIG_TARGET_XILINX_MBV=y CONFIG_RISCV_SMODE=y CONFIG_FIT=y
Create also u-boot.elf out of u-boot ELF. It is better to align it with other Xilinx SOC where u-boot.elf also exists and tools like bootgen works only with files with .elf extension.
Signed-off-by: Michal Simek michal.simek@amd.com ---
configs/xilinx_mbv32_defconfig | 1 + configs/xilinx_mbv32_smode_defconfig | 1 + 2 files changed, 2 insertions(+)
diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig index 912355f42911..89fb3fbd2fbd 100644 --- a/configs/xilinx_mbv32_defconfig +++ b/configs/xilinx_mbv32_defconfig @@ -12,6 +12,7 @@ CONFIG_BOOT_SCRIPT_OFFSET=0x0 CONFIG_SYS_LOAD_ADDR=0x20200000 CONFIG_DEBUG_UART=y CONFIG_TARGET_XILINX_MBV=y +CONFIG_REMAKE_ELF=y CONFIG_FIT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_DISPLAY_CPUINFO=y diff --git a/configs/xilinx_mbv32_smode_defconfig b/configs/xilinx_mbv32_smode_defconfig index 3c911607a8d9..844afdecebf5 100644 --- a/configs/xilinx_mbv32_smode_defconfig +++ b/configs/xilinx_mbv32_smode_defconfig @@ -12,6 +12,7 @@ CONFIG_BOOT_SCRIPT_OFFSET=0x0 CONFIG_SYS_LOAD_ADDR=0x20200000 CONFIG_TARGET_XILINX_MBV=y CONFIG_RISCV_SMODE=y +CONFIG_REMAKE_ELF=y CONFIG_FIT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_DISPLAY_CPUINFO=y
Hardcode DTB address to specific address.
Signed-off-by: Michal Simek michal.simek@amd.com ---
board/xilinx/Kconfig | 1 + configs/xilinx_mbv32_defconfig | 1 - configs/xilinx_mbv32_smode_defconfig | 1 - 3 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/board/xilinx/Kconfig b/board/xilinx/Kconfig index 843198fa0da8..5c4ad8f1df9a 100644 --- a/board/xilinx/Kconfig +++ b/board/xilinx/Kconfig @@ -45,6 +45,7 @@ config XILINX_OF_BOARD_DTB_ADDR default 0x1000 if ARCH_VERSAL || ARCH_VERSAL_NET default 0x8000 if MICROBLAZE default 0x100000 if ARCH_ZYNQ || ARCH_ZYNQMP + default 0x23000000 if TARGET_XILINX_MBV depends on OF_BOARD || OF_SEPARATE help Offset in the memory where the board configuration DTB is placed. diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig index 89fb3fbd2fbd..a08a12570d34 100644 --- a/configs/xilinx_mbv32_defconfig +++ b/configs/xilinx_mbv32_defconfig @@ -20,7 +20,6 @@ CONFIG_DISPLAY_BOARDINFO=y # CONFIG_BOARD_LATE_INIT is not set # CONFIG_CMD_MII is not set CONFIG_CMD_TIMER=y -CONFIG_OF_EMBED=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y CONFIG_DEBUG_UART_ANNOUNCE=y diff --git a/configs/xilinx_mbv32_smode_defconfig b/configs/xilinx_mbv32_smode_defconfig index 844afdecebf5..fd3ef931f6ca 100644 --- a/configs/xilinx_mbv32_smode_defconfig +++ b/configs/xilinx_mbv32_smode_defconfig @@ -20,7 +20,6 @@ CONFIG_DISPLAY_BOARDINFO=y # CONFIG_BOARD_LATE_INIT is not set # CONFIG_CMD_MII is not set CONFIG_CMD_TIMER=y -CONFIG_OF_EMBED=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_MTD=y CONFIG_DEBUG_UART_UARTLITE=y
SPL is cleaning bss after calling board_init_f. Setting up console is done and little_endian global variable is cleared which caused that console stops to work. That's why move it to data seciton now. The patch should be reverted when bss is cleared before board_init_f is called.
Signed-off-by: Michal Simek michal.simek@amd.com ---
drivers/serial/serial_xuartlite.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/serial/serial_xuartlite.c b/drivers/serial/serial_xuartlite.c index b6197da97cc1..35df413321fe 100644 --- a/drivers/serial/serial_xuartlite.c +++ b/drivers/serial/serial_xuartlite.c @@ -23,7 +23,7 @@ #define ULITE_CONTROL_RST_TX 0x01 #define ULITE_CONTROL_RST_RX 0x02
-static bool little_endian; +static bool little_endian __section(".data");
struct uartlite { unsigned int rx_fifo;
Enable SPL and binman to generate u-boot.img (machine mode) and u-boot.itb (supervisor mode). DTB is placed at fixed address to ensure that it is 8 byte aligned which is not ensured when dtb is attached behind SPL binary that's why SPL and U-Boot are taking DTB from the same address. Also align addresses for both defconfigs.
Signed-off-by: Michal Simek michal.simek@amd.com ---
arch/riscv/dts/xilinx-mbv32.dts | 3 +++ board/xilinx/common/board.c | 8 ++++++++ board/xilinx/mbv/Kconfig | 11 +++++++++++ board/xilinx/mbv/board.c | 10 ++++++++++ configs/xilinx_mbv32_defconfig | 18 ++++++++++++++++-- configs/xilinx_mbv32_smode_defconfig | 20 ++++++++++++++++++-- 6 files changed, 66 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/dts/xilinx-mbv32.dts b/arch/riscv/dts/xilinx-mbv32.dts index 94e42c268115..48ee11549566 100644 --- a/arch/riscv/dts/xilinx-mbv32.dts +++ b/arch/riscv/dts/xilinx-mbv32.dts @@ -8,6 +8,9 @@ */
/dts-v1/; + +#include "binman.dtsi" + / { #address-cells = <1>; #size-cells = <1>; diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index 9641ed307b75..e5ab32f901b9 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -358,6 +358,14 @@ void *board_fdt_blob_setup(int *err) void *fdt_blob;
*err = 0; + + if (IS_ENABLED(CONFIG_TARGET_XILINX_MBV)) { + fdt_blob = (void *)CONFIG_XILINX_OF_BOARD_DTB_ADDR; + + if (fdt_magic(fdt_blob) == FDT_MAGIC) + return fdt_blob; + } + if (!IS_ENABLED(CONFIG_SPL_BUILD) && !IS_ENABLED(CONFIG_VERSAL_NO_DDR) && !IS_ENABLED(CONFIG_ZYNQMP_NO_DDR)) { diff --git a/board/xilinx/mbv/Kconfig b/board/xilinx/mbv/Kconfig index 553c2320697d..9d5ee65cea6f 100644 --- a/board/xilinx/mbv/Kconfig +++ b/board/xilinx/mbv/Kconfig @@ -15,12 +15,23 @@ config SYS_CONFIG_NAME config TEXT_BASE default 0x21200000
+config SPL_TEXT_BASE + default 0x20000000 + +config SPL_OPENSBI_LOAD_ADDR + hex + default 0x20200000 + config BOARD_SPECIFIC_OPTIONS def_bool y select GENERIC_RISCV + select SUPPORT_SPL imply BOARD_LATE_INIT + imply SPL_RAM_SUPPORT + imply SPL_RAM_DEVICE imply CMD_SBI imply CMD_PING + imply OF_HAS_PRIOR_STAGE
source "board/xilinx/Kconfig"
diff --git a/board/xilinx/mbv/board.c b/board/xilinx/mbv/board.c index ccf4395d6ace..c478f7e04a0c 100644 --- a/board/xilinx/mbv/board.c +++ b/board/xilinx/mbv/board.c @@ -5,7 +5,17 @@ * Michal Simek michal.simek@amd.com */
+#include <spl.h> + int board_init(void) { return 0; } + +#ifdef CONFIG_SPL +u32 spl_boot_device(void) +{ + /* RISC-V QEMU only supports RAM as SPL boot device */ + return BOOT_DEVICE_RAM; +} +#endif diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig index a08a12570d34..4113409efbb2 100644 --- a/configs/xilinx_mbv32_defconfig +++ b/configs/xilinx_mbv32_defconfig @@ -1,10 +1,13 @@ CONFIG_RISCV=y -CONFIG_SYS_MALLOC_LEN=0x800000 +CONFIG_SYS_MALLOC_LEN=0xe00000 CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20200000 +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x21200000 CONFIG_ENV_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32" +CONFIG_SPL_STACK=0x20200000 +CONFIG_SPL_SIZE_LIMIT=0x40000 +CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0x40600000 CONFIG_DEBUG_UART_CLOCK=1000000 CONFIG_SYS_CLK_FREQ=100000000 @@ -12,18 +15,29 @@ CONFIG_BOOT_SCRIPT_OFFSET=0x0 CONFIG_SYS_LOAD_ADDR=0x20200000 CONFIG_DEBUG_UART=y CONFIG_TARGET_XILINX_MBV=y +# CONFIG_SPL_SMP is not set CONFIG_REMAKE_ELF=y CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x20200000 CONFIG_DISTRO_DEFAULTS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y # CONFIG_BOARD_LATE_INIT is not set +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_BSS_START_ADDR=0x24000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 # CONFIG_CMD_MII is not set CONFIG_CMD_TIMER=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DM_MTD=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_XILINX_UARTLITE=y CONFIG_XILINX_TIMER=y +# CONFIG_BINMAN_FDT is not set CONFIG_PANIC_HANG=y +CONFIG_SPL_GZIP=y diff --git a/configs/xilinx_mbv32_smode_defconfig b/configs/xilinx_mbv32_smode_defconfig index fd3ef931f6ca..99381478ac5c 100644 --- a/configs/xilinx_mbv32_smode_defconfig +++ b/configs/xilinx_mbv32_smode_defconfig @@ -1,26 +1,40 @@ CONFIG_RISCV=y -CONFIG_SYS_MALLOC_LEN=0x800000 +CONFIG_SYS_MALLOC_LEN=0xe00000 CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20200000 +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x21200000 CONFIG_ENV_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32" +CONFIG_SPL_STACK=0x20200000 +CONFIG_SPL_SIZE_LIMIT=0x40000 +CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0x40600000 CONFIG_DEBUG_UART_CLOCK=1000000 CONFIG_SYS_CLK_FREQ=100000000 CONFIG_BOOT_SCRIPT_OFFSET=0x0 CONFIG_SYS_LOAD_ADDR=0x20200000 CONFIG_TARGET_XILINX_MBV=y +CONFIG_SPL_OPENSBI_LOAD_ADDR=0x20100000 CONFIG_RISCV_SMODE=y +# CONFIG_SPL_SMP is not set CONFIG_REMAKE_ELF=y CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x20200000 CONFIG_DISTRO_DEFAULTS=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y # CONFIG_BOARD_LATE_INIT is not set +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_BSS_START_ADDR=0x24000000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 +CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x2 # CONFIG_CMD_MII is not set CONFIG_CMD_TIMER=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DM_MTD=y CONFIG_DEBUG_UART_UARTLITE=y CONFIG_DEBUG_UART_ANNOUNCE=y @@ -28,4 +42,6 @@ CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_XILINX_UARTLITE=y # CONFIG_RISCV_TIMER is not set CONFIG_XILINX_TIMER=y +# CONFIG_BINMAN_FDT is not set CONFIG_PANIC_HANG=y +CONFIG_SPL_GZIP=y
On 2/14/24 12:52, Michal Simek wrote:
Hi,
enhance MB-V support with SPL configuration to support OpenSBI. All of that changes are out of generic Risc-V support that's why happy to take it via my tree. Please let me know if you want this to take via riscv subtree.
Applied via my xilinx tree.
Thanks, Michal
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Michal Simek