grf is needed by various drivers for rk3066 soc.

Signed-off-by: Paweł Jarosz paweljarosz3691@gmail.com Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com --- Changes since v1: - updated to shifted masks

Changes since v2: - none

Changes since v3: - none

arch/arm/include/asm/arch-rockchip/grf_rk3066.h | 621 ++++++++++++++++++++++++ 1 file changed, 621 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3066.h

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3066.h b/arch/arm/include/asm/arch-rockchip/grf_rk3066.h new file mode 100644 index 0000000..be40884 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3066.h @@ -0,0 +1,621 @@ +/* + * Copyright (c) 2017 Paweł Jarosz paweljarosz3691@gmail.com + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ASM_ARCH_GRF_RK3066_H +#define _ASM_ARCH_GRF_RK3066_H + +struct rk3066_grf_gpio_lh { + u32 l; + u32 h; +}; + +struct rk3066_grf { + struct rk3066_grf_gpio_lh gpio_dir[7]; + struct rk3066_grf_gpio_lh gpio_do[7]; + struct rk3066_grf_gpio_lh gpio_en[7]; + + u32 gpio0a_iomux; + u32 gpio0b_iomux; + u32 gpio0c_iomux; + u32 gpio0d_iomux; + + u32 gpio1a_iomux; + u32 gpio1b_iomux; + u32 gpio1c_iomux; + u32 gpio1d_iomux; + + u32 gpio2a_iomux; + u32 gpio2b_iomux; + u32 gpio2c_iomux; + u32 gpio2d_iomux; + + u32 gpio3a_iomux; + u32 gpio3b_iomux; + u32 gpio3c_iomux; + u32 gpio3d_iomux; + + u32 gpio4a_iomux; + u32 gpio4b_iomux; + u32 gpio4c_iomux; + u32 gpio4d_iomux; + + u32 reserved0[5]; + + u32 gpio6b_iomux; + + u32 reserved1[2]; + + struct rk3066_grf_gpio_lh gpio_pull[7]; + + u32 soc_con0; + u32 soc_con1; + u32 soc_con2; + + u32 soc_status0; + + u32 dmac1_con[3]; + u32 dmac2_con[4]; + + u32 uoc0_con[3]; + u32 uoc1_con[4]; + u32 ddrc_con; + u32 ddrc_stat; + + u32 reserved2[10]; + + u32 os_reg[4]; +}; +check_member(rk3066_grf, os_reg[3], 0x01d4); + +/* GRF_GPIO0A_IOMUX */ +enum { + GPIO0A6_SHIFT = 12, + GPIO0A6_MASK = 1 << GPIO0A6_SHIFT, + GPIO0A6_GPIO = 0, + GPIO0A6_HOST_DRV_VBUS, + + GPIO0A5_SHIFT = 10, + GPIO0A5_MASK = 1 << GPIO0A5_SHIFT, + GPIO0A5_GPIO = 0, + GPIO0A5_OTG_DRV_VBUS, + + GPIO0A4_SHIFT = 8, + GPIO0A4_MASK = 1 << GPIO0A4_SHIFT, + GPIO0A4_GPIO = 0, + GPIO0A4_PWM1, + + GPIO0A3_SHIFT = 6, + GPIO0A3_MASK = 1 << GPIO0A3_SHIFT, + GPIO0A3_GPIO = 0, + GPIO0A3_PWM0 +}; + +/* GRF_GPIO0D_IOMUX */ +enum { + GPIO0D7_SHIFT = 14, + GPIO0D7_MASK = 1 << GPIO0D7_SHIFT, + GPIO0D7_GPIO = 0, + GPIO0D7_PWM3, + + GPIO0D6_SHIFT = 12, + GPIO0D6_MASK = 1 << GPIO0D6_SHIFT, + GPIO0D6_GPIO = 0, + GPIO0D6_PWM2 +}; + +/* GRF_GPIO1A_IOMUX */ +enum { + GPIO1A7_SHIFT = 14, + GPIO1A7_MASK = 3 << GPIO1A7_SHIFT, + GPIO1A7_GPIO = 0, + GPIO1A7_UART1_RTS_N, + GPIO1A7_SPI0_TXD, + + GPIO1A6_SHIFT = 12, + GPIO1A6_MASK = 3 << GPIO1A6_SHIFT, + GPIO1A6_GPIO = 0, + GPIO1A6_UART1_CTS_N, + GPIO1A6_SPI0_RXD, + + GPIO1A5_SHIFT = 10, + GPIO1A5_MASK = 3 << GPIO1A5_SHIFT, + GPIO1A5_GPIO = 0, + GPIO1A5_UART1_SOUT, + GPIO1A5_SPI0_CLK, + + GPIO1A4_SHIFT = 8, + GPIO1A4_MASK = 3 << GPIO1A4_SHIFT, + GPIO1A4_GPIO = 0, + GPIO1A4_UART1_SIN, + GPIO1A4_SPI0_CSN0, + + GPIO1A3_SHIFT = 6, + GPIO1A3_MASK = 1 << GPIO1A3_SHIFT, + GPIO1A3_GPIO = 0, + GPIO1A3_UART0_RTS_N, + + GPIO1A2_SHIFT = 4, + GPIO1A2_MASK = 1 << GPIO1A2_SHIFT, + GPIO1A2_GPIO = 0, + GPIO1A2_UART0_CTS_N, + + GPIO1A1_SHIFT = 2, + GPIO1A1_MASK = 1 << GPIO1A1_SHIFT, + GPIO1A1_GPIO = 0, + GPIO1A1_UART0_SOUT, + + GPIO1A0_SHIFT = 0, + GPIO1A0_MASK = 1 << GPIO1A0_SHIFT, + GPIO1A0_GPIO = 0, + GPIO1A0_UART0_SIN +}; + +/* GRF_GPIO1B_IOMUX */ +enum { + GPIO1B1_SHIFT = 2, + GPIO1B1_MASK = 1 << GPIO1B1_SHIFT, + GPIO1B1_GPIO = 0, + GPIO1B1_UART2_SOUT, + + GPIO1B0_SHIFT = 0, + GPIO1B0_MASK = 1 << GPIO1B0_SHIFT, + GPIO1B0_GPIO = 0, + GPIO1B0_UART2_SIN +}; + +/* GRF_GPIO2C_IOMUX */ +enum { + GPIO2C7_SHIFT = 14, + GPIO2C7_MASK = 3 << GPIO2C7_SHIFT, + GPIO2C7_GPIO = 0, + GPIO2C7_LCDC1_DATA23, + GPIO2C7_SPI1_CSN1, + GPIO2C7_HSADC_DATA4, + + GPIO2C6_SHIFT = 12, + GPIO2C6_MASK = 3 << GPIO2C6_SHIFT, + GPIO2C6_GPIO = 0, + GPIO2C6_LCDC1_DATA22, + GPIO2C6_SPI1_RXD, + GPIO2C6_HSADC_DATA3, + + GPIO2C5_SHIFT = 10, + GPIO2C5_MASK = 3 << GPIO2C5_SHIFT, + GPIO2C5_GPIO = 0, + GPIO2C5_LCDC1_DATA21, + GPIO2C5_SPI1_TXD, + GPIO2C5_HSADC_DATA2, + + GPIO2C4_SHIFT = 8, + GPIO2C4_MASK = 3 << GPIO2C4_SHIFT, + GPIO2C4_GPIO = 0, + GPIO2C4_LCDC1_DATA20, + GPIO2C4_SPI1_CSN0, + GPIO2C4_HSADC_DATA1, + + GPIO2C3_SHIFT = 6, + GPIO2C3_MASK = 3 << GPIO2C3_SHIFT, + GPIO2C3_GPIO = 0, + GPIO2C3_LCDC1_DATA19, + GPIO2C3_SPI1_CLK, + GPIO2C3_HSADC_DATA0 +}; + +/* GRF_GPIO2D_IOMUX */ +enum { + GPIO2D7_SHIFT = 14, + GPIO2D7_MASK = 1 << GPIO2D7_SHIFT, + GPIO2D7_GPIO = 0, + GPIO2D7_I2C1_SCL, + + GPIO2D6_SHIFT = 12, + GPIO2D6_MASK = 1 << GPIO2D6_SHIFT, + GPIO2D6_GPIO = 0, + GPIO2D6_I2C1_SDA, + + GPIO2D5_SHIFT = 10, + GPIO2D5_MASK = 1 << GPIO2D5_SHIFT, + GPIO2D5_GPIO = 0, + GPIO2D5_I2C0_SCL, + + GPIO2D4_SHIFT = 8, + GPIO2D4_MASK = 1 << GPIO2D4_SHIFT, + GPIO2D4_GPIO = 0, + GPIO2D4_I2C0_SDA + +}; + +/* GRF_GPIO3A_IOMUX */ +enum { + GPIO3A7_SHIFT = 14, + GPIO3A7_MASK = 1 << GPIO3A7_SHIFT, + GPIO3A7_GPIO = 0, + GPIO3A7_SDMMC0_WRITE_PRT, + + GPIO3A6_SHIFT = 12, + GPIO3A6_MASK = 1 << GPIO3A6_SHIFT, + GPIO3A6_GPIO = 0, + GPIO3A6_SDMMC0_RSTN_OUT, + + GPIO3A5_SHIFT = 10, + GPIO3A5_MASK = 1 << GPIO3A5_SHIFT, + GPIO3A5_GPIO = 0, + GPIO3A5_I2C4_SCL, + + GPIO3A4_SHIFT = 8, + GPIO3A4_MASK = 1 << GPIO3A4_SHIFT, + GPIO3A4_GPIO = 0, + GPIO3A4_I2C4_SDA, + + GPIO3A3_SHIFT = 6, + GPIO3A3_MASK = 1 << GPIO3A3_SHIFT, + GPIO3A3_GPIO = 0, + GPIO3A3_I2C3_SCL, + + GPIO3A2_SHIFT = 4, + GPIO3A2_MASK = 1 << GPIO3A2_SHIFT, + GPIO3A2_GPIO = 0, + GPIO3A2_I2C3_SDA, + + GPIO3A1_SHIFT = 2, + GPIO3A1_MASK = 1 << GPIO3A1_SHIFT, + GPIO3A1_GPIO = 0, + GPIO3A1_I2C2_SCL, + + GPIO3A0_SHIFT = 0, + GPIO3A0_MASK = 1 << GPIO3A0_SHIFT, + GPIO3A0_GPIO = 0, + GPIO3A0_I2C2_SDA, +}; + +/* GRF_GPIO3B_IOMUX */ +enum { + GPIO3B7_SHIFT = 14, + GPIO3B7_MASK = 1 << GPIO3B7_SHIFT, + GPIO3B7_GPIO = 0, + GPIO3B7_SDMMC0_WRITE_PRT, + + GPIO3B6_SHIFT = 12, + GPIO3B6_MASK = 1 << GPIO3B6_SHIFT, + GPIO3B6_GPIO = 0, + GPIO3B6_SDMMC0_DETECT_N, + + GPIO3B5_SHIFT = 10, + GPIO3B5_MASK = 1 << GPIO3B5_SHIFT, + GPIO3B5_GPIO = 0, + GPIO3B5_SDMMC0_DATA3, + + GPIO3B4_SHIFT = 8, + GPIO3B4_MASK = 1 << GPIO3B4_SHIFT, + GPIO3B4_GPIO = 0, + GPIO3B4_SDMMC0_DATA2, + + GPIO3B3_SHIFT = 6, + GPIO3B3_MASK = 1 << GPIO3B3_SHIFT, + GPIO3B3_GPIO = 0, + GPIO3B3_SDMMC0_DATA1, + + GPIO3B2_SHIFT = 4, + GPIO3B2_MASK = 1 << GPIO3B2_SHIFT, + GPIO3B2_GPIO = 0, + GPIO3B2_SDMMC0_DATA0, + + GPIO3B1_SHIFT = 2, + GPIO3B1_MASK = 1 << GPIO3B1_SHIFT, + GPIO3B1_GPIO = 0, + GPIO3B1_SDMMC0_CMD, + + GPIO3B0_SHIFT = 0, + GPIO3B0_MASK = 1 << GPIO3B0_SHIFT, + GPIO3B0_GPIO = 0, + GPIO3B0_SDMMC0_CLKOUT + +}; + +/* GRF_GPIO3C_IOMUX */ +enum { + GPIO3C7_SHIFT = 14, + GPIO3C7_MASK = 1 << GPIO3C7_SHIFT, + GPIO3C7_GPIO = 0, + GPIO3C7_SDMMC1_WRITE_PRT, + + GPIO3C6_SHIFT = 12, + GPIO3C6_MASK = 1 << GPIO3C6_SHIFT, + GPIO3C6_GPIO = 0, + GPIO3C6_SDMMC1_DETECT_N, + + GPIO3C5_SHIFT = 10, + GPIO3C5_MASK = 1 << GPIO3C5_SHIFT, + GPIO3C5_GPIO = 0, + GPIO3C5_SDMMC1_CLKOUT, + + GPIO3C4_SHIFT = 8, + GPIO3C4_MASK = 1 << GPIO3C4_SHIFT, + GPIO3C4_GPIO = 0, + GPIO3C4_SDMMC1_DATA3, + + GPIO3C3_SHIFT = 6, + GPIO3C3_MASK = 1 << GPIO3C3_SHIFT, + GPIO3C3_GPIO = 0, + GPIO3C3_SDMMC1_DATA2, + + GPIO3C2_SHIFT = 4, + GPIO3C2_MASK = 1 << GPIO3C2_SHIFT, + GPIO3C2_GPIO = 0, + GPIO3C2_SDMMC1_DATA1, + + GPIO3C1_SHIFT = 2, + GPIO3C1_MASK = 1 << GPIO3C1_SHIFT, + GPIO3C1_GPIO = 0, + GPIO3C1_SDMMC1_DATA0, + + GPIO3C0_SHIFT = 0, + GPIO3C0_MASK = 1 << GPIO3C0_SHIFT, + GPIO3C0_GPIO = 0, + GPIO3C0_SMMC1_CMD +}; + +/* GRF_GPIO3D_IOMUX */ +enum { + GPIO3D7_SHIFT = 14, + GPIO3D7_MASK = 3 << GPIO3D7_SHIFT, + GPIO3D7_GPIO = 0, + GPIO3D7_FLASH_DQS, + GPIO3D7_EMMC_CLKOUT, + + GPIO3D6_SHIFT = 12, + GPIO3D6_MASK = 1 << GPIO3D6_SHIFT, + GPIO3D6_GPIO = 0, + GPIO3D6_UART3_RTS_N, + + GPIO3D5_SHIFT = 10, + GPIO3D5_MASK = 1 << GPIO3D5_SHIFT, + GPIO3D5_GPIO = 0, + GPIO3D5_UART3_CTS_N, + + GPIO3D4_SHIFT = 8, + GPIO3D4_MASK = 1 << GPIO3D4_SHIFT, + GPIO3D4_GPIO = 0, + GPIO3D4_UART3_SOUT, + + GPIO3D3_SHIFT = 6, + GPIO3D3_MASK = 1 << GPIO3D3_SHIFT, + GPIO3D3_GPIO = 0, + GPIO3D3_UART3_SIN, + + GPIO3D2_SHIFT = 4, + GPIO3D2_MASK = 1 << GPIO3D2_SHIFT, + GPIO3D2_GPIO = 0, + GPIO3D2_SDMMC1_INT_N, + + GPIO3D1_SHIFT = 2, + GPIO3D1_MASK = 1 << GPIO3D1_SHIFT, + GPIO3D1_GPIO = 0, + GPIO3D1_SDMMC1_BACKEND_PWR, + + GPIO3D0_SHIFT = 0, + GPIO3D0_MASK = 1 << GPIO3D0_SHIFT, + GPIO3D0_GPIO = 0, + GPIO3D0_SDMMC1_PWR_EN + +}; + +/* GRF_GPIO4A_IOMUX */ +enum { + GPIO4A7_SHIFT = 14, + GPIO4A7_MASK = 1 << GPIO4A7_SHIFT, + GPIO4A7_GPIO = 0, + GPIO4A7_FLASH_DATA15, + + GPIO4A6_SHIFT = 12, + GPIO4A6_MASK = 1 << GPIO4A6_SHIFT, + GPIO4A6_GPIO = 0, + GPIO4A6_FLASH_DATA14, + + GPIO4A5_SHIFT = 10, + GPIO4A5_MASK = 1 << GPIO4A5_SHIFT, + GPIO4A5_GPIO = 0, + GPIO4A5_FLASH_DATA13, + + GPIO4A4_SHIFT = 8, + GPIO4A4_MASK = 1 << GPIO4A4_SHIFT, + GPIO4A4_GPIO = 0, + GPIO4A4_FLASH_DATA12, + + GPIO4A3_SHIFT = 6, + GPIO4A3_MASK = 1 << GPIO4A3_SHIFT, + GPIO4A3_GPIO = 0, + GPIO4A3_FLASH_DATA11, + + GPIO4A2_SHIFT = 4, + GPIO4A2_MASK = 1 << GPIO4A2_SHIFT, + GPIO4A2_GPIO = 0, + GPIO4A2_FLASH_DATA10, + + GPIO4A1_SHIFT = 2, + GPIO4A1_MASK = 1 << GPIO4A1_SHIFT, + GPIO4A1_GPIO = 0, + GPIO4A1_FLASH_DATA9, + + GPIO4A0_SHIFT = 0, + GPIO4A0_MASK = 1 << GPIO4A0_SHIFT, + GPIO4A0_GPIO = 0, + GPIO4A0_FLASH_DATA8 + +}; + +/* GRF_GPIO4B_IOMUX */ +enum { + GPIO4B7_SHIFT = 14, + GPIO4B7_MASK = 1 << GPIO4B7_SHIFT, + GPIO4B7_GPIO = 0, + GPIO4B7_SPI0_CSN1, + + GPIO4B6_SHIFT = 12, + GPIO4B6_MASK = 1 << GPIO4B6_SHIFT, + GPIO4B6_GPIO = 0, + GPIO4B6_FLASH_CSN7, + + GPIO4B5_SHIFT = 10, + GPIO4B5_MASK = 1 << GPIO4B5_SHIFT, + GPIO4B5_GPIO = 0, + GPIO4B5_FLASH_CSN6, + + GPIO4B4_SHIFT = 8, + GPIO4B4_MASK = 1 << GPIO4B4_SHIFT, + GPIO4B4_GPIO = 0, + GPIO4B4_FLASH_CSN5, + + GPIO4B3_SHIFT = 6, + GPIO4B3_MASK = 1 << GPIO4B3_SHIFT, + GPIO4B3_GPIO = 0, + GPIO4B3_FLASH_CSN4, + + GPIO4B2_SHIFT = 4, + GPIO4B2_MASK = 3 << GPIO4B2_SHIFT, + GPIO4B2_GPIO = 0, + GPIO4B2_FLASH_CSN3, + GPIO4B2_EMMC_RSTN_OUT, + + GPIO4B1_SHIFT = 2, + GPIO4B1_MASK = 3 << GPIO4B1_SHIFT, + GPIO4B1_GPIO = 0, + GPIO4B1_FLASH_CSN2, + GPIO4B1_EMMC_CMD, + + GPIO4B0_SHIFT = 0, + GPIO4B0_MASK = 1 << GPIO4B0_SHIFT, + GPIO4B0_GPIO = 0, + GPIO4B0_FLASH_CSN1 +}; + +/* GRF_SOC_CON0 */ +enum { + SMC_MUX_CON_SHIFT = 13, + SMC_MUX_CON_MASK = 1 << SMC_MUX_CON_SHIFT, + + NOC_REMAP_SHIFT = 12, + NOC_REMAP_MASK = 1 << NOC_REMAP_SHIFT, + + EMMC_FLASH_SEL_SHIFT = 11, + EMMC_FLASH_SEL_MASK = 1 << EMMC_FLASH_SEL_SHIFT, + + TZPC_REVISION_SHIFT = 7, + TZPC_REVISION_MASK = 0xf << TZPC_REVISION_SHIFT, + + L2CACHE_ACC_SHIFT = 5, + L2CACHE_ACC_MASK = 3 << L2CACHE_ACC_SHIFT, + + L2RD_WAIT_SHIFT = 3, + L2RD_WAIT_MASK = 3 << L2RD_WAIT_SHIFT, + + IMEMRD_WAIT_SHIFT = 1, + IMEMRD_WAIT_MASK = 3 << IMEMRD_WAIT_SHIFT, + + SOC_REMAP_SHIFT = 0, + SOC_REMAP_MASK = 1 << SOC_REMAP_SHIFT, +}; + +/* GRF_SOC_CON1 */ +enum { + RKI2C4_SEL_SHIFT = 15, + RKI2C4_SEL_MASK = 1 << RKI2C4_SEL_SHIFT, + + RKI2C3_SEL_SHIFT = 14, + RKI2C3_SEL_MASK = 1 << RKI2C3_SEL_SHIFT, + + RKI2C2_SEL_SHIFT = 13, + RKI2C2_SEL_MASK = 1 << RKI2C2_SEL_SHIFT, + + RKI2C1_SEL_SHIFT = 12, + RKI2C1_SEL_MASK = 1 << RKI2C1_SEL_SHIFT, + + RKI2C0_SEL_SHIFT = 11, + RKI2C0_SEL_MASK = 1 << RKI2C0_SEL_SHIFT, + + VCODEC_SEL_SHIFT = 10, + VCODEC_SEL_MASK = 1 << VCODEC_SEL_SHIFT, + + PERI_EMEM_PAUSE_SHIFT = 9, + PERI_EMEM_PAUSE_MASK = 1 << PERI_EMEM_PAUSE_SHIFT, + + PERI_USB_PAUSE_SHIFT = 8, + PERI_USB_PAUSE_MASK = 1 << PERI_USB_PAUSE_SHIFT, + + SMC_MUX_MODE_0_SHIFT = 6, + SMC_MUX_MODE_0_MASK = 1 << SMC_MUX_MODE_0_SHIFT, + + SMC_SRAM_MW_0_SHIFT = 4, + SMC_SRAM_MW_0_MASK = 3 << SMC_SRAM_MW_0_SHIFT, + + SMC_REMAP_0_SHIFT = 3, + SMC_REMAP_0_MASK = 1 << SMC_REMAP_0_SHIFT, + + SMC_A_GT_M0_SYNC_SHIFT = 2, + SMC_A_GT_M0_SYNC_MASK = 1 << SMC_A_GT_M0_SYNC_SHIFT, + + EMAC_SPEED_SHIFT = 1, + EMAC_SPEEC_MASK = 1 << EMAC_SPEED_SHIFT, + + EMAC_MODE_SHIFT = 0, + EMAC_MODE_MASK = 1 << EMAC_MODE_SHIFT, +}; + +/* GRF_SOC_CON2 */ +enum { + + MSCH4_MAINDDR3_SHIFT = 7, + MSCH4_MAINDDR3_MASK = 1 << MSCH4_MAINDDR3_SHIFT, + MSCH4_MAINDDR3_DDR3 = 1, + + EMAC_NEWRCV_EN_SHIFT = 6, + EMAC_NEWRCV_EN_MASK = 1 << EMAC_NEWRCV_EN_SHIFT, + + SW_ADDR15_EN_SHIFT = 5, + SW_ADDR15_EN_MASK = 1 << SW_ADDR15_EN_SHIFT, + + SW_ADDR16_EN_SHIFT = 4, + SW_ADDR16_EN_MASK = 1 << SW_ADDR16_EN_SHIFT, + + SW_ADDR17_EN_SHIFT = 3, + SW_ADDR17_EN_MASK = 1 << SW_ADDR17_EN_SHIFT, + + BANK2_TO_RANK_EN_SHIFT = 2, + BANK2_TO_RANK_EN_MASK = 1 << BANK2_TO_RANK_EN_SHIFT, + + RANK_TO_ROW15_EN_SHIFT = 1, + RANK_TO_ROW15_EN_MASK = 1 << RANK_TO_ROW15_EN_SHIFT, + + UPCTL_C_ACTIVE_IN_SHIFT = 0, + UPCTL_C_ACTIVE_IN_MASK = 1 << UPCTL_C_ACTIVE_IN_SHIFT, + UPCTL_C_ACTIVE_IN_MAY = 0, + UPCTL_C_ACTIVE_IN_WILL, +}; + +/* GRF_DDRC_CON0 */ +enum { + DTO_LB_SHIFT = 11, + DTO_LB_MASK = 3 << DTO_LB_SHIFT, + + DTO_TE_SHIFT = 9, + DTO_TE_MASK = 3 << DTO_TE_SHIFT, + + DTO_PDR_SHIFT = 7, + DTO_PDR_MASK = 3 << DTO_PDR_SHIFT, + + DTO_PDD_SHIFT = 5, + DTO_PDD_MASK = 3 << DTO_PDD_SHIFT, + + DTO_IOM_SHIFT = 3, + DTO_IOM_MASK = 3 << DTO_IOM_SHIFT, + + DTO_OE_SHIFT = 1, + DTO_OE_MASK = 3 << DTO_OE_SHIFT, + + ATO_AE_SHIFT = 0, + ATO_AE_MASK = 1 << ATO_AE_SHIFT, +}; +#endif

Add driver supporting pin multiplexing on rk3066 platform.

Signed-off-by: Paweł Jarosz paweljarosz3691@gmail.com Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com --- Changes since v1: - updated to shifted masks - added nand support

Changes since v2: - none

Changes since v3: - none

arch/arm/include/asm/arch-rockchip/periph.h | 1 + drivers/pinctrl/Kconfig | 9 + drivers/pinctrl/rockchip/Makefile | 1 + drivers/pinctrl/rockchip/pinctrl_rk3066.c | 340 ++++++++++++++++++++++++++++ 4 files changed, 351 insertions(+) create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3066.c

diff --git a/arch/arm/include/asm/arch-rockchip/periph.h b/arch/arm/include/asm/arch-rockchip/periph.h index 9f4bc2e..6c8c77d 100644 --- a/arch/arm/include/asm/arch-rockchip/periph.h +++ b/arch/arm/include/asm/arch-rockchip/periph.h @@ -43,6 +43,7 @@ enum periph_id { PERIPH_ID_HDMI, PERIPH_ID_GMAC, PERIPH_ID_SFC, + PERIPH_ID_NAND,

PERIPH_ID_COUNT,

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index bcbe4a1..c9eb49d 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -168,6 +168,15 @@ config PINCTRL_ROCKCHIP_RK3036 the GPIO definitions and pin control functions for each available multiplex function.

+config PINCTRL_ROCKCHIP_RK3066 + bool "Rockchip rk3066 pin control driver" + depends on DM + help + Support pin multiplexing control on Rockchip rk3066 SoCs. The driver is + controlled by a device tree node which contains both the GPIO + definitions and pin control functions for each available multiplex + function. + config PINCTRL_ROCKCHIP_RK3188 bool "Rockchip rk3188 pin control driver" depends on DM diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile index 5251771..65923f9 100644 --- a/drivers/pinctrl/rockchip/Makefile +++ b/drivers/pinctrl/rockchip/Makefile @@ -6,6 +6,7 @@ #

obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3036) += pinctrl_rk3036.o +obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3066) += pinctrl_rk3066.o obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3188) += pinctrl_rk3188.o obj-$(CONFIG_PINCTRL_ROCKCHIP_RK322X) += pinctrl_rk322x.o obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3288) += pinctrl_rk3288.o diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3066.c b/drivers/pinctrl/rockchip/pinctrl_rk3066.c new file mode 100644 index 0000000..79e0a54 --- /dev/null +++ b/drivers/pinctrl/rockchip/pinctrl_rk3066.c @@ -0,0 +1,340 @@ +/* + * Pinctrl driver for Rockchip 3066 SoCs + * (C) Copyright 2017 Paweł Jarosz paweljarosz3691@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <dm/device.h> +#include <errno.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/grf_rk3066.h> +#include <asm/arch/hardware.h> +#include <asm/arch/periph.h> +#include <dm/pinctrl.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct rk3066_pinctrl_priv { + struct rk3066_grf *grf; +}; + +static void pinctrl_rk3066_pwm_config(struct rk3066_grf *grf, int pwm_id) +{ + switch (pwm_id) { + case PERIPH_ID_PWM0: + rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A3_MASK, + GPIO0A3_PWM0 << GPIO0A3_SHIFT); + break; + case PERIPH_ID_PWM1: + rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A4_MASK, + GPIO0A4_PWM1 << GPIO0A4_SHIFT); + break; + case PERIPH_ID_PWM2: + rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D6_MASK, + GPIO0D6_PWM2 << GPIO0D6_SHIFT); + break; + case PERIPH_ID_PWM3: + rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D7_MASK, + GPIO0D7_PWM3 << GPIO0D7_SHIFT); + break; + default: + debug("pwm id = %d iomux error!\n", pwm_id); + break; + } +} + +static void pinctrl_rk3066_i2c_config(struct rk3066_grf *grf, int i2c_id) +{ + switch (i2c_id) { + case PERIPH_ID_I2C0: + rk_clrsetreg(&grf->gpio2d_iomux, + GPIO2D4_MASK | GPIO2D5_MASK, + GPIO2D4_I2C0_SDA << GPIO2D4_SHIFT | + GPIO2D5_I2C0_SCL << GPIO2D5_SHIFT); + rk_clrsetreg(&grf->soc_con1, 1 << RKI2C0_SEL_SHIFT, + 1 << RKI2C0_SEL_SHIFT); + break; + case PERIPH_ID_I2C1: + rk_clrsetreg(&grf->gpio2d_iomux, + GPIO2D6_MASK | GPIO2D7_MASK, + GPIO2D6_I2C1_SDA << GPIO2D6_SHIFT | + GPIO2D7_I2C1_SCL << GPIO2D7_SHIFT); + rk_clrsetreg(&grf->soc_con1, 1 << RKI2C1_SEL_SHIFT, + 1 << RKI2C1_SEL_SHIFT); + break; + case PERIPH_ID_I2C2: + rk_clrsetreg(&grf->gpio3a_iomux, + GPIO3A1_MASK | GPIO3A0_MASK, + GPIO3A1_I2C2_SCL << GPIO3A1_SHIFT | + GPIO3A0_I2C2_SDA << GPIO3A0_SHIFT); + rk_clrsetreg(&grf->soc_con1, 1 << RKI2C2_SEL_SHIFT, + 1 << RKI2C2_SEL_SHIFT); + case PERIPH_ID_I2C3: + rk_clrsetreg(&grf->gpio3a_iomux, + GPIO3A3_MASK | GPIO3A2_MASK, + GPIO3A3_I2C3_SCL << GPIO3A3_SHIFT | + GPIO3A2_I2C3_SDA << GPIO3A2_SHIFT); + rk_clrsetreg(&grf->soc_con1, 1 << RKI2C3_SEL_SHIFT, + 1 << RKI2C3_SEL_SHIFT); + case PERIPH_ID_I2C4: + rk_clrsetreg(&grf->gpio3a_iomux, + GPIO3A5_MASK | GPIO3A4_MASK, + GPIO3A5_I2C4_SCL << GPIO3A5_SHIFT | + GPIO3A4_I2C4_SDA << GPIO3A4_SHIFT); + rk_clrsetreg(&grf->soc_con1, 1 << RKI2C4_SEL_SHIFT, + 1 << RKI2C4_SEL_SHIFT); + break; + } +} + +static void pinctrl_rk3066_spi_config(struct rk3066_grf *grf, int spi_id, int cs) +{ + switch (spi_id) { + case PERIPH_ID_SPI0: + rk_clrsetreg(&grf->gpio1a_iomux, + GPIO1A7_MASK | GPIO1A6_MASK | GPIO1A5_MASK, + GPIO1A7_SPI0_TXD << GPIO1A7_SHIFT | + GPIO1A6_SPI0_RXD << GPIO1A6_SHIFT | + GPIO1A5_SPI0_CLK << GPIO1A5_SHIFT); + if(cs == 0) + rk_clrsetreg(&grf->gpio1a_iomux, + GPIO1A4_MASK, + GPIO1A4_SPI0_CSN0 << GPIO1A4_SHIFT); + else + rk_clrsetreg(&grf->gpio4b_iomux, + GPIO4B7_MASK, + GPIO4B7_SPI0_CSN1 << GPIO4B7_SHIFT); + break; + case PERIPH_ID_SPI1: + rk_clrsetreg(&grf->gpio2c_iomux, + GPIO2C5_MASK | GPIO2C6_MASK | GPIO2C3_MASK, + GPIO2C5_SPI1_TXD << GPIO2C5_SHIFT | + GPIO2C6_SPI1_RXD << GPIO2C6_SHIFT | + GPIO2C3_SPI1_CLK << GPIO2C3_SHIFT); + if(cs == 0) + rk_clrsetreg(&grf->gpio2c_iomux, + GPIO2C4_MASK, + GPIO2C4_SPI1_CSN0 << GPIO2C4_SHIFT); + else + rk_clrsetreg(&grf->gpio2c_iomux, + GPIO2C7_MASK, + GPIO2C7_SPI1_CSN1 << GPIO2C7_SHIFT); + break; + } +} + +static void pinctrl_rk3066_uart_config(struct rk3066_grf *grf, int uart_id) +{ + switch (uart_id) { + case PERIPH_ID_UART0: + rk_clrsetreg(&grf->gpio1a_iomux, + GPIO1A2_MASK | GPIO1A3_MASK | + GPIO1A0_MASK | GPIO1A1_MASK, + GPIO1A2_UART0_CTS_N << GPIO1A2_SHIFT | + GPIO1A3_UART0_RTS_N << GPIO1A3_SHIFT | + GPIO1A0_UART0_SIN << GPIO1A0_SHIFT | + GPIO1A1_UART0_SOUT << GPIO1A1_SHIFT); + break; + case PERIPH_ID_UART1: + rk_clrsetreg(&grf->gpio1a_iomux, + GPIO1A7_MASK | GPIO1A6_MASK | + GPIO1A5_MASK | GPIO1A4_MASK, + GPIO1A7_UART1_RTS_N << GPIO1A7_SHIFT | + GPIO1A6_UART1_CTS_N << GPIO1A6_SHIFT | + GPIO1A5_UART1_SOUT << GPIO1A5_SHIFT | + GPIO1A4_UART1_SIN << GPIO1A4_SHIFT); + break; + case PERIPH_ID_UART2: + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B1_MASK | GPIO1B0_MASK, + GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT | + GPIO1B0_UART2_SIN << GPIO1B0_SHIFT); + break; + case PERIPH_ID_UART3: + rk_clrsetreg(&grf->gpio3d_iomux, + GPIO3D6_MASK | GPIO3D5_MASK | + GPIO3D4_MASK | GPIO3D3_MASK, + GPIO3D6_UART3_RTS_N << GPIO3D6_SHIFT | + GPIO3D5_UART3_CTS_N << GPIO3D5_SHIFT | + GPIO3D4_UART3_SOUT << GPIO3D4_SHIFT | + GPIO3D3_UART3_SIN << GPIO3D3_SHIFT); + break; + } +} + +static void pinctrl_rk3066_sdmmc_config(struct rk3066_grf *grf, int mmc_id) +{ + switch (mmc_id) { + case PERIPH_ID_EMMC: + rk_clrsetreg(&grf->soc_con0, + EMMC_FLASH_SEL_MASK, + 1 << EMMC_FLASH_SEL_SHIFT); + rk_clrsetreg(&grf->gpio3d_iomux, + GPIO3D7_MASK, + GPIO3D7_EMMC_CLKOUT << GPIO3D7_SHIFT); + rk_clrsetreg(&grf->gpio4b_iomux, + GPIO4B2_MASK | GPIO4B1_MASK, + GPIO4B2_EMMC_RSTN_OUT << GPIO4B2_SHIFT | + GPIO4B1_EMMC_CMD << GPIO4B1_SHIFT); + break; + case PERIPH_ID_SDCARD: + rk_clrsetreg(&grf->gpio3b_iomux, 0xffff, + GPIO3B7_SDMMC0_WRITE_PRT << GPIO3B7_SHIFT | + GPIO3B6_SDMMC0_DETECT_N << GPIO3B6_SHIFT | + GPIO3B5_SDMMC0_DATA3 << GPIO3B5_SHIFT | + GPIO3B4_SDMMC0_DATA2 << GPIO3B4_SHIFT | + GPIO3B3_SDMMC0_DATA1 << GPIO3B3_SHIFT | + GPIO3B2_SDMMC0_DATA0 << GPIO3B2_SHIFT | + GPIO3B1_SDMMC0_CMD << GPIO3B1_SHIFT | + GPIO3B0_SDMMC0_CLKOUT << GPIO3B0_SHIFT); + break; + } +} + +static void pinctrl_rk3066_nand_config(struct rk3066_grf *grf) +{ + rk_clrsetreg(&grf->soc_con0, + EMMC_FLASH_SEL_MASK, + 0 << EMMC_FLASH_SEL_SHIFT); + rk_clrsetreg(&grf->gpio3d_iomux, + GPIO3D7_MASK, + GPIO3D7_FLASH_DQS << GPIO3D7_SHIFT); +} + +static int rk3066_pinctrl_request(struct udevice *dev, int func, int flags) +{ + struct rk3066_pinctrl_priv *priv = dev_get_priv(dev); + + debug("%s: func=%x, flags=%x\n", __func__, func, flags); + switch (func) { + case PERIPH_ID_PWM0: + case PERIPH_ID_PWM1: + case PERIPH_ID_PWM2: + case PERIPH_ID_PWM3: + pinctrl_rk3066_pwm_config(priv->grf, func); + break; + case PERIPH_ID_I2C0: + case PERIPH_ID_I2C1: + case PERIPH_ID_I2C2: + case PERIPH_ID_I2C3: + case PERIPH_ID_I2C4: + pinctrl_rk3066_i2c_config(priv->grf, func); + break; + case PERIPH_ID_SPI0: + case PERIPH_ID_SPI1: + pinctrl_rk3066_spi_config(priv->grf, func, flags); + break; + case PERIPH_ID_UART0: + case PERIPH_ID_UART1: + case PERIPH_ID_UART2: + case PERIPH_ID_UART3: + pinctrl_rk3066_uart_config(priv->grf, func); + break; + case PERIPH_ID_EMMC: + case PERIPH_ID_SDCARD: + pinctrl_rk3066_sdmmc_config(priv->grf, func); + break; + case PERIPH_ID_NAND: + pinctrl_rk3066_nand_config(priv->grf); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int rk3066_pinctrl_get_periph_id(struct udevice *dev, + struct udevice *periph) +{ +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + u32 cell[3]; + int ret; + + ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph), + "interrupts", cell, ARRAY_SIZE(cell)); + if (ret < 0) + return -EINVAL; + + switch (cell[1]) { + case 23: + return PERIPH_ID_SDCARD; + case 25: + return PERIPH_ID_EMMC; + case 27: + return PERIPH_ID_NAND; + case 34: + return PERIPH_ID_UART0; + case 35: + return PERIPH_ID_UART1; + case 36: + return PERIPH_ID_UART2; + case 37: + return PERIPH_ID_UART3; + case 38: + return PERIPH_ID_SPI0; + case 39: + return PERIPH_ID_SPI1; + case 40: + return PERIPH_ID_I2C0; + case 41: + return PERIPH_ID_I2C1; + case 42: + return PERIPH_ID_I2C2; + case 43: + return PERIPH_ID_I2C3; + case 30: + return PERIPH_ID_PWM0; + } +#endif + return -ENOENT; +} + +static int rk3066_pinctrl_set_state_simple(struct udevice *dev, + struct udevice *periph) +{ + int func; + + func = rk3066_pinctrl_get_periph_id(dev, periph); + if (func < 0) + return func; + return rk3066_pinctrl_request(dev, func, 0); +} + +static struct pinctrl_ops rk3066_pinctrl_ops = { + .set_state_simple = rk3066_pinctrl_set_state_simple, + .request = rk3066_pinctrl_request, + .get_periph_id = rk3066_pinctrl_get_periph_id, +}; + +static int rk3066_pinctrl_probe(struct udevice *dev) +{ + struct rk3066_pinctrl_priv *priv = dev_get_priv(dev); + + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + if (IS_ERR(priv->grf)) + debug("%s: grf=%p\n", __func__, priv->grf); + return 0; +} + +static const struct udevice_id rk3066_pinctrl_ids[] = { + { .compatible = "rockchip,rk3066a-pinctrl" }, + { } +}; + +U_BOOT_DRIVER(rockchip_rk3066a_pinctrl) = { + .name = "rockchip_rk3066a_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = rk3066_pinctrl_ids, + .priv_auto_alloc_size = sizeof(struct rk3066_pinctrl_priv), + .ops = &rk3066_pinctrl_ops, +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + .bind = dm_scan_fdt_dev, +#endif + .probe = rk3066_pinctrl_probe, +};

Add support for system reset for rk3066 socs.

Signed-off-by: Paweł Jarosz paweljarosz3691@gmail.com Reviewed-by: Simon Glass sjg@chromium.org Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com --- Changes since v1: - updated to shifted masks

Changes since v2: - none

Changes since v3: - none

drivers/sysreset/Makefile | 1 + drivers/sysreset/sysreset_rk3066.c | 61 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+) create mode 100644 drivers/sysreset/sysreset_rk3066.c

diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile index a5200d3..7d4d0cd 100644 --- a/drivers/sysreset/Makefile +++ b/drivers/sysreset/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_ROCKCHIP_RK3036) += sysreset_rk3036.o endif +obj-$(CONFIG_ROCKCHIP_RK3066) += sysreset_rk3066.o obj-$(CONFIG_ROCKCHIP_RK3188) += sysreset_rk3188.o obj-$(CONFIG_ROCKCHIP_RK3288) += sysreset_rk3288.o obj-$(CONFIG_ROCKCHIP_RK3328) += sysreset_rk3328.o diff --git a/drivers/sysreset/sysreset_rk3066.c b/drivers/sysreset/sysreset_rk3066.c new file mode 100644 index 0000000..b5dcb9a --- /dev/null +++ b/drivers/sysreset/sysreset_rk3066.c @@ -0,0 +1,61 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <syscon.h> +#include <sysreset.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3066.h> +#include <asm/arch/grf_rk3066.h> +#include <asm/arch/hardware.h> +#include <linux/err.h> + +int rk3066_sysreset_request(struct udevice *dev, enum sysreset_t type) +{ + struct rk3066_cru *cru = rockchip_get_cru(); + struct rk3066_grf *grf; + + if (IS_ERR(cru)) + return PTR_ERR(cru); + + switch (type) { + case SYSRESET_WARM: + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + if (IS_ERR(grf)) + return -EPROTONOSUPPORT; + /* + * warm-reset keeps the remap value, + * so make sure it's disabled. + */ + rk_clrsetreg(&grf->soc_con0, + NOC_REMAP_MASK, 0 << NOC_REMAP_SHIFT); + + rk_clrreg(&cru->cru_mode_con, 0xffff); + writel(0xeca8, &cru->cru_glb_srst_snd_value); + break; + case SYSRESET_COLD: + rk_clrreg(&cru->cru_mode_con, 0xffff); + writel(0xfdb9, &cru->cru_glb_srst_fst_value); + break; + default: + return -EPROTONOSUPPORT; + } + + return -EINPROGRESS; +} + +static struct sysreset_ops rk3066_sysreset = { + .request = rk3066_sysreset_request, +}; + +U_BOOT_DRIVER(sysreset_rk3066) = { + .name = "rk3066_sysreset", + .id = UCLASS_SYSRESET, + .ops = &rk3066_sysreset, +};

Add clock driver for rk3066 platform.

Signed-off-by: Paweł Jarosz paweljarosz3691@gmail.com Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com --- Changes since v1: - updated to shifted masks - moved clk init to tpl

Changes since v2: - none

Changes since v3: - none

arch/arm/include/asm/arch-rockchip/cru_rk3066.h | 189 ++++++++ drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk_rk3066.c | 587 ++++++++++++++++++++++++ 3 files changed, 777 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3066.h create mode 100644 drivers/clk/rockchip/clk_rk3066.c

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3066.h b/arch/arm/include/asm/arch-rockchip/cru_rk3066.h new file mode 100644 index 0000000..c4a6951 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3066.h @@ -0,0 +1,189 @@ +/* + * (C) Copyright 2016 Heiko Stuebner heiko@sntech.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_CRU_RK3066_H +#define _ASM_ARCH_CRU_RK3066_H + +#define OSC_HZ (24 * 1000 * 1000) + +#define APLL_HZ (1416 * 1000000) +#define APLL_SAFE_HZ (600 * 1000000) +#define GPLL_HZ (594 * 1000000) +#define CPLL_HZ (384 * 1000000) + +/* The SRAM is clocked off aclk_cpu, so we want to max it out for boot speed */ +#define CPU_ACLK_HZ 297000000 +#define CPU_HCLK_HZ 148500000 +#define CPU_PCLK_HZ 74250000 +#define CPU_H2P_HZ 74250000 + +#define PERI_ACLK_HZ 148500000 +#define PERI_HCLK_HZ 148500000 +#define PERI_PCLK_HZ 74250000 + +/* Private data for the clock driver - used by rockchip_get_cru() */ +struct rk3066_clk_priv { + struct rk3066_grf *grf; + struct rk3066_cru *cru; + ulong rate; + bool has_bwadj; +}; + +struct rk3066_cru { + struct rk3066_pll { + u32 con0; + u32 con1; + u32 con2; + u32 con3; + } pll[4]; + u32 cru_mode_con; + u32 cru_clksel_con[35]; + u32 cru_clkgate_con[10]; + u32 reserved1[2]; + u32 cru_glb_srst_fst_value; + u32 cru_glb_srst_snd_value; + u32 reserved2[2]; + u32 cru_softrst_con[9]; + u32 cru_misc_con; + u32 reserved3[2]; + u32 cru_glb_cnt_th; +}; +check_member(rk3066_cru, cru_glb_cnt_th, 0x0140); + +/* CRU_CLKSEL0_CON */ +enum { + /* a9_core_div: core = core_src / (a9_core_div + 1) */ + A9_CORE_DIV_SHIFT = 9, + A9_CORE_DIV_MASK = 0x1f << A9_CORE_DIV_SHIFT, + CORE_PLL_SHIFT = 8, + CORE_PLL_MASK = 1 << CORE_PLL_SHIFT, + CORE_PLL_SELECT_APLL = 0, + CORE_PLL_SELECT_GPLL, + + /* core peri div: core:core_peri = 2:1, 4:1, 8:1 or 16:1 */ + CORE_PERI_DIV_SHIFT = 6, + CORE_PERI_DIV_MASK = 3 << CORE_PERI_DIV_SHIFT, + + /* aclk_cpu pll selection */ + CPU_ACLK_PLL_SHIFT = 5, + CPU_ACLK_PLL_MASK = 1 << CPU_ACLK_PLL_SHIFT, + CPU_ACLK_PLL_SELECT_APLL = 0, + CPU_ACLK_PLL_SELECT_GPLL, + + /* a9_cpu_div: aclk_cpu = cpu_src / (a9_cpu_div + 1) */ + A9_CPU_DIV_SHIFT = 0, + A9_CPU_DIV_MASK = 0x1f << A9_CPU_DIV_SHIFT, +}; + +/* CRU_CLKSEL1_CON */ +enum { + /* ahb2apb_pclk_div: hclk_cpu:pclk_cpu = 1:1, 2:1 or 4:1 */ + AHB2APB_DIV_SHIFT = 14, + AHB2APB_DIV_MASK = 3 << AHB2APB_DIV_SHIFT, + + /* cpu_pclk_div: aclk_cpu:pclk_cpu = 1:1, 2:1, 4:1 or 8:1 */ + CPU_PCLK_DIV_SHIFT = 12, + CPU_PCLK_DIV_MASK = 3 << CPU_PCLK_DIV_SHIFT, + + /* cpu_hclk_div: aclk_cpu:hclk_cpu = 1:1, 2:1 or 4:1 */ + CPU_HCLK_DIV_SHIFT = 8, + CPU_HCLK_DIV_MASK = 3 << CPU_HCLK_DIV_SHIFT, + + /* core_aclk_div: cire:aclk_core = 1:1, 2:1, 3:1, 4:1 or 8:1 */ + CORE_ACLK_DIV_SHIFT = 3, + CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT, +}; + +/* CRU_CLKSEL10_CON */ +enum { + PERI_SEL_PLL_SHIFT = 15, + PERI_SEL_PLL_MASK = 1 << PERI_SEL_PLL_SHIFT, + PERI_SEL_CPLL = 0, + PERI_SEL_GPLL, + + /* peri pclk div: aclk_bus:pclk_bus = 1:1, 2:1, 4:1 or 8:1 */ + PERI_PCLK_DIV_SHIFT = 12, + PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT, + + /* peripheral bus hclk div:aclk_bus: hclk_bus = 1:1, 2:1 or 4:1 */ + PERI_HCLK_DIV_SHIFT = 8, + PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT, + + /* peri aclk div: aclk_peri = periph_src / (peri_aclk_div + 1) */ + PERI_ACLK_DIV_SHIFT = 0, + PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, +}; +/* CRU_CLKSEL11_CON */ +enum { + MMC0_DIV_SHIFT = 0, + MMC0_DIV_MASK = 0x3f << MMC0_DIV_SHIFT, +}; + +/* CRU_CLKSEL12_CON */ +enum { + UART_PLL_SHIFT = 15, + UART_PLL_MASK = 1 << UART_PLL_SHIFT, + UART_PLL_SELECT_GENERAL = 0, + UART_PLL_SELECT_CODEC, + + EMMC_DIV_SHIFT = 8, + EMMC_DIV_MASK = 0x3f << EMMC_DIV_SHIFT, + + SDIO_DIV_SHIFT = 0, + SDIO_DIV_MASK = 0x3f << SDIO_DIV_SHIFT, +}; + +/* CRU_CLKSEL25_CON */ +enum { + SPI1_DIV_SHIFT = 8, + SPI1_DIV_MASK = 0x7f << SPI1_DIV_SHIFT, + + SPI0_DIV_SHIFT = 0, + SPI0_DIV_MASK = 0x7f << SPI0_DIV_SHIFT, +}; + +/* CRU_MODE_CON */ +enum { + GPLL_MODE_SHIFT = 12, + GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT, + GPLL_MODE_SLOW = 0, + GPLL_MODE_NORMAL, + GPLL_MODE_DEEP, + + CPLL_MODE_SHIFT = 8, + CPLL_MODE_MASK = 3 << CPLL_MODE_SHIFT, + CPLL_MODE_SLOW = 0, + CPLL_MODE_NORMAL, + CPLL_MODE_DEEP, + + DPLL_MODE_SHIFT = 4, + DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT, + DPLL_MODE_SLOW = 0, + DPLL_MODE_NORMAL, + DPLL_MODE_DEEP, + + APLL_MODE_SHIFT = 0, + APLL_MODE_MASK = 3 << APLL_MODE_SHIFT, + APLL_MODE_SLOW = 0, + APLL_MODE_NORMAL, + APLL_MODE_DEEP, +}; + +/* CRU_APLL_CON0 */ +enum { + CLKR_SHIFT = 8, + CLKR_MASK = 0x3f << CLKR_SHIFT, + + CLKOD_SHIFT = 0, + CLKOD_MASK = 0x3f << CLKOD_SHIFT, +}; + +/* CRU_APLL_CON1 */ +enum { + CLKF_SHIFT = 0, + CLKF_MASK = 0x1fff << CLKF_SHIFT, +}; + +#endif diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index c50aff2..167b08e 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -5,6 +5,7 @@ #

obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o +obj-$(CONFIG_ROCKCHIP_RK3066) += clk_rk3066.o obj-$(CONFIG_ROCKCHIP_RK3188) += clk_rk3188.o obj-$(CONFIG_ROCKCHIP_RK322X) += clk_rk322x.o obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o diff --git a/drivers/clk/rockchip/clk_rk3066.c b/drivers/clk/rockchip/clk_rk3066.c new file mode 100644 index 0000000..bcf65e0 --- /dev/null +++ b/drivers/clk/rockchip/clk_rk3066.c @@ -0,0 +1,587 @@ +/* + * (C) Copyright 2015 Google, Inc + * (C) Copyright 2016 Heiko Stuebner heiko@sntech.de + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <dt-structs.h> +#include <errno.h> +#include <mapmem.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3066.h> +#include <asm/arch/grf_rk3066.h> +#include <asm/arch/hardware.h> +#include <dt-bindings/clock/rk3066a-cru.h> +#include <dm/device-internal.h> +#include <dm/lists.h> +#include <dm/uclass-internal.h> +#include <linux/log2.h> + +DECLARE_GLOBAL_DATA_PTR; + +enum rk3066_clk_type { + RK3066_CRU, + RK3066A_CRU, +}; + +struct rk3066_clk_plat { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_rockchip_rk3066a_cru dtd; +#endif +}; + +struct pll_div { + u32 nr; + u32 nf; + u32 no; +}; + +enum { + VCO_MAX_HZ = 1416U * 1000000, + VCO_MIN_HZ = 300 * 1000000, + OUTPUT_MAX_HZ = 1416U * 1000000, + OUTPUT_MIN_HZ = 30 * 1000000, + FREF_MAX_HZ = 1416U * 1000000, + FREF_MIN_HZ = 30 * 1000, +}; + +enum { + /* PLL CON0 */ + PLL_OD_MASK = 0x0f, + + /* PLL CON1 */ + PLL_NF_MASK = 0x1fff, + + /* PLL CON2 */ + PLL_BWADJ_MASK = 0x0fff, + + /* PLL CON3 */ + PLL_RESET_SHIFT = 5, + + /* GRF_SOC_STATUS0 */ + SOCSTS_DPLL_LOCK = 1 << 4, + SOCSTS_APLL_LOCK = 1 << 5, + SOCSTS_CPLL_LOCK = 1 << 6, + SOCSTS_GPLL_LOCK = 1 << 7, +}; + +#define RATE_TO_DIV(input_rate, output_rate) \ + ((input_rate) / (output_rate) - 1); + +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) + +#define PLL_DIVISORS(hz, _nr, _no) {\ + .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\ + _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\ + (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\ + "divisors on line " __stringify(__LINE__)); + +/* Keep divisors as low as possible to reduce jitter and power usage */ +#ifdef CONFIG_TPL_BUILD +static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2); +static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2); +#endif + +static int rkclk_set_pll(struct rk3066_cru *cru, enum rk_clk_id clk_id, + const struct pll_div *div, bool has_bwadj) +{ + int pll_id = rk_pll_id(clk_id); + struct rk3066_pll *pll = &cru->pll[pll_id]; + /* All PLLs have same VCO and output frequency range restrictions. */ + uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; + uint output_hz = vco_hz / div->no; + + debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n", + (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz); + assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && + output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ && + (div->no == 1 || !(div->no % 2))); + + /* enter reset */ + rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT); + + rk_clrsetreg(&pll->con0, + CLKR_MASK | PLL_OD_MASK, + ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1)); + rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1); + + if (has_bwadj) + rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1); + + udelay(10); + + /* return from reset */ + rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT); + + return 0; +} + +static int rkclk_configure_ddr(struct rk3066_cru *cru, struct rk3066_grf *grf, + unsigned int hz, bool has_bwadj) +{ + static const struct pll_div dpll_cfg[] = { + {.nf = 25, .nr = 2, .no = 1}, + {.nf = 400, .nr = 9, .no = 2}, + {.nf = 500, .nr = 9, .no = 2}, + {.nf = 100, .nr = 3, .no = 1}, + }; + int cfg; + + switch (hz) { + case 300000000: + cfg = 0; + break; + case 533000000: /* actually 533.3P MHz */ + cfg = 1; + break; + case 666000000: /* actually 666.6P MHz */ + cfg = 2; + break; + case 800000000: + cfg = 3; + break; + default: + debug("Unsupported SDRAM frequency"); + return -EINVAL; + } + + /* pll enter slow-mode */ + rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, + DPLL_MODE_SLOW << DPLL_MODE_SHIFT); + + rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg], has_bwadj); + + /* wait for pll lock */ + while (!(readl(&grf->soc_status0) & SOCSTS_DPLL_LOCK)) + udelay(1); + + /* PLL enter normal-mode */ + rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, + DPLL_MODE_NORMAL << DPLL_MODE_SHIFT); + + return 0; +} + +static int rkclk_configure_cpu(struct rk3066_cru *cru, struct rk3066_grf *grf, + unsigned int hz, bool has_bwadj) +{ + static const struct pll_div apll_cfg[] = { + {.nf = 50, .nr = 1, .no = 2}, + {.nf = 59, .nr = 1, .no = 1}, + }; + int div_core_peri, div_aclk_core, cfg; + + /* + * We support two possible frequencies, the safe 600MHz + * which will work with default pmic settings and will + * be set to get away from the 24MHz default and + * the maximum of 1.416Ghz, which boards can set if they + * were able to get pmic support for it. + */ + switch (hz) { + case APLL_SAFE_HZ: + cfg = 0; + div_core_peri = 1; + div_aclk_core = 3; + break; + case APLL_HZ: + cfg = 1; + div_core_peri = 2; + div_aclk_core = 3; + break; + default: + debug("Unsupported ARMCLK frequency"); + return -EINVAL; + } + + /* pll enter slow-mode */ + rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, + APLL_MODE_SLOW << APLL_MODE_SHIFT); + + rkclk_set_pll(cru, CLK_ARM, &apll_cfg[cfg], has_bwadj); + + /* waiting for pll lock */ + while (!(readl(&grf->soc_status0) & SOCSTS_APLL_LOCK)) + udelay(1); + + /* Set divider for peripherals attached to the cpu core. */ + rk_clrsetreg(&cru->cru_clksel_con[0], + CORE_PERI_DIV_MASK, + div_core_peri << CORE_PERI_DIV_SHIFT); + + /* set up dependent divisor for aclk_core */ + rk_clrsetreg(&cru->cru_clksel_con[1], + CORE_ACLK_DIV_MASK, + div_aclk_core << CORE_ACLK_DIV_SHIFT); + + /* PLL enter normal-mode */ + rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK, + APLL_MODE_NORMAL << APLL_MODE_SHIFT); + + return hz; +} + +/* Get pll rate by id */ +static uint32_t rkclk_pll_get_rate(struct rk3066_cru *cru, + enum rk_clk_id clk_id) +{ + uint32_t nr, no, nf; + uint32_t con; + int pll_id = rk_pll_id(clk_id); + struct rk3066_pll *pll = &cru->pll[pll_id]; + static u8 clk_shift[CLK_COUNT] = { + 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT, + GPLL_MODE_SHIFT + }; + uint shift; + + con = readl(&cru->cru_mode_con); + shift = clk_shift[clk_id]; + switch ((con >> shift) & APLL_MODE_MASK >> APLL_MODE_SHIFT) { + case APLL_MODE_SLOW: + return OSC_HZ; + case APLL_MODE_NORMAL: + /* normal mode */ + con = readl(&pll->con0); + no = ((con >> CLKOD_SHIFT) & (CLKOD_MASK >> CLKOD_SHIFT)) + 1; + nr = ((con >> CLKR_SHIFT) & (CLKR_MASK >> CLKR_SHIFT)) + 1; + con = readl(&pll->con1); + nf = ((con >> CLKF_SHIFT) & (CLKF_MASK >> CLKF_SHIFT)) + 1; + + return (24 * nf / (nr * no)) * 1000000; + case APLL_MODE_DEEP: + default: + return 32768; + } +} + +static ulong rockchip_mmc_get_clk(struct rk3066_cru *cru, uint gclk_rate, + int periph) +{ + uint div; + u32 con; + + switch (periph) { + case HCLK_EMMC: + con = readl(&cru->cru_clksel_con[12]); + div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK >> EMMC_DIV_SHIFT; + break; + case HCLK_SDMMC: + con = readl(&cru->cru_clksel_con[11]); + div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK >> MMC0_DIV_SHIFT; + break; + case HCLK_SDIO: + con = readl(&cru->cru_clksel_con[12]); + div = (con >> SDIO_DIV_SHIFT) & SDIO_DIV_MASK >> SDIO_DIV_SHIFT; + break; + default: + return -EINVAL; + } + + return DIV_TO_RATE(gclk_rate, div); +} + +static ulong rockchip_mmc_set_clk(struct rk3066_cru *cru, uint gclk_rate, + int periph, uint freq) +{ + int src_clk_div; + + debug("%s: gclk_rate=%u\n", __func__, gclk_rate); + src_clk_div = RATE_TO_DIV(gclk_rate, freq); + if (src_clk_div > 0x3f) + src_clk_div = 0x3f; + + switch (periph) { + case HCLK_EMMC: + rk_clrsetreg(&cru->cru_clksel_con[12], + EMMC_DIV_MASK, + src_clk_div << EMMC_DIV_SHIFT); + break; + case HCLK_SDMMC: + rk_clrsetreg(&cru->cru_clksel_con[11], + MMC0_DIV_MASK, + src_clk_div << MMC0_DIV_SHIFT); + break; + case HCLK_SDIO: + rk_clrsetreg(&cru->cru_clksel_con[12], + SDIO_DIV_MASK, + src_clk_div << SDIO_DIV_SHIFT); + break; + default: + return -EINVAL; + } + + return rockchip_mmc_get_clk(cru, gclk_rate, periph); +} + +static ulong rockchip_spi_get_clk(struct rk3066_cru *cru, uint gclk_rate, + int periph) +{ + uint div; + u32 con; + + switch (periph) { + case SCLK_SPI0: + con = readl(&cru->cru_clksel_con[25]); + div = (con >> SPI0_DIV_SHIFT) & SPI0_DIV_MASK >> SPI0_DIV_SHIFT; + break; + case SCLK_SPI1: + con = readl(&cru->cru_clksel_con[25]); + div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK >> SPI1_DIV_SHIFT; + break; + default: + return -EINVAL; + } + + return DIV_TO_RATE(gclk_rate, div); +} + +static ulong rockchip_spi_set_clk(struct rk3066_cru *cru, uint gclk_rate, + int periph, uint freq) +{ + int src_clk_div = RATE_TO_DIV(gclk_rate, freq); + + switch (periph) { + case SCLK_SPI0: + assert(src_clk_div <= SPI0_DIV_MASK >> SPI0_DIV_SHIFT); + rk_clrsetreg(&cru->cru_clksel_con[25], + SPI0_DIV_MASK, + src_clk_div << SPI0_DIV_SHIFT); + break; + case SCLK_SPI1: + assert(src_clk_div <= SPI1_DIV_MASK >> SPI1_DIV_SHIFT); + rk_clrsetreg(&cru->cru_clksel_con[25], + SPI1_DIV_MASK, + src_clk_div << SPI1_DIV_SHIFT); + break; + default: + return -EINVAL; + } + + return rockchip_spi_get_clk(cru, gclk_rate, periph); +} +#ifdef CONFIG_TPL_BUILD +static void rkclk_init(struct rk3066_cru *cru, struct rk3066_grf *grf, + bool has_bwadj) +{ + u32 aclk_div, hclk_div, pclk_div, h2p_div; + + /* pll enter slow-mode */ + rk_clrsetreg(&cru->cru_mode_con, + GPLL_MODE_MASK | + CPLL_MODE_MASK, + GPLL_MODE_SLOW << GPLL_MODE_SHIFT | + CPLL_MODE_SLOW << CPLL_MODE_SHIFT); + + /* init pll */ + rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg, has_bwadj); + rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg, has_bwadj); + + /* waiting for pll lock */ + while ((readl(&grf->soc_status0) & + (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) != + (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) + udelay(1); + + /* + * cpu clock pll source selection and + * reparent aclk_cpu_pre from apll to gpll + * set up dependent divisors for PCLK/HCLK and ACLK clocks. + */ + aclk_div = RATE_TO_DIV(GPLL_HZ, CPU_ACLK_HZ); + assert((aclk_div + 1) * CPU_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); + + rk_clrsetreg(&cru->cru_clksel_con[0], + CPU_ACLK_PLL_MASK | + A9_CPU_DIV_MASK, + CPU_ACLK_PLL_SELECT_GPLL << CPU_ACLK_PLL_SHIFT | + aclk_div << A9_CPU_DIV_SHIFT); + + hclk_div = ilog2(CPU_ACLK_HZ / CPU_HCLK_HZ); + assert((1 << hclk_div) * CPU_HCLK_HZ == CPU_ACLK_HZ && hclk_div < 0x3); + pclk_div = ilog2(CPU_ACLK_HZ / CPU_PCLK_HZ); + assert((1 << pclk_div) * CPU_PCLK_HZ == CPU_ACLK_HZ && pclk_div < 0x4); + h2p_div = ilog2(CPU_HCLK_HZ / CPU_H2P_HZ); + assert((1 << h2p_div) * CPU_H2P_HZ == CPU_HCLK_HZ && pclk_div < 0x3); + + rk_clrsetreg(&cru->cru_clksel_con[1], + AHB2APB_DIV_MASK | + CPU_PCLK_DIV_MASK | + CPU_HCLK_DIV_MASK, + h2p_div << AHB2APB_DIV_SHIFT | + pclk_div << CPU_PCLK_DIV_SHIFT | + hclk_div << CPU_HCLK_DIV_SHIFT); + + /* + * peri clock pll source selection and + * set up dependent divisors for PCLK/HCLK and ACLK clocks. + */ + aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; + assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); + + hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); + assert((1 << hclk_div) * PERI_HCLK_HZ == + PERI_ACLK_HZ && (hclk_div < 0x4)); + + pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); + assert((1 << pclk_div) * PERI_PCLK_HZ == + PERI_ACLK_HZ && (pclk_div < 0x4)); + + rk_clrsetreg(&cru->cru_clksel_con[10], + PERI_PCLK_DIV_MASK | + PERI_HCLK_DIV_MASK | + PERI_ACLK_DIV_MASK, + PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT | + pclk_div << PERI_PCLK_DIV_SHIFT | + hclk_div << PERI_HCLK_DIV_SHIFT | + aclk_div << PERI_ACLK_DIV_SHIFT); + + /* PLL enter normal-mode */ + rk_clrsetreg(&cru->cru_mode_con, + GPLL_MODE_MASK | + CPLL_MODE_MASK, + GPLL_MODE_NORMAL << GPLL_MODE_SHIFT | + CPLL_MODE_NORMAL << CPLL_MODE_SHIFT); + + rockchip_mmc_set_clk(cru, PERI_HCLK_HZ, HCLK_SDMMC, 16000000); +} +#endif + +static ulong rk3066_clk_get_rate(struct clk *clk) +{ + struct rk3066_clk_priv *priv = dev_get_priv(clk->dev); + ulong new_rate, gclk_rate; + + gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); + switch (clk->id) { + case 1 ... 4: + new_rate = rkclk_pll_get_rate(priv->cru, clk->id); + break; + case HCLK_EMMC: + case HCLK_SDMMC: + case HCLK_SDIO: + new_rate = rockchip_mmc_get_clk(priv->cru, PERI_HCLK_HZ, + clk->id); + break; + case SCLK_SPI0: + case SCLK_SPI1: + new_rate = rockchip_spi_get_clk(priv->cru, PERI_PCLK_HZ, + clk->id); + break; + case PCLK_I2C0: + case PCLK_I2C1: + case PCLK_I2C2: + case PCLK_I2C3: + case PCLK_I2C4: + return gclk_rate; + default: + return -ENOENT; + } + + return new_rate; +} + +static ulong rk3066_clk_set_rate(struct clk *clk, ulong rate) +{ + struct rk3066_clk_priv *priv = dev_get_priv(clk->dev); + struct rk3066_cru *cru = priv->cru; + ulong new_rate; + + switch (clk->id) { + case PLL_APLL: + new_rate = rkclk_configure_cpu(priv->cru, priv->grf, rate, + priv->has_bwadj); + break; + case CLK_DDR: + new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate, + priv->has_bwadj); + break; + case HCLK_EMMC: + case HCLK_SDMMC: + case HCLK_SDIO: + new_rate = rockchip_mmc_set_clk(cru, PERI_HCLK_HZ, + clk->id, rate); + break; + case SCLK_SPI0: + case SCLK_SPI1: + new_rate = rockchip_spi_set_clk(cru, PERI_PCLK_HZ, + clk->id, rate); + break; + default: + return -ENOENT; + } + + return new_rate; +} + +static struct clk_ops rk3066_clk_ops = { + .get_rate = rk3066_clk_get_rate, + .set_rate = rk3066_clk_set_rate, +}; + +static int rk3066_clk_ofdata_to_platdata(struct udevice *dev) +{ +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct rk3066_clk_priv *priv = dev_get_priv(dev); + + priv->cru = (struct rk3066_cru *)devfdt_get_addr(dev); +#endif + + return 0; +} + +static int rk3066_clk_probe(struct udevice *dev) +{ + struct rk3066_clk_priv *priv = dev_get_priv(dev); + + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + if (IS_ERR(priv->grf)) + return PTR_ERR(priv->grf); + +#ifdef CONFIG_TPL_BUILD +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct rk3066_clk_plat *plat = dev_get_platdata(dev); + + priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); +#endif + + rkclk_init(priv->cru, priv->grf, 1); +#endif + + return 0; +} + +static int rk3066_clk_bind(struct udevice *dev) +{ + int ret; + + /* The reset driver does not have a device node, so bind it here */ + ret = device_bind_driver(gd->dm_root, "rk3066_sysreset", "reset", &dev); + if (ret) + debug("Warning: No rk3066 reset driver: ret=%d\n", ret); + + return 0; +} + +static const struct udevice_id rk3066_clk_ids[] = { + { .compatible = "rockchip,rk3066a-cru" }, + { } +}; + +U_BOOT_DRIVER(rockchip_rk3066a_cru) = { + .name = "rockchip_rk3066a_cru", + .id = UCLASS_CLK, + .of_match = rk3066_clk_ids, + .priv_auto_alloc_size = sizeof(struct rk3066_clk_priv), + .platdata_auto_alloc_size = sizeof(struct rk3066_clk_plat), + .ops = &rk3066_clk_ops, + .bind = rk3066_clk_bind, + .ofdata_to_platdata = rk3066_clk_ofdata_to_platdata, + .probe = rk3066_clk_probe, +};

rk3066 peripherials include usb, i2c, pwm, gpio, sdio, sdmmc, emmc, spi, watchdog and uart

Signed-off-by: Paweł Jarosz paweljarosz3691@gmail.com Reviewed-by: Simon Glass sjg@chromium.org Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com Reviewed-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com --- Changes since v1: - added nand dts node

Changes since v2: - none

Changes since v3: - none

arch/arm/dts/rk3066a.dtsi | 707 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 707 insertions(+) create mode 100644 arch/arm/dts/rk3066a.dtsi

diff --git a/arch/arm/dts/rk3066a.dtsi b/arch/arm/dts/rk3066a.dtsi new file mode 100644 index 0000000..92ee1c2 --- /dev/null +++ b/arch/arm/dts/rk3066a.dtsi @@ -0,0 +1,707 @@ +/* + * Copyright (c) 2013 MundoReader S.L. + * Author: Heiko Stuebner heiko@sntech.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/clock/rk3066a-cru.h> +#include "rk3xxx.dtsi" + +/ { + compatible = "rockchip,rk3066a"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "rockchip,rk3066-smp"; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x0>; + operating-points = < + /* kHz uV */ + 1416000 1300000 + 1200000 1175000 + 1008000 1125000 + 816000 1125000 + 600000 1100000 + 504000 1100000 + 312000 1075000 + >; + clock-latency = <40000>; + clocks = <&cru ARMCLK>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x1>; + }; + }; + + sram: sram@10080000 { + compatible = "mmio-sram"; + reg = <0x10080000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x10080000 0x10000>; + + smp-sram@0 { + compatible = "rockchip,rk3066-smp-sram"; + reg = <0x0 0x50>; + }; + }; + + i2s0: i2s@10118000 { + compatible = "rockchip,rk3066-i2s"; + reg = <0x10118000 0x2000>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_bus>; + dmas = <&dmac1_s 4>, <&dmac1_s 5>; + dma-names = "tx", "rx"; + clock-names = "i2s_hclk", "i2s_clk"; + clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; + rockchip,playback-channels = <8>; + rockchip,capture-channels = <2>; + status = "disabled"; + }; + + i2s1: i2s@1011a000 { + compatible = "rockchip,rk3066-i2s"; + reg = <0x1011a000 0x2000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_bus>; + dmas = <&dmac1_s 6>, <&dmac1_s 7>; + dma-names = "tx", "rx"; + clock-names = "i2s_hclk", "i2s_clk"; + clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>; + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + status = "disabled"; + }; + + i2s2: i2s@1011c000 { + compatible = "rockchip,rk3066-i2s"; + reg = <0x1011c000 0x2000>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s2_bus>; + dmas = <&dmac1_s 9>, <&dmac1_s 10>; + dma-names = "tx", "rx"; + clock-names = "i2s_hclk", "i2s_clk"; + clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>; + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + status = "disabled"; + }; + + nandc: nandc@10500000 { + compatible = "rockchip,nandc"; + reg = <0x10500000 0x2000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "hclk"; + clocks = <&cru HCLK_NANDC0>; + status = "disabled"; + }; + + cru: clock-controller@20000000 { + compatible = "rockchip,rk3066a-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + u-boot,dm-pre-reloc; + + #clock-cells = <1>; + #reset-cells = <1>; + assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>, + <&cru ACLK_CPU>, <&cru HCLK_CPU>, + <&cru PCLK_CPU>, <&cru ACLK_PERI>, + <&cru HCLK_PERI>, <&cru PCLK_PERI>; + assigned-clock-rates = <400000000>, <594000000>, + <300000000>, <150000000>, + <75000000>, <300000000>, + <150000000>, <75000000>; + }; + + timer@2000e000 { + compatible = "snps,dw-apb-timer-osc"; + reg = <0x2000e000 0x100>; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>; + clock-names = "timer", "pclk"; + }; + + efuse: efuse@20010000 { + compatible = "rockchip,rk3066a-efuse"; + reg = <0x20010000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru PCLK_EFUSE>; + clock-names = "pclk_efuse"; + + cpu_leakage: cpu_leakage@17 { + reg = <0x17 0x1>; + }; + }; + + timer@20038000 { + compatible = "snps,dw-apb-timer-osc"; + reg = <0x20038000 0x100>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>; + clock-names = "timer", "pclk"; + }; + + timer@2003a000 { + compatible = "snps,dw-apb-timer-osc"; + reg = <0x2003a000 0x100>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>; + clock-names = "timer", "pclk"; + }; + + tsadc: tsadc@20060000 { + compatible = "rockchip,rk3066-tsadc"; + reg = <0x20060000 0x100>; + clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "saradc", "apb_pclk"; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + #io-channel-cells = <1>; + resets = <&cru SRST_TSADC>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + usbphy: phy { + compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + usbphy0: usb-phy@17c { + #phy-cells = <0>; + reg = <0x17c>; + clocks = <&cru SCLK_OTGPHY0>; + clock-names = "phyclk"; + #clock-cells = <0>; + }; + + usbphy1: usb-phy@188 { + #phy-cells = <0>; + reg = <0x188>; + clocks = <&cru SCLK_OTGPHY1>; + clock-names = "phyclk"; + #clock-cells = <0>; + }; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3066a-pinctrl"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + u-boot,dm-pre-reloc; + + gpio0: gpio0@20034000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20034000 0x100>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO0>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1@2003c000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003c000 0x100>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO1>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio2@2003e000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2003e000 0x100>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO2>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio3@20080000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20080000 0x100>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO3>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio4@20084000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20084000 0x100>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO4>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio6@2000a000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2000a000 0x100>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO6>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_default: pcfg_pull_default { + bias-pull-pin-default; + }; + + pcfg_pull_none: pcfg_pull_none { + bias-disable; + }; + + emac { + emac_xfer: emac-xfer { + rockchip,pins = <RK_GPIO1 16 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */ + <RK_GPIO1 17 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */ + <RK_GPIO1 18 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */ + <RK_GPIO1 19 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */ + <RK_GPIO1 20 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */ + <RK_GPIO1 21 RK_FUNC_2 &pcfg_pull_none>, /* crs_dvalid */ + <RK_GPIO1 22 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */ + <RK_GPIO1 23 RK_FUNC_2 &pcfg_pull_none>; /* rxd0 */ + }; + + emac_mdio: emac-mdio { + rockchip,pins = <RK_GPIO1 24 RK_FUNC_2 &pcfg_pull_none>, /* mac_md */ + <RK_GPIO1 25 RK_FUNC_2 &pcfg_pull_none>; /* mac_mdclk */ + }; + }; + + emmc { + emmc_clk: emmc-clk { + rockchip,pins = <RK_GPIO3 31 RK_FUNC_2 &pcfg_pull_default>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = <RK_GPIO4 9 RK_FUNC_2 &pcfg_pull_default>; + }; + + emmc_rst: emmc-rst { + rockchip,pins = <RK_GPIO4 10 RK_FUNC_2 &pcfg_pull_default>; + }; + + /* + * The data pins are shared between nandc and emmc and + * not accessible through pinctrl. Also they should've + * been already set correctly by firmware, as + * flash/emmc is the boot-device. + */ + }; + + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>, + <RK_GPIO2 29 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = <RK_GPIO2 30 RK_FUNC_1 &pcfg_pull_none>, + <RK_GPIO2 31 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c2 { + i2c2_xfer: i2c2-xfer { + rockchip,pins = <RK_GPIO3 0 RK_FUNC_1 &pcfg_pull_none>, + <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { + rockchip,pins = <RK_GPIO3 2 RK_FUNC_2 &pcfg_pull_none>, + <RK_GPIO3 3 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + i2c4 { + i2c4_xfer: i2c4-xfer { + rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>, + <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwm0 { + pwm0_out: pwm0-out { + rockchip,pins = <RK_GPIO0 3 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_out: pwm1-out { + rockchip,pins = <RK_GPIO0 4 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwm2 { + pwm2_out: pwm2-out { + rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwm3 { + pwm3_out: pwm3-out { + rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + spi0 { + spi0_clk: spi0-clk { + rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_default>; + }; + spi0_cs0: spi0-cs0 { + rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_default>; + }; + spi0_tx: spi0-tx { + rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_default>; + }; + spi0_rx: spi0-rx { + rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_default>; + }; + spi0_cs1: spi0-cs1 { + rockchip,pins = <RK_GPIO4 15 RK_FUNC_1 &pcfg_pull_default>; + }; + }; + + spi1 { + spi1_clk: spi1-clk { + rockchip,pins = <RK_GPIO2 19 RK_FUNC_2 &pcfg_pull_default>; + }; + spi1_cs0: spi1-cs0 { + rockchip,pins = <RK_GPIO2 20 RK_FUNC_2 &pcfg_pull_default>; + }; + spi1_rx: spi1-rx { + rockchip,pins = <RK_GPIO2 22 RK_FUNC_2 &pcfg_pull_default>; + }; + spi1_tx: spi1-tx { + rockchip,pins = <RK_GPIO2 21 RK_FUNC_2 &pcfg_pull_default>; + }; + spi1_cs1: spi1-cs1 { + rockchip,pins = <RK_GPIO2 23 RK_FUNC_2 &pcfg_pull_default>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>; + }; + + uart1_cts: uart1-cts { + rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>; + }; + + uart1_rts: uart1-rts { + rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>; + }; + }; + + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>; + }; + /* no rts / cts for uart2 */ + }; + + uart3 { + uart3_xfer: uart3-xfer { + rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>; + }; + + uart3_cts: uart3-cts { + rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>; + }; + + uart3_rts: uart3-rts { + rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>; + }; + }; + + sd0 { + sd0_clk: sd0-clk { + rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>; + }; + + sd0_cmd: sd0-cmd { + rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>; + }; + + sd0_cd: sd0-cd { + rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>; + }; + + sd0_wp: sd0-wp { + rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>; + }; + + sd0_bus1: sd0-bus-width1 { + rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>; + }; + + sd0_bus4: sd0-bus-width4 { + rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>; + }; + }; + + sd1 { + sd1_clk: sd1-clk { + rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>; + }; + + sd1_cmd: sd1-cmd { + rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>; + }; + + sd1_cd: sd1-cd { + rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>; + }; + + sd1_wp: sd1-wp { + rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>; + }; + + sd1_bus1: sd1-bus-width1 { + rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>; + }; + + sd1_bus4: sd1-bus-width4 { + rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>; + }; + }; + + i2s0 { + i2s0_bus: i2s0-bus { + rockchip,pins = <RK_GPIO0 7 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO0 8 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO0 9 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO0 10 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO0 11 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO0 12 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO0 13 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO0 14 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO0 15 RK_FUNC_1 &pcfg_pull_default>; + }; + }; + + i2s1 { + i2s1_bus: i2s1-bus { + rockchip,pins = <RK_GPIO0 16 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO0 17 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO0 18 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO0 19 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO0 20 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO0 21 RK_FUNC_1 &pcfg_pull_default>; + }; + }; + + i2s2 { + i2s2_bus: i2s2-bus { + rockchip,pins = <RK_GPIO0 24 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO0 25 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO0 26 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO0 27 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_default>; + }; + }; + }; +}; + +&grf { + compatible = "rockchip,rk3066-grf", "syscon"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_xfer>; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_xfer>; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_xfer>; +}; + +&mmc0 { + clock-frequency = <50000000>; + dmas = <&dmac2 1>; + dma-names = "rx-tx"; + max-frequency = <50000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>; + u-boot,dm-pre-reloc; +}; + +&mmc1 { + dmas = <&dmac2 3>; + dma-names = "rx-tx"; + pinctrl-names = "default"; + pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>; +}; + +&emmc { + dmas = <&dmac2 4>; + dma-names = "rx-tx"; +}; + +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_out>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_out>; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_out>; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_out>; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; +}; + +&uart0 { + compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; + dmas = <&dmac1_s 0>, <&dmac1_s 1>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; +}; + +&uart1 { + compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; + dmas = <&dmac1_s 2>, <&dmac1_s 3>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; +}; + +&uart2 { + compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; + dmas = <&dmac2 6>, <&dmac2 7>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_xfer>; +}; + +&uart3 { + compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart"; + dmas = <&dmac2 8>, <&dmac2 9>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_xfer>; +}; + +&wdt { + compatible = "rockchip,rk3066-wdt", "snps,dw-wdt"; +}; + +&emac { + compatible = "rockchip,rk3066-emac"; +};

Add rockchip rk3066 sdram driver

Signed-off-by: Paweł Jarosz paweljarosz3691@gmail.com Acked-by: Simon Glass sjg@chromium.org Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com --- Changes since v1: - use common rockchip_sdram_size - moved sdram init from sdram_init.c

Changes since v2: - none

Changes since v3: - none

arch/arm/mach-rockchip/rk3066/Makefile | 1 + arch/arm/mach-rockchip/rk3066/sdram_rk3066.c | 943 +++++++++++++++++++++++++++ 2 files changed, 944 insertions(+) create mode 100644 arch/arm/mach-rockchip/rk3066/sdram_rk3066.c

diff --git a/arch/arm/mach-rockchip/rk3066/Makefile b/arch/arm/mach-rockchip/rk3066/Makefile index 61b7fd4..7663b6a 100644 --- a/arch/arm/mach-rockchip/rk3066/Makefile +++ b/arch/arm/mach-rockchip/rk3066/Makefile @@ -5,4 +5,5 @@ #

obj-y += clk_rk3066.o +obj-y += sdram_rk3066.o obj-y += syscon_rk3066.o diff --git a/arch/arm/mach-rockchip/rk3066/sdram_rk3066.c b/arch/arm/mach-rockchip/rk3066/sdram_rk3066.c new file mode 100644 index 0000000..e7475b8 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3066/sdram_rk3066.c @@ -0,0 +1,943 @@ +/* + * (C) Copyright 2015 Google, Inc + * Copyright 2014 Rockchip Inc. + * + * SPDX-License-Identifier: GPL-2.0 + * + * Adapted from the very similar rk3188 ddr init. + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dt-structs.h> +#include <errno.h> +#include <ram.h> +#include <regmap.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3066.h> +#include <asm/arch/ddr_rk3188.h> +#include <asm/arch/grf_rk3066.h> +#include <asm/arch/pmu_rk3188.h> +#include <asm/arch/sdram.h> +#include <asm/arch/sdram_common.h> +#include <linux/err.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct chan_info { + struct rk3288_ddr_pctl *pctl; + struct rk3288_ddr_publ *publ; + struct rk3188_msch *msch; +}; + +struct dram_info { + struct chan_info chan[1]; + struct ram_info info; + struct clk ddr_clk; + struct rk3066_cru *cru; + struct rk3066_grf *grf; + struct rk3066_sgrf *sgrf; + struct rk3188_pmu *pmu; +}; + +struct rk3066_sdram_params { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_rockchip_rk3066_dmc of_plat; +#endif + struct rk3288_sdram_channel ch[2]; + struct rk3288_sdram_pctl_timing pctl_timing; + struct rk3288_sdram_phy_timing phy_timing; + struct rk3288_base_params base; + int num_channels; + struct regmap *map; +}; + +const int ddrconf_table[] = { + /* + * [5:4] row(13+n) + * [1:0] col(9+n), assume bw=2 + * row col,bw + */ + 0, + (2 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT, + (1 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT, + (0 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT, + (2 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT, + (1 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT, + (0 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT, + (1 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT, + (0 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT, + 0, + 0, + 0, + 0, + 0, + 0, + 0, +}; + +#define TEST_PATTEN 0x5aa5f00f +#define DQS_GATE_TRAINING_ERROR_RANK0 (1 << 4) +#define DQS_GATE_TRAINING_ERROR_RANK1 (2 << 4) + +#ifdef CONFIG_TPL_BUILD +static void copy_to_reg(u32 *dest, const u32 *src, u32 n) +{ + int i; + + for (i = 0; i < n / sizeof(u32); i++) { + writel(*src, dest); + src++; + dest++; + } +} + +static void ddr_reset(struct rk3066_cru *cru, u32 ch, u32 ctl, u32 phy) +{ + u32 phy_ctl_srstn_shift = 13; + u32 ctl_psrstn_shift = 11; + u32 ctl_srstn_shift = 10; + u32 phy_psrstn_shift = 9; + u32 phy_srstn_shift = 8; + + rk_clrsetreg(&cru->cru_softrst_con[5], + 1 << phy_ctl_srstn_shift | 1 << ctl_psrstn_shift | + 1 << ctl_srstn_shift | 1 << phy_psrstn_shift | + 1 << phy_srstn_shift, + phy << phy_ctl_srstn_shift | ctl << ctl_psrstn_shift | + ctl << ctl_srstn_shift | phy << phy_psrstn_shift | + phy << phy_srstn_shift); +} + +static void ddr_phy_ctl_reset(struct rk3066_cru *cru, u32 ch, u32 n) +{ + u32 phy_ctl_srstn_shift = 13; + + rk_clrsetreg(&cru->cru_softrst_con[5], + 1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift); +} + +static void phy_pctrl_reset(struct rk3066_cru *cru, + struct rk3288_ddr_publ *publ, + int channel) +{ + int i; + + ddr_reset(cru, channel, 1, 1); + udelay(1); + clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); + for (i = 0; i < 4; i++) + clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); + + udelay(10); + setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); + for (i = 0; i < 4; i++) + setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); + + udelay(10); + ddr_reset(cru, channel, 1, 0); + udelay(10); + ddr_reset(cru, channel, 0, 0); + udelay(10); +} + +static void phy_dll_bypass_set(struct rk3288_ddr_publ *publ, + u32 freq) +{ + int i; + + if (freq <= 250000000) { + if (freq <= 150000000) + clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); + else + setbits_le32(&publ->dllgcr, SBIAS_BYPASS); + setbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS); + for (i = 0; i < 4; i++) + setbits_le32(&publ->datx8[i].dxdllcr, + DXDLLCR_DLLDIS); + + setbits_le32(&publ->pir, PIR_DLLBYP); + } else { + clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); + clrbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS); + for (i = 0; i < 4; i++) { + clrbits_le32(&publ->datx8[i].dxdllcr, + DXDLLCR_DLLDIS); + } + + clrbits_le32(&publ->pir, PIR_DLLBYP); + } +} + +static void dfi_cfg(struct rk3288_ddr_pctl *pctl, u32 dramtype) +{ + writel(DFI_INIT_START, &pctl->dfistcfg0); + writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN, + &pctl->dfistcfg1); + writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2); + writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN, + &pctl->dfilpcfg0); + + writel(2 << TCTRL_DELAY_TIME_SHIFT, &pctl->dfitctrldelay); + writel(1 << TPHY_WRDATA_TIME_SHIFT, &pctl->dfitphywrdata); + writel(0xf << TPHY_RDLAT_TIME_SHIFT, &pctl->dfitphyrdlat); + writel(2 << TDRAM_CLK_DIS_TIME_SHIFT, &pctl->dfitdramclkdis); + writel(2 << TDRAM_CLK_EN_TIME_SHIFT, &pctl->dfitdramclken); + writel(1, &pctl->dfitphyupdtype0); + + /* cs0 and cs1 write odt enable */ + writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), + &pctl->dfiodtcfg); + /* odt write length */ + writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1); + /* phyupd and ctrlupd disabled */ + writel(0, &pctl->dfiupdcfg); +} + +static void ddr_set_ddr3_mode(struct rk3066_grf *grf, uint channel, + bool ddr3_mode) +{ + uint mask, val; + + mask = MSCH4_MAINDDR3_MASK << MSCH4_MAINDDR3_SHIFT; + val = ddr3_mode << MSCH4_MAINDDR3_SHIFT; + rk_clrsetreg(&grf->soc_con2, mask, val); +} + +static void ddr_rank_2_row15en(struct rk3066_grf *grf, bool enable) +{ + uint mask, val; + + mask = RANK_TO_ROW15_EN_MASK << RANK_TO_ROW15_EN_SHIFT; + val = enable << RANK_TO_ROW15_EN_SHIFT; + rk_clrsetreg(&grf->soc_con2, mask, val); +} + +static void pctl_cfg(int channel, struct rk3288_ddr_pctl *pctl, + struct rk3066_sdram_params *sdram_params, + struct rk3066_grf *grf) +{ + copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u, + sizeof(sdram_params->pctl_timing)); + switch (sdram_params->base.dramtype) { + case DDR3: + if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) { + writel(sdram_params->pctl_timing.tcl - 3, + &pctl->dfitrddataen); + } else { + writel(sdram_params->pctl_timing.tcl - 2, + &pctl->dfitrddataen); + } + writel(sdram_params->pctl_timing.tcwl - 1, + &pctl->dfitphywrlat); + writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | DDR3_EN | + DDR2_DDR3_BL_8 | (6 - 4) << TFAW_SHIFT | PD_EXIT_SLOW | + 1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT, + &pctl->mcfg); + ddr_set_ddr3_mode(grf, channel, true); + break; + } + + setbits_le32(&pctl->scfg, 1); +} + +static void phy_cfg(const struct chan_info *chan, int channel, + struct rk3066_sdram_params *sdram_params) +{ + struct rk3288_ddr_publ *publ = chan->publ; + struct rk3188_msch *msch = chan->msch; + uint ddr_freq_mhz = sdram_params->base.ddr_freq / 1000000; + u32 dinit2; + int i; + + dinit2 = DIV_ROUND_UP(ddr_freq_mhz * 200000, 1000); + /* DDR PHY Timing */ + copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0, + sizeof(sdram_params->phy_timing)); + writel(sdram_params->base.noc_timing, &msch->ddrtiming); + writel(0x3f, &msch->readlatency); + writel(DIV_ROUND_UP(ddr_freq_mhz * 5120, 1000) << PRT_DLLLOCK_SHIFT | + DIV_ROUND_UP(ddr_freq_mhz * 50, 1000) << PRT_DLLSRST_SHIFT | + 8 << PRT_ITMSRST_SHIFT, &publ->ptr[0]); + writel(DIV_ROUND_UP(ddr_freq_mhz * 500000, 1000) << PRT_DINIT0_SHIFT | + DIV_ROUND_UP(ddr_freq_mhz * 400, 1000) << PRT_DINIT1_SHIFT, + &publ->ptr[1]); + writel(min(dinit2, 0x1ffffU) << PRT_DINIT2_SHIFT | + DIV_ROUND_UP(ddr_freq_mhz * 1000, 1000) << PRT_DINIT3_SHIFT, + &publ->ptr[2]); + + switch (sdram_params->base.dramtype) { + case DDR3: + clrbits_le32(&publ->pgcr, 0x1f); + clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT, + DDRMD_DDR3 << DDRMD_SHIFT); + break; + } + if (sdram_params->base.odt) { + /*dynamic RTT enable */ + for (i = 0; i < 4; i++) + setbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT); + } else { + /*dynamic RTT disable */ + for (i = 0; i < 4; i++) + clrbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT); + } +} + +static void phy_init(struct rk3288_ddr_publ *publ) +{ + setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST + | PIR_DLLLOCK | PIR_ZCAL | PIR_ITMSRST | PIR_CLRSR); + udelay(1); + while ((readl(&publ->pgsr) & + (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) != + (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) + ; +} + +static void send_command(struct rk3288_ddr_pctl *pctl, u32 rank, + u32 cmd, u32 arg) +{ + writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); + udelay(1); + while (readl(&pctl->mcmd) & START_CMD) + ; +} + +static inline void send_command_op(struct rk3288_ddr_pctl *pctl, + u32 rank, u32 cmd, u32 ma, u32 op) +{ + send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT | + (op & LPDDR2_OP_MASK) << LPDDR2_OP_SHIFT); +} + +static void memory_init(struct rk3288_ddr_publ *publ, + u32 dramtype) +{ + setbits_le32(&publ->pir, + (PIR_INIT | PIR_DRAMINIT | PIR_LOCKBYP + | PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC + | (dramtype == DDR3 ? PIR_DRAMRST : 0))); + udelay(1); + while ((readl(&publ->pgsr) & (PGSR_IDONE | PGSR_DLDONE)) + != (PGSR_IDONE | PGSR_DLDONE)) + ; +} + +static void move_to_config_state(struct rk3288_ddr_publ *publ, + struct rk3288_ddr_pctl *pctl) +{ + unsigned int state; + + while (1) { + state = readl(&pctl->stat) & PCTL_STAT_MSK; + + switch (state) { + case LOW_POWER: + writel(WAKEUP_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) + != ACCESS) + ; + /* wait DLL lock */ + while ((readl(&publ->pgsr) & PGSR_DLDONE) + != PGSR_DLDONE) + ; + /* + * if at low power state,need wakeup first, + * and then enter the config, so + * fallthrough + */ + case ACCESS: + /* fallthrough */ + case INIT_MEM: + writel(CFG_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) + ; + break; + case CONFIG: + return; + default: + break; + } + } +} + +static void set_bandwidth_ratio(const struct chan_info *chan, int channel, + u32 n, struct rk3066_grf *grf) +{ + struct rk3288_ddr_pctl *pctl = chan->pctl; + struct rk3288_ddr_publ *publ = chan->publ; + struct rk3188_msch *msch = chan->msch; + + if (n == 1) { + setbits_le32(&pctl->ppcfg, 1); + setbits_le32(&msch->ddrtiming, 1 << 31); + /* Data Byte disable*/ + clrbits_le32(&publ->datx8[2].dxgcr, 1); + clrbits_le32(&publ->datx8[3].dxgcr, 1); + /* disable DLL */ + setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS); + setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS); + } else { + clrbits_le32(&pctl->ppcfg, 1); + clrbits_le32(&msch->ddrtiming, 1 << 31); + /* Data Byte enable*/ + setbits_le32(&publ->datx8[2].dxgcr, 1); + setbits_le32(&publ->datx8[3].dxgcr, 1); + + /* enable DLL */ + clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS); + clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS); + /* reset DLL */ + clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST); + clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST); + udelay(10); + setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST); + setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST); + } + setbits_le32(&pctl->dfistcfg0, 1 << 2); +} + +static int data_training(const struct chan_info *chan, int channel, + struct rk3066_sdram_params *sdram_params) +{ + unsigned int j; + int ret = 0; + u32 rank; + int i; + u32 step[2] = { PIR_QSTRN, PIR_RVTRN }; + struct rk3288_ddr_publ *publ = chan->publ; + struct rk3288_ddr_pctl *pctl = chan->pctl; + + /* disable auto refresh */ + writel(0, &pctl->trefi); + + if (sdram_params->base.dramtype != LPDDR3) + setbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT); + rank = sdram_params->ch[channel].rank | 1; + for (j = 0; j < ARRAY_SIZE(step); j++) { + /* + * trigger QSTRN and RVTRN + * clear DTDONE status + */ + setbits_le32(&publ->pir, PIR_CLRSR); + + /* trigger DTT */ + setbits_le32(&publ->pir, + PIR_INIT | step[j] | PIR_LOCKBYP | PIR_ZCALBYP | + PIR_CLRSR); + udelay(1); + /* wait echo byte DTDONE */ + while ((readl(&publ->datx8[0].dxgsr[0]) & rank) + != rank) + ; + while ((readl(&publ->datx8[1].dxgsr[0]) & rank) + != rank) + ; + if (!(readl(&pctl->ppcfg) & 1)) { + while ((readl(&publ->datx8[2].dxgsr[0]) + & rank) != rank) + ; + while ((readl(&publ->datx8[3].dxgsr[0]) + & rank) != rank) + ; + } + if (readl(&publ->pgsr) & + (PGSR_DTERR | PGSR_RVERR | PGSR_RVEIRR)) { + ret = -1; + break; + } + } + /* send some auto refresh to complement the lost while DTT */ + for (i = 0; i < (rank > 1 ? 8 : 4); i++) + send_command(pctl, rank, REF_CMD, 0); + + if (sdram_params->base.dramtype != LPDDR3) + clrbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT); + + /* resume auto refresh */ + writel(sdram_params->pctl_timing.trefi, &pctl->trefi); + + return ret; +} + +static void move_to_access_state(const struct chan_info *chan) +{ + struct rk3288_ddr_publ *publ = chan->publ; + struct rk3288_ddr_pctl *pctl = chan->pctl; + unsigned int state; + + while (1) { + state = readl(&pctl->stat) & PCTL_STAT_MSK; + + switch (state) { + case LOW_POWER: + if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) & + LP_TRIG_MASK) == 1) + return; + + writel(WAKEUP_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS) + ; + /* wait DLL lock */ + while ((readl(&publ->pgsr) & PGSR_DLDONE) + != PGSR_DLDONE) + ; + break; + case INIT_MEM: + writel(CFG_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) + ; + /* fallthrough */ + case CONFIG: + writel(GO_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG) + ; + break; + case ACCESS: + return; + default: + break; + } + } +} + +static void dram_cfg_rbc(const struct chan_info *chan, u32 chnum, + struct rk3066_sdram_params *sdram_params) +{ + struct rk3288_ddr_publ *publ = chan->publ; + + if (sdram_params->ch[chnum].bk == 3) + clrsetbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT, + 1 << PDQ_SHIFT); + else + clrbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT); + + writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf); +} + +static void dram_all_config(const struct dram_info *dram, + struct rk3066_sdram_params *sdram_params) +{ + unsigned int chan; + u32 sys_reg = 0; + + sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT; + sys_reg |= (sdram_params->num_channels - 1) << SYS_REG_NUM_CH_SHIFT; + for (chan = 0; chan < sdram_params->num_channels; chan++) { + const struct rk3288_sdram_channel *info = + &sdram_params->ch[chan]; + + sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan); + sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan); + sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan); + sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan); + sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan); + sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan); + sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan); + sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan); + sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan); + + dram_cfg_rbc(&dram->chan[chan], chan, sdram_params); + } + if (sdram_params->ch[0].rank == 2) + ddr_rank_2_row15en(dram->grf, 0); + else + ddr_rank_2_row15en(dram->grf, 1); + + writel(sys_reg, &dram->pmu->sys_reg[2]); +} + +static int sdram_rank_bw_detect(struct dram_info *dram, int channel, + struct rk3066_sdram_params *sdram_params) +{ + int reg; + int need_trainig = 0; + const struct chan_info *chan = &dram->chan[channel]; + struct rk3288_ddr_publ *publ = chan->publ; + + ddr_rank_2_row15en(dram->grf, 0); + + if (data_training(chan, channel, sdram_params) < 0) { + debug("first data training fail!\n"); + reg = readl(&publ->datx8[0].dxgsr[0]); + /* Check the result for rank 0 */ + if ((channel == 0) && (reg & DQS_GATE_TRAINING_ERROR_RANK0)) { + debug("data training fail!\n"); + return -EIO; + } + + /* Check the result for rank 1 */ + if (reg & DQS_GATE_TRAINING_ERROR_RANK1) { + sdram_params->ch[channel].rank = 1; + clrsetbits_le32(&publ->pgcr, 0xF << 18, + sdram_params->ch[channel].rank << 18); + need_trainig = 1; + } + reg = readl(&publ->datx8[2].dxgsr[0]); + if (reg & (1 << 4)) { + sdram_params->ch[channel].bw = 1; + set_bandwidth_ratio(chan, channel, + sdram_params->ch[channel].bw, + dram->grf); + need_trainig = 1; + } + } + /* Assume the Die bit width are the same with the chip bit width */ + sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw; + + if (need_trainig && + (data_training(chan, channel, sdram_params) < 0)) { + if (sdram_params->base.dramtype == LPDDR3) { + ddr_phy_ctl_reset(dram->cru, channel, 1); + udelay(10); + ddr_phy_ctl_reset(dram->cru, channel, 0); + udelay(10); + } + debug("2nd data training failed!"); + return -EIO; + } + + return 0; +} + +/* + * Detect ram columns and rows. + * @dram: dram info struct + * @channel: channel number to handle + * @sdram_params: sdram parameters, function will fill in col and row values + * + * Returns 0 or negative on error. + */ +static int sdram_col_row_detect(struct dram_info *dram, int channel, + struct rk3066_sdram_params *sdram_params) +{ + int row, col; + unsigned int addr; + const struct chan_info *chan = &dram->chan[channel]; + struct rk3288_ddr_pctl *pctl = chan->pctl; + struct rk3288_ddr_publ *publ = chan->publ; + int ret = 0; + + /* Detect col */ + for (col = 11; col >= 9; col--) { + writel(0, CONFIG_SYS_SDRAM_BASE); + addr = CONFIG_SYS_SDRAM_BASE + + (1 << (col + sdram_params->ch[channel].bw - 1)); + writel(TEST_PATTEN, addr); + if ((readl(addr) == TEST_PATTEN) && + (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + break; + } + if (col == 8) { + debug("Col detect error\n"); + ret = -EINVAL; + goto out; + } else { + sdram_params->ch[channel].col = col; + } + + ddr_rank_2_row15en(dram->grf, 1); + move_to_config_state(publ, pctl); + writel(1, &chan->msch->ddrconf); + move_to_access_state(chan); + /* Detect row, max 15,min13 in rk3066*/ + for (row = 16; row >= 13; row--) { + writel(0, CONFIG_SYS_SDRAM_BASE); + addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); + writel(TEST_PATTEN, addr); + if ((readl(addr) == TEST_PATTEN) && + (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + break; + } + if (row == 12) { + debug("Row detect error\n"); + ret = -EINVAL; + } else { + sdram_params->ch[channel].cs1_row = row; + sdram_params->ch[channel].row_3_4 = 0; + debug("chn %d col %d, row %d\n", channel, col, row); + sdram_params->ch[channel].cs0_row = row; + } + +out: + return ret; +} + +static int sdram_get_niu_config(struct rk3066_sdram_params *sdram_params) +{ + int i, tmp, size, ret = 0; + + tmp = sdram_params->ch[0].col - 9; + tmp -= (sdram_params->ch[0].bw == 2) ? 0 : 1; + tmp |= ((sdram_params->ch[0].cs0_row - 13) << 4); + size = sizeof(ddrconf_table)/sizeof(ddrconf_table[0]); + for (i = 0; i < size; i++) + if (tmp == ddrconf_table[i]) + break; + if (i >= size) { + debug("niu config not found\n"); + ret = -EINVAL; + } else { + debug("niu config %d\n", i); + sdram_params->base.ddrconfig = i; + } + + return ret; +} + +static int sdram_init(struct dram_info *dram, + struct rk3066_sdram_params *sdram_params) +{ + int channel; + int zqcr; + int ret; + + if ((sdram_params->base.dramtype == DDR3 && + sdram_params->base.ddr_freq > 800000000)) { + debug("SDRAM frequency is too high!"); + return -E2BIG; + } + + ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq); + if (ret) { + debug("Could not set DDR clock\n"); + return ret; + } + + for (channel = 0; channel < 1; channel++) { + const struct chan_info *chan = &dram->chan[channel]; + struct rk3288_ddr_pctl *pctl = chan->pctl; + struct rk3288_ddr_publ *publ = chan->publ; + + phy_pctrl_reset(dram->cru, publ, channel); + phy_dll_bypass_set(publ, sdram_params->base.ddr_freq); + + dfi_cfg(pctl, sdram_params->base.dramtype); + + pctl_cfg(channel, pctl, sdram_params, dram->grf); + + phy_cfg(chan, channel, sdram_params); + + phy_init(publ); + + writel(POWER_UP_START, &pctl->powctl); + while (!(readl(&pctl->powstat) & POWER_UP_DONE)) + ; + + memory_init(publ, sdram_params->base.dramtype); + move_to_config_state(publ, pctl); + + /* Using 32bit bus width for detect */ + sdram_params->ch[channel].bw = 2; + set_bandwidth_ratio(chan, channel, + sdram_params->ch[channel].bw, dram->grf); + /* + * set cs, using n=3 for detect + * CS0, n=1 + * CS1, n=2 + * CS0 & CS1, n = 3 + */ + sdram_params->ch[channel].rank = 2, + clrsetbits_le32(&publ->pgcr, 0xF << 18, + (sdram_params->ch[channel].rank | 1) << 18); + + /* DS=40ohm,ODT=155ohm */ + zqcr = 1 << ZDEN_SHIFT | 2 << PU_ONDIE_SHIFT | + 2 << PD_ONDIE_SHIFT | 0x19 << PU_OUTPUT_SHIFT | + 0x19 << PD_OUTPUT_SHIFT; + writel(zqcr, &publ->zq1cr[0]); + writel(zqcr, &publ->zq0cr[0]); + + /* Detect the rank and bit-width with data-training */ + writel(1, &chan->msch->ddrconf); + sdram_rank_bw_detect(dram, channel, sdram_params); + + if (sdram_params->base.dramtype == LPDDR3) { + u32 i; + writel(0, &pctl->mrrcfg0); + for (i = 0; i < 17; i++) + send_command_op(pctl, 1, MRR_CMD, i, 0); + } + writel(4, &chan->msch->ddrconf); + move_to_access_state(chan); + /* DDR3 and LPDDR3 are always 8 bank, no need detect */ + sdram_params->ch[channel].bk = 3; + /* Detect Col and Row number*/ + ret = sdram_col_row_detect(dram, channel, sdram_params); + if (ret) + goto error; + } + /* Find NIU DDR configuration */ + ret = sdram_get_niu_config(sdram_params); + if (ret) + goto error; + + dram_all_config(dram, sdram_params); + debug("%s done\n", __func__); + + return 0; +error: + debug("DRAM init failed!\n"); + hang(); +} +#endif /* CONFIG_TPL_BUILD */ + +#ifdef CONFIG_TPL_BUILD +static int setup_sdram(struct udevice *dev) +{ + struct dram_info *priv = dev_get_priv(dev); + struct rk3066_sdram_params *params = dev_get_platdata(dev); + + return sdram_init(priv, params); +} + +static int rk3066_dmc_ofdata_to_platdata(struct udevice *dev) +{ +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct rk3066_sdram_params *params = dev_get_platdata(dev); + const void *blob = gd->fdt_blob; + int node = dev_of_offset(dev); + int ret; + + /* rk3066 supports only one-channel */ + params->num_channels = 1; + ret = fdtdec_get_int_array(blob, node, "rockchip,pctl-timing", + (u32 *)&params->pctl_timing, + sizeof(params->pctl_timing) / sizeof(u32)); + if (ret) { + debug("%s: Cannot read rockchip,pctl-timing\n", __func__); + return -EINVAL; + } + ret = fdtdec_get_int_array(blob, node, "rockchip,phy-timing", + (u32 *)&params->phy_timing, + sizeof(params->phy_timing) / sizeof(u32)); + if (ret) { + debug("%s: Cannot read rockchip,phy-timing\n", __func__); + return -EINVAL; + } + ret = fdtdec_get_int_array(blob, node, "rockchip,sdram-params", + (u32 *)&params->base, + sizeof(params->base) / sizeof(u32)); + if (ret) { + debug("%s: Cannot read rockchip,sdram-params\n", __func__); + return -EINVAL; + } + ret = regmap_init_mem(dev, &params->map); + if (ret) + return ret; +#endif + + return 0; +} +#endif /* CONFIG_TPL_BUILD */ + +#if CONFIG_IS_ENABLED(OF_PLATDATA) +static int conv_of_platdata(struct udevice *dev) +{ + struct rk3066_sdram_params *plat = dev_get_platdata(dev); + struct dtd_rockchip_rk3066_dmc *of_plat = &plat->of_plat; + int ret; + + memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing, + sizeof(plat->pctl_timing)); + memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing, + sizeof(plat->phy_timing)); + memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base)); + /* rk3066 supports dual-channel, set default channel num to 2 */ + plat->num_channels = 1; + ret = regmap_init_mem_platdata(dev, of_plat->reg, + ARRAY_SIZE(of_plat->reg) / 2, + &plat->map); + if (ret) + return ret; + return 0; +} +#endif + +static int rk3066_dmc_probe(struct udevice *dev) +{ +#ifdef CONFIG_TPL_BUILD + struct rk3066_sdram_params *plat = dev_get_platdata(dev); +#endif + struct dram_info *priv = dev_get_priv(dev); + struct regmap *map; + int ret; + struct udevice *dev_clk; + +#if CONFIG_IS_ENABLED(OF_PLATDATA) + ret = conv_of_platdata(dev); + if (ret) + return ret; +#endif + map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_NOC); + if (IS_ERR(map)) + return PTR_ERR(map); + priv->chan[0].msch = regmap_get_range(map, 0); + + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); + +#ifdef CONFIG_TPL_BUILD + priv->chan[0].pctl = regmap_get_range(plat->map, 0); + priv->chan[0].publ = regmap_get_range(plat->map, 1); +#endif + ret = rockchip_get_clk(&dev_clk); + if (ret) + return ret; + priv->ddr_clk.id = CLK_DDR; + + ret = clk_request(dev_clk, &priv->ddr_clk); + if (ret) + return ret; + + priv->cru = rockchip_get_cru(); + if (IS_ERR(priv->cru)) + return PTR_ERR(priv->cru); +#ifdef CONFIG_TPL_BUILD + ret = setup_sdram(dev); + if (ret) + return ret; +#endif + priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.size = rockchip_sdram_size( + (phys_addr_t)&priv->pmu->sys_reg[2]); + + return 0; +} + +static int rk3066_dmc_get_info(struct udevice *dev, struct ram_info *info) +{ + struct dram_info *priv = dev_get_priv(dev); + + *info = priv->info; + + return 0; +} + +static struct ram_ops rk3066_dmc_ops = { + .get_info = rk3066_dmc_get_info, +}; + +static const struct udevice_id rk3066_dmc_ids[] = { + { .compatible = "rockchip,rk3066-dmc" }, + { } +}; + +U_BOOT_DRIVER(dmc_rk3066) = { + .name = "rockchip_rk3066_dmc", + .id = UCLASS_RAM, + .of_match = rk3066_dmc_ids, + .ops = &rk3066_dmc_ops, +#ifdef CONFIG_TPL_BUILD + .ofdata_to_platdata = rk3066_dmc_ofdata_to_platdata, +#endif + .probe = rk3066_dmc_probe, + .priv_auto_alloc_size = sizeof(struct dram_info), +#ifdef CONFIG_TPL_BUILD + .platdata_auto_alloc_size = sizeof(struct rk3066_sdram_params), +#endif +};

Sandisk SDTNQGAMA is a 8GB size, 3.3V 8 bit chip with 16KB page size, 1KB write size and 40 bit ecc support

Signed-off-by: Paweł Jarosz paweljarosz3691@gmail.com --- Changes since v1: - none

Changes since v2: - none

Changes since v3: - none

drivers/mtd/nand/nand_ids.c | 3 +++ 1 file changed, 3 insertions(+)

diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c index d36f900..7bd9f7d 100644 --- a/drivers/mtd/nand/nand_ids.c +++ b/drivers/mtd/nand/nand_ids.c @@ -58,6 +58,9 @@ struct nand_flash_dev nand_flash_ids[] = { {"TC58NVG6D2 64G 3.3V 8-bit", { .id = {0x98, 0xde, 0x94, 0x82, 0x76, 0x56, 0x04, 0x20} }, SZ_8K, SZ_8K, SZ_2M, 0, 8, 640, NAND_ECC_INFO(40, SZ_1K) }, + {"SDTNQGAMA 64G 3.3V 8-bit", + { .id = {0x45, 0xde, 0x94, 0x93, 0x76, 0x57} }, + SZ_16K, SZ_8K, SZ_4M, 0, 6, 1280, NAND_ECC_INFO(40, SZ_1K) }, {"SDTNRGAMA 64G 3.3V 8-bit", { .id = {0x45, 0xde, 0x94, 0x93, 0x76, 0x50} }, SZ_16K, SZ_8K, SZ_4M, 0, 6, 1280, NAND_ECC_INFO(40, SZ_1K) },

Add basic Rockchip nand driver.

Driver in current state has 16, 24, 40, 60 per 1024B BCH/ECC ability and 8 bit asynchronous flash interface support. Other features will come later.

Signed-off-by: Paweł Jarosz paweljarosz3691@gmail.com --- Changes since v1: - none

Changes since v2: - fixed correct ecc checking

Changes since v3: - none

drivers/mtd/nand/Kconfig | 6 + drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/rockchip_nand.c | 660 +++++++++++++++++++++++++++++++++++++++ include/fdtdec.h | 1 + lib/fdtdec.c | 1 + 5 files changed, 669 insertions(+) create mode 100644 drivers/mtd/nand/rockchip_nand.c

diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 71d678f..c308497 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -69,6 +69,12 @@ config NAND_PXA3XX This enables the driver for the NAND flash device found on PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).

+config NAND_ROCKCHIP + bool "Support for NAND on Rockchip SoCs" + select SYS_NAND_SELF_INIT + ---help--- + Enable support for Rockchip nand. + config NAND_SUNXI bool "Support for NAND on Allwinner SoCs" depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index c3d4a99..0659253 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -65,6 +65,7 @@ obj-$(CONFIG_NAND_OMAP_ELM) += omap_elm.o obj-$(CONFIG_NAND_PLAT) += nand_plat.o obj-$(CONFIG_NAND_SUNXI) += sunxi_nand.o obj-$(CONFIG_NAND_ZYNQ) += zynq_nand.o +obj-$(CONFIG_NAND_ROCKCHIP) += rockchip_nand.o

else # minimal SPL drivers

diff --git a/drivers/mtd/nand/rockchip_nand.c b/drivers/mtd/nand/rockchip_nand.c new file mode 100644 index 0000000..d8f4439 --- /dev/null +++ b/drivers/mtd/nand/rockchip_nand.c @@ -0,0 +1,660 @@ +/* + * Copyright (c) 2017 Yifeng Zhao yifeng.zhao@rock-chips.com + * Copyright (c) 2017 Paweł Jarosz paweljarosz3691@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fdtdec.h> +#include <inttypes.h> +#include <nand.h> +#include <linux/kernel.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/partitions.h> +#include <linux/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define NANDC_V6_BOOTROM_ECC 24 +#define NANDC_V6_NUM_BANKS 8 +#define NANDC_V6_DEF_TIMEOUT 20000 +#define NANDC_V6_READ 0 +#define NANDC_V6_WRITE 1 + +#define NANDC_REG_V6_FMCTL 0x00 +#define NANDC_REG_V6_FMWAIT 0x04 +#define NANDC_REG_V6_FLCTL 0x08 +#define NANDC_REG_V6_BCHCTL 0x0c +#define NANDC_REG_V6_DMA_CFG 0x10 +#define NANDC_REG_V6_DMA_BUF0 0x14 +#define NANDC_REG_V6_DMA_BUF1 0x18 +#define NANDC_REG_V6_DMA_ST 0x1C +#define NANDC_REG_V6_BCHST 0x20 +#define NANDC_REG_V6_RANDMZ 0x150 +#define NANDC_REG_V6_VER 0x160 +#define NANDC_REG_V6_INTEN 0x16C +#define NANDC_REG_V6_INTCLR 0x170 +#define NANDC_REG_V6_INTST 0x174 +#define NANDC_REG_V6_SPARE0 0x200 +#define NANDC_REG_V6_SPARE1 0x230 +#define NANDC_REG_V6_BANK0 0x800 +#define NANDC_REG_V6_SRAM0 0x1000 +#define NANDC_REG_V6_SRAM_SIZE 0x400 + +#define NANDC_REG_V6_DATA 0x00 +#define NANDC_REG_V6_ADDR 0x04 +#define NANDC_REG_V6_CMD 0x08 + +/* FMCTL */ +#define NANDC_V6_FM_WP BIT(8) +#define NANDC_V6_FM_CE_SEL_M 0xFF +#define NANDC_V6_FM_CE_SEL(x) (1 << (x)) +#define NANDC_V6_FM_FREADY BIT(9) + +/* FLCTL */ +#define NANDC_V6_FL_RST BIT(0) +#define NANDC_V6_FL_DIR_S 0x1 +#define NANDC_V6_FL_XFER_START BIT(2) +#define NANDC_V6_FL_XFER_EN BIT(3) +#define NANDC_V6_FL_ST_BUF_S 0x4 +#define NANDC_V6_FL_XFER_COUNT BIT(5) +#define NANDC_V6_FL_ACORRECT BIT(10) +#define NANDC_V6_FL_XFER_READY BIT(20) + +/* BCHCTL */ +#define NAND_V6_BCH_REGION_S 0x5 +#define NAND_V6_BCH_REGION_M 0x7 + +/* BCHST */ +#define NANDC_V6_BCH0_ST_ERR BIT(2) +#define NANDC_V6_BCH1_ST_ERR BIT(15) +#define NANDC_V6_ECC_ERR_CNT0(x) ((((x & (0x1F << 3)) >> 3) \ + | ((x & (1 << 27)) >> 22)) & 0x3F) +#define NANDC_V6_ECC_ERR_CNT1(x) ((((x & (0x1F << 16)) >> 16) \ + | ((x & (1 << 29)) >> 24)) & 0x3F) + +struct rk_nand { + uint32_t banks[NANDC_V6_NUM_BANKS]; + struct nand_hw_control controller; + uint32_t ecc_strength; + struct mtd_info mtd; + bool bootromblocks; + void __iomem *regs; + int selected_bank; +}; + +static struct nand_ecclayout nand_oob_fix = { + .eccbytes = 24, + .eccpos = { + 4, 5, 6, 7, 8, 9, 10}, + .oobfree = { + {.offset = 0, + .length = 4} } +}; + +static inline struct rk_nand *to_rknand(struct nand_hw_control *ctrl) +{ + return container_of(ctrl, struct rk_nand, controller); +} + +static void rockchip_nand_init(struct rk_nand *rknand) +{ + writel(0, rknand->regs + NANDC_REG_V6_RANDMZ); + writel(0, rknand->regs + NANDC_REG_V6_DMA_CFG); + writel(0, rknand->regs + NANDC_REG_V6_BCHCTL); + writel(NANDC_V6_FM_WP, rknand->regs + NANDC_REG_V6_FMCTL); + writel(0x1081, rknand->regs + NANDC_REG_V6_FMWAIT); +} + +static void rockchip_nand_select_chip(struct mtd_info *mtd, int chipnr) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct rk_nand *rknand = to_rknand(chip->controller); + void __iomem *bank_base; + uint32_t reg; + int banknr; + + reg = readl(rknand->regs + NANDC_REG_V6_FMCTL); + reg &= ~NANDC_V6_FM_CE_SEL_M; + + if (chipnr == -1) { + banknr = -1; + } else { + banknr = rknand->banks[chipnr]; + bank_base = rknand->regs + NANDC_REG_V6_BANK0 + banknr * 0x100; + + chip->IO_ADDR_R = bank_base; + chip->IO_ADDR_W = bank_base; + + reg |= 1 << banknr; + } + writel(reg, rknand->regs + NANDC_REG_V6_FMCTL); + + rknand->selected_bank = banknr; +} + +static void rockchip_nand_cmd_ctrl(struct mtd_info *mtd, + int dat, + unsigned int ctrl) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct rk_nand *rknand = to_rknand(chip->controller); + void __iomem *bank_base = rknand->regs + NANDC_REG_V6_BANK0 + + rknand->selected_bank * 0x100; + + if (ctrl & NAND_CTRL_CHANGE) { + if (ctrl & NAND_ALE) + bank_base += NANDC_REG_V6_ADDR; + else if (ctrl & NAND_CLE) + bank_base += NANDC_REG_V6_CMD; + chip->IO_ADDR_W = bank_base; + } + + if (dat != NAND_CMD_NONE) + writeb(dat & 0xFF, chip->IO_ADDR_W); +} + +static void rockchip_nand_read_buf(struct mtd_info *mtd, + uint8_t *buf, + int len) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct rk_nand *rknand = to_rknand(chip->controller); + int offs = 0; + void __iomem *bank_base = rknand->regs + NANDC_REG_V6_BANK0 + + rknand->selected_bank * 0x100; + + for (offs = 0; offs < len; offs++) + buf[offs] = readb(bank_base); +} + +static void rockchip_nand_write_buf(struct mtd_info *mtd, + const uint8_t *buf, + int len) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct rk_nand *rknand = to_rknand(chip->controller); + int offs = 0; + void __iomem *bank_base = rknand->regs + NANDC_REG_V6_BANK0 + + rknand->selected_bank * 0x100; + + for (offs = 0; offs < len; offs++) + writeb(buf[offs], bank_base); +} + +static uint8_t rockchip_nand_read_byte(struct mtd_info *mtd) +{ + uint8_t ret; + + rockchip_nand_read_buf(mtd, &ret, 1); + + return ret; +} + +static int rockchip_nand_dev_ready(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct rk_nand *rknand = to_rknand(chip->controller); + + if (readl(rknand->regs + NANDC_REG_V6_FMCTL) & NANDC_V6_FM_FREADY) + return 1; + + return 0; +} + +static int rockchip_nand_hw_ecc_setup(struct mtd_info *mtd, + struct nand_ecc_ctrl *ecc, + uint32_t strength) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct rk_nand *rknand = to_rknand(chip->controller); + u32 reg; + + ecc->strength = strength; + ecc->bytes = DIV_ROUND_UP(ecc->strength * 14, 8); + ecc->bytes = ALIGN(ecc->bytes, 2); + + switch (ecc->strength) { + case 60: + reg = 0x00040010; + break; + case 40: + reg = 0x00040000; + break; + case 24: + reg = 0x00000010; + break; + case 16: + reg = 0x00000000; + break; + default: + return -EINVAL; + } + writel(reg, rknand->regs + NANDC_REG_V6_BCHCTL); + + return 0; +} + +static void rockchip_nand_pio_xfer_start(struct rk_nand *rknand, + u8 dir, + u8 st_buf) +{ + u32 reg; + + reg = readl(rknand->regs + NANDC_REG_V6_BCHCTL); + reg = (reg & (~(NAND_V6_BCH_REGION_M << NAND_V6_BCH_REGION_S))) | + (rknand->selected_bank << NAND_V6_BCH_REGION_S); + writel(reg, rknand->regs + NANDC_REG_V6_BCHCTL); + + reg = (dir << NANDC_V6_FL_DIR_S) | (st_buf << NANDC_V6_FL_ST_BUF_S) | + NANDC_V6_FL_XFER_EN | NANDC_V6_FL_XFER_COUNT | + NANDC_V6_FL_ACORRECT; + writel(reg, rknand->regs + NANDC_REG_V6_FLCTL); + + reg |= NANDC_V6_FL_XFER_START; + writel(reg, rknand->regs + NANDC_REG_V6_FLCTL); +} + +static int rockchip_nand_wait_pio_xfer_done(struct rk_nand *rknand) +{ + int timeout = NANDC_V6_DEF_TIMEOUT; + int reg; + + while (timeout--) { + reg = readl(rknand->regs + NANDC_REG_V6_FLCTL); + + if ((reg & NANDC_V6_FL_XFER_READY) != 0) + break; + + udelay(1); + } + + if (timeout == 0) + return -1; + + return 0; +} + +static void rockchip_nand_read_extra_oob(struct mtd_info *mtd, u8 *oob) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct nand_ecc_ctrl *ecc = &chip->ecc; + int offset = ((ecc->bytes + ecc->prepad) * ecc->steps); + int len = mtd->oobsize - offset; + + if (len <= 0) + return; + + chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset + mtd->writesize, -1); + + rockchip_nand_read_buf(mtd, oob + offset, len); +} + +static void rockchip_nand_write_extra_oob(struct mtd_info *mtd, u8 *oob) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct nand_ecc_ctrl *ecc = &chip->ecc; + int offset = ((ecc->bytes + ecc->prepad) * ecc->steps); + int len = mtd->oobsize - offset; + + if (len <= 0) + return; + + chip->cmdfunc(mtd, NAND_CMD_RNDIN, offset + mtd->writesize, -1); + + rockchip_nand_write_buf(mtd, oob + offset, len); +} + + +static int rockchip_nand_hw_syndrome_pio_read_page(struct mtd_info *mtd, + struct nand_chip *chip, + uint8_t *buf, + int oob_required, + int page) +{ + struct rk_nand *rknand = to_rknand(chip->controller); + struct nand_ecc_ctrl *ecc = &chip->ecc; + void __iomem *sram_base = rknand->regs + NANDC_REG_V6_SRAM0; + unsigned int max_bitflips = 0; + int ret, step, bch_st; + int offset = page * mtd->writesize; + + if (rknand->bootromblocks && (offset < (7 * mtd->erasesize))) + rockchip_nand_hw_ecc_setup(mtd, ecc, NANDC_V6_BOOTROM_ECC); + + rockchip_nand_pio_xfer_start(rknand, NANDC_V6_READ, 0); + + for (step = 0; step < ecc->steps; step++) { + int data_off = step * ecc->size; + int oob_off = step * (ecc->bytes + ecc->prepad); + u8 *data = buf + data_off; + u8 *oob = chip->oob_poi + oob_off; + + ret = rockchip_nand_wait_pio_xfer_done(rknand); + if (ret) + return ret; + + bch_st = readl(rknand->regs + NANDC_REG_V6_BCHST); + + if (bch_st & NANDC_V6_BCH0_ST_ERR) { + mtd->ecc_stats.failed++; + max_bitflips = -1; + } else { + ret = NANDC_V6_ECC_ERR_CNT0(bch_st); + mtd->ecc_stats.corrected += ret; + max_bitflips = max_t(unsigned int, max_bitflips, ret); + } + + if ((step + 1) < ecc->steps) + rockchip_nand_pio_xfer_start(rknand, NANDC_V6_READ, + (step + 1) & 0x1); + + memcpy_fromio(data, sram_base + NANDC_REG_V6_SRAM_SIZE * + (step & 1), ecc->size); + + if (step & 1) + memcpy_fromio(oob, rknand->regs + NANDC_REG_V6_SPARE1, 4); + else + memcpy_fromio(oob, rknand->regs + NANDC_REG_V6_SPARE0, 4); + } + + rockchip_nand_read_extra_oob(mtd, chip->oob_poi); + + if (rknand->bootromblocks) + rockchip_nand_hw_ecc_setup(mtd, ecc, rknand->ecc_strength); + + return max_bitflips; +} + +static uint32_t rockchip_nand_make_bootrom_compat(struct mtd_info *mtd, + int page, + const u8 *oob, + bool bootromblocks) +{ + int pages_per_block = mtd->erasesize / mtd->writesize; + int offset = page * mtd->writesize; + + if ((offset < (2 * mtd->erasesize)) || !(page % 2) || + (offset >= (7 * mtd->erasesize)) || !bootromblocks) + return oob[3] | (oob[2] << 8) | (oob[1] << 16) | (oob[0] << 24); + + return (page % pages_per_block + 1) * 4; +} + +static int rockchip_nand_hw_syndrome_pio_write_page(struct mtd_info *mtd, + struct nand_chip *chip, + const uint8_t *buf, + int oob_required, + int page) +{ + struct rk_nand *rknand = to_rknand(chip->controller); + struct nand_ecc_ctrl *ecc = &chip->ecc; + void __iomem *sram_base = rknand->regs + NANDC_REG_V6_SRAM0; + int ret, index, step = 0; + int offset = page * mtd->writesize; + int data_off = step * ecc->size; + int oob_off = step * (ecc->bytes + ecc->prepad); + const u8 *data = buf + data_off; + const u8 *oob = chip->oob_poi + oob_off; + + if (rknand->bootromblocks && (offset < (7 * mtd->erasesize))) + rockchip_nand_hw_ecc_setup(mtd, ecc, NANDC_V6_BOOTROM_ECC); + + index = rockchip_nand_make_bootrom_compat(mtd, page, oob, + rknand->bootromblocks); + + memcpy_toio(sram_base, data, ecc->size); + memcpy_toio(rknand->regs + NANDC_REG_V6_SPARE0, &index, ecc->prepad); + + for (step = 1; step <= ecc->steps; step++) { + rockchip_nand_pio_xfer_start(rknand, NANDC_V6_WRITE, + (step - 1) & 0x1); + + data_off = step * ecc->size; + oob_off = step * (ecc->bytes + ecc->prepad); + data = buf + data_off; + oob = chip->oob_poi + oob_off; + + if (step < ecc->steps) { + memcpy_toio(sram_base + NANDC_REG_V6_SRAM_SIZE * + (step & 1), data, ecc->size); + if (step & 1) + memcpy_toio(rknand->regs + NANDC_REG_V6_SPARE1, + oob, ecc->prepad); + else + memcpy_toio(rknand->regs + NANDC_REG_V6_SPARE0, + oob, ecc->prepad); + } + + ret = rockchip_nand_wait_pio_xfer_done(rknand); + if (ret) + return ret; + } + + rockchip_nand_write_extra_oob(mtd, chip->oob_poi); + + rockchip_nand_hw_ecc_setup(mtd, ecc, rknand->ecc_strength); + + return 0; +} + +static const u8 strengths[] = {60, 40, 24, 16}; + +static int rockchip_nand_ecc_max_strength(struct mtd_info *mtd, + struct nand_ecc_ctrl *ecc) +{ + uint32_t max_strength, index; + + max_strength = ((mtd->oobsize / ecc->steps) - ecc->prepad) * 8 / 14; + + for (index = 0; index < ARRAY_SIZE(strengths); index++) + if (max_strength >= strengths[index]) + break; + + if (index >= ARRAY_SIZE(strengths)) + return -ENOTSUPP; + + return strengths[index]; +} + +static bool rockchip_nand_strength_is_valid(int strength) +{ + uint32_t index; + + for (index = 0; index < ARRAY_SIZE(strengths); index++) + if (strength == strengths[index]) + break; + + if (index == ARRAY_SIZE(strengths)) + return false; + + return true; +} + +static int rockchip_nand_hw_ecc_ctrl_init(struct mtd_info *mtd, + struct nand_ecc_ctrl *ecc) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct rk_nand *rknand = to_rknand(chip->controller); + uint32_t strength; + int index; + + ecc->prepad = 4; + ecc->steps = mtd->writesize / ecc->size; + + if (fdtdec_get_bool(gd->fdt_blob, chip->flash_node, + "rockchip,protect-bootrom-blocks")) + rknand->bootromblocks = true; + else + rknand->bootromblocks = false; + + if (rockchip_nand_strength_is_valid(ecc->strength)) + strength = ecc->strength; + else + strength = rockchip_nand_ecc_max_strength(mtd, ecc); + + rockchip_nand_hw_ecc_setup(mtd, ecc, strength); + + rknand->ecc_strength = ecc->strength; + + nand_oob_fix.eccbytes = ecc->bytes * ecc->steps; + for (index = 0; index < ecc->bytes; index++) + nand_oob_fix.eccpos[index] = index + ecc->prepad; + ecc->layout = &nand_oob_fix; + + if (mtd->oobsize < ((ecc->bytes + ecc->prepad) * ecc->steps)) { + return -EINVAL; + } + + return 0; +} + +static int rockchip_nand_ecc_init(struct mtd_info *mtd, + struct nand_ecc_ctrl *ecc) +{ + int ret; + + switch (ecc->mode) { + case NAND_ECC_HW_SYNDROME: + ret = rockchip_nand_hw_ecc_ctrl_init(mtd, ecc); + if (ret) + return ret; + ecc->read_page = rockchip_nand_hw_syndrome_pio_read_page; + ecc->write_page = rockchip_nand_hw_syndrome_pio_write_page; + break; + case NAND_ECC_SOFT_BCH: + case NAND_ECC_NONE: + case NAND_ECC_SOFT: + break; + default: + return -EINVAL; + } + + return 0; +} + +static int rockchip_nand_chip_init(int node, struct rk_nand *rknand, int devnum) +{ + const void *blob = gd->fdt_blob; + struct nand_chip *chip; + struct mtd_info *mtd; + int ret; + + chip = kzalloc(sizeof(*chip), GFP_KERNEL); + + chip->chip_delay = 50; + chip->flash_node = node; + chip->select_chip = rockchip_nand_select_chip; + chip->cmd_ctrl = rockchip_nand_cmd_ctrl; + chip->read_buf = rockchip_nand_read_buf; + chip->write_buf = rockchip_nand_write_buf; + chip->read_byte = rockchip_nand_read_byte; + chip->dev_ready = rockchip_nand_dev_ready; + chip->controller = &rknand->controller; + + rknand->banks[devnum] = fdtdec_get_int(blob, node, "reg", -1); + + if (rknand->banks[devnum] < 0) + return -EINVAL; + + mtd = nand_to_mtd(chip); + mtd->name = "rknand"; + + ret = nand_scan_ident(mtd, 1, NULL); + if (ret) + return ret; + + ret = rockchip_nand_ecc_init(mtd, &chip->ecc); + if (ret) { + debug("rockchip_nand_ecc_init failed: %d\n", ret); + return ret; + } + + ret = nand_scan_tail(mtd); + if (ret) { + debug("nand_scan_tail failed: %d\n", ret); + return ret; + } + + ret = nand_register(devnum, mtd); + if (ret) { + debug("Failed to register mtd device: %d\n", ret); + return ret; + } + + return 0; +} + +static int rockchip_nand_chips_init(int node, struct rk_nand *rknand) +{ + const void *blob = gd->fdt_blob; + int nand_node; + int ret, i = 0; + + for (nand_node = fdt_first_subnode(blob, node); nand_node >= 0; + nand_node = fdt_next_subnode(blob, nand_node)) { + ret = rockchip_nand_chip_init(nand_node, rknand, i++); + if (ret) + return ret; + } + + return 0; +} + +void board_nand_init(void) +{ + const void *blob = gd->fdt_blob; + struct rk_nand *rknand; + fdt_addr_t regs; + int node; + int ret; + + rknand = kzalloc(sizeof(*rknand), GFP_KERNEL); + + node = fdtdec_next_compatible(blob, 0, COMPAT_ROCKCHIP_NANDC); + + if (node < 0) { + debug("Nand node not found\n"); + goto err; + } + + if (!fdtdec_get_is_enabled(blob, node)) { + debug("Nand disabled in device tree\n"); + goto err; + } + + regs = fdtdec_get_addr(blob, node, "reg"); + if (regs == FDT_ADDR_T_NONE) { + debug("Nand address not found\n"); + goto err; + } + + rknand->regs = (void *)regs; + + spin_lock_init(&rknand->controller.lock); + init_waitqueue_head(&rknand->controller.wq); + + rockchip_nand_init(rknand); + + ret = rockchip_nand_chips_init(node, rknand); + if (ret) { + debug("Failed to init nand chips\n"); + goto err; + } + + return; +err: + kfree(rknand); +} + +int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) +{ + struct mtd_info *mtd; + + mtd = get_nand_dev_by_index(0); + return nand_read_skip_bad(mtd, offs, &size, NULL, size, (u_char *)dst); +} + +void nand_deselect(void) {} diff --git a/include/fdtdec.h b/include/fdtdec.h index 4a0947c..0e68788 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -157,6 +157,7 @@ enum fdt_compat_id { COMPAT_ALTERA_SOCFPGA_F2SDR0, /* SoCFPGA fpga2SDRAM0 bridge */ COMPAT_ALTERA_SOCFPGA_F2SDR1, /* SoCFPGA fpga2SDRAM1 bridge */ COMPAT_ALTERA_SOCFPGA_F2SDR2, /* SoCFPGA fpga2SDRAM2 bridge */ + COMPAT_ROCKCHIP_NANDC, /* Rockchip NAND controller */

COMPAT_COUNT, }; diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 107a892..4a8a8d7 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -70,6 +70,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(ALTERA_SOCFPGA_F2SDR0, "altr,socfpga-fpga2sdram0-bridge"), COMPAT(ALTERA_SOCFPGA_F2SDR1, "altr,socfpga-fpga2sdram1-bridge"), COMPAT(ALTERA_SOCFPGA_F2SDR2, "altr,socfpga-fpga2sdram2-bridge"), + COMPAT(ROCKCHIP_NANDC, "rockchip,nandc"), };

const char *fdtdec_get_compatible(enum fdt_compat_id id)