sourcing of sub directiory kconfig files are not in proper order, so keep them in ascending order.

Signed-off-by: Jagan Teki jagan@amarulasolutions.com Reviewed-by: Joe Hershberger joe.hershberger@ni.com --- drivers/clk/Kconfig | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 18bf8a6d28..a99abed9e9 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -83,13 +83,13 @@ config CLK_STM32MP1 Enable the STM32 clock (RCC) driver. Enable support for manipulating STM32MP1's on-SoC clocks.

-source "drivers/clk/tegra/Kconfig" -source "drivers/clk/uniphier/Kconfig" -source "drivers/clk/exynos/Kconfig" source "drivers/clk/at91/Kconfig" -source "drivers/clk/renesas/Kconfig" +source "drivers/clk/exynos/Kconfig" source "drivers/clk/mvebu/Kconfig" source "drivers/clk/owl/Kconfig" +source "drivers/clk/renesas/Kconfig" +source "drivers/clk/tegra/Kconfig" +source "drivers/clk/uniphier/Kconfig"

config ICS8N3QV01 bool "Enable ICS8N3QV01 VCXO driver"

Add initial clock driver for Allwinner A64.

Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers.

Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- arch/arm/include/asm/arch-sunxi/ccu.h | 47 ++++++++++++++++++++ drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/sunxi/Kconfig | 18 ++++++++ drivers/clk/sunxi/Makefile | 9 ++++ drivers/clk/sunxi/clk_a64.c | 62 +++++++++++++++++++++++++++ drivers/clk/sunxi/clk_sunxi.c | 58 +++++++++++++++++++++++++ 7 files changed, 196 insertions(+) create mode 100644 arch/arm/include/asm/arch-sunxi/ccu.h create mode 100644 drivers/clk/sunxi/Kconfig create mode 100644 drivers/clk/sunxi/Makefile create mode 100644 drivers/clk/sunxi/clk_a64.c create mode 100644 drivers/clk/sunxi/clk_sunxi.c

diff --git a/arch/arm/include/asm/arch-sunxi/ccu.h b/arch/arm/include/asm/arch-sunxi/ccu.h new file mode 100644 index 0000000000..f628c893de --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/ccu.h @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Amarula Solutions. + * Author: Jagan Teki jagan@amarulasolutions.com + */ + +#ifndef _ASM_ARCH_CCU_H +#define _ASM_ARCH_CCU_H + +/** + * ccu_clk_map - common clock unit clock map + * + * @off: ccu clock offset + * @bit: ccu clock bit value + * @ccu_clk_set_rate: ccu clock set rate func + */ +struct ccu_clk_map { + u16 off; + u32 bit; + int (*ccu_clk_set_rate)(void *base, u32 bit, ulong rate); +}; + +/** + * struct ccu_desc - common clock unit descriptor + * + * @clks: mapping clocks descriptor + * @num_clks: number of mapped clocks + */ +struct ccu_desc { + struct ccu_clk_map *clks; + unsigned long num_clks; +}; + +/** + * struct sunxi_clk_priv - sunxi clock private structure + * + * @base: base address + * @desc: ccu descriptor + */ +struct sunxi_clk_priv { + void *base; + const struct ccu_desc *desc; +}; + +extern struct clk_ops sunxi_clk_ops; + +#endif /* _ASM_ARCH_CCU_H */ diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index a99abed9e9..b4992e9ff1 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -88,6 +88,7 @@ source "drivers/clk/exynos/Kconfig" source "drivers/clk/mvebu/Kconfig" source "drivers/clk/owl/Kconfig" source "drivers/clk/renesas/Kconfig" +source "drivers/clk/sunxi/Kconfig" source "drivers/clk/tegra/Kconfig" source "drivers/clk/uniphier/Kconfig"

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 146283c723..7cefcd99a0 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -11,6 +11,7 @@ obj-y += tegra/ obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-$(CONFIG_ARCH_MESON) += clk_meson.o obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ +obj-$(CONFIG_ARCH_SUNXI) += sunxi/ obj-$(CONFIG_CLK_AT91) += at91/ obj-$(CONFIG_CLK_MVEBU) += mvebu/ obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig new file mode 100644 index 0000000000..bf5ecb3801 --- /dev/null +++ b/drivers/clk/sunxi/Kconfig @@ -0,0 +1,18 @@ +config CLK_SUNXI + bool "Clock support for Allwinner SoCs" + depends on CLK && ARCH_SUNXI + default y + help + This enables support for common clock driver API on Allwinner + SoCs. + +if CLK_SUNXI + +config CLK_SUN50I_A64 + bool "Clock driver for Allwinner A64" + default MACH_SUN50I + help + This enables common clock driver support for platforms based + on Allwinner A64 SoC. + +endif # CLK_SUNXI diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile new file mode 100644 index 0000000000..fb20d28333 --- /dev/null +++ b/drivers/clk/sunxi/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (C) 2018 Amarula Solutions. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o + +obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c new file mode 100644 index 0000000000..9393a01ccf --- /dev/null +++ b/drivers/clk/sunxi/clk_a64.c @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Amarula Solutions. + * Author: Jagan Teki jagan@amarulasolutions.com + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <errno.h> +#include <asm/arch/ccu.h> +#include <dt-bindings/clock/sun50i-a64-ccu.h> + +static struct ccu_clk_map a64_clks[] = { + [CLK_BUS_OTG] = { 0x060, BIT(23), NULL }, + [CLK_BUS_EHCI0] = { 0x060, BIT(24), NULL }, + [CLK_BUS_EHCI1] = { 0x060, BIT(25), NULL }, + [CLK_BUS_OHCI0] = { 0x060, BIT(28), NULL }, + [CLK_BUS_OHCI1] = { 0x060, BIT(29), NULL }, + + [CLK_USB_PHY0] = { 0x0cc, BIT(8), NULL }, + [CLK_USB_PHY1] = { 0x0cc, BIT(9), NULL }, + [CLK_USB_HSIC] = { 0x0cc, BIT(10), NULL }, + [CLK_USB_HSIC_12M] = { 0x0cc, BIT(11), NULL }, + [CLK_USB_OHCI0] = { 0x0cc, BIT(16), NULL }, + [CLK_USB_OHCI1] = { 0x0cc, BIT(17), NULL }, +}; + +static const struct ccu_desc sun50i_a64_ccu_desc = { + .clks = a64_clks, + .num_clks = ARRAY_SIZE(a64_clks), +}; + +static int a64_clk_probe(struct udevice *dev) +{ + struct sunxi_clk_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -ENOMEM; + + priv->desc = (const struct ccu_desc *)dev_get_driver_data(dev); + if (!priv->desc) + return -EINVAL; + + return 0; +} + +static const struct udevice_id a64_clk_ids[] = { + { .compatible = "allwinner,sun50i-a64-ccu", + .data = (ulong)&sun50i_a64_ccu_desc }, + { } +}; + +U_BOOT_DRIVER(clk_sun50i_a64) = { + .name = "sun50i_a64_ccu", + .id = UCLASS_CLK, + .of_match = a64_clk_ids, + .priv_auto_alloc_size = sizeof(struct sunxi_clk_priv), + .ops = &sunxi_clk_ops, + .probe = a64_clk_probe, +}; diff --git a/drivers/clk/sunxi/clk_sunxi.c b/drivers/clk/sunxi/clk_sunxi.c new file mode 100644 index 0000000000..791b1ac7f2 --- /dev/null +++ b/drivers/clk/sunxi/clk_sunxi.c @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Amarula Solutions. + * Author: Jagan Teki jagan@amarulasolutions.com + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/arch/ccu.h> +#include <linux/log2.h> + +static int sunxi_clk_enable(struct clk *clk) +{ + struct sunxi_clk_priv *priv = dev_get_priv(clk->dev); + struct ccu_clk_map *map = &priv->desc->clks[clk->id]; + u32 reg; + + if (!map->off || !map->bit) { + debug("%s (CLK#%ld) unhandled\n", __func__, clk->id); + return 0; + } + + debug("%s(#%ld) off#0x%x, BIT(%d)\n", __func__, + clk->id, map->off, ilog2(map->bit)); + + reg = readl(priv->base + map->off); + writel(reg | map->bit, priv->base + map->off); + + return 0; +} + +static int sunxi_clk_disable(struct clk *clk) +{ + struct sunxi_clk_priv *priv = dev_get_priv(clk->dev); + struct ccu_clk_map *map = &priv->desc->clks[clk->id]; + u32 reg; + + if (!map->off || !map->bit) { + debug("%s (CLK#%ld) unhandled\n", __func__, clk->id); + return 0; + } + + debug("%s(#%ld) off#0x%x, BIT(%d)\n", __func__, + clk->id, map->off, ilog2(map->bit)); + + reg = readl(priv->base + map->off); + writel(reg & ~map->bit, priv->base + map->off); + + return 0; +} + +struct clk_ops sunxi_clk_ops = { + .enable = sunxi_clk_enable, + .disable = sunxi_clk_disable, +};

Add common reset driver for all Allwinner SoC's.

Since CLK and RESET share common DT compatible, it is CLK driver job is to bind the reset driver. So add CLK bind call on respective SoC driver by passing ccu map descriptor so-that reset deassert, deassert operations held based on reset register map defined by CLK driver.

Select DM_RESET via CLK_SUNXI, this make hidden section of RESET since CLK and RESET share common DT compatible and code.

Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- arch/arm/include/asm/arch-sunxi/ccu.h | 25 ++++++ drivers/clk/sunxi/Kconfig | 1 + drivers/clk/sunxi/clk_a64.c | 22 +++++ drivers/reset/Kconfig | 8 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-sunxi.c | 124 ++++++++++++++++++++++++++ 6 files changed, 181 insertions(+) create mode 100644 drivers/reset/reset-sunxi.c

diff --git a/arch/arm/include/asm/arch-sunxi/ccu.h b/arch/arm/include/asm/arch-sunxi/ccu.h index f628c893de..bacd052ef3 100644 --- a/arch/arm/include/asm/arch-sunxi/ccu.h +++ b/arch/arm/include/asm/arch-sunxi/ccu.h @@ -20,15 +20,31 @@ struct ccu_clk_map { int (*ccu_clk_set_rate)(void *base, u32 bit, ulong rate); };

+/** + * ccu_reset_map - common clock unit reset map + * + * @off: ccu reset offset + * @bit: ccu reset bit value + */ +struct ccu_reset_map { + u16 off; + u32 bit; +}; + /** * struct ccu_desc - common clock unit descriptor * * @clks: mapping clocks descriptor * @num_clks: number of mapped clocks + * @resets: mapping resets descriptor + * @num_resets: number of mapped resets */ struct ccu_desc { struct ccu_clk_map *clks; unsigned long num_clks; + + struct ccu_reset_map *resets; + unsigned long num_resets; };

/** @@ -44,4 +60,13 @@ struct sunxi_clk_priv {

extern struct clk_ops sunxi_clk_ops;

+/** + * sunxi_reset_bind() - reset binding + * + * @dev: reset device + * @count: reset count + * @return 0 success, or error value + */ +int sunxi_reset_bind(struct udevice *dev, ulong count); + #endif /* _ASM_ARCH_CCU_H */ diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig index bf5ecb3801..041d711e58 100644 --- a/drivers/clk/sunxi/Kconfig +++ b/drivers/clk/sunxi/Kconfig @@ -1,6 +1,7 @@ config CLK_SUNXI bool "Clock support for Allwinner SoCs" depends on CLK && ARCH_SUNXI + select DM_RESET default y help This enables support for common clock driver API on Allwinner diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c index 9393a01ccf..e5257b62c7 100644 --- a/drivers/clk/sunxi/clk_a64.c +++ b/drivers/clk/sunxi/clk_a64.c @@ -10,6 +10,7 @@ #include <errno.h> #include <asm/arch/ccu.h> #include <dt-bindings/clock/sun50i-a64-ccu.h> +#include <dt-bindings/reset/sun50i-a64-ccu.h>

static struct ccu_clk_map a64_clks[] = { [CLK_BUS_OTG] = { 0x060, BIT(23), NULL }, @@ -26,9 +27,24 @@ static struct ccu_clk_map a64_clks[] = { [CLK_USB_OHCI1] = { 0x0cc, BIT(17), NULL }, };

+static struct ccu_reset_map a64_resets[] = { + [RST_USB_PHY0] = { 0x0cc, BIT(0) }, + [RST_USB_PHY1] = { 0x0cc, BIT(1) }, + [RST_USB_HSIC] = { 0x0cc, BIT(2) }, + + [RST_BUS_OTG] = { 0x2c0, BIT(23) }, + [RST_BUS_EHCI0] = { 0x2c0, BIT(24) }, + [RST_BUS_EHCI1] = { 0x2c0, BIT(25) }, + [RST_BUS_OHCI0] = { 0x2c0, BIT(28) }, + [RST_BUS_OHCI1] = { 0x2c0, BIT(29) }, +}; + static const struct ccu_desc sun50i_a64_ccu_desc = { .clks = a64_clks, .num_clks = ARRAY_SIZE(a64_clks), + + .resets = a64_resets, + .num_resets = ARRAY_SIZE(a64_resets), };

static int a64_clk_probe(struct udevice *dev) @@ -46,6 +62,11 @@ static int a64_clk_probe(struct udevice *dev) return 0; }

+static int a64_clk_bind(struct udevice *dev) +{ + return sunxi_reset_bind(dev, 50); +} + static const struct udevice_id a64_clk_ids[] = { { .compatible = "allwinner,sun50i-a64-ccu", .data = (ulong)&sun50i_a64_ccu_desc }, @@ -59,4 +80,5 @@ U_BOOT_DRIVER(clk_sun50i_a64) = { .priv_auto_alloc_size = sizeof(struct sunxi_clk_priv), .ops = &sunxi_clk_ops, .probe = a64_clk_probe, + .bind = a64_clk_bind, }; diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 33c39b7fb6..bdc06564a0 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -98,4 +98,12 @@ config RESET_SOCFPGA help Support for reset controller on SoCFPGA platform.

+config RESET_SUNXI + bool "RESET support for Allwinner SoCs" + depends on DM_RESET && ARCH_SUNXI + default y + help + This enables support for common reset driver for + Allwinner SoCs. + endmenu diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index ad08be4c8c..698d15a0e0 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -15,3 +15,4 @@ obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o obj-$(CONFIG_RESET_MESON) += reset-meson.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o +obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o diff --git a/drivers/reset/reset-sunxi.c b/drivers/reset/reset-sunxi.c new file mode 100644 index 0000000000..c0abe41bec --- /dev/null +++ b/drivers/reset/reset-sunxi.c @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Amarula Solutions. + * Author: Jagan Teki jagan@amarulasolutions.com + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <reset-uclass.h> +#include <asm/io.h> +#include <dm/lists.h> +#include <linux/log2.h> +#include <asm/arch/ccu.h> + +struct sunxi_reset_priv { + void *base; + ulong count; + const struct ccu_desc *desc; +}; + +static int sunxi_reset_request(struct reset_ctl *reset_ctl) +{ + struct sunxi_reset_priv *priv = dev_get_priv(reset_ctl->dev); + + debug("%s (RST#%ld)\n", __func__, reset_ctl->id); + + /* check dt-bindings/reset/sun8i-h3-ccu.h for max id */ + if (reset_ctl->id >= priv->count) + return -EINVAL; + + return 0; +} + +static int sunxi_reset_free(struct reset_ctl *reset_ctl) +{ + debug("%s (RST#%ld)\n", __func__, reset_ctl->id); + + return 0; +} + +static int sunxi_reset_assert(struct reset_ctl *reset_ctl) +{ + struct sunxi_reset_priv *priv = dev_get_priv(reset_ctl->dev); + struct ccu_reset_map *map = &priv->desc->resets[reset_ctl->id]; + u32 reg; + + if (!map->off || !map->bit) { + debug("%s (RST#%ld) unhandled\n", __func__, reset_ctl->id); + return 0; + } + + debug("%s(#%ld) off#0x%x, BIT(%d)\n", __func__, + reset_ctl->id, map->off, ilog2(map->bit)); + + reg = readl(priv->base + map->off); + writel(reg & ~map->bit, priv->base + map->off); + + return 0; +} + +static int sunxi_reset_deassert(struct reset_ctl *reset_ctl) +{ + struct sunxi_reset_priv *priv = dev_get_priv(reset_ctl->dev); + struct ccu_reset_map *map = &priv->desc->resets[reset_ctl->id]; + u32 reg; + + if (!map->off || !map->bit) { + debug("%s (RST#%ld) unhandled\n", __func__, reset_ctl->id); + return 0; + } + + debug("%s(#%ld) off#0x%x, BIT(%d)\n", __func__, + reset_ctl->id, map->off, ilog2(map->bit)); + + reg = readl(priv->base + map->off); + writel(reg | map->bit, priv->base + map->off); + + return 0; +} + +struct reset_ops sunxi_reset_ops = { + .request = sunxi_reset_request, + .free = sunxi_reset_free, + .rst_assert = sunxi_reset_assert, + .rst_deassert = sunxi_reset_deassert, +}; + +static int sunxi_reset_probe(struct udevice *dev) +{ + struct sunxi_reset_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + + return 0; +} + +int sunxi_reset_bind(struct udevice *dev, ulong count) +{ + struct udevice *rst_dev; + struct sunxi_reset_priv *priv; + int ret; + + ret = device_bind_driver_to_node(dev, "sunxi_reset", "reset", + dev_ofnode(dev), &rst_dev); + if (ret) { + debug("Warning: failed to bind sunxi_reset driver: ret=%d\n", ret); + return ret; + } + priv = malloc(sizeof(struct sunxi_reset_priv)); + priv->count = count; + priv->desc = (const struct ccu_desc *)dev_get_driver_data(dev); + rst_dev->priv = priv; + + return 0; +} + +U_BOOT_DRIVER(reset_sun8i_h3) = { + .name = "sunxi_reset", + .id = UCLASS_RESET, + .ops = &sunxi_reset_ops, + .probe = sunxi_reset_probe, + .priv_auto_alloc_size = sizeof(struct sunxi_reset_priv), +};

Add initial clock driver for Allwinner A10/A20.

- Implement USB ahb and USB clocks via ccu_clk_map descriptor for A10/A20, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB resets via ccu_reset_map descriptor for A10/A20, so it can accessed in common reset deassert and assert functions from reset-sunxi.c

Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/clk/sunxi/Kconfig | 7 ++++ drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk_a10.c | 77 +++++++++++++++++++++++++++++++++++++ 3 files changed, 85 insertions(+) create mode 100644 drivers/clk/sunxi/clk_a10.c

diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig index c3713bbac2..fbbf94ef55 100644 --- a/drivers/clk/sunxi/Kconfig +++ b/drivers/clk/sunxi/Kconfig @@ -9,6 +9,13 @@ config CLK_SUNXI

if CLK_SUNXI

+config CLK_SUN4I_A10 + bool "Clock driver for Allwinner A10/A20" + default MACH_SUN4I || MACH_SUN7I + help + This enables common clock driver support for platforms based + on Allwinner A10/A20 SoC. + config CLK_SUN8I_H3 bool "Clock driver for Allwinner H3/H5" default MACH_SUNXI_H3_H5 diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index dec49f27a1..bba830922f 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -6,5 +6,6 @@

obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o

+obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c new file mode 100644 index 0000000000..7492e1367a --- /dev/null +++ b/drivers/clk/sunxi/clk_a10.c @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Amarula Solutions. + * Author: Jagan Teki jagan@amarulasolutions.com + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <errno.h> +#include <asm/arch/ccu.h> +#include <dt-bindings/clock/sun4i-a10-ccu.h> +#include <dt-bindings/reset/sun4i-a10-ccu.h> + +static struct ccu_clk_map a10_clks[] = { + [CLK_AHB_OTG] = { 0x060, BIT(0), NULL }, + [CLK_AHB_EHCI0] = { 0x060, BIT(1), NULL }, + [CLK_AHB_OHCI0] = { 0x060, BIT(2), NULL }, + [CLK_AHB_EHCI1] = { 0x060, BIT(3), NULL }, + [CLK_AHB_OHCI1] = { 0x060, BIT(4), NULL }, + + [CLK_USB_OHCI0] = { 0x0cc, BIT(6), NULL }, + [CLK_USB_OHCI1] = { 0x0cc, BIT(7), NULL }, + [CLK_USB_PHY] = { 0x0cc, BIT(8), NULL }, +}; + +static struct ccu_reset_map a10_resets[] = { + [RST_USB_PHY0] = { 0x0cc, BIT(0) }, + [RST_USB_PHY1] = { 0x0cc, BIT(1) }, + [RST_USB_PHY2] = { 0x0cc, BIT(2) }, +}; + +static const struct ccu_desc sun4i_a10_ccu_desc = { + .clks = a10_clks, + .num_clks = ARRAY_SIZE(a10_clks), + + .resets = a10_resets, + .num_resets = ARRAY_SIZE(a10_resets), +}; + +static int a10_clk_probe(struct udevice *dev) +{ + struct sunxi_clk_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -ENOMEM; + + priv->desc = (const struct ccu_desc *)dev_get_driver_data(dev); + if (!priv->desc) + return -EINVAL; + + return 0; +} + +static int a10_clk_bind(struct udevice *dev) +{ + return sunxi_reset_bind(dev, 22); +} + +static const struct udevice_id a10_clk_ids[] = { + { .compatible = "allwinner,sun4i-a10-ccu", + .data = (ulong)&sun4i_a10_ccu_desc }, + { .compatible = "allwinner,sun7i-a20-ccu", + .data = (ulong)&sun4i_a10_ccu_desc }, + { } +}; + +U_BOOT_DRIVER(clk_sun4i_a10) = { + .name = "sun4i_a10_ccu", + .id = UCLASS_CLK, + .of_match = a10_clk_ids, + .priv_auto_alloc_size = sizeof(struct sunxi_clk_priv), + .ops = &sunxi_clk_ops, + .probe = a10_clk_probe, + .bind = a10_clk_bind, +};

Add initial clock driver for Allwinner A31.

- Implement USB ahb1 and USB clocks via ccu_clk_map descriptor for A31, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB ahb1 and USB resets via ccu_reset_map descriptor for A31, so it can accessed in common reset deassert and assert functions from reset-sunxi.c

Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/clk/sunxi/Kconfig | 7 +++ drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk_a31.c | 86 +++++++++++++++++++++++++++++++++++++ 3 files changed, 94 insertions(+) create mode 100644 drivers/clk/sunxi/clk_a31.c

diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig index b228c2fa3a..535b0dc02c 100644 --- a/drivers/clk/sunxi/Kconfig +++ b/drivers/clk/sunxi/Kconfig @@ -23,6 +23,13 @@ config CLK_SUN5I_A10S This enables common clock driver support for platforms based on Allwinner A10s/A13 SoC.

+config CLK_SUN6I_A31 + bool "Clock driver for Allwinner A31/A31s" + default MACH_SUN6I + help + This enables common clock driver support for platforms based + on Allwinner A31/A31s SoC. + config CLK_SUN8I_H3 bool "Clock driver for Allwinner H3/H5" default MACH_SUNXI_H3_H5 diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index 466d4b79d6..3cf0071b0c 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -8,5 +8,6 @@ obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o

obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o +obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c new file mode 100644 index 0000000000..c6d82be120 --- /dev/null +++ b/drivers/clk/sunxi/clk_a31.c @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Amarula Solutions B.V. + * Author: Jagan Teki jagan@amarulasolutions.com + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <errno.h> +#include <asm/arch/ccu.h> +#include <dt-bindings/clock/sun6i-a31-ccu.h> +#include <dt-bindings/reset/sun6i-a31-ccu.h> + +static struct ccu_clk_map a31_clks[] = { + [CLK_AHB1_OTG] = { 0x060, BIT(24), NULL }, + [CLK_AHB1_EHCI0] = { 0x060, BIT(26), NULL }, + [CLK_AHB1_EHCI1] = { 0x060, BIT(27), NULL }, + [CLK_AHB1_OHCI0] = { 0x060, BIT(29), NULL }, + [CLK_AHB1_OHCI1] = { 0x060, BIT(30), NULL }, + [CLK_AHB1_OHCI2] = { 0x060, BIT(31), NULL }, + + [CLK_USB_PHY0] = { 0x0cc, BIT(8), NULL }, + [CLK_USB_PHY1] = { 0x0cc, BIT(9), NULL }, + [CLK_USB_PHY2] = { 0x0cc, BIT(10), NULL }, + [CLK_USB_OHCI0] = { 0x0cc, BIT(16), NULL }, + [CLK_USB_OHCI1] = { 0x0cc, BIT(17), NULL }, + [CLK_USB_OHCI2] = { 0x0cc, BIT(18), NULL }, +}; + +static struct ccu_reset_map a31_resets[] = { + [RST_USB_PHY0] = { 0x0cc, BIT(0) }, + [RST_USB_PHY1] = { 0x0cc, BIT(1) }, + [RST_USB_PHY2] = { 0x0cc, BIT(2) }, + + [RST_AHB1_OTG] = { 0x2c0, BIT(24) }, + [RST_AHB1_EHCI0] = { 0x2c0, BIT(26) }, + [RST_AHB1_EHCI1] = { 0x2c0, BIT(27) }, + [RST_AHB1_OHCI0] = { 0x2c0, BIT(29) }, + [RST_AHB1_OHCI1] = { 0x2c0, BIT(30) }, + [RST_AHB1_OHCI2] = { 0x2c0, BIT(31) }, +}; + +static const struct ccu_desc sun6i_a31_ccu_desc = { + .clks = a31_clks, + .num_clks = ARRAY_SIZE(a31_clks), + + .resets = a31_resets, + .num_resets = ARRAY_SIZE(a31_resets), +}; + +static int a31_clk_probe(struct udevice *dev) +{ + struct sunxi_clk_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -ENOMEM; + + priv->desc = (const struct ccu_desc *)dev_get_driver_data(dev); + if (!priv->desc) + return -EINVAL; + + return 0; +} + +static int a31_clk_bind(struct udevice *dev) +{ + return sunxi_reset_bind(dev, 56); +} + +static const struct udevice_id a31_clk_ids[] = { + { .compatible = "allwinner,sun6i-a31-ccu", + .data = (ulong)&sun6i_a31_ccu_desc }, + { } +}; + +U_BOOT_DRIVER(clk_sun6i_a31) = { + .name = "sun6i_a31_ccu", + .id = UCLASS_CLK, + .of_match = a31_clk_ids, + .priv_auto_alloc_size = sizeof(struct sunxi_clk_priv), + .ops = &sunxi_clk_ops, + .probe = a31_clk_probe, + .bind = a31_clk_bind, +};

A33 has separate clock driver in Linux because of few clock differences wrt to A23 like audio etc,. these may not useful for U-Boot so added a33 ccu compatible on existing a23 clock driver.

Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/clk/sunxi/Kconfig | 6 +++--- drivers/clk/sunxi/clk_a23.c | 2 ++ 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig index 54600e8e1f..38ff99d345 100644 --- a/drivers/clk/sunxi/Kconfig +++ b/drivers/clk/sunxi/Kconfig @@ -31,11 +31,11 @@ config CLK_SUN6I_A31 on Allwinner A31/A31s SoC.

config CLK_SUN8I_A23 - bool "Clock driver for Allwinner A23" - default MACH_SUN8I_A23 + bool "Clock driver for Allwinner A23/A33" + default MACH_SUN8I_A23 || MACH_SUN8I_A33 help This enables common clock driver support for platforms based - on Allwinner A23 SoC. + on Allwinner A23/A33 SoC.

config CLK_SUN8I_H3 bool "Clock driver for Allwinner H3/H5" diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c index 799c8ac0aa..ec9834e1a8 100644 --- a/drivers/clk/sunxi/clk_a23.c +++ b/drivers/clk/sunxi/clk_a23.c @@ -65,6 +65,8 @@ static int a23_clk_bind(struct udevice *dev) static const struct udevice_id a23_clk_ids[] = { { .compatible = "allwinner,sun8i-a23-ccu", .data = (ulong)&sun8i_a23_ccu_desc }, + { .compatible = "allwinner,sun8i-a33-ccu", + .data = (ulong)&sun8i_a23_ccu_desc }, { } };

Add initial clock driver for Allwinner R40.

- Implement USB bus and USB clocks via ccu_clk_map descriptor for R40, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB bus and USB resets via ccu_reset_map descriptor for R40, so it can accessed in common reset deassert and assert functions from reset-sunxi.c

Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/clk/sunxi/Kconfig | 7 +++ drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk_r40.c | 89 +++++++++++++++++++++++++++++++++++++ 3 files changed, 97 insertions(+) create mode 100644 drivers/clk/sunxi/clk_r40.c

diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig index 90af70d171..c45a4ba378 100644 --- a/drivers/clk/sunxi/Kconfig +++ b/drivers/clk/sunxi/Kconfig @@ -44,6 +44,13 @@ config CLK_SUN8I_A83T This enables common clock driver support for platforms based on Allwinner A83T SoC.

+config CLK_SUN8I_R40 + bool "Clock driver for Allwinner R40" + default MACH_SUN8I_R40 + help + This enables common clock driver support for platforms based + on Allwinner R40 SoC. + config CLK_SUN8I_H3 bool "Clock driver for Allwinner H3/H5" default MACH_SUNXI_H3_H5 diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index 4a254c8671..61f8b87396 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -11,5 +11,6 @@ obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o +obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c new file mode 100644 index 0000000000..746d6734b2 --- /dev/null +++ b/drivers/clk/sunxi/clk_r40.c @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Amarula Solutions. + * Author: Jagan Teki jagan@amarulasolutions.com + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <errno.h> +#include <asm/arch/ccu.h> +#include <dt-bindings/clock/sun8i-r40-ccu.h> +#include <dt-bindings/reset/sun8i-r40-ccu.h> + +static struct ccu_clk_map r40_clks[] = { + [CLK_BUS_OTG] = { 0x060, BIT(25), NULL }, + [CLK_BUS_EHCI0] = { 0x060, BIT(26), NULL }, + [CLK_BUS_EHCI1] = { 0x060, BIT(27), NULL }, + [CLK_BUS_EHCI2] = { 0x060, BIT(28), NULL }, + [CLK_BUS_OHCI0] = { 0x060, BIT(29), NULL }, + [CLK_BUS_OHCI1] = { 0x060, BIT(30), NULL }, + [CLK_BUS_OHCI2] = { 0x060, BIT(31), NULL }, + + + [CLK_USB_PHY0] = { 0x0cc, BIT(8), NULL }, + [CLK_USB_PHY1] = { 0x0cc, BIT(9), NULL }, + [CLK_USB_PHY2] = { 0x0cc, BIT(10), NULL }, + [CLK_USB_OHCI0] = { 0x0cc, BIT(16), NULL }, + [CLK_USB_OHCI1] = { 0x0cc, BIT(17), NULL }, + [CLK_USB_OHCI2] = { 0x0cc, BIT(18), NULL }, +}; + +static struct ccu_reset_map r40_resets[] = { + [RST_USB_PHY0] = { 0x0cc, BIT(0) }, + [RST_USB_PHY1] = { 0x0cc, BIT(1) }, + [RST_USB_PHY2] = { 0x0cc, BIT(2) }, + + [RST_BUS_OTG] = { 0x2c0, BIT(25) }, + [RST_BUS_EHCI0] = { 0x2c0, BIT(26) }, + [RST_BUS_EHCI1] = { 0x2c0, BIT(27) }, + [RST_BUS_EHCI2] = { 0x2c0, BIT(28) }, + [RST_BUS_OHCI0] = { 0x2c0, BIT(29) }, + [RST_BUS_OHCI1] = { 0x2c0, BIT(30) }, + [RST_BUS_OHCI2] = { 0x2c0, BIT(31) }, +}; + +static const struct ccu_desc sun8i_r40_ccu_desc = { + .clks = r40_clks, + .num_clks = ARRAY_SIZE(r40_clks), + + .resets = r40_resets, + .num_resets = ARRAY_SIZE(r40_resets), +}; + +static int r40_clk_probe(struct udevice *dev) +{ + struct sunxi_clk_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -ENOMEM; + + priv->desc = (const struct ccu_desc *)dev_get_driver_data(dev); + if (!priv->desc) + return -EINVAL; + + return 0; +} + +static int r40_clk_bind(struct udevice *dev) +{ + return sunxi_reset_bind(dev, 80); +} + +static const struct udevice_id r40_clk_ids[] = { + { .compatible = "allwinner,sun8i-r40-ccu", + .data = (ulong)&sun8i_r40_ccu_desc }, + { } +}; + +U_BOOT_DRIVER(clk_sun8i_r40) = { + .name = "sun8i_r40_ccu", + .id = UCLASS_CLK, + .of_match = r40_clk_ids, + .priv_auto_alloc_size = sizeof(struct sunxi_clk_priv), + .ops = &sunxi_clk_ops, + .probe = r40_clk_probe, + .bind = r40_clk_bind, +};

CLK and DM_RESET drivers are now available for most of the Allwinner platforms, so enable in mach-sunxi/Kconfig

Enabling CLK will select DM_RESET by default.

Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- arch/arm/mach-sunxi/Kconfig | 12 ++++++++++++ 1 file changed, 12 insertions(+)

diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 558363b52d..dce81b7d53 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -132,6 +132,7 @@ endif

config MACH_SUNXI_H3_H5 bool + select CLK select DM_I2C select PHY_SUN4I_USB select SUNXI_DE2 @@ -147,6 +148,7 @@ choice config MACH_SUN4I bool "sun4i (Allwinner A10)" select CPU_V7A + select CLK select ARM_CORTEX_CPU_IS_UP select DM_MMC if MMC select DM_SCSI if SCSI @@ -158,6 +160,7 @@ config MACH_SUN4I config MACH_SUN5I bool "sun5i (Allwinner A13)" select CPU_V7A + select CLK select ARM_CORTEX_CPU_IS_UP select DRAM_SUN4I select PHY_SUN4I_USB @@ -171,6 +174,7 @@ config MACH_SUN6I select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT select ARCH_SUPPORT_PSCI + select CLK select DRAM_SUN6I select PHY_SUN4I_USB select SUN6I_P2WI @@ -185,6 +189,7 @@ config MACH_SUN7I select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT select ARCH_SUPPORT_PSCI + select CLK select DRAM_SUN4I select PHY_SUN4I_USB select SUNXI_GEN_SUN4I @@ -197,6 +202,7 @@ config MACH_SUN8I_A23 select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT select ARCH_SUPPORT_PSCI + select CLK select DRAM_SUN8I_A23 select PHY_SUN4I_USB select SUNXI_GEN_SUN6I @@ -210,6 +216,7 @@ config MACH_SUN8I_A33 select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT select ARCH_SUPPORT_PSCI + select CLK select DRAM_SUN8I_A33 select PHY_SUN4I_USB select SUNXI_GEN_SUN6I @@ -220,6 +227,7 @@ config MACH_SUN8I_A33 config MACH_SUN8I_A83T bool "sun8i (Allwinner A83T)" select CPU_V7A + select CLK select DRAM_SUN8I_A83T select PHY_SUN4I_USB select SUNXI_GEN_SUN6I @@ -231,6 +239,7 @@ config MACH_SUN8I_H3 select CPU_V7A select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT + select CLK select ARCH_SUPPORT_PSCI select MACH_SUNXI_H3_H5 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT @@ -241,6 +250,7 @@ config MACH_SUN8I_R40 select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT select ARCH_SUPPORT_PSCI + select CLK select SUNXI_GEN_SUN6I select SUPPORT_SPL select SUNXI_DRAM_DW @@ -252,6 +262,7 @@ config MACH_SUN8I_V3S select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT select ARCH_SUPPORT_PSCI + select CLK select SUNXI_GEN_SUN6I select SUNXI_DRAM_DW select SUNXI_DRAM_DW_16BIT @@ -270,6 +281,7 @@ config MACH_SUN9I config MACH_SUN50I bool "sun50i (Allwinner A64)" select ARM64 + select CLK select DM_I2C select PHY_SUN4I_USB select SUNXI_DE2

Now clock and reset drivers are available for respective SoC's so use clk and reset ops on phy driver.

Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/phy/allwinner/phy-sun4i-usb.c | 77 ++++++++++++++++++++------- 1 file changed, 57 insertions(+), 20 deletions(-)

diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c index a7d7e3f044..f206fa3f5d 100644 --- a/drivers/phy/allwinner/phy-sun4i-usb.c +++ b/drivers/phy/allwinner/phy-sun4i-usb.c @@ -11,10 +11,12 @@ */

#include <common.h> +#include <clk.h> #include <dm.h> #include <dm/device.h> #include <generic-phy.h> #include <phy-sun4i-usb.h> +#include <reset.h> #include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/clock.h> @@ -80,6 +82,7 @@ struct sun4i_usb_phy_cfg { enum sun4i_usb_phy_type type; u32 disc_thresh; u8 phyctl_offset; + bool dedicated_clocks; bool enable_pmu_unk1; bool phy0_dual_route; }; @@ -88,30 +91,21 @@ struct sun4i_usb_phy_info { const char *gpio_vbus; const char *gpio_vbus_det; const char *gpio_id_det; - int rst_mask; } phy_info[] = { { .gpio_vbus = CONFIG_USB0_VBUS_PIN, .gpio_vbus_det = CONFIG_USB0_VBUS_DET, .gpio_id_det = CONFIG_USB0_ID_DET, - .rst_mask = (CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK), }, { .gpio_vbus = CONFIG_USB1_VBUS_PIN, .gpio_vbus_det = NULL, .gpio_id_det = NULL, - .rst_mask = (CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK), }, { .gpio_vbus = CONFIG_USB2_VBUS_PIN, .gpio_vbus_det = NULL, .gpio_id_det = NULL, -#ifdef CONFIG_MACH_SUN8I_A83T - .rst_mask = (CCM_USB_CTRL_HSIC_RST | CCM_USB_CTRL_HSIC_CLK | - CCM_USB_CTRL_12M_CLK), -#else - .rst_mask = (CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK), -#endif }, { .gpio_vbus = CONFIG_USB3_VBUS_PIN, @@ -126,13 +120,13 @@ struct sun4i_usb_phy_plat { int gpio_vbus; int gpio_vbus_det; int gpio_id_det; - int rst_mask; + struct clk clocks; + struct reset_ctl resets; int id; };

struct sun4i_usb_phy_data { void __iomem *base; - struct sunxi_ccm_reg *ccm; const struct sun4i_usb_phy_cfg *cfg; struct sun4i_usb_phy_plat *usb_phy; }; @@ -266,8 +260,19 @@ static int sun4i_usb_phy_init(struct phy *phy) struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev); struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id]; u32 val; + int ret;

- setbits_le32(&data->ccm->usb_clk_cfg, usb_phy->rst_mask); + ret = clk_enable(&usb_phy->clocks); + if (ret) { + dev_err(dev, "failed to enable usb_%ldphy clock\n", phy->id); + return ret; + } + + ret = reset_deassert(&usb_phy->resets); + if (ret) { + dev_err(dev, "failed to deassert usb_%ldreset reset\n", phy->id); + return ret; + }

if (data->cfg->type == sun8i_a83t_phy) { if (phy->id == 0) { @@ -308,6 +313,7 @@ static int sun4i_usb_phy_exit(struct phy *phy) { struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev); struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id]; + int ret;

if (phy->id == 0) { if (data->cfg->type == sun8i_a83t_phy) { @@ -320,7 +326,17 @@ static int sun4i_usb_phy_exit(struct phy *phy)

sun4i_usb_phy_passby(phy, false);

- clrbits_le32(&data->ccm->usb_clk_cfg, usb_phy->rst_mask); + ret = clk_disable(&usb_phy->clocks); + if (ret) { + dev_err(dev, "failed to disable usb_%ldphy clock\n", phy->id); + return ret; + } + + ret = reset_assert(&usb_phy->resets); + if (ret) { + dev_err(dev, "failed to assert usb_%ldreset reset\n", phy->id); + return ret; + }

return 0; } @@ -407,10 +423,6 @@ static int sun4i_usb_phy_probe(struct udevice *dev) if (IS_ERR(data->base)) return PTR_ERR(data->base);

- data->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - if (IS_ERR(data->ccm)) - return PTR_ERR(data->ccm); - data->usb_phy = plat; for (i = 0; i < data->cfg->num_phys; i++) { struct sun4i_usb_phy_plat *phy = &plat[i]; @@ -448,6 +460,24 @@ static int sun4i_usb_phy_probe(struct udevice *dev) sunxi_gpio_set_pull(phy->gpio_id_det, SUNXI_GPIO_PULL_UP); }

+ if (data->cfg->dedicated_clocks) + snprintf(name, sizeof(name), "usb%d_phy", i); + else + strlcpy(name, "usb_phy", sizeof(name)); + + ret = clk_get_by_name(dev, name, &phy->clocks); + if (ret) { + dev_err(dev, "failed to get usb%d_phy clock phandle\n", i); + return ret; + } + + snprintf(name, sizeof(name), "usb%d_reset", i); + ret = reset_get_by_name(dev, name, &phy->resets); + if (ret) { + dev_err(dev, "failed to get usb%d_reset reset phandle\n", i); + return ret; + } + if (i || data->cfg->phy0_dual_route) { snprintf(name, sizeof(name), "pmu%d", i); phy->pmu = (void __iomem *)devfdt_get_addr_name(dev, name); @@ -456,9 +486,6 @@ static int sun4i_usb_phy_probe(struct udevice *dev) }

phy->id = i; - phy->rst_mask = info->rst_mask; - if ((data->cfg->type == sun8i_h3_phy) && (phy->id == 3)) - phy->rst_mask = (BIT(3) | BIT(11)); };

debug("Allwinner Sun4I USB PHY driver loaded\n"); @@ -470,6 +497,7 @@ static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = { .type = sun4i_a10_phy, .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A10, + .dedicated_clocks = false, .enable_pmu_unk1 = false, };

@@ -478,6 +506,7 @@ static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = { .type = sun4i_a10_phy, .disc_thresh = 2, .phyctl_offset = REG_PHYCTL_A10, + .dedicated_clocks = false, .enable_pmu_unk1 = false, };

@@ -486,6 +515,7 @@ static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = { .type = sun6i_a31_phy, .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A10, + .dedicated_clocks = true, .enable_pmu_unk1 = false, };

@@ -494,6 +524,7 @@ static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = { .type = sun4i_a10_phy, .disc_thresh = 2, .phyctl_offset = REG_PHYCTL_A10, + .dedicated_clocks = false, .enable_pmu_unk1 = false, };

@@ -502,6 +533,7 @@ static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = { .type = sun4i_a10_phy, .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A10, + .dedicated_clocks = true, .enable_pmu_unk1 = false, };

@@ -510,6 +542,7 @@ static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = { .type = sun8i_a33_phy, .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A33, + .dedicated_clocks = true, .enable_pmu_unk1 = false, };

@@ -517,6 +550,7 @@ static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = { .num_phys = 3, .type = sun8i_a83t_phy, .phyctl_offset = REG_PHYCTL_A33, + .dedicated_clocks = true, };

static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = { @@ -524,6 +558,7 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = { .type = sun8i_h3_phy, .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A33, + .dedicated_clocks = true, .enable_pmu_unk1 = true, .phy0_dual_route = true, }; @@ -533,6 +568,7 @@ static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = { .type = sun8i_v3s_phy, .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A33, + .dedicated_clocks = true, .enable_pmu_unk1 = true, .phy0_dual_route = true, }; @@ -542,6 +578,7 @@ static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = { .type = sun50i_a64_phy, .disc_thresh = 3, .phyctl_offset = REG_PHYCTL_A33, + .dedicated_clocks = true, .enable_pmu_unk1 = true, .phy0_dual_route = true, };

Now Allwinner platform is all set to use Generic USB controller drivers, so remove the legacy sunxi drivers.

Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/usb/host/Makefile | 2 - drivers/usb/host/ehci-sunxi.c | 204 ----------------------------- drivers/usb/host/ohci-sunxi.c | 233 ---------------------------------- scripts/config_whitelist.txt | 2 - 4 files changed, 441 deletions(-) delete mode 100644 drivers/usb/host/ehci-sunxi.c delete mode 100644 drivers/usb/host/ohci-sunxi.c

diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index cb8c315a15..b62fdbb1d2 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -15,7 +15,6 @@ obj-$(CONFIG_USB_OHCI_DA8XX) += ohci-da8xx.o obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o obj-$(CONFIG_USB_SL811HS) += sl811-hcd.o obj-$(CONFIG_USB_OHCI_EP93XX) += ohci-ep93xx.o -obj-$(CONFIG_USB_OHCI_SUNXI) += ohci-sunxi.o obj-$(CONFIG_USB_OHCI_LPC32XX) += ohci-lpc32xx.o obj-$(CONFIG_USB_OHCI_GENERIC) += ohci-generic.o

@@ -37,7 +36,6 @@ obj-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o obj-$(CONFIG_USB_EHCI_MSM) += ehci-msm.o obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o -obj-$(CONFIG_USB_EHCI_SUNXI) += ehci-sunxi.o obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o obj-$(CONFIG_USB_EHCI_VF) += ehci-vf.o diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c deleted file mode 100644 index 7a79931a97..0000000000 --- a/drivers/usb/host/ehci-sunxi.c +++ /dev/null @@ -1,204 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Sunxi ehci glue - * - * Copyright (C) 2015 Hans de Goede hdegoede@redhat.com - * Copyright (C) 2014 Roman Byshko rbyshko@gmail.com - * - * Based on code from - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - */ - -#include <common.h> -#include <asm/arch/clock.h> -#include <asm/io.h> -#include <dm.h> -#include "ehci.h" -#include <generic-phy.h> - -#ifdef CONFIG_SUNXI_GEN_SUN4I -#define BASE_DIST 0x8000 -#define AHB_CLK_DIST 2 -#else -#define BASE_DIST 0x1000 -#define AHB_CLK_DIST 1 -#endif - -#define SUN6I_AHB_RESET0_CFG_OFFSET 0x2c0 -#define SUN9I_AHB_RESET0_CFG_OFFSET 0x5a0 - -struct ehci_sunxi_cfg { - bool has_reset; - u32 extra_ahb_gate_mask; - u32 reset0_cfg_offset; -}; - -struct ehci_sunxi_priv { - struct ehci_ctrl ehci; - struct sunxi_ccm_reg *ccm; - u32 *reset0_cfg; - int ahb_gate_mask; /* Mask of ahb_gate0 clk gate bits for this hcd */ - struct phy phy; - const struct ehci_sunxi_cfg *cfg; -}; - -static int ehci_usb_probe(struct udevice *dev) -{ - struct usb_platdata *plat = dev_get_platdata(dev); - struct ehci_sunxi_priv *priv = dev_get_priv(dev); - struct ehci_hccr *hccr = (struct ehci_hccr *)devfdt_get_addr(dev); - struct ehci_hcor *hcor; - int extra_ahb_gate_mask = 0; - u8 reg_mask = 0; - int phys, ret; - - priv->cfg = (const struct ehci_sunxi_cfg *)dev_get_driver_data(dev); - priv->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - if (IS_ERR(priv->ccm)) - return PTR_ERR(priv->ccm); - - priv->reset0_cfg = (void *)priv->ccm + - priv->cfg->reset0_cfg_offset; - - phys = dev_count_phandle_with_args(dev, "phys", "#phy-cells"); - if (phys < 0) { - phys = 0; - goto no_phy; - } - - ret = generic_phy_get_by_name(dev, "usb", &priv->phy); - if (ret) { - pr_err("failed to get %s usb PHY\n", dev->name); - return ret; - } - - ret = generic_phy_init(&priv->phy); - if (ret) { - pr_err("failed to init %s USB PHY\n", dev->name); - return ret; - } - - ret = generic_phy_power_on(&priv->phy); - if (ret) { - pr_err("failed to power on %s USB PHY\n", dev->name); - return ret; - } - -no_phy: - /* - * This should go away once we've moved to the driver model for - * clocks resp. phys. - */ - reg_mask = ((uintptr_t)hccr - SUNXI_USB1_BASE) / BASE_DIST; - priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0; - extra_ahb_gate_mask = priv->cfg->extra_ahb_gate_mask; - priv->ahb_gate_mask <<= reg_mask * AHB_CLK_DIST; - extra_ahb_gate_mask <<= reg_mask * AHB_CLK_DIST; - - setbits_le32(&priv->ccm->ahb_gate0, - priv->ahb_gate_mask | extra_ahb_gate_mask); - if (priv->cfg->has_reset) - setbits_le32(priv->reset0_cfg, - priv->ahb_gate_mask | extra_ahb_gate_mask); - - hcor = (struct ehci_hcor *)((uintptr_t)hccr + - HC_LENGTH(ehci_readl(&hccr->cr_capbase))); - - return ehci_register(dev, hccr, hcor, NULL, 0, plat->init_type); -} - -static int ehci_usb_remove(struct udevice *dev) -{ - struct ehci_sunxi_priv *priv = dev_get_priv(dev); - int ret; - - if (generic_phy_valid(&priv->phy)) { - ret = generic_phy_exit(&priv->phy); - if (ret) { - pr_err("failed to exit %s USB PHY\n", dev->name); - return ret; - } - } - - ret = ehci_deregister(dev); - if (ret) - return ret; - - if (priv->cfg->has_reset) - clrbits_le32(priv->reset0_cfg, priv->ahb_gate_mask); - clrbits_le32(&priv->ccm->ahb_gate0, priv->ahb_gate_mask); - - return 0; -} - -static const struct ehci_sunxi_cfg sun4i_a10_cfg = { - .has_reset = false, -}; - -static const struct ehci_sunxi_cfg sun6i_a31_cfg = { - .has_reset = true, - .reset0_cfg_offset = SUN6I_AHB_RESET0_CFG_OFFSET, -}; - -static const struct ehci_sunxi_cfg sun8i_h3_cfg = { - .has_reset = true, - .extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0, - .reset0_cfg_offset = SUN6I_AHB_RESET0_CFG_OFFSET, -}; - -static const struct ehci_sunxi_cfg sun9i_a80_cfg = { - .has_reset = true, - .reset0_cfg_offset = SUN9I_AHB_RESET0_CFG_OFFSET, -}; - -static const struct udevice_id ehci_usb_ids[] = { - { - .compatible = "allwinner,sun4i-a10-ehci", - .data = (ulong)&sun4i_a10_cfg, - }, - { - .compatible = "allwinner,sun5i-a13-ehci", - .data = (ulong)&sun4i_a10_cfg, - }, - { - .compatible = "allwinner,sun6i-a31-ehci", - .data = (ulong)&sun6i_a31_cfg, - }, - { - .compatible = "allwinner,sun7i-a20-ehci", - .data = (ulong)&sun4i_a10_cfg, - }, - { - .compatible = "allwinner,sun8i-a23-ehci", - .data = (ulong)&sun6i_a31_cfg, - }, - { - .compatible = "allwinner,sun8i-a83t-ehci", - .data = (ulong)&sun6i_a31_cfg, - }, - { - .compatible = "allwinner,sun8i-h3-ehci", - .data = (ulong)&sun8i_h3_cfg, - }, - { - .compatible = "allwinner,sun9i-a80-ehci", - .data = (ulong)&sun9i_a80_cfg, - }, - { - .compatible = "allwinner,sun50i-a64-ehci", - .data = (ulong)&sun8i_h3_cfg, - }, - { /* sentinel */ } -}; - -U_BOOT_DRIVER(ehci_sunxi) = { - .name = "ehci_sunxi", - .id = UCLASS_USB, - .of_match = ehci_usb_ids, - .probe = ehci_usb_probe, - .remove = ehci_usb_remove, - .ops = &ehci_usb_ops, - .platdata_auto_alloc_size = sizeof(struct usb_platdata), - .priv_auto_alloc_size = sizeof(struct ehci_sunxi_priv), - .flags = DM_FLAG_ALLOC_PRIV_DMA, -}; diff --git a/drivers/usb/host/ohci-sunxi.c b/drivers/usb/host/ohci-sunxi.c deleted file mode 100644 index bb3c2475df..0000000000 --- a/drivers/usb/host/ohci-sunxi.c +++ /dev/null @@ -1,233 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Sunxi ohci glue - * - * Copyright (C) 2015 Hans de Goede hdegoede@redhat.com - * - * Based on code from - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - */ - -#include <common.h> -#include <asm/arch/clock.h> -#include <asm/io.h> -#include <dm.h> -#include <usb.h> -#include "ohci.h" -#include <generic-phy.h> - -#ifdef CONFIG_SUNXI_GEN_SUN4I -#define BASE_DIST 0x8000 -#define AHB_CLK_DIST 2 -#else -#define BASE_DIST 0x1000 -#define AHB_CLK_DIST 1 -#endif - -#define SUN6I_AHB_RESET0_CFG_OFFSET 0x2c0 -#define SUN9I_AHB_RESET0_CFG_OFFSET 0x5a0 - -struct ohci_sunxi_cfg { - bool has_reset; - u32 extra_ahb_gate_mask; - u32 extra_usb_gate_mask; - u32 reset0_cfg_offset; -}; - -struct ohci_sunxi_priv { - ohci_t ohci; - struct sunxi_ccm_reg *ccm; - u32 *reset0_cfg; - int ahb_gate_mask; /* Mask of ahb_gate0 clk gate bits for this hcd */ - int usb_gate_mask; /* Mask of usb_clk_cfg clk gate bits for this hcd */ - struct phy phy; - const struct ohci_sunxi_cfg *cfg; -}; - -static fdt_addr_t last_ohci_addr = 0; - -static int ohci_usb_probe(struct udevice *dev) -{ - struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev); - struct ohci_sunxi_priv *priv = dev_get_priv(dev); - struct ohci_regs *regs = (struct ohci_regs *)devfdt_get_addr(dev); - int extra_ahb_gate_mask = 0; - u8 reg_mask = 0; - int phys, ret; - - if ((fdt_addr_t)regs > last_ohci_addr) - last_ohci_addr = (fdt_addr_t)regs; - - priv->cfg = (const struct ohci_sunxi_cfg *)dev_get_driver_data(dev); - priv->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - if (IS_ERR(priv->ccm)) - return PTR_ERR(priv->ccm); - - priv->reset0_cfg = (void *)priv->ccm + - priv->cfg->reset0_cfg_offset; - - phys = dev_count_phandle_with_args(dev, "phys", "#phy-cells"); - if (phys < 0) { - phys = 0; - goto no_phy; - } - - ret = generic_phy_get_by_name(dev, "usb", &priv->phy); - if (ret) { - pr_err("failed to get %s usb PHY\n", dev->name); - return ret; - } - - ret = generic_phy_init(&priv->phy); - if (ret) { - pr_err("failed to init %s USB PHY\n", dev->name); - return ret; - } - - ret = generic_phy_power_on(&priv->phy); - if (ret) { - pr_err("failed to power on %s USB PHY\n", dev->name); - return ret; - } - -no_phy: - bus_priv->companion = true; - - /* - * This should go away once we've moved to the driver model for - * clocks resp. phys. - */ - reg_mask = ((uintptr_t)regs - (SUNXI_USB1_BASE + 0x400)) / BASE_DIST; - priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0; - extra_ahb_gate_mask = priv->cfg->extra_ahb_gate_mask; - priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK; - priv->ahb_gate_mask <<= reg_mask * AHB_CLK_DIST; - extra_ahb_gate_mask <<= reg_mask * AHB_CLK_DIST; - priv->usb_gate_mask <<= reg_mask; - - setbits_le32(&priv->ccm->ahb_gate0, - priv->ahb_gate_mask | extra_ahb_gate_mask); - setbits_le32(&priv->ccm->usb_clk_cfg, - priv->usb_gate_mask | priv->cfg->extra_usb_gate_mask); - if (priv->cfg->has_reset) - setbits_le32(priv->reset0_cfg, - priv->ahb_gate_mask | extra_ahb_gate_mask); - - return ohci_register(dev, regs); -} - -static int ohci_usb_remove(struct udevice *dev) -{ - struct ohci_sunxi_priv *priv = dev_get_priv(dev); - fdt_addr_t base_addr = devfdt_get_addr(dev); - int ret; - - if (generic_phy_valid(&priv->phy)) { - ret = generic_phy_exit(&priv->phy); - if (ret) { - pr_err("failed to exit %s USB PHY\n", dev->name); - return ret; - } - } - - ret = ohci_deregister(dev); - if (ret) - return ret; - - if (priv->cfg->has_reset) - clrbits_le32(priv->reset0_cfg, priv->ahb_gate_mask); - /* - * On the A64 CLK_USB_OHCI0 is the parent of CLK_USB_OHCI1, so - * we have to wait with bringing down any clock until the last - * OHCI controller is removed. - */ - if (!priv->cfg->extra_usb_gate_mask || base_addr == last_ohci_addr) { - u32 usb_gate_mask = priv->usb_gate_mask; - - usb_gate_mask |= priv->cfg->extra_usb_gate_mask; - clrbits_le32(&priv->ccm->usb_clk_cfg, usb_gate_mask); - } - - clrbits_le32(&priv->ccm->ahb_gate0, priv->ahb_gate_mask); - - return 0; -} - -static const struct ohci_sunxi_cfg sun4i_a10_cfg = { - .has_reset = false, -}; - -static const struct ohci_sunxi_cfg sun6i_a31_cfg = { - .has_reset = true, - .reset0_cfg_offset = SUN6I_AHB_RESET0_CFG_OFFSET, -}; - -static const struct ohci_sunxi_cfg sun8i_h3_cfg = { - .has_reset = true, - .extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0, - .reset0_cfg_offset = SUN6I_AHB_RESET0_CFG_OFFSET, -}; - -static const struct ohci_sunxi_cfg sun9i_a80_cfg = { - .has_reset = true, - .reset0_cfg_offset = SUN9I_AHB_RESET0_CFG_OFFSET, -}; - -static const struct ohci_sunxi_cfg sun50i_a64_cfg = { - .has_reset = true, - .extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0, - .extra_usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK, - .reset0_cfg_offset = SUN6I_AHB_RESET0_CFG_OFFSET, -}; - -static const struct udevice_id ohci_usb_ids[] = { - { - .compatible = "allwinner,sun4i-a10-ohci", - .data = (ulong)&sun4i_a10_cfg, - }, - { - .compatible = "allwinner,sun5i-a13-ohci", - .data = (ulong)&sun4i_a10_cfg, - }, - { - .compatible = "allwinner,sun6i-a31-ohci", - .data = (ulong)&sun6i_a31_cfg, - }, - { - .compatible = "allwinner,sun7i-a20-ohci", - .data = (ulong)&sun4i_a10_cfg, - }, - { - .compatible = "allwinner,sun8i-a23-ohci", - .data = (ulong)&sun6i_a31_cfg, - }, - { - .compatible = "allwinner,sun8i-a83t-ohci", - .data = (ulong)&sun6i_a31_cfg, - }, - { - .compatible = "allwinner,sun8i-h3-ohci", - .data = (ulong)&sun8i_h3_cfg, - }, - { - .compatible = "allwinner,sun9i-a80-ohci", - .data = (ulong)&sun9i_a80_cfg, - }, - { - .compatible = "allwinner,sun50i-a64-ohci", - .data = (ulong)&sun50i_a64_cfg, - }, - { /* sentinel */ } -}; - -U_BOOT_DRIVER(usb_ohci) = { - .name = "ohci_sunxi", - .id = UCLASS_USB, - .of_match = ohci_usb_ids, - .probe = ohci_usb_probe, - .remove = ohci_usb_remove, - .ops = &ohci_usb_ops, - .platdata_auto_alloc_size = sizeof(struct usb_platdata), - .priv_auto_alloc_size = sizeof(struct ohci_sunxi_priv), - .flags = DM_FLAG_ALLOC_PRIV_DMA, -}; diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 0d60da3f28..4cca3d1c73 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -4611,7 +4611,6 @@ CONFIG_USB_EHCI_MX5 CONFIG_USB_EHCI_MXC CONFIG_USB_EHCI_MXS CONFIG_USB_EHCI_SPEAR -CONFIG_USB_EHCI_SUNXI CONFIG_USB_EHCI_TEGRA CONFIG_USB_EHCI_TXFIFO_THRESH CONFIG_USB_EHCI_VCT @@ -4653,7 +4652,6 @@ CONFIG_USB_OHCI CONFIG_USB_OHCI_EP93XX CONFIG_USB_OHCI_LPC32XX CONFIG_USB_OHCI_NEW -CONFIG_USB_OHCI_SUNXI CONFIG_USB_OTG CONFIG_USB_OTG_BLACKLIST_HUB CONFIG_USB_PHY_CFG_BASE

Implement direct MMC clocks for all Allwinner SoC clock drivers via clock map descriptor table.

This includes adding ccu_clk_set_rate function pointer, which indeed support CLK set_rate API, so update clock handling in sunxi_mmc driver to support both no-dm and dm code.

Cc: Jaehoon Chung jh80.chung@samsung.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- arch/arm/include/asm/arch-sunxi/ccu.h | 10 +++++ drivers/clk/sunxi/clk_a10.c | 5 +++ drivers/clk/sunxi/clk_a10s.c | 6 +++ drivers/clk/sunxi/clk_a23.c | 6 +++ drivers/clk/sunxi/clk_a31.c | 5 +++ drivers/clk/sunxi/clk_a64.c | 4 ++ drivers/clk/sunxi/clk_a83t.c | 4 ++ drivers/clk/sunxi/clk_h3.c | 4 ++ drivers/clk/sunxi/clk_r40.c | 4 ++ drivers/clk/sunxi/clk_sunxi.c | 19 +++++++++ drivers/clk/sunxi/clk_v3s.c | 4 ++ drivers/mmc/sunxi_mmc.c | 58 +++++++++++++++++---------- 12 files changed, 107 insertions(+), 22 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/ccu.h b/arch/arm/include/asm/arch-sunxi/ccu.h index bacd052ef3..4e30ab330c 100644 --- a/arch/arm/include/asm/arch-sunxi/ccu.h +++ b/arch/arm/include/asm/arch-sunxi/ccu.h @@ -60,6 +60,16 @@ struct sunxi_clk_priv {

extern struct clk_ops sunxi_clk_ops;

+/** + * mmc_clk_set_rate - mmc clock set rate + * + * @base: clock register base address + * @bit: clock bit value + * @rate: clock input rate in Hz + * @return 0, or -ve error code. + */ +int mmc_clk_set_rate(void *base, u32 bit, ulong rate); + /** * sunxi_reset_bind() - reset binding * diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c index fb11231dd1..55176bc174 100644 --- a/drivers/clk/sunxi/clk_a10.c +++ b/drivers/clk/sunxi/clk_a10.c @@ -23,6 +23,11 @@ static struct ccu_clk_map a10_clks[] = { [CLK_AHB_MMC2] = { 0x060, BIT(10), NULL }, [CLK_AHB_MMC3] = { 0x060, BIT(11), NULL },

+ [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, + [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, + [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate }, + [CLK_MMC3] = { 0x094, BIT(31), &mmc_clk_set_rate }, + [CLK_USB_OHCI0] = { 0x0cc, BIT(6), NULL }, [CLK_USB_OHCI1] = { 0x0cc, BIT(7), NULL }, [CLK_USB_PHY] = { 0x0cc, BIT(8), NULL }, diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c index bc4ae7352b..fbac0ad751 100644 --- a/drivers/clk/sunxi/clk_a10s.c +++ b/drivers/clk/sunxi/clk_a10s.c @@ -20,6 +20,12 @@ static struct ccu_clk_map a10s_clks[] = { [CLK_AHB_MMC1] = { 0x060, BIT(9), NULL }, [CLK_AHB_MMC2] = { 0x060, BIT(10), NULL },

+#ifdef CONFIG_MMC + [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, + [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, + [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate }, +#endif + [CLK_USB_OHCI] = { 0x0cc, BIT(6), NULL }, [CLK_USB_PHY0] = { 0x0cc, BIT(8), NULL }, [CLK_USB_PHY1] = { 0x0cc, BIT(9), NULL }, diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c index 62770a58fe..0b5406c5b3 100644 --- a/drivers/clk/sunxi/clk_a23.c +++ b/drivers/clk/sunxi/clk_a23.c @@ -20,6 +20,12 @@ static struct ccu_clk_map a23_clks[] = { [CLK_BUS_EHCI] = { 0x060, BIT(26), NULL }, [CLK_BUS_OHCI] = { 0x060, BIT(29), NULL },

+#ifdef CONFIG_MMC + [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, + [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, + [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate }, +#endif + [CLK_USB_PHY0] = { 0x0cc, BIT(8), NULL }, [CLK_USB_PHY1] = { 0x0cc, BIT(9), NULL }, [CLK_USB_HSIC] = { 0x0cc, BIT(10), NULL }, diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c index f314feff69..3c807bde77 100644 --- a/drivers/clk/sunxi/clk_a31.c +++ b/drivers/clk/sunxi/clk_a31.c @@ -24,6 +24,11 @@ static struct ccu_clk_map a31_clks[] = { [CLK_AHB1_OHCI1] = { 0x060, BIT(30), NULL }, [CLK_AHB1_OHCI2] = { 0x060, BIT(31), NULL },

+ [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, + [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, + [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate }, + [CLK_MMC3] = { 0x094, BIT(31), &mmc_clk_set_rate }, + [CLK_USB_PHY0] = { 0x0cc, BIT(8), NULL }, [CLK_USB_PHY1] = { 0x0cc, BIT(9), NULL }, [CLK_USB_PHY2] = { 0x0cc, BIT(10), NULL }, diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c index 71f3510c74..62cd6d6464 100644 --- a/drivers/clk/sunxi/clk_a64.c +++ b/drivers/clk/sunxi/clk_a64.c @@ -22,6 +22,10 @@ static struct ccu_clk_map a64_clks[] = { [CLK_BUS_OHCI0] = { 0x060, BIT(28), NULL }, [CLK_BUS_OHCI1] = { 0x060, BIT(29), NULL },

+ [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, + [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, + [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate }, + [CLK_USB_PHY0] = { 0x0cc, BIT(8), NULL }, [CLK_USB_PHY1] = { 0x0cc, BIT(9), NULL }, [CLK_USB_HSIC] = { 0x0cc, BIT(10), NULL }, diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c index cc18975a06..a2e0ac7a26 100644 --- a/drivers/clk/sunxi/clk_a83t.c +++ b/drivers/clk/sunxi/clk_a83t.c @@ -21,6 +21,10 @@ static struct ccu_clk_map a83t_clks[] = { [CLK_BUS_EHCI1] = { 0x060, BIT(27), NULL }, [CLK_BUS_OHCI0] = { 0x060, BIT(29), NULL },

+ [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, + [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, + [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate }, + [CLK_USB_PHY0] = { 0x0cc, BIT(8), NULL }, [CLK_USB_PHY1] = { 0x0cc, BIT(9), NULL }, [CLK_USB_HSIC] = { 0x0cc, BIT(10), NULL }, diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c index 85dd06ee2d..f467187c01 100644 --- a/drivers/clk/sunxi/clk_h3.c +++ b/drivers/clk/sunxi/clk_h3.c @@ -26,6 +26,10 @@ static struct ccu_clk_map h3_clks[] = { [CLK_BUS_OHCI2] = { 0x060, BIT(30), NULL }, [CLK_BUS_OHCI3] = { 0x060, BIT(31), NULL },

+ [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, + [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, + [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate }, + [CLK_USB_PHY0] = { 0x0cc, BIT(8), NULL }, [CLK_USB_PHY1] = { 0x0cc, BIT(9), NULL }, [CLK_USB_PHY2] = { 0x0cc, BIT(10), NULL }, diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c index 006aa138b6..9273f3b7ea 100644 --- a/drivers/clk/sunxi/clk_r40.c +++ b/drivers/clk/sunxi/clk_r40.c @@ -25,6 +25,10 @@ static struct ccu_clk_map r40_clks[] = { [CLK_BUS_OHCI1] = { 0x060, BIT(30), NULL }, [CLK_BUS_OHCI2] = { 0x060, BIT(31), NULL },

+ [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, + [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, + [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate }, + [CLK_MMC3] = { 0x094, BIT(31), &mmc_clk_set_rate },

[CLK_USB_PHY0] = { 0x0cc, BIT(8), NULL }, [CLK_USB_PHY1] = { 0x0cc, BIT(9), NULL }, diff --git a/drivers/clk/sunxi/clk_sunxi.c b/drivers/clk/sunxi/clk_sunxi.c index 791b1ac7f2..ca147ec9cc 100644 --- a/drivers/clk/sunxi/clk_sunxi.c +++ b/drivers/clk/sunxi/clk_sunxi.c @@ -12,6 +12,24 @@ #include <asm/arch/ccu.h> #include <linux/log2.h>

+static ulong sunxi_clk_set_rate(struct clk *clk, ulong rate) +{ + struct sunxi_clk_priv *priv = dev_get_priv(clk->dev); + struct ccu_clk_map *map = &priv->desc->clks[clk->id]; + u32 *base; + + if (!map->ccu_clk_set_rate) { + debug("%s (CLK#%ld) unhandled\n", __func__, clk->id); + return 0; + } + + debug("%s(#%ld) off#0x%x, BIT(%d)\n", __func__, + clk->id, map->off, ilog2(map->bit)); + + base = priv->base + map->off; + return map->ccu_clk_set_rate(base, map->bit, rate); +} + static int sunxi_clk_enable(struct clk *clk) { struct sunxi_clk_priv *priv = dev_get_priv(clk->dev); @@ -55,4 +73,5 @@ static int sunxi_clk_disable(struct clk *clk) struct clk_ops sunxi_clk_ops = { .enable = sunxi_clk_enable, .disable = sunxi_clk_disable, + .set_rate = sunxi_clk_set_rate, }; diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c index ab2cc45640..e0d757debe 100644 --- a/drivers/clk/sunxi/clk_v3s.c +++ b/drivers/clk/sunxi/clk_v3s.c @@ -18,6 +18,10 @@ static struct ccu_clk_map v3s_clks[] = { [CLK_BUS_MMC2] = { 0x060, BIT(10), NULL }, [CLK_BUS_OTG] = { 0x060, BIT(24), NULL },

+ [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, + [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, + [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate }, + [CLK_USB_PHY0] = { 0x0cc, BIT(8), NULL }, };

diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 39f15eb423..bf82014a64 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -13,6 +13,7 @@ #include <malloc.h> #include <mmc.h> #include <asm/io.h> +#include <asm/arch/ccu.h> #include <asm/arch/clock.h> #include <asm/arch/cpu.h> #include <asm/arch/gpio.h> @@ -34,6 +35,8 @@ struct sunxi_mmc_priv { struct mmc_config cfg; };

+bool new_mode; + #if !CONFIG_IS_ENABLED(DM_MMC) /* support 4 mmc hosts */ struct sunxi_mmc_priv mmc_host[4]; @@ -95,23 +98,19 @@ static int mmc_resource_init(int sdc_no) } #endif

-static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) +int mmc_clk_set_rate(void *base, u32 bit, ulong rate) { unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly; - bool new_mode = false; u32 val = 0;

- if (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && (priv->mmc_no == 2)) - new_mode = true; - /* * The MMC clock has an extra /2 post-divider when operating in the new * mode. */ if (new_mode) - hz = hz * 2; + rate = rate * 2;

- if (hz <= 24000000) { + if (rate <= 24000000) { pll = CCM_MMC_CTRL_OSCM24; pll_hz = 24000000; } else { @@ -127,8 +126,8 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) #endif }

- div = pll_hz / hz; - if (pll_hz % hz) + div = pll_hz / rate; + if (pll_hz % rate) div++;

n = 0; @@ -138,32 +137,31 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) }

if (n > 3) { - printf("mmc %u error cannot set clock to %u\n", priv->mmc_no, - hz); + printf("mmc error cannot set clock to %ld\n", rate); return -1; }

/* determine delays */ - if (hz <= 400000) { + if (rate <= 400000) { oclk_dly = 0; sclk_dly = 0; - } else if (hz <= 25000000) { + } else if (rate <= 25000000) { oclk_dly = 0; sclk_dly = 5; #ifdef CONFIG_MACH_SUN9I - } else if (hz <= 52000000) { + } else if (rate <= 52000000) { oclk_dly = 5; sclk_dly = 4; } else { - /* hz > 52000000 */ + /* rate > 52000000 */ oclk_dly = 2; sclk_dly = 4; #else - } else if (hz <= 52000000) { + } else if (rate <= 52000000) { oclk_dly = 3; sclk_dly = 4; } else { - /* hz > 52000000 */ + /* rate > 52000000 */ oclk_dly = 1; sclk_dly = 4; #endif @@ -172,22 +170,35 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) if (new_mode) { #ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE val = CCM_MMC_CTRL_MODE_SEL_NEW; - setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW); #endif } else { val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) | CCM_MMC_CTRL_SCLK_DLY(sclk_dly); }

- writel(CCM_MMC_CTRL_ENABLE| pll | CCM_MMC_CTRL_N(n) | - CCM_MMC_CTRL_M(div) | val, priv->mclkreg); + writel(bit | pll | CCM_MMC_CTRL_N(n) | + CCM_MMC_CTRL_M(div) | val, base);

- debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n", - priv->mmc_no, hz, pll_hz, 1u << n, div, pll_hz / (1u << n) / div); + debug("mmc set mod-clk req %ld parent %u n %u m %u rate %u\n", + rate, pll_hz, 1u << n, div, pll_hz / (1u << n) / div);

return 0; }

+static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) +{ +#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(CLK) +#else + if (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && (priv->mmc_no == 2)) + new_mode = true; + + if (new_mode) + setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW); + + return mmc_clk_set_rate(priv->mclkreg, CCM_MMC_CTRL_ENABLE, hz); +#endif +} + static int mmc_update_clk(struct sunxi_mmc_priv *priv) { unsigned int cmd; @@ -599,6 +610,9 @@ static int sunxi_mmc_probe(struct udevice *dev) cfg->f_min = 400000; cfg->f_max = 52000000;

+ if (device_is_compatible(dev, "allwinner,sun8i-a83t-emmc")) + new_mode = true; + priv->reg = (void *)dev_read_addr(dev);

/* We don't have a sunxi clock driver so find the clock address here */

Reset is an optional for some controllers with some families of CPU's with same SoC where the common IP driver can handle to drive the entire SoC families. optional reset get by name is useful for those drivers to make common way of reset handling.

Example, In Allwinner SoC with MMC controllers has no reset for Sun4i, 5i, 7i but reset have reset.

Cc: Simon Glass sjg@chromium.org Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/reset/reset-uclass.c | 18 ++++++++++++++++++ include/reset.h | 25 +++++++++++++++++++++++++ 2 files changed, 43 insertions(+)

diff --git a/drivers/reset/reset-uclass.c b/drivers/reset/reset-uclass.c index 99881b8b99..6320efcb49 100644 --- a/drivers/reset/reset-uclass.c +++ b/drivers/reset/reset-uclass.c @@ -138,6 +138,24 @@ int reset_get_by_name(struct udevice *dev, const char *name, return reset_get_by_index(dev, index, reset_ctl); }

+int reset_get_by_name_optional(struct udevice *dev, const char *name, + struct reset_ctl *reset_ctl, bool optional) +{ + int index; + + debug("%s(dev=%p, name=%s, reset_ctl=%p)\n", __func__, dev, name, + reset_ctl); + reset_ctl->dev = NULL; + + index = dev_read_stringlist_search(dev, "reset-names", name); + if (index < 0) { + debug("fdt_stringlist_search() failed: %d\n", index); + return optional ? 0 : index; + } + + return reset_get_by_index(dev, index, reset_ctl); +} + int reset_request(struct reset_ctl *reset_ctl) { struct reset_ops *ops = reset_dev_ops(reset_ctl->dev); diff --git a/include/reset.h b/include/reset.h index a7bbc1c331..a5af31f549 100644 --- a/include/reset.h +++ b/include/reset.h @@ -132,6 +132,23 @@ int reset_get_bulk(struct udevice *dev, struct reset_ctl_bulk *bulk); int reset_get_by_name(struct udevice *dev, const char *name, struct reset_ctl *reset_ctl);

+/** + * reset_get_by_name_optional - Get/request a reset signal by name optionally. + * + * This look up and requests a reset signal similar to reset_get_by_name() + * but with optional flag. + * + * @dev: The client device. + * @name: The name of the reset signal to request, within the client's + * list of reset signals. + * @reset_ctl: A pointer to a reset control struct to initialize. + * @optional: Optional flag, true if reset is optional, false if reset is + * necessary which is same as reset_get_by_name() + * @return 0 if OK, or a negative error code. + */ +int reset_get_by_name_optional(struct udevice *dev, const char *name, + struct reset_ctl *reset_ctl, bool optional); + /** * reset_request - Request a reset signal. * @@ -254,6 +271,14 @@ static inline int reset_get_by_name(struct udevice *dev, const char *name, return -ENOTSUPP; }

+static inline int reset_get_by_name_optional(struct udevice *dev, + const char *name, + struct reset_ctl *reset_ctl, + bool optional) +{ + return -ENOTSUPP; +} + static inline int reset_free(struct reset_ctl *reset_ctl) { return 0;

Now CLK and RESET driver for Allwinner SoC are available, so add the relevant operations on mmc sunxi driver.

Cc: Jaehoon Chung jh80.chung@samsung.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/mmc/sunxi_mmc.c | 60 +++++++++++++++++++++++++++++++---------- 1 file changed, 46 insertions(+), 14 deletions(-)

diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index bf82014a64..3011ec9498 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -8,10 +8,12 @@ */

#include <common.h> +#include <clk.h> #include <dm.h> #include <errno.h> #include <malloc.h> #include <mmc.h> +#include <reset.h> #include <asm/io.h> #include <asm/arch/ccu.h> #include <asm/arch/clock.h> @@ -26,8 +28,12 @@ struct sunxi_mmc_plat { };

struct sunxi_mmc_priv { +#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(CLK) + struct clk mmc_clk; +#else unsigned mmc_no; uint32_t *mclkreg; +#endif unsigned fatal_err; struct gpio_desc cd_gpio; /* Change Detect GPIO */ int cd_inverted; /* Inverted Card Detect */ @@ -188,6 +194,15 @@ int mmc_clk_set_rate(void *base, u32 bit, ulong rate) static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) { #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(CLK) + int ret; + + ret = clk_set_rate(&priv->mmc_clk, hz); + if (ret) { + dev_err(dev, "failed to set rate for mmc_clk\n"); + return ret; + } + + return ret; #else if (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && (priv->mmc_no == 2)) new_mode = true; @@ -379,7 +394,7 @@ static int sunxi_mmc_send_cmd_common(struct sunxi_mmc_priv *priv, writel(data->blocks * data->blocksize, &priv->reg->bytecnt); }

- debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", priv->mmc_no, + debug("mmc cmd %d(0x%08x), arg 0x%08x\n", cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg); writel(cmd->cmdarg, &priv->reg->arg);

@@ -591,8 +606,8 @@ static int sunxi_mmc_probe(struct udevice *dev) struct sunxi_mmc_plat *plat = dev_get_platdata(dev); struct sunxi_mmc_priv *priv = dev_get_priv(dev); struct mmc_config *cfg = &plat->cfg; - struct ofnode_phandle_args args; - u32 *gate_reg; + struct clk ahb_clk; + struct reset_ctl reset; int bus_width, ret;

cfg->name = dev->name; @@ -615,20 +630,37 @@ static int sunxi_mmc_probe(struct udevice *dev)

priv->reg = (void *)dev_read_addr(dev);

- /* We don't have a sunxi clock driver so find the clock address here */ - ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0, - 1, &args); - if (ret) + ret = clk_get_by_name(dev, "ahb", &ahb_clk); + if (ret) { + dev_err(dev, "falied to get ahb clock\n"); return ret; - priv->mclkreg = (u32 *)ofnode_get_addr(args.node); + }

- ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0, - 0, &args); - if (ret) + ret = clk_get_by_name(dev, "mmc", &priv->mmc_clk); + if (ret) { + dev_err(dev, "falied to get mmc clock\n"); return ret; - gate_reg = (u32 *)ofnode_get_addr(args.node); - setbits_le32(gate_reg, 1 << args.args[0]); - priv->mmc_no = args.args[0] - 8; + } + + ret = reset_get_by_name_optional(dev, "ahb", &reset, true); + if (ret) { + dev_err(dev, "falied to get ahb reset\n"); + return ret; + } + + ret = clk_enable(&ahb_clk); + if (ret) { + dev_err(dev, "failed to enable ahb clock\n"); + return ret; + } + + if (reset_valid(&reset)) { + ret = reset_deassert(&reset); + if (ret) { + dev_err(dev, "failed to deassert ahb reset\n"); + return ret; + } + }

ret = mmc_set_mod_clk(priv, 24000000); if (ret)

Usually eMMC is default env fat device for environment, if MMC_SUNXI_SLOT_EXTRA != 1 Sunxi always probed emmc device as 1. but with DM_MMC it can be more possible to probe eMMC as device 2 since for most of the sunxi platforms eMMC is configured mmc2.

So update the env default device as 2 if DM_MMC and MMC_SUNXI_SLOT_EXTRA != 1 but some boards may not use all possible mmc devices or partly disabled in DT, for those update the device in board specific defconfig.

Cc: Olliver Schinagl oliver@schinagl.nl Cc: Hans de Goede hdegoede@redhat.com Cc: Marcus Cooper codekipper@gmail.com Cc: Stefan Mavrodiev stefan@olimex.com Cc: Paul Kocialkowski contact@paulk.fr Cc: Chen-Yu Tsai wens@csie.org Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 + configs/A20-OLinuXino_MICRO-eMMC_defconfig | 1 + configs/A20-OLinuXino_MICRO_defconfig | 1 + configs/A20-Olimex-SOM-EVB_defconfig | 1 + configs/A20-Olimex-SOM204-EVB-eMMC_defconfig | 1 + configs/Mele_M3_defconfig | 1 + configs/Orangepi_mini_defconfig | 1 + configs/Sinlinx_SinA33_defconfig | 1 + configs/Yones_Toptech_BD1078_defconfig | 1 + configs/amarula_a64_relic_defconfig | 1 + env/Kconfig | 3 ++- 11 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig index 8cedf9cf24..bc5820263c 100644 --- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig +++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig @@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 CONFIG_MMC0_CD_PIN="PH1" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto" CONFIG_USB0_VBUS_PIN="PC17" CONFIG_USB0_VBUS_DET="PH5" CONFIG_I2C1_ENABLE=y diff --git a/configs/A20-OLinuXino_MICRO-eMMC_defconfig b/configs/A20-OLinuXino_MICRO-eMMC_defconfig index f7e7cbab0a..1552960d88 100644 --- a/configs/A20-OLinuXino_MICRO-eMMC_defconfig +++ b/configs/A20-OLinuXino_MICRO-eMMC_defconfig @@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 CONFIG_MMC0_CD_PIN="PH1" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto" CONFIG_I2C1_ENABLE=y CONFIG_VIDEO_VGA=y CONFIG_SATAPWR="PB8" diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig index 8dcbdc08f9..b5f1b7efe2 100644 --- a/configs/A20-OLinuXino_MICRO_defconfig +++ b/configs/A20-OLinuXino_MICRO_defconfig @@ -6,6 +6,7 @@ CONFIG_DRAM_CLK=384 CONFIG_MMC0_CD_PIN="PH1" CONFIG_MMC3_CD_PIN="PH11" CONFIG_MMC_SUNXI_SLOT_EXTRA=3 +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto" CONFIG_I2C1_ENABLE=y CONFIG_VIDEO_VGA=y CONFIG_SATAPWR="PB8" diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig index a06499e2d0..58f6fbad91 100644 --- a/configs/A20-Olimex-SOM-EVB_defconfig +++ b/configs/A20-Olimex-SOM-EVB_defconfig @@ -7,6 +7,7 @@ CONFIG_MMC0_CD_PIN="PH1" CONFIG_MMC3_CD_PIN="PH0" CONFIG_MMC3_PINS="PH" CONFIG_MMC_SUNXI_SLOT_EXTRA=3 +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto" CONFIG_USB0_VBUS_PIN="PB9" CONFIG_USB0_VBUS_DET="PH5" CONFIG_SATAPWR="PC3" diff --git a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig index 3bb8c4c7e6..ac4f841c4e 100644 --- a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig +++ b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig @@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 CONFIG_MMC0_CD_PIN="PH1" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto" CONFIG_USB0_VBUS_PIN="PC17" CONFIG_USB0_VBUS_DET="PH5" CONFIG_I2C1_ENABLE=y diff --git a/configs/Mele_M3_defconfig b/configs/Mele_M3_defconfig index 22497aaeb4..bc447a4a90 100644 --- a/configs/Mele_M3_defconfig +++ b/configs/Mele_M3_defconfig @@ -5,6 +5,7 @@ CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 CONFIG_MMC0_CD_PIN="PH1" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto" CONFIG_VIDEO_VGA=y CONFIG_VIDEO_COMPOSITE=y CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m3" diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig index 7eeae25010..cfab739552 100644 --- a/configs/Orangepi_mini_defconfig +++ b/configs/Orangepi_mini_defconfig @@ -7,6 +7,7 @@ CONFIG_MACPWR="PH23" CONFIG_MMC0_CD_PIN="PH10" CONFIG_MMC3_CD_PIN="PH11" CONFIG_MMC_SUNXI_SLOT_EXTRA=3 +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto" CONFIG_USB1_VBUS_PIN="PH26" CONFIG_USB2_VBUS_PIN="PH22" CONFIG_VIDEO_COMPOSITE=y diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig index 80741b58f9..2d7b295188 100644 --- a/configs/Sinlinx_SinA33_defconfig +++ b/configs/Sinlinx_SinA33_defconfig @@ -6,6 +6,7 @@ CONFIG_DRAM_CLK=552 CONFIG_DRAM_ZQ=15291 CONFIG_MMC0_CD_PIN="PB4" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto" CONFIG_USB0_ID_DET="PH8" CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:66000,le:90,ri:160,up:3,lo:127,hs:70,vs:20,sync:3,vmode:0" CONFIG_VIDEO_LCD_DCLK_PHASE=0 diff --git a/configs/Yones_Toptech_BD1078_defconfig b/configs/Yones_Toptech_BD1078_defconfig index c49cbcbc3c..cad5618d54 100644 --- a/configs/Yones_Toptech_BD1078_defconfig +++ b/configs/Yones_Toptech_BD1078_defconfig @@ -7,6 +7,7 @@ CONFIG_MMC0_CD_PIN="PH1" CONFIG_MMC1_CD_PIN="PH2" CONFIG_MMC1_PINS="PH" CONFIG_MMC_SUNXI_SLOT_EXTRA=1 +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto" CONFIG_USB0_VBUS_PIN="PB9" CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_AXP_GPIO=y diff --git a/configs/amarula_a64_relic_defconfig b/configs/amarula_a64_relic_defconfig index caeb3f6008..bb5c0ff7b2 100644 --- a/configs/amarula_a64_relic_defconfig +++ b/configs/amarula_a64_relic_defconfig @@ -5,6 +5,7 @@ CONFIG_MACH_SUN50I=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_DRAM_ODT_EN=y CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_ENV_FAT_DEVICE_AND_PART="0:auto" # CONFIG_VIDEO_DE2 is not set CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-amarula-relic" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set diff --git a/env/Kconfig b/env/Kconfig index be99efb937..99577f1b2e 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -374,7 +374,8 @@ config ENV_FAT_DEVICE_AND_PART default "0:1" if TI_COMMON_CMD_OPTIONS default "0:auto" if ARCH_ZYNQMP default "0:auto" if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA = -1 - default "1:auto" if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA != -1 + default "1:auto" if ARCH_SUNXI && !DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1 + default "2:auto" if ARCH_SUNXI && DM_MMC && MMC_SUNXI_SLOT_EXTRA != -1 default "0" if ARCH_AT91 help Define this to a string to specify the partition of the device. It can

Enable DM_MMC for Allwinner A20 SoC.

Tested on A20-OLinuXino-LIME2.

Cc: Stefan Mavrodiev stefan@olimex.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- arch/arm/mach-sunxi/Kconfig | 1 + 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index dce81b7d53..3fc30ee268 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -191,6 +191,7 @@ config MACH_SUN7I select ARCH_SUPPORT_PSCI select CLK select DRAM_SUN4I + select DM_MMC if MMC select PHY_SUN4I_USB select SUNXI_GEN_SUN4I select SUPPORT_SPL

Enable DM_MMC for Allwinner H3/H5 SoCs.

Tested on H3: BPI-M2+ H5: Orangepi pc2, prime, zero+2

Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- arch/arm/mach-sunxi/Kconfig | 1 + 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 3fc30ee268..e911dd0722 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -134,6 +134,7 @@ config MACH_SUNXI_H3_H5 bool select CLK select DM_I2C + select DM_MMC if MMC select PHY_SUN4I_USB select SUNXI_DE2 select SUNXI_DRAM_DW

Add emmc compatible for A83T SoC.

Cc: VishnuPatekar vishnupatekar0510@gmail.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/mmc/sunxi_mmc.c | 1 + 1 file changed, 1 insertion(+)

diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 5191a3e3dd..229a7b2811 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -697,6 +697,7 @@ static const struct udevice_id sunxi_mmc_ids[] = { { .compatible = "allwinner,sun4i-a10-mmc" }, { .compatible = "allwinner,sun5i-a13-mmc" }, { .compatible = "allwinner,sun7i-a20-mmc" }, + { .compatible = "allwinner,sun8i-a83t-emmc" }, { .compatible = "allwinner,sun50i-a64-mmc" }, { .compatible = "allwinner,sun50i-a64-emmc" }, { }

Enable DM_MMC for Allwinner V40 SoC.

Tested on BPI-M2 Ultra, BPI-M2 Berry.

Cc: Lothar Felten lothar.felten@gmail.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- arch/arm/mach-sunxi/Kconfig | 1 + 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index d28ab9879f..584d22bfaf 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -254,6 +254,7 @@ config MACH_SUN8I_R40 select CPU_V7_HAS_VIRT select ARCH_SUPPORT_PSCI select CLK + select DM_MMC if MMC select SUNXI_GEN_SUN6I select SUPPORT_SPL select SUNXI_DRAM_DW

Enable DM_MMC for Allwinner A23/A33/V3S SoC.

Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- arch/arm/mach-sunxi/Kconfig | 3 +++ 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 9e7021c574..3de595c687 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -207,6 +207,7 @@ config MACH_SUN8I_A23 select CPU_V7_HAS_VIRT select ARCH_SUPPORT_PSCI select CLK + select DM_MMC if MMC select DRAM_SUN8I_A23 select PHY_SUN4I_USB select SUNXI_GEN_SUN6I @@ -221,6 +222,7 @@ config MACH_SUN8I_A33 select CPU_V7_HAS_VIRT select ARCH_SUPPORT_PSCI select CLK + select DM_MMC if MMC select DRAM_SUN8I_A33 select PHY_SUN4I_USB select SUNXI_GEN_SUN6I @@ -269,6 +271,7 @@ config MACH_SUN8I_V3S select CPU_V7_HAS_VIRT select ARCH_SUPPORT_PSCI select CLK + select DM_MMC if MMC select SUNXI_GEN_SUN6I select SUNXI_DRAM_DW select SUNXI_DRAM_DW_16BIT

Implement SPI resets for all relevant Allwinner SoC clock drivers via reset map descriptor table.

Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/clk/sunxi/clk_a31.c | 4 ++++ drivers/clk/sunxi/clk_a64.c | 2 ++ drivers/clk/sunxi/clk_h3.c | 2 ++ drivers/clk/sunxi/clk_v3s.c | 1 + 4 files changed, 9 insertions(+)

diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c index 1fa77e1272..a5c6628c63 100644 --- a/drivers/clk/sunxi/clk_a31.c +++ b/drivers/clk/sunxi/clk_a31.c @@ -55,6 +55,10 @@ static struct ccu_reset_map a31_resets[] = { [RST_AHB1_MMC1] = { 0x2c0, BIT(9) }, [RST_AHB1_MMC2] = { 0x2c0, BIT(10) }, [RST_AHB1_MMC3] = { 0x2c0, BIT(11) }, + [RST_AHB1_SPI0] = { 0x2c0, BIT(20) }, + [RST_AHB1_SPI1] = { 0x2c0, BIT(21) }, + [RST_AHB1_SPI2] = { 0x2c0, BIT(22) }, + [RST_AHB1_SPI3] = { 0x2c0, BIT(23) }, [RST_AHB1_OTG] = { 0x2c0, BIT(24) }, [RST_AHB1_EHCI0] = { 0x2c0, BIT(26) }, [RST_AHB1_EHCI1] = { 0x2c0, BIT(27) }, diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c index aa2e69d0a3..218d4f09ea 100644 --- a/drivers/clk/sunxi/clk_a64.c +++ b/drivers/clk/sunxi/clk_a64.c @@ -47,6 +47,8 @@ static struct ccu_reset_map a64_resets[] = { [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, [RST_BUS_MMC2] = { 0x2c0, BIT(10) }, + [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, + [RST_BUS_SPI1] = { 0x2c0, BIT(21) }, [RST_BUS_OTG] = { 0x2c0, BIT(23) }, [RST_BUS_EHCI0] = { 0x2c0, BIT(24) }, [RST_BUS_EHCI1] = { 0x2c0, BIT(25) }, diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c index 386289b654..f610cee745 100644 --- a/drivers/clk/sunxi/clk_h3.c +++ b/drivers/clk/sunxi/clk_h3.c @@ -54,6 +54,8 @@ static struct ccu_reset_map h3_resets[] = { [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, [RST_BUS_MMC2] = { 0x2c0, BIT(10) }, + [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, + [RST_BUS_SPI1] = { 0x2c0, BIT(21) }, [RST_BUS_OTG] = { 0x2c0, BIT(23) }, [RST_BUS_EHCI0] = { 0x2c0, BIT(24) }, [RST_BUS_EHCI1] = { 0x2c0, BIT(25) }, diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c index 1cca57e065..ae4f6ee066 100644 --- a/drivers/clk/sunxi/clk_v3s.c +++ b/drivers/clk/sunxi/clk_v3s.c @@ -34,6 +34,7 @@ static struct ccu_reset_map v3s_resets[] = { [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, [RST_BUS_MMC2] = { 0x2c0, BIT(10) }, + [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, [RST_BUS_OTG] = { 0x2c0, BIT(24) }, };

Add Allwinner sun6i SPI driver for A31, H3/H5 an A64.

Cc: Fahad Sadah fahad@sadah.uk Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/spi/Kconfig | 6 + drivers/spi/Makefile | 1 + drivers/spi/sun6i_spi.c | 475 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 482 insertions(+) create mode 100644 drivers/spi/sun6i_spi.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index dcd719ff0a..671658dddc 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -179,6 +179,12 @@ config SUN4I_SPI help SPI driver for Allwinner sun4i, sun5i and sun7i SoCs

+config SUN6I_SPI + bool "Allwinner A31 SPI controller" + depends on ARCH_SUNXI + help + This enables using the SPI controller on the Allwinner A31 SoCs. + config TEGRA114_SPI bool "nVidia Tegra114 SPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 728e30c538..6e60091bc1 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -45,6 +45,7 @@ obj-$(CONFIG_SH_SPI) += sh_spi.o obj-$(CONFIG_SH_QSPI) += sh_qspi.o obj-$(CONFIG_STM32_QSPI) += stm32_qspi.o obj-$(CONFIG_SUN4I_SPI) += sun4i_spi.o +obj-$(CONFIG_SUN6I_SPI) += sun6i_spi.o obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o diff --git a/drivers/spi/sun6i_spi.c b/drivers/spi/sun6i_spi.c new file mode 100644 index 0000000000..236ed86a25 --- /dev/null +++ b/drivers/spi/sun6i_spi.c @@ -0,0 +1,475 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Amarula Solutions. + * Author: Jagan Teki jagan@amarulasolutions.com + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <spi.h> +#include <errno.h> +#include <fdt_support.h> +#include <reset.h> +#include <wait_bit.h> + +#include <asm/bitops.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/arch/clock.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define SUN6I_FIFO_DEPTH 128 +#define SUN8I_FIFO_DEPTH 64 + +#define SUN6I_GBL_CTL_BUS_ENABLE BIT(0) +#define SUN6I_GBL_CTL_MASTER BIT(1) +#define SUN6I_GBL_CTL_TP BIT(7) +#define SUN6I_GBL_CTL_RST BIT(31) + +#define SUN6I_TFR_CTL_CPHA BIT(0) +#define SUN6I_TFR_CTL_CPOL BIT(1) +#define SUN6I_TFR_CTL_SPOL BIT(2) +#define SUN6I_TFR_CTL_CS_MASK 0x30 +#define SUN6I_TFR_CTL_CS(cs) (((cs) << 4) & SUN6I_TFR_CTL_CS_MASK) +#define SUN6I_TFR_CTL_CS_MANUAL BIT(6) +#define SUN6I_TFR_CTL_CS_LEVEL BIT(7) +#define SUN6I_TFR_CTL_DHB BIT(8) +#define SUN6I_TFR_CTL_FBS BIT(12) +#define SUN6I_TFR_CTL_XCH_MASK 0x80000000 +#define SUN6I_TFR_CTL_XCH BIT(31) + +#define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_MASK 0xff +#define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS 0 +#define SUN6I_FIFO_CTL_RF_RST BIT(15) +#define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_MASK 0xff +#define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS 16 +#define SUN6I_FIFO_CTL_TF_RST BIT(31) + +#define SUN6I_CLK_CTL_CDR2_MASK 0xff +#define SUN6I_CLK_CTL_CDR2(div) (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0) +#define SUN6I_CLK_CTL_CDR1_MASK 0xf +#define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8) +#define SUN6I_CLK_CTL_DRS BIT(12) + +#define SUN6I_MAX_XFER_SIZE 0xffffff +#define SUN6I_BURST_CNT(cnt) ((cnt) & SUN6I_MAX_XFER_SIZE) +#define SUN6I_XMIT_CNT(cnt) ((cnt) & SUN6I_MAX_XFER_SIZE) +#define SUN6I_BURST_CTL_CNT_STC(cnt) ((cnt) & SUN6I_MAX_XFER_SIZE) + +#define SUN6I_SPI_MAX_RATE 24000000 +#define SUN6I_SPI_MIN_RATE 3000 +#define SUN6I_SPI_DEFAULT_RATE 1000000 +#define SUN6I_SPI_TIMEOUT_US 1000000 + +/* sun6i spi register set */ +struct sun6i_spi_regs { + u32 res1; /* 0x00 */ + u32 gblctl; /* 0x04 */ + u32 tfrctl; /* 0x08 */ + u32 res2; /* 0x0c */ + u32 intctl; /* 0x10 */ + u32 intsta; /* 0x14 */ + u32 fifoctl; /* 0x18 */ + u32 fifosta; /* 0x1c */ + u32 res3; /* 0x20 */ + u32 clkctl; /* 0x24 */ + u32 res4[2]; /* 0x28 */ + u32 bc; /* 0x30 */ + u32 tc; /* 0x34 */ + u32 bctlc; /* 0x38 */ + u32 res5[113]; /* 0x3c */ + u32 txdata; /* 0x200 */ + u32 res6[63]; /* 0x204 */ + u32 rxdata; /* 0x300 */ +}; + +struct sun6i_spi_platdata { + u32 base_addr; + u32 max_hz; +}; + +struct sun6i_spi_priv { + struct sun6i_spi_regs *regs; + u32 freq; + u32 mode; + u32 fifo_depth; + + const u8 *tx_buf; + u8 *rx_buf; +}; + +static inline void sun6i_spi_drain_fifo(struct sun6i_spi_priv *priv, int len) +{ + u8 byte; + + while (len--) { + byte = readb(&priv->regs->rxdata); + *priv->rx_buf++ = byte; + } +} + +static inline void sun6i_spi_fill_fifo(struct sun6i_spi_priv *priv, int len) +{ + u8 byte; + + while (len--) { + byte = priv->tx_buf ? *priv->tx_buf++ : 0; + writeb(byte, &priv->regs->txdata); + } +} + +static void sun6i_spi_set_cs(struct udevice *bus, u8 cs, bool enable) +{ + struct sun6i_spi_priv *priv = dev_get_priv(bus); + u32 reg; + + reg = readl(&priv->regs->tfrctl); + reg &= ~SUN6I_TFR_CTL_CS_MASK; + reg |= SUN6I_TFR_CTL_CS(cs); + + if (enable) + reg &= ~SUN6I_TFR_CTL_CS_LEVEL; + else + reg |= SUN6I_TFR_CTL_CS_LEVEL; + + writel(reg, &priv->regs->tfrctl); +} + +static int sun6i_spi_parse_pins(struct udevice *dev) +{ + const void *fdt = gd->fdt_blob; + const char *pin_name; + const fdt32_t *list; + u32 phandle; + int drive, pull = 0, pin, i; + int offset; + int size; + + list = fdt_getprop(fdt, dev_of_offset(dev), "pinctrl-0", &size); + if (!list) { + printf("WARNING: sun6i_spi: cannot find pinctrl-0 node\n"); + return -EINVAL; + } + + while (size) { + phandle = fdt32_to_cpu(*list++); + size -= sizeof(*list); + + offset = fdt_node_offset_by_phandle(fdt, phandle); + if (offset < 0) + return offset; + + drive = fdt_getprop_u32_default_node(fdt, offset, 0, + "drive-strength", 0); + if (drive) { + if (drive <= 10) + drive = 0; + else if (drive <= 20) + drive = 1; + else if (drive <= 30) + drive = 2; + else + drive = 3; + } else { + drive = fdt_getprop_u32_default_node(fdt, offset, 0, + "allwinner,drive", + 0); + drive = min(drive, 3); + } + + if (fdt_get_property(fdt, offset, "bias-disable", NULL)) + pull = 0; + else if (fdt_get_property(fdt, offset, "bias-pull-up", NULL)) + pull = 1; + else if (fdt_get_property(fdt, offset, "bias-pull-down", NULL)) + pull = 2; + else + pull = fdt_getprop_u32_default_node(fdt, offset, 0, + "allwinner,pull", + 0); + pull = min(pull, 2); + + for (i = 0; ; i++) { + pin_name = fdt_stringlist_get(fdt, offset, + "pins", i, NULL); + if (!pin_name) { + pin_name = fdt_stringlist_get(fdt, offset, + "allwinner,pins", + i, NULL); + if (!pin_name) + break; + } + + pin = name_to_gpio(pin_name); + if (pin < 0) + break; + + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SPI0); + sunxi_gpio_set_drv(pin, drive); + sunxi_gpio_set_pull(pin, pull); + } + } + return 0; +} + +static inline int sun6i_spi_enable_ccu(struct udevice *dev) +{ + struct clk ahb_clk, mod_clk; + struct reset_ctl reset; + int ret; + + ret = clk_get_by_name(dev, "ahb", &ahb_clk); + if (ret) { + dev_err(dev, "failed to get ahb clock\n"); + return ret; + } + + ret = clk_get_by_name(dev, "mod", &mod_clk); + if (ret) { + dev_err(dev, "failed to get mod clock\n"); + return ret; + } + + ret = reset_get_by_index(dev, 0, &reset); + if (ret) { + dev_err(dev, "failed to get reset\n"); + return ret; + } + + ret = clk_enable(&ahb_clk); + if (ret) { + dev_err(dev, "failed to enable ahb clock\n"); + return ret; + } + + ret = clk_enable(&mod_clk); + if (ret) { + dev_err(dev, "failed to enable mod clock\n"); + return ret; + } + + ret = reset_deassert(&reset); + if (ret) { + dev_err(dev, "failed to deassert reset\n"); + return ret; + } + + return 0; +} + +static int sun6i_spi_ofdata_to_platdata(struct udevice *bus) +{ + struct sun6i_spi_platdata *plat = dev_get_platdata(bus); + int node = dev_of_offset(bus); + + plat->base_addr = devfdt_get_addr(bus); + plat->max_hz = fdtdec_get_int(gd->fdt_blob, node, + "spi-max-frequency", + SUN6I_SPI_DEFAULT_RATE); + + if (plat->max_hz > SUN6I_SPI_MAX_RATE) + plat->max_hz = SUN6I_SPI_MAX_RATE; + + return 0; +} + +static int sun6i_spi_probe(struct udevice *bus) +{ + struct sun6i_spi_platdata *plat = dev_get_platdata(bus); + struct sun6i_spi_priv *priv = dev_get_priv(bus); + int ret; + + ret = sun6i_spi_enable_ccu(bus); + if (ret) + return ret; + + sun6i_spi_parse_pins(bus); + + priv->regs = (struct sun6i_spi_regs *)(uintptr_t)plat->base_addr; + priv->freq = plat->max_hz; + priv->fifo_depth = dev_get_driver_data(bus); + + return 0; +} + +static int sun6i_spi_claim_bus(struct udevice *dev) +{ + struct sun6i_spi_priv *priv = dev_get_priv(dev->parent); + + writel(SUN6I_GBL_CTL_BUS_ENABLE | SUN6I_GBL_CTL_MASTER | + SUN6I_GBL_CTL_TP, &priv->regs->gblctl); + writel(SUN6I_TFR_CTL_CS_MANUAL, &priv->regs->tfrctl); + + return 0; +} + +static int sun6i_spi_release_bus(struct udevice *dev) +{ + struct sun6i_spi_priv *priv = dev_get_priv(dev->parent); + u32 reg; + + reg = readl(&priv->regs->gblctl); + reg &= ~SUN6I_GBL_CTL_BUS_ENABLE; + writel(reg, &priv->regs->gblctl); + + return 0; +} + +static int sun6i_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct sun6i_spi_priv *priv = dev_get_priv(bus); + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); + + u32 len = bitlen / 8; + u32 reg; + u8 nbytes; + int ret; + + priv->tx_buf = dout; + priv->rx_buf = din; + + if (bitlen % 8) { + debug("%s: non byte-aligned SPI transfer.\n", __func__); + return -ENAVAIL; + } + + if (flags & SPI_XFER_BEGIN) + sun6i_spi_set_cs(bus, slave_plat->cs, true); + + /* Reset FIFOs */ + writel(SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST, + &priv->regs->fifoctl); + + while (len) { + /* Setup the transfer now... */ + nbytes = min(len, priv->fifo_depth); + + /* Setup the counters */ + writel(SUN6I_BURST_CNT(nbytes), &priv->regs->bc); + writel(SUN6I_XMIT_CNT(nbytes), &priv->regs->tc); + writel(SUN6I_BURST_CTL_CNT_STC(nbytes), &priv->regs->bctlc); + + /* Fill the TX FIFO */ + sun6i_spi_fill_fifo(priv, nbytes); + + /* Start the transfer */ + reg = readl(&priv->regs->tfrctl); + writel(reg | SUN6I_TFR_CTL_XCH, &priv->regs->tfrctl); + + /* Wait transfer to complete */ + ret = wait_for_bit_le32(&priv->regs->tfrctl, + SUN6I_TFR_CTL_XCH_MASK, false, + SUN6I_SPI_TIMEOUT_US, false); + if (ret) { + printf("ERROR: sun6i_spi: Timeout transferring data\n"); + sun6i_spi_set_cs(bus, slave_plat->cs, false); + return ret; + } + + /* Drain the RX FIFO */ + sun6i_spi_drain_fifo(priv, nbytes); + + len -= nbytes; + } + + if (flags & SPI_XFER_END) + sun6i_spi_set_cs(bus, slave_plat->cs, false); + + return 0; +} + +static int sun6i_spi_set_speed(struct udevice *dev, uint speed) +{ + struct sun6i_spi_platdata *plat = dev_get_platdata(dev); + struct sun6i_spi_priv *priv = dev_get_priv(dev); + unsigned int div; + u32 reg; + + if (speed > plat->max_hz) + speed = plat->max_hz; + + if (speed < SUN6I_SPI_MIN_RATE) + speed = SUN6I_SPI_MIN_RATE; + + /* + * Setup clock divider. + * + * We have two choices there. Either we can use the clock + * divide rate 1, which is calculated thanks to this formula: + * SPI_CLK = MOD_CLK / (2 ^ cdr) + * Or we can use CDR2, which is calculated with the formula: + * SPI_CLK = MOD_CLK / (2 * (cdr + 1)) + * Whether we use the former or the latter is set through the + * DRS bit. + * + * First try CDR2, and if we can't reach the expected + * frequency, fall back to CDR1. + */ + reg = readl(&priv->regs->clkctl); + div = SUN6I_SPI_MAX_RATE / (2 * speed); + if (div <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) { + if (div > 0) + div--; + + reg |= SUN6I_CLK_CTL_CDR2(div) | SUN6I_CLK_CTL_DRS; + } else { + div = __ilog2(SUN6I_SPI_MAX_RATE) - __ilog2(speed); + reg |= SUN6I_CLK_CTL_CDR1(div); + } + + writel(reg, &priv->regs->clkctl); + priv->freq = speed; + + return 0; +} + +static int sun6i_spi_set_mode(struct udevice *dev, uint mode) +{ + struct sun6i_spi_priv *priv = dev_get_priv(dev); + u32 reg; + + reg = readl(&priv->regs->tfrctl); + reg &= ~(SUN6I_TFR_CTL_CPOL | SUN6I_TFR_CTL_CPHA); + + if (mode & SPI_CPOL) + reg |= SUN6I_TFR_CTL_CPOL; + + if (mode & SPI_CPHA) + reg |= SUN6I_TFR_CTL_CPHA; + + priv->mode = mode; + writel(reg, &priv->regs->tfrctl); + + return 0; +} + +static const struct dm_spi_ops sun6i_spi_ops = { + .claim_bus = sun6i_spi_claim_bus, + .release_bus = sun6i_spi_release_bus, + .xfer = sun6i_spi_xfer, + .set_speed = sun6i_spi_set_speed, + .set_mode = sun6i_spi_set_mode, +}; + +static const struct udevice_id sun6i_spi_ids[] = { + { .compatible = "allwinner,sun6i-a31-spi", + .data = SUN6I_FIFO_DEPTH }, + { .compatible = "allwinner,sun8i-h3-spi", + .data = SUN8I_FIFO_DEPTH }, + { } +}; + +U_BOOT_DRIVER(sun6i_spi) = { + .name = "sun6i_spi", + .id = UCLASS_SPI, + .of_match = sun6i_spi_ids, + .ops = &sun6i_spi_ops, + .ofdata_to_platdata = sun6i_spi_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct sun6i_spi_platdata), + .priv_auto_alloc_size = sizeof(struct sun6i_spi_priv), + .probe = sun6i_spi_probe, +};

Implement UART clocks for all Allwinner SoC clock drivers via clock map descriptor table.

Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/clk/sunxi/clk_a10.c | 9 +++++++++ drivers/clk/sunxi/clk_a10s.c | 5 +++++ drivers/clk/sunxi/clk_a23.c | 6 ++++++ drivers/clk/sunxi/clk_a31.c | 7 +++++++ drivers/clk/sunxi/clk_a64.c | 6 ++++++ drivers/clk/sunxi/clk_a83t.c | 6 ++++++ drivers/clk/sunxi/clk_h3.c | 5 +++++ drivers/clk/sunxi/clk_r40.c | 9 +++++++++ drivers/clk/sunxi/clk_v3s.c | 4 ++++ 9 files changed, 57 insertions(+)

diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c index ee499c402a..d145d37217 100644 --- a/drivers/clk/sunxi/clk_a10.c +++ b/drivers/clk/sunxi/clk_a10.c @@ -27,6 +27,15 @@ static struct ccu_clk_map a10_clks[] = { [CLK_AHB_SPI2] = { 0x060, BIT(22), NULL }, [CLK_AHB_SPI3] = { 0x060, BIT(23), NULL },

+ [CLK_APB1_UART0] = { 0x06c, BIT(16), NULL }, + [CLK_APB1_UART1] = { 0x06c, BIT(17), NULL }, + [CLK_APB1_UART2] = { 0x06c, BIT(18), NULL }, + [CLK_APB1_UART3] = { 0x06c, BIT(19), NULL }, + [CLK_APB1_UART4] = { 0x06c, BIT(20), NULL }, + [CLK_APB1_UART5] = { 0x06c, BIT(21), NULL }, + [CLK_APB1_UART6] = { 0x06c, BIT(22), NULL }, + [CLK_APB1_UART7] = { 0x06c, BIT(23), NULL }, + [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate }, diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c index bca248f59f..5912043f19 100644 --- a/drivers/clk/sunxi/clk_a10s.c +++ b/drivers/clk/sunxi/clk_a10s.c @@ -23,6 +23,11 @@ static struct ccu_clk_map a10s_clks[] = { [CLK_AHB_SPI1] = { 0x060, BIT(21), NULL }, [CLK_AHB_SPI2] = { 0x060, BIT(22), NULL },

+ [CLK_APB1_UART0] = { 0x06c, BIT(16), NULL }, + [CLK_APB1_UART1] = { 0x06c, BIT(17), NULL }, + [CLK_APB1_UART2] = { 0x06c, BIT(18), NULL }, + [CLK_APB1_UART3] = { 0x06c, BIT(19), NULL }, + #ifdef CONFIG_MMC [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c index 183c6275f3..331c79af81 100644 --- a/drivers/clk/sunxi/clk_a23.c +++ b/drivers/clk/sunxi/clk_a23.c @@ -20,6 +20,12 @@ static struct ccu_clk_map a23_clks[] = { [CLK_BUS_EHCI] = { 0x060, BIT(26), NULL }, [CLK_BUS_OHCI] = { 0x060, BIT(29), NULL },

+ [CLK_BUS_UART0] = { 0x06c, BIT(16), NULL }, + [CLK_BUS_UART1] = { 0x06c, BIT(17), NULL }, + [CLK_BUS_UART2] = { 0x06c, BIT(18), NULL }, + [CLK_BUS_UART3] = { 0x06c, BIT(19), NULL }, + [CLK_BUS_UART4] = { 0x06c, BIT(20), NULL }, + #ifdef CONFIG_MMC [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c index a5c6628c63..40803a1d64 100644 --- a/drivers/clk/sunxi/clk_a31.c +++ b/drivers/clk/sunxi/clk_a31.c @@ -28,6 +28,13 @@ static struct ccu_clk_map a31_clks[] = { [CLK_AHB1_OHCI1] = { 0x060, BIT(30), NULL }, [CLK_AHB1_OHCI2] = { 0x060, BIT(31), NULL },

+ [CLK_APB2_UART0] = { 0x06c, BIT(16), NULL }, + [CLK_APB2_UART1] = { 0x06c, BIT(17), NULL }, + [CLK_APB2_UART2] = { 0x06c, BIT(18), NULL }, + [CLK_APB2_UART3] = { 0x06c, BIT(19), NULL }, + [CLK_APB2_UART4] = { 0x06c, BIT(20), NULL }, + [CLK_APB2_UART5] = { 0x06c, BIT(21), NULL }, + [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate }, diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c index 218d4f09ea..13b506f983 100644 --- a/drivers/clk/sunxi/clk_a64.c +++ b/drivers/clk/sunxi/clk_a64.c @@ -24,6 +24,12 @@ static struct ccu_clk_map a64_clks[] = { [CLK_BUS_OHCI0] = { 0x060, BIT(28), NULL }, [CLK_BUS_OHCI1] = { 0x060, BIT(29), NULL },

+ [CLK_BUS_UART0] = { 0x06c, BIT(16), NULL }, + [CLK_BUS_UART1] = { 0x06c, BIT(17), NULL }, + [CLK_BUS_UART2] = { 0x06c, BIT(18), NULL }, + [CLK_BUS_UART3] = { 0x06c, BIT(19), NULL }, + [CLK_BUS_UART4] = { 0x06c, BIT(20), NULL }, + [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate }, diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c index 47b7672e7f..5c1235fa7b 100644 --- a/drivers/clk/sunxi/clk_a83t.c +++ b/drivers/clk/sunxi/clk_a83t.c @@ -21,6 +21,12 @@ static struct ccu_clk_map a83t_clks[] = { [CLK_BUS_EHCI1] = { 0x060, BIT(27), NULL }, [CLK_BUS_OHCI0] = { 0x060, BIT(29), NULL },

+ [CLK_BUS_UART0] = { 0x06c, BIT(16), NULL }, + [CLK_BUS_UART1] = { 0x06c, BIT(17), NULL }, + [CLK_BUS_UART2] = { 0x06c, BIT(18), NULL }, + [CLK_BUS_UART3] = { 0x06c, BIT(19), NULL }, + [CLK_BUS_UART4] = { 0x06c, BIT(20), NULL }, + [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate }, diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c index f610cee745..b132ae0a0d 100644 --- a/drivers/clk/sunxi/clk_h3.c +++ b/drivers/clk/sunxi/clk_h3.c @@ -28,6 +28,11 @@ static struct ccu_clk_map h3_clks[] = { [CLK_BUS_OHCI2] = { 0x060, BIT(30), NULL }, [CLK_BUS_OHCI3] = { 0x060, BIT(31), NULL },

+ [CLK_BUS_UART0] = { 0x06c, BIT(16), NULL }, + [CLK_BUS_UART1] = { 0x06c, BIT(17), NULL }, + [CLK_BUS_UART2] = { 0x06c, BIT(18), NULL }, + [CLK_BUS_UART3] = { 0x06c, BIT(19), NULL }, + [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate }, diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c index 24c26ad3be..1e5b1d10f7 100644 --- a/drivers/clk/sunxi/clk_r40.c +++ b/drivers/clk/sunxi/clk_r40.c @@ -25,6 +25,15 @@ static struct ccu_clk_map r40_clks[] = { [CLK_BUS_OHCI1] = { 0x060, BIT(30), NULL }, [CLK_BUS_OHCI2] = { 0x060, BIT(31), NULL },

+ [CLK_BUS_UART0] = { 0x06c, BIT(16), NULL }, + [CLK_BUS_UART1] = { 0x06c, BIT(17), NULL }, + [CLK_BUS_UART2] = { 0x06c, BIT(18), NULL }, + [CLK_BUS_UART3] = { 0x06c, BIT(19), NULL }, + [CLK_BUS_UART4] = { 0x06c, BIT(20), NULL }, + [CLK_BUS_UART5] = { 0x06c, BIT(21), NULL }, + [CLK_BUS_UART6] = { 0x06c, BIT(22), NULL }, + [CLK_BUS_UART7] = { 0x06c, BIT(23), NULL }, + [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate }, diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c index ae4f6ee066..c6e57147ee 100644 --- a/drivers/clk/sunxi/clk_v3s.c +++ b/drivers/clk/sunxi/clk_v3s.c @@ -19,6 +19,10 @@ static struct ccu_clk_map v3s_clks[] = { [CLK_BUS_SPI0] = { 0x060, BIT(20), NULL }, [CLK_BUS_OTG] = { 0x060, BIT(24), NULL },

+ [CLK_BUS_UART0] = { 0x06c, BIT(16), NULL }, + [CLK_BUS_UART1] = { 0x06c, BIT(17), NULL }, + [CLK_BUS_UART2] = { 0x06c, BIT(18), NULL }, + [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate },

Implement Ethernet clocks for all Allwinner SoCs clock drivers via clock map descriptor table.

Cc: Joe Hershberger joe.hershberger@ni.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/clk/sunxi/clk_a10.c | 3 +++ drivers/clk/sunxi/clk_a10s.c | 1 + drivers/clk/sunxi/clk_a31.c | 1 + drivers/clk/sunxi/clk_a64.c | 1 + drivers/clk/sunxi/clk_a83t.c | 1 + drivers/clk/sunxi/clk_h3.c | 1 + drivers/clk/sunxi/clk_r40.c | 2 ++ 7 files changed, 10 insertions(+)

diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c index d145d37217..fc939a313d 100644 --- a/drivers/clk/sunxi/clk_a10.c +++ b/drivers/clk/sunxi/clk_a10.c @@ -22,11 +22,14 @@ static struct ccu_clk_map a10_clks[] = { [CLK_AHB_MMC1] = { 0x060, BIT(9), NULL }, [CLK_AHB_MMC2] = { 0x060, BIT(10), NULL }, [CLK_AHB_MMC3] = { 0x060, BIT(11), NULL }, + [CLK_AHB_EMAC] = { 0x060, BIT(17), NULL }, [CLK_AHB_SPI0] = { 0x060, BIT(20), NULL }, [CLK_AHB_SPI1] = { 0x060, BIT(21), NULL }, [CLK_AHB_SPI2] = { 0x060, BIT(22), NULL }, [CLK_AHB_SPI3] = { 0x060, BIT(23), NULL },

+ [CLK_AHB_GMAC] = { 0x064, BIT(17), NULL }, + [CLK_APB1_UART0] = { 0x06c, BIT(16), NULL }, [CLK_APB1_UART1] = { 0x06c, BIT(17), NULL }, [CLK_APB1_UART2] = { 0x06c, BIT(18), NULL }, diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c index 5912043f19..6ce53dc27d 100644 --- a/drivers/clk/sunxi/clk_a10s.c +++ b/drivers/clk/sunxi/clk_a10s.c @@ -19,6 +19,7 @@ static struct ccu_clk_map a10s_clks[] = { [CLK_AHB_MMC0] = { 0x060, BIT(8), NULL }, [CLK_AHB_MMC1] = { 0x060, BIT(9), NULL }, [CLK_AHB_MMC2] = { 0x060, BIT(10), NULL }, + [CLK_AHB_EMAC] = { 0x060, BIT(17), NULL }, [CLK_AHB_SPI0] = { 0x060, BIT(20), NULL }, [CLK_AHB_SPI1] = { 0x060, BIT(21), NULL }, [CLK_AHB_SPI2] = { 0x060, BIT(22), NULL }, diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c index 288979a18f..d7a6b2421f 100644 --- a/drivers/clk/sunxi/clk_a31.c +++ b/drivers/clk/sunxi/clk_a31.c @@ -17,6 +17,7 @@ static struct ccu_clk_map a31_clks[] = { [CLK_AHB1_MMC1] = { 0x060, BIT(9), NULL }, [CLK_AHB1_MMC2] = { 0x060, BIT(10), NULL }, [CLK_AHB1_MMC3] = { 0x060, BIT(12), NULL }, + [CLK_AHB1_EMAC] = { 0x060, BIT(17), NULL }, [CLK_AHB1_SPI0] = { 0x060, BIT(20), NULL }, [CLK_AHB1_SPI1] = { 0x060, BIT(21), NULL }, [CLK_AHB1_SPI2] = { 0x060, BIT(22), NULL }, diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c index 344cfb59aa..546ddcffa2 100644 --- a/drivers/clk/sunxi/clk_a64.c +++ b/drivers/clk/sunxi/clk_a64.c @@ -16,6 +16,7 @@ static struct ccu_clk_map a64_clks[] = { [CLK_BUS_MMC0] = { 0x060, BIT(8), NULL }, [CLK_BUS_MMC1] = { 0x060, BIT(9), NULL }, [CLK_BUS_MMC2] = { 0x060, BIT(10), NULL }, + [CLK_BUS_EMAC] = { 0x060, BIT(17), NULL }, [CLK_BUS_SPI0] = { 0x060, BIT(20), NULL }, [CLK_BUS_SPI1] = { 0x060, BIT(21), NULL }, [CLK_BUS_OTG] = { 0x060, BIT(23), NULL }, diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c index cf9455da97..593ce1ac1b 100644 --- a/drivers/clk/sunxi/clk_a83t.c +++ b/drivers/clk/sunxi/clk_a83t.c @@ -16,6 +16,7 @@ static struct ccu_clk_map a83t_clks[] = { [CLK_BUS_MMC0] = { 0x060, BIT(8), NULL }, [CLK_BUS_MMC1] = { 0x060, BIT(9), NULL }, [CLK_BUS_MMC2] = { 0x060, BIT(10), NULL }, + [CLK_BUS_EMAC] = { 0x060, BIT(17), NULL }, [CLK_BUS_OTG] = { 0x060, BIT(24), NULL }, [CLK_BUS_EHCI0] = { 0x060, BIT(26), NULL }, [CLK_BUS_EHCI1] = { 0x060, BIT(27), NULL }, diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c index 15d933a6c5..ff9f294097 100644 --- a/drivers/clk/sunxi/clk_h3.c +++ b/drivers/clk/sunxi/clk_h3.c @@ -16,6 +16,7 @@ static struct ccu_clk_map h3_clks[] = { [CLK_BUS_MMC0] = { 0x060, BIT(8), NULL }, [CLK_BUS_MMC1] = { 0x060, BIT(9), NULL }, [CLK_BUS_MMC2] = { 0x060, BIT(10), NULL }, + [CLK_BUS_EMAC] = { 0x060, BIT(17), NULL }, [CLK_BUS_SPI0] = { 0x060, BIT(20), NULL }, [CLK_BUS_SPI1] = { 0x060, BIT(21), NULL }, [CLK_BUS_OTG] = { 0x060, BIT(23), NULL }, diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c index ee699d26ee..e5bddc77ee 100644 --- a/drivers/clk/sunxi/clk_r40.c +++ b/drivers/clk/sunxi/clk_r40.c @@ -25,6 +25,8 @@ static struct ccu_clk_map r40_clks[] = { [CLK_BUS_OHCI1] = { 0x060, BIT(30), NULL }, [CLK_BUS_OHCI2] = { 0x060, BIT(31), NULL },

+ [CLK_BUS_GMAC] = { 0x064, BIT(17), NULL }, + [CLK_BUS_UART0] = { 0x06c, BIT(16), NULL }, [CLK_BUS_UART1] = { 0x06c, BIT(17), NULL }, [CLK_BUS_UART2] = { 0x06c, BIT(18), NULL },

Add CLk support for sunxi_emac to enable AHB_EMAC clock via CLK framework.

Cc: Joe Hershberger joe.hershberger@ni.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/net/sunxi_emac.c | 28 ++++++++++++++++++++++------ 1 file changed, 22 insertions(+), 6 deletions(-)

diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c index 8dbd3c50c1..4d152b0ca0 100644 --- a/drivers/net/sunxi_emac.c +++ b/drivers/net/sunxi_emac.c @@ -6,6 +6,7 @@ */

#include <common.h> +#include <clk.h> #include <dm.h> #include <linux/err.h> #include <malloc.h> @@ -157,6 +158,7 @@ struct sunxi_sramc_regs {

struct emac_eth_dev { struct emac_regs *regs; + struct clk clk; struct mii_dev *bus; struct phy_device *phydev; int link_printed; @@ -500,14 +502,12 @@ static int _sunxi_emac_eth_send(struct emac_eth_dev *priv, void *packet, return 0; }

-static void sunxi_emac_board_setup(struct emac_eth_dev *priv) +static int sunxi_emac_board_setup(struct emac_eth_dev *priv) { - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; struct sunxi_sramc_regs *sram = (struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE; struct emac_regs *regs = priv->regs; - int pin; + int pin, ret;

/* Map SRAM to EMAC */ setbits_le32(&sram->ctrl1, 0x5 << 2); @@ -517,10 +517,16 @@ static void sunxi_emac_board_setup(struct emac_eth_dev *priv) sunxi_gpio_set_cfgpin(pin, SUNXI_GPA_EMAC);

/* Set up clock gating */ - setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_EMAC); + ret = clk_enable(&priv->clk); + if (ret) { + dev_err(dev, "failed to enable emac clock\n"); + return ret; + }

/* Set MII clock */ clrsetbits_le32(&regs->mac_mcfg, 0xf << 2, 0xd << 2); + + return 0; }

static int sunxi_emac_eth_start(struct udevice *dev) @@ -557,9 +563,19 @@ static int sunxi_emac_eth_probe(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); struct emac_eth_dev *priv = dev_get_priv(dev); + int ret;

priv->regs = (struct emac_regs *)pdata->iobase; - sunxi_emac_board_setup(priv); + + ret = clk_get_by_index(dev, 0, &priv->clk); + if (ret) { + dev_err(dev, "falied to get emac clock\n"); + return ret; + } + + ret = sunxi_emac_board_setup(priv); + if (ret) + return ret;

return sunxi_emac_init_phy(priv, dev); }

Add CLK and RESET support for sun8i_emac driver to enable TX clock and reset pins via CLK and RESET framework.

Cc: Joe Hershberger joe.hershberger@ni.com Cc: Lothar Felten lothar.felten@gmail.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/net/sun8i_emac.c | 56 ++++++++++++++++++++++++++++------------ 1 file changed, 40 insertions(+), 16 deletions(-)

diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index 5ee4c2f993..ad2d390f4e 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -10,6 +10,7 @@ * */

+#include <clk.h> #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/gpio.h> @@ -20,6 +21,7 @@ #include <malloc.h> #include <miiphy.h> #include <net.h> +#include <reset.h> #include <dt-bindings/pinctrl/sun4i-a10.h> #ifdef CONFIG_DM_GPIO #include <asm-generic/gpio.h> @@ -131,6 +133,8 @@ struct emac_eth_dev { phys_addr_t sysctl_reg; struct phy_device *phydev; struct mii_dev *bus; + struct clk tx_clk; + struct reset_ctl tx_rst; #ifdef CONFIG_DM_GPIO struct gpio_desc reset_gpio; #endif @@ -632,9 +636,24 @@ static int sun8i_eth_write_hwaddr(struct udevice *dev) return _sun8i_write_hwaddr(priv, pdata->enetaddr); }

-static void sun8i_emac_board_setup(struct emac_eth_dev *priv) +static int sun8i_emac_board_setup(struct emac_eth_dev *priv) { struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + int ret; + + ret = clk_enable(&priv->tx_clk); + if (ret) { + dev_err(dev, "failed to enable TX clock\n"); + return ret; + } + + if (reset_valid(&priv->tx_rst)) { + ret = reset_deassert(&priv->tx_rst); + if (ret) { + dev_err(dev, "failed to deassert TX reset\n"); + return ret; + } + }

if (priv->variant == H3_EMAC) { /* Only H3/H5 have clock controls for internal EPHY */ @@ -649,19 +668,7 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv) } }

- if (priv->variant == R40_GMAC) { - /* Set clock gating for emac */ - setbits_le32(&ccm->ahb_reset1_cfg, BIT(AHB_RESET_OFFSET_GMAC)); - - /* De-assert EMAC */ - setbits_le32(&ccm->ahb_gate1, BIT(AHB_GATE_OFFSET_GMAC)); - } else { - /* Set clock gating for emac */ - setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC)); - - /* De-assert EMAC */ - setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC)); - } + return 0; }

#if defined(CONFIG_DM_GPIO) @@ -787,10 +794,14 @@ static int sun8i_emac_eth_probe(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); struct emac_eth_dev *priv = dev_get_priv(dev); + int ret;

priv->mac_reg = (void *)pdata->iobase;

- sun8i_emac_board_setup(priv); + ret = sun8i_emac_board_setup(priv); + if (ret) + return ret; + sun8i_emac_set_syscon(priv);

sun8i_mdio_init(dev->name, dev); @@ -819,8 +830,8 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) int offset = 0; #ifdef CONFIG_DM_GPIO int reset_flags = GPIOD_IS_OUT; - int ret = 0; #endif + int ret;

pdata->iobase = devfdt_get_addr(dev); if (pdata->iobase == FDT_ADDR_T_NONE) { @@ -835,6 +846,19 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) return -EINVAL; }

+ ret = clk_get_by_name(dev, "stmmaceth", &priv->tx_clk); + if (ret) { + dev_err(dev, "failed to get TX clock\n"); + return ret; + } + + ret = reset_get_by_name_optional(dev, "stmmaceth", + &priv->tx_rst, true); + if (ret) { + dev_err(dev, "failed to get TX reset\n"); + return ret; + } + offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon"); if (offset < 0) { debug("%s: cannot find syscon node\n", __func__);

clk_get_by_index_tail() now handle common clk get by index code so use it in relevant places.

Cc: Simon Glass sjg@chromium.org Cc: Joe Hershberger joe.hershberger@ni.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/clk/clk-uclass.c | 77 +++++++++++++--------------------------- 1 file changed, 25 insertions(+), 52 deletions(-)

diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 8bb41a4de5..d439d216f2 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -54,50 +54,6 @@ static int clk_of_xlate_default(struct clk *clk, return 0; }

-static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name, - int index, struct clk *clk) -{ - int ret; - struct ofnode_phandle_args args; - struct udevice *dev_clk; - const struct clk_ops *ops; - - debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk); - - assert(clk); - clk->dev = NULL; - - ret = dev_read_phandle_with_args(dev, prop_name, "#clock-cells", 0, - index, &args); - if (ret) { - debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n", - __func__, ret); - return ret; - } - - ret = uclass_get_device_by_ofnode(UCLASS_CLK, args.node, &dev_clk); - if (ret) { - debug("%s: uclass_get_device_by_of_offset failed: err=%d\n", - __func__, ret); - return ret; - } - - clk->dev = dev_clk; - - ops = clk_dev_ops(dev_clk); - - if (ops->of_xlate) - ret = ops->of_xlate(clk, &args); - else - ret = clk_of_xlate_default(clk, &args); - if (ret) { - debug("of_xlate() failed: %d\n", ret); - return ret; - } - - return clk_request(dev_clk, clk); -} - static int clk_get_by_index_tail(int ret, ofnode node, struct ofnode_phandle_args *args, const char *list_name, int index, @@ -197,10 +153,11 @@ bulk_get_err:

static int clk_set_default_parents(struct udevice *dev) { + struct ofnode_phandle_args args; struct clk clk, parent_clk; int index; int num_parents; - int ret; + int ret, err;

num_parents = dev_count_phandle_with_args(dev, "assigned-clock-parents", "#clock-cells"); @@ -211,8 +168,13 @@ static int clk_set_default_parents(struct udevice *dev) }

for (index = 0; index < num_parents; index++) { - ret = clk_get_by_indexed_prop(dev, "assigned-clock-parents", - index, &parent_clk); + err = dev_read_phandle_with_args(dev, "assigned-clock-parents", + "#clock-cells", 0, + index, &args); + + ret = clk_get_by_index_tail(err, dev_ofnode(dev), &args, + "assigned-clock-parents", + index > 0, &parent_clk); /* If -ENOENT, this is a no-op entry */ if (ret == -ENOENT) continue; @@ -223,8 +185,13 @@ static int clk_set_default_parents(struct udevice *dev) return ret; }

- ret = clk_get_by_indexed_prop(dev, "assigned-clocks", - index, &clk); + err = dev_read_phandle_with_args(dev, "assigned-clocks", + "#clock-cells", 0, + index, &args); + + ret = clk_get_by_index_tail(err, dev_ofnode(dev), &args, + "assigned-clocks", + index > 0, &clk); if (ret) { debug("%s: could not get assigned clock %d for %s\n", __func__, index, dev_read_name(dev)); @@ -252,11 +219,12 @@ static int clk_set_default_parents(struct udevice *dev)

static int clk_set_default_rates(struct udevice *dev) { + struct ofnode_phandle_args args; struct clk clk; int index; int num_rates; int size; - int ret = 0; + int err, ret = 0; u32 *rates = NULL;

size = dev_read_size(dev, "assigned-clock-rates"); @@ -277,8 +245,13 @@ static int clk_set_default_rates(struct udevice *dev) if (!rates[index]) continue;

- ret = clk_get_by_indexed_prop(dev, "assigned-clocks", - index, &clk); + err = dev_read_phandle_with_args(dev, "assigned-clocks", + "#clock-cells", 0, + index, &args); + + ret = clk_get_by_index_tail(err, dev_ofnode(dev), &args, + "assigned-clocks", + index > 0, &clk); if (ret) { debug("%s: could not get assigned clock %d for %s\n", __func__, index, dev_read_name(dev));

EPHY CLK and RESET is availble in Allwinner H3 EMAC via mdio-mux node of internal PHY. Add the respetive clock and reset reg and bits.

Cc: Joe Hershberger joe.hershberger@ni.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- drivers/clk/sunxi/clk_h3.c | 4 ++++ 1 file changed, 4 insertions(+)

diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c index 88086580f4..3d5dc2cbed 100644 --- a/drivers/clk/sunxi/clk_h3.c +++ b/drivers/clk/sunxi/clk_h3.c @@ -34,6 +34,8 @@ static struct ccu_clk_map h3_clks[] = { [CLK_BUS_UART2] = { 0x06c, BIT(18), NULL }, [CLK_BUS_UART3] = { 0x06c, BIT(19), NULL },

+ [CLK_BUS_EPHY] = { 0x070, BIT(0), NULL }, + [CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate }, [CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate }, [CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate }, @@ -73,6 +75,8 @@ static struct ccu_reset_map h3_resets[] = { [RST_BUS_OHCI2] = { 0x2c0, BIT(30) }, [RST_BUS_OHCI3] = { 0x2c0, BIT(31) },

+ [RST_BUS_EPHY] = { 0x2c8, BIT(2) }, + [RST_BUS_UART0] = { 0x2d8, BIT(16) }, [RST_BUS_UART1] = { 0x2d8, BIT(17) }, [RST_BUS_UART2] = { 0x2d8, BIT(18) },

Since Ethernet clock and reset is now handling via CLK and RESET frameworks via driver API's remove explicit ccm writes.

Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- board/sunxi/gmac.c | 8 -------- 1 file changed, 8 deletions(-)

diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c index 826650c89b..d8fdf7728e 100644 --- a/board/sunxi/gmac.c +++ b/board/sunxi/gmac.c @@ -12,14 +12,6 @@ void eth_init_board(void) struct sunxi_ccm_reg *const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;

- /* Set up clock gating */ -#ifdef CONFIG_SUNXI_GEN_SUN6I - setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC); - setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC); -#else - setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC); -#endif - /* Set MII clock */ #ifdef CONFIG_RGMII setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |