This patch add support new SoCs that are s5pc100 and s5pc110 s5pc1xx SoC is ARM Cortex A8 processor

Signed-off-by: Minkyu Kang mk7.kang@samsung.com Signed-off-by: HeungJun, Kim riverful.kim@samsung.com --- cpu/arm_cortexa8/s5pc1xx/Makefile | 53 ++++++ cpu/arm_cortexa8/s5pc1xx/cache.c | 43 +++++ cpu/arm_cortexa8/s5pc1xx/clock.c | 282 ++++++++++++++++++++++++++++++ cpu/arm_cortexa8/s5pc1xx/cpu_info.c | 71 ++++++++ cpu/arm_cortexa8/s5pc1xx/reset.S | 47 +++++ cpu/arm_cortexa8/s5pc1xx/timer.c | 200 +++++++++++++++++++++ include/asm-arm/arch-s5pc1xx/clk.h | 46 +++++ include/asm-arm/arch-s5pc1xx/clock.h | 79 +++++++++ include/asm-arm/arch-s5pc1xx/cpu.h | 73 ++++++++ include/asm-arm/arch-s5pc1xx/gpio.h | 127 ++++++++++++++ include/asm-arm/arch-s5pc1xx/hardware.h | 63 +++++++ include/asm-arm/arch-s5pc1xx/i2c.h | 43 +++++ include/asm-arm/arch-s5pc1xx/interrupt.h | 40 +++++ include/asm-arm/arch-s5pc1xx/keypad.h | 33 ++++ include/asm-arm/arch-s5pc1xx/mem.h | 58 ++++++ include/asm-arm/arch-s5pc1xx/power.h | 42 +++++ include/asm-arm/arch-s5pc1xx/pwm.h | 65 +++++++ include/asm-arm/arch-s5pc1xx/uart.h | 72 ++++++++ 18 files changed, 1437 insertions(+), 0 deletions(-) create mode 100644 cpu/arm_cortexa8/s5pc1xx/Makefile create mode 100644 cpu/arm_cortexa8/s5pc1xx/cache.c create mode 100644 cpu/arm_cortexa8/s5pc1xx/clock.c create mode 100644 cpu/arm_cortexa8/s5pc1xx/cpu_info.c create mode 100644 cpu/arm_cortexa8/s5pc1xx/reset.S create mode 100644 cpu/arm_cortexa8/s5pc1xx/timer.c create mode 100644 include/asm-arm/arch-s5pc1xx/clk.h create mode 100644 include/asm-arm/arch-s5pc1xx/clock.h create mode 100644 include/asm-arm/arch-s5pc1xx/cpu.h create mode 100644 include/asm-arm/arch-s5pc1xx/gpio.h create mode 100644 include/asm-arm/arch-s5pc1xx/hardware.h create mode 100644 include/asm-arm/arch-s5pc1xx/i2c.h create mode 100644 include/asm-arm/arch-s5pc1xx/interrupt.h create mode 100644 include/asm-arm/arch-s5pc1xx/keypad.h create mode 100644 include/asm-arm/arch-s5pc1xx/mem.h create mode 100644 include/asm-arm/arch-s5pc1xx/power.h create mode 100644 include/asm-arm/arch-s5pc1xx/pwm.h create mode 100644 include/asm-arm/arch-s5pc1xx/uart.h

diff --git a/cpu/arm_cortexa8/s5pc1xx/Makefile b/cpu/arm_cortexa8/s5pc1xx/Makefile new file mode 100644 index 0000000..6ccb09a --- /dev/null +++ b/cpu/arm_cortexa8/s5pc1xx/Makefile @@ -0,0 +1,53 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Guennadi Liakhovetki, DENX Software Engineering, lg@denx.de +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +SOBJS = reset.o + +COBJS += timer.o +COBJS += clock.o +COBJS += cpu_info.o +COBJS += cache.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm_cortexa8/s5pc1xx/cache.c b/cpu/arm_cortexa8/s5pc1xx/cache.c new file mode 100644 index 0000000..8652a45 --- /dev/null +++ b/cpu/arm_cortexa8/s5pc1xx/cache.c @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2009 Samsung Electronics + * Minkyu Kang mk7.kang@samsung.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/cache.h> + +void l2_cache_enable(void) +{ + unsigned long i; + + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); + __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); +} + +void l2_cache_disable(void) +{ + unsigned long i; + + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); + __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); +} diff --git a/cpu/arm_cortexa8/s5pc1xx/clock.c b/cpu/arm_cortexa8/s5pc1xx/clock.c new file mode 100644 index 0000000..59690d7 --- /dev/null +++ b/cpu/arm_cortexa8/s5pc1xx/clock.c @@ -0,0 +1,282 @@ +/* + * Copyright (C) 2009 Samsung Electronics + * Minkyu Kang mk7.kang@samsung.com + * Heungjun Kim riverful.kim@samsung.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This code should work for both the S3C2400 and the S3C2410 + * as they seem to have the same PLL and clock machinery inside. + * The different address mapping is handled by the s3c24xx.h files below. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clk.h> +#include <asm/arch/clock.h> + +#define APLL 0 +#define MPLL 1 +#define EPLL 2 +#define HPLL 3 +#define VPLL 4 + +#ifndef CONFIG_SYS_CLK_FREQ_C100 +#define CONFIG_SYS_CLK_FREQ_C100 12000000 +#endif +#ifndef CONFIG_SYS_CLK_FREQ_C110 +#define CONFIG_SYS_CLK_FREQ_C110 24000000 +#endif + +static int s5pc1xx_clock_read_reg(int offset) +{ + return readl(S5PC1XX_CLOCK_BASE + offset); +} + +/* ------------------------------------------------------------------------- */ +/* + * NOTE: This describes the proper use of this file. + * + * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL. + * + * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of + * the specified bus in HZ. + */ +/* ------------------------------------------------------------------------- */ + +unsigned long get_pll_clk(int pllreg) +{ + unsigned long r, m, p, s, mask, fout; + unsigned int freq; + + switch (pllreg) { + case APLL: + if (cpu_is_s5pc110()) + r = s5pc1xx_clock_read_reg(S5PC110_APLL_CON_OFFSET); + else + r = s5pc1xx_clock_read_reg(S5PC100_APLL_CON_OFFSET); + break; + case MPLL: + if (cpu_is_s5pc110()) + r = s5pc1xx_clock_read_reg(S5PC110_MPLL_CON_OFFSET); + else + r = s5pc1xx_clock_read_reg(S5PC100_MPLL_CON_OFFSET); + break; + case EPLL: + if (cpu_is_s5pc110()) + r = s5pc1xx_clock_read_reg(S5PC110_EPLL_CON_OFFSET); + else + r = s5pc1xx_clock_read_reg(S5PC100_EPLL_CON_OFFSET); + break; + case HPLL: + if (cpu_is_s5pc110()) + hang(); + r = s5pc1xx_clock_read_reg(S5PC100_HPLL_CON_OFFSET); + break; + case VPLL: + if (cpu_is_s5pc100()) + hang(); + r = s5pc1xx_clock_read_reg(S5PC110_VPLL_CON_OFFSET); + break; + default: + hang(); + } + + if (cpu_is_s5pc110()) { + if (pllreg == APLL || pllreg == MPLL) + mask = 0x3ff; + else + mask = 0x1ff; + } else { + if (pllreg == APLL) + mask = 0x3ff; + else + mask = 0x0ff; + } + + m = (r >> 16) & mask; + p = (r >> 8) & 0x3f; + s = r & 0x7; + + if (cpu_is_s5pc110()) { + freq = CONFIG_SYS_CLK_FREQ_C110; + if (pllreg == APLL) { + if (s < 1) + s = 1; + fout = m * (freq / (p * (1 << (s - 1)))); + } else + fout = m * (freq / (p * (1 << s))); + } else { + freq = CONFIG_SYS_CLK_FREQ_C100; + fout = m * (freq / (p * (1 << s))); + } + + return fout; +} + +/* return ARMCORE frequency */ +unsigned long get_arm_clk(void) +{ + unsigned long div; + unsigned long dout_apll, armclk; + unsigned int apll_ratio, arm_ratio; + + div = s5pc1xx_clock_read_reg(S5P_CLK_DIV0_OFFSET); + if (cpu_is_s5pc110()) { + /* ARM_RATIO: don't use */ + arm_ratio = 0; + /* APLL_RATIO: [2:0] */ + apll_ratio = div & 0x7; + } else { + /* ARM_RATIO: [6:4] */ + arm_ratio = (div >> 4) & 0x7; + /* APLL_RATIO: [0] */ + apll_ratio = div & 0x1; + } + + dout_apll = get_pll_clk(APLL) / (apll_ratio + 1); + armclk = dout_apll / (arm_ratio + 1); + + return armclk; +} + +/* return FCLK frequency */ +unsigned long get_fclk(void) +{ + return get_pll_clk(APLL); +} + +/* return MCLK frequency */ +unsigned long get_mclk(void) +{ + return get_pll_clk(MPLL); +} + +/* s5pc100: return HCLKD0 frequency */ +unsigned long get_hclk(void) +{ + unsigned long hclkd0; + uint div, d0_bus_ratio; + + div = s5pc1xx_clock_read_reg(S5P_CLK_DIV0_OFFSET); + /* D0_BUS_RATIO: [10:8] */ + d0_bus_ratio = (div >> 8) & 0x7; + + hclkd0 = get_arm_clk() / (d0_bus_ratio + 1); + + return hclkd0; +} + +/* s5pc100: return PCLKD0 frequency */ +unsigned long get_pclkd0(void) +{ + unsigned long pclkd0; + uint div, pclkd0_ratio; + + div = s5pc1xx_clock_read_reg(S5P_CLK_DIV0_OFFSET); + /* PCLKD0_RATIO: [14:12] */ + pclkd0_ratio = (div >> 12) & 0x7; + + pclkd0 = get_hclk() / (pclkd0_ratio + 1); + + return pclkd0; +} + +/* s5pc100: return PCLKD1 frequency */ +unsigned long get_pclkd1(void) +{ + unsigned long d1_bus, pclkd1; + uint div, d1_bus_ratio, pclkd1_ratio; + + div = s5pc1xx_clock_read_reg(S5P_CLK_DIV1_OFFSET); + /* D1_BUS_RATIO: [14:12] */ + d1_bus_ratio = (div >> 12) & 0x7; + /* PCLKD1_RATIO: [18:16] */ + pclkd1_ratio = (div >> 16) & 0x7; + + /* ASYNC Mode */ + d1_bus = get_pll_clk(MPLL) / (d1_bus_ratio + 1); + pclkd1 = d1_bus / (pclkd1_ratio + 1); + + return pclkd1; +} + +/* s5pc110: return HCLKs frequency */ +unsigned long get_hclk_sys(int clk) +{ + unsigned long hclk; + unsigned int div; + unsigned int offset; + unsigned int hclk_sys_ratio; + + if (clk == CLK_M) + return get_hclk(); + + div = s5pc1xx_clock_read_reg(S5P_CLK_DIV0_OFFSET); + + /* HCLK_MSYS_RATIO: [10:8] + * HCLK_DSYS_RATIO: [19:16] + * HCLK_PSYS_RATIO: [27:24] */ + offset = 8 + (clk << 0x3); + + hclk_sys_ratio = (div >> offset) & 0xf; + + hclk = get_pll_clk(MPLL) / (hclk_sys_ratio + 1); + + return hclk; +} + +/* s5pc110: return PCLKs frequency */ +unsigned long get_pclk_sys(int clk) +{ + unsigned long pclk; + unsigned int div; + unsigned int offset; + unsigned int pclk_sys_ratio; + + div = s5pc1xx_clock_read_reg(S5P_CLK_DIV0_OFFSET); + + /* PCLK_MSYS_RATIO: [14:12] + * PCLK_DSYS_RATIO: [22:20] + * PCLK_PSYS_RATIO: [30:28] */ + offset = 12 + (clk << 0x3); + + pclk_sys_ratio = (div >> offset) & 0x7; + + pclk = get_hclk_sys(clk) / (pclk_sys_ratio + 1); + + return pclk; +} + +/* return peripheral clock */ +unsigned long get_pclk(void) +{ + if (cpu_is_s5pc110()) + return get_pclk_sys(CLK_P); + else + return get_pclkd1(); +} + +/* return UCLK frequency */ +unsigned long get_uclk(void) +{ + return get_pll_clk(EPLL); +} diff --git a/cpu/arm_cortexa8/s5pc1xx/cpu_info.c b/cpu/arm_cortexa8/s5pc1xx/cpu_info.c new file mode 100644 index 0000000..cd37738 --- /dev/null +++ b/cpu/arm_cortexa8/s5pc1xx/cpu_info.c @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2009 Samsung Electronics + * Minkyu Kang mk7.kang@samsung.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clk.h> + +/* Default is s5pc100 */ +unsigned int s5pc1xx_cpu_id = 0xC100; + +#ifdef CONFIG_ARCH_CPU_INIT +int arch_cpu_init(void) +{ + s5pc1xx_cpu_id = readl(S5PC1XX_PRO_ID); + s5pc1xx_cpu_id = 0xC000 | ((s5pc1xx_cpu_id & 0x00FFF000) >> 12); + + return 0; +} +#endif + +u32 get_device_type(void) +{ + return s5pc1xx_cpu_id; +} + +#ifdef CONFIG_DISPLAY_CPUINFO +int print_cpuinfo(void) +{ + printf("CPU:\tS5P%X@%luMHz\n", s5pc1xx_cpu_id, get_arm_clk() / 1000000); + if (cpu_is_s5pc110()) { + printf("\tAPLL = %luMHz, MPLL = %luMHz, EPLL = %luMHz\n", + get_fclk() / 1000000, + get_mclk() / 1000000, + get_uclk() / 1000000); + printf("\tHclk: Msys %luMhz, Dsys %luMhz, Psys %luMhz\n", + get_hclk_sys(CLK_M) / 1000000, + get_hclk_sys(CLK_D) / 1000000, + get_hclk_sys(CLK_P) / 1000000); + printf("\tPclk: Msys %3luMhz, Dsys %3luMhz, Psys %3luMhz\n", + get_pclk_sys(CLK_M) / 1000000, + get_pclk_sys(CLK_D) / 1000000, + get_pclk_sys(CLK_P) / 1000000); + } else { + printf("\tFclk = %luMHz, HclkD0 = %luMHz, PclkD0 = %luMHz," + " PclkD1 = %luMHz\n", + get_fclk() / 1000000, get_hclk() / 1000000, + get_pclkd0() / 1000000, get_pclkd1() / 1000000); + } + + return 0; +} +#endif diff --git a/cpu/arm_cortexa8/s5pc1xx/reset.S b/cpu/arm_cortexa8/s5pc1xx/reset.S new file mode 100644 index 0000000..7f6ff9c --- /dev/null +++ b/cpu/arm_cortexa8/s5pc1xx/reset.S @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2009 Samsung Electronics. + * Minkyu Kang mk7.kang@samsung.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm/arch/cpu.h> + +#define S5PC100_SWRESET 0xE0200000 +#define S5PC110_SWRESET 0xE0102000 + +.globl reset_cpu +reset_cpu: + ldr r1, =S5PC1XX_PRO_ID + ldr r2, [r1] + ldr r4, =0x00010000 + and r4, r2, r4 + cmp r4, #0 + bne 110f + /* S5PC100 */ + ldr r1, =S5PC100_SWRESET + ldr r2, =0xC100 + b 200f +110: /* S5PC110 */ + ldr r1, =S5PC110_SWRESET + mov r2, #1 +200: + str r2, [r1] +_loop_forever: + b _loop_forever diff --git a/cpu/arm_cortexa8/s5pc1xx/timer.c b/cpu/arm_cortexa8/s5pc1xx/timer.c new file mode 100644 index 0000000..de4ebb5 --- /dev/null +++ b/cpu/arm_cortexa8/s5pc1xx/timer.c @@ -0,0 +1,200 @@ +/* + * Copyright (C) 2009 Samsung Electronics + * Heungjun Kim riverful.kim@samsung.com + * Inki Dae inki.dae@samsung.com + * Minkyu Kang mk7.kang@samsung.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/pwm.h> +#include <asm/arch/clk.h> + +#define PRESCALER_1 (16 - 1) /* prescaler of timer 2, 3, 4 */ +#define MUX_DIV_2 1 /* 1/2 period */ +#define MUX_DIV_4 2 /* 1/4 period */ +#define MUX_DIV_8 3 /* 1/8 period */ +#define MUX_DIV_16 4 /* 1/16 period */ +#define MUX4_DIV_SHIFT 16 + +#define TCON_TIMER4_SHIFT 20 + +static unsigned long count_value; + +/* Internal tick units */ +static unsigned long long timestamp; /* Monotonic incrementing timer */ +static unsigned long lastdec; /* Last decremneter snapshot */ + +/* macro to read the 16 bit timer */ +static inline unsigned long READ_TIMER(void) +{ + s5pc1xx_timers_t *timers; + + if (cpu_is_s5pc110()) + timers = (s5pc1xx_timers_t *) S5PC110_TIMER_BASE; + else + timers = (s5pc1xx_timers_t *) S5PC100_TIMER_BASE; + + return timers->TCNTO4; +} + +int timer_init(void) +{ + s5pc1xx_timers_t *timers; + + if (cpu_is_s5pc110()) + timers = (s5pc1xx_timers_t *) S5PC110_TIMER_BASE; + else + timers = (s5pc1xx_timers_t *) S5PC100_TIMER_BASE; + + /* + * @ PWM Timer 4 + * Timer Freq(HZ) = + * PCLK / { (prescaler_value + 1) * (divider_value) } + */ + + /* set prescaler : 16 */ + /* set divider : 2 */ + timers->TCFG0 = (PRESCALER_1 & 0xff) << 8; + timers->TCFG1 = (MUX_DIV_2 & 0xf) << MUX4_DIV_SHIFT; + + if (count_value == 0) { + /* reset initial value */ + /* count_value = 2085937.5(HZ) (per 1 sec)*/ + count_value = get_pclk() / ((PRESCALER_1 + 1) * + (MUX_DIV_2 + 1)); + + /* count_value / 100 = 20859.375(HZ) (per 10 msec) */ + count_value = count_value / 100; + } + + /* set count value */ + timers->TCNTB4 = count_value; + lastdec = count_value; + + /* auto reload & manual update */ + timers->TCON = (timers->TCON & ~(0x07 << TCON_TIMER4_SHIFT)) | + S5PC1XX_TCON4_AUTO_RELOAD | S5PC1XX_TCON4_UPDATE; + + /* start PWM timer 4 */ + timers->TCON = (timers->TCON & ~(0x07 << TCON_TIMER4_SHIFT)) | + S5PC1XX_TCON4_AUTO_RELOAD | S5PC1XX_TCON4_START; + + timestamp = 0; + + return 0; +} + +/* + * timer without interrupts + */ +void reset_timer(void) +{ + reset_timer_masked(); +} + +unsigned long get_timer(unsigned long base) +{ + return get_timer_masked() - base; +} + +void set_timer(unsigned long t) +{ + timestamp = t; +} + +/* delay x useconds */ +void udelay(unsigned long usec) +{ + unsigned long tmo, tmp; + + if (usec >= 1000) { + /* + * if "big" number, spread normalization + * to seconds + * 1. start to normalize for usec to ticks per sec + * 2. find number of "ticks" to wait to achieve target + * 3. finish normalize. + */ + tmo = usec / 1000; + tmo *= CONFIG_SYS_HZ; + tmo /= 1000; + } else { + /* else small number, don't kill it prior to HZ multiply */ + tmo = usec * CONFIG_SYS_HZ; + tmo /= (1000 * 1000); + } + + /* get current timestamp */ + tmp = get_timer(0); + + /* if setting this fordward will roll time stamp */ + /* reset "advancing" timestamp to 0, set lastdec value */ + /* else, set advancing stamp wake up time */ + if ((tmo + tmp + 1) < tmp) + reset_timer_masked(); + else + tmo += tmp; + + /* loop till event */ + while (get_timer_masked() < tmo) + ; /* nop */ +} + +void reset_timer_masked(void) +{ + /* reset time */ + lastdec = READ_TIMER(); + timestamp = 0; +} + +unsigned long get_timer_masked(void) +{ + /* current tick value */ + unsigned long now = READ_TIMER(); + + if (lastdec >= now) + timestamp += lastdec - now; + else + timestamp += lastdec + count_value - now; + + lastdec = now; + + return timestamp; +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +unsigned long get_tbclk(void) +{ + /* We overrun in 100s */ + return CONFIG_SYS_HZ * 100; +} diff --git a/include/asm-arm/arch-s5pc1xx/clk.h b/include/asm-arm/arch-s5pc1xx/clk.h new file mode 100644 index 0000000..c0f46d2 --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/clk.h @@ -0,0 +1,46 @@ +/* + * (C) Copyright 2009 Samsung Electronics + * Minkyu Kang mk7.kang@samsung.com + * Heungjun Kim riverful.kim@samsung.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARM_ARCH_CLK_H_ +#define __ASM_ARM_ARCH_CLK_H_ + +unsigned long get_pll_clk(int pllreg); +unsigned long get_arm_clk(void); +unsigned long get_fclk(void); +unsigned long get_mclk(void); +unsigned long get_hclk(void); +unsigned long get_pclk(void); +unsigned long get_uclk(void); + +/*s5pc110 */ +#define CLK_M 0 +#define CLK_D 1 +#define CLK_P 2 + +unsigned long get_hclk_sys(int clk); +unsigned long get_pclk_sys(int clk); + +/* s5pc100 */ +unsigned long get_pclkd0(void); +unsigned long get_pclkd1(void); + +#endif diff --git a/include/asm-arm/arch-s5pc1xx/clock.h b/include/asm-arm/arch-s5pc1xx/clock.h new file mode 100644 index 0000000..ac28e15 --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/clock.h @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2009 Samsung Electronics + * Minkyu Kang mk7.kang@samsung.com + * Heungjun Kim riverful.kim@samsung.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARM_ARCH_CLOCK_H_ +#define __ASM_ARM_ARCH_CLOCK_H_ + +/* + * Clock control + */ + +/* Clock Register */ +#define S5PC100_APLL_LOCK_OFFSET 0x0 +#define S5PC100_MPLL_LOCK_OFFSET 0x4 +#define S5PC100_EPLL_LOCK_OFFSET 0x8 +#define S5PC100_HPLL_LOCK_OFFSET 0xc + +#define S5PC100_APLL_CON_OFFSET 0x100 +#define S5PC100_MPLL_CON_OFFSET 0x104 +#define S5PC100_EPLL_CON_OFFSET 0x108 +#define S5PC100_HPLL_CON_OFFSET 0x10c + +#define S5PC110_APLL_LOCK_OFFSET 0x00 +#define S5PC110_MPLL_LOCK_OFFSET 0x08 +#define S5PC110_EPLL_LOCK_OFFSET 0x10 +#define S5PC110_VPLL_LOCK_OFFSET 0x20 + +#define S5PC110_APLL_CON_OFFSET 0x100 +#define S5PC110_MPLL_CON_OFFSET 0x108 +#define S5PC110_EPLL_CON_OFFSET 0x110 +#define S5PC110_VPLL_CON_OFFSET 0x120 + +#define S5P_CLK_SRC0_OFFSET 0x200 +#define S5P_CLK_SRC1_OFFSET 0x204 +#define S5P_CLK_SRC2_OFFSET 0x208 +#define S5P_CLK_SRC3_OFFSET 0x20c + +#define S5P_CLK_DIV0_OFFSET 0x300 +#define S5P_CLK_DIV1_OFFSET 0x304 +#define S5P_CLK_DIV2_OFFSET 0x308 +#define S5P_CLK_DIV3_OFFSET 0x30c +#define S5P_CLK_DIV4_OFFSET 0x310 + +#define S5P_CLK_OUT_OFFSET 0x400 + +#define S5P_CLK_GATE_D00_OFFSET 0x500 +#define S5P_CLK_GATE_D01_OFFSET 0x504 +#define S5P_CLK_GATE_D02_OFFSET 0x508 + +#define S5P_CLK_GATE_D10_OFFSET 0x520 +#define S5P_CLK_GATE_D11_OFFSET 0x524 +#define S5P_CLK_GATE_D12_OFFSET 0x528 +#define S5P_CLK_GATE_D13_OFFSET 0x530 +#define S5P_CLK_GATE_D14_OFFSET 0x534 + +#define S5P_CLK_GATE_D20_OFFSET 0x540 + +#define S5P_CLK_GATE_SCLK0_OFFSET 0x560 +#define S5P_CLK_GATE_SCLK1_OFFSET 0x564 + +#endif diff --git a/include/asm-arm/arch-s5pc1xx/cpu.h b/include/asm-arm/arch-s5pc1xx/cpu.h new file mode 100644 index 0000000..c7d7183 --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/cpu.h @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2009 Samsung Electronics + * Minkyu Kang mk7.kang@samsung.com + * Heungjun Kim riverful.kim@samsung.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _S5PC1XX_CPU_H +#define _S5PC1XX_CPU_H + +#include <asm/hardware.h> + +#define S5PC1XX_ADDR_BASE 0xe0000000 +#define S5P_ADDR(x) (S5PC1XX_ADDR_BASE + (x)) + +#define S5PC1XX_CLOCK_BASE 0xE0100000 +#define S5P_PA_CLK_OTHERS S5P_ADDR(0x00200000) /* Clock Others Base */ + +/* Note that write the macro by address order */ +#define S5PC100_VIC0_BASE 0xE4000000 +#define S5PC100_VIC1_BASE 0xE4100000 +#define S5PC100_VIC2_BASE 0xE4200000 +#define S5PC100_SROMC_BASE 0xE7000000 +#define S5PC100_ONENAND_BASE 0xE7100000 +#define S5PC100_WATCHDOG_BASE 0xEA200000 + +#define S5PC110_WATCHDOG_BASE 0xE2700000 +#define S5PC110_SROMC_BASE 0xE8000000 +#define S5PC110_VIC0_BASE 0xF2000000 +#define S5PC110_VIC1_BASE 0xF2100000 +#define S5PC110_VIC2_BASE 0xF2200000 +#define S5PC110_VIC3_BASE 0xF2300000 + +/* + * Chip ID + */ +#define S5PC1XX_CHIP_ID(x) (0xE0000000 + (x)) +#define S5PC1XX_PRO_ID S5PC1XX_CHIP_ID(0) +#define S5PC1XX_OMR S5PC1XX_CHIP_ID(4) + +#ifndef __ASSEMBLY__ +/* CPU detection macros */ +extern unsigned int s5pc1xx_cpu_id; + +#define IS_SAMSUNG_TYPE(type, id) \ +static inline int is_##type(void) \ +{ \ + return (s5pc1xx_cpu_id == (id)) ? 1 : 0; \ +} + +IS_SAMSUNG_TYPE(s5pc100, 0xc100) +IS_SAMSUNG_TYPE(s5pc110, 0xc110) + +#define cpu_is_s5pc100() is_s5pc100() +#define cpu_is_s5pc110() is_s5pc110() +#endif + +#endif /* _S5PC1XX_CPU_H */ diff --git a/include/asm-arm/arch-s5pc1xx/gpio.h b/include/asm-arm/arch-s5pc1xx/gpio.h new file mode 100644 index 0000000..26d0950 --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/gpio.h @@ -0,0 +1,127 @@ +/* + * (C) Copyright 2009 Samsung Electronics + * Minkyu Kang mk7.kang@samsung.com + * Heungjun Kim riverful.kim@samsung.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __S5PC1XX_GPIO_H +#define __S5PC1XX_GPIO_H + +/* GPIO Bank Base */ +#define S5PC100_GPIO_BASE(x) (0xE0300000 + (x)) +#define S5PC110_GPIO_BASE(x) (0xE0200000 + (x)) + +/* S5PC100 bank offset */ +#define S5PC100_GPIO_A0_OFFSET 0x000 +#define S5PC100_GPIO_A1_OFFSET 0x020 +#define S5PC100_GPIO_B_OFFSET 0x040 +#define S5PC100_GPIO_C_OFFSET 0x060 +#define S5PC100_GPIO_D_OFFSET 0x080 +#define S5PC100_GPIO_E0_OFFSET 0x0A0 +#define S5PC100_GPIO_E1_OFFSET 0x0C0 +#define S5PC100_GPIO_F0_OFFSET 0x0E0 +#define S5PC100_GPIO_F1_OFFSET 0x100 +#define S5PC100_GPIO_F2_OFFSET 0x120 +#define S5PC100_GPIO_F3_OFFSET 0x140 +#define S5PC100_GPIO_G0_OFFSET 0x160 +#define S5PC100_GPIO_G1_OFFSET 0x180 +#define S5PC100_GPIO_G2_OFFSET 0x1A0 +#define S5PC100_GPIO_G3_OFFSET 0x1C0 +#define S5PC100_GPIO_I_OFFSET 0x1E0 +#define S5PC100_GPIO_J0_OFFSET 0x200 +#define S5PC100_GPIO_J1_OFFSET 0x220 +#define S5PC100_GPIO_J2_OFFSET 0x240 +#define S5PC100_GPIO_J3_OFFSET 0x260 +#define S5PC100_GPIO_J4_OFFSET 0x280 +#define S5PC100_GPIO_K0_OFFSET 0x2A0 +#define S5PC100_GPIO_K1_OFFSET 0x2C0 +#define S5PC100_GPIO_K2_OFFSET 0x2E0 +#define S5PC100_GPIO_K3_OFFSET 0x300 +#define S5PC100_GPIO_L0_OFFSET 0x320 +#define S5PC100_GPIO_L1_OFFSET 0x340 +#define S5PC100_GPIO_L2_OFFSET 0x360 +#define S5PC100_GPIO_L3_OFFSET 0x380 +#define S5PC100_GPIO_L4_OFFSET 0x3A0 +#define S5PC100_GPIO_H0_OFFSET 0xC00 +#define S5PC100_GPIO_H1_OFFSET 0xC20 +#define S5PC100_GPIO_H2_OFFSET 0xC40 +#define S5PC100_GPIO_H3_OFFSET 0xC60 + +/* S5PC110 bank offset */ +#define S5PC110_GPIO_A0_OFFSET 0x000 +#define S5PC110_GPIO_A1_OFFSET 0x020 +#define S5PC110_GPIO_B_OFFSET 0x040 +#define S5PC110_GPIO_C0_OFFSET 0x060 +#define S5PC110_GPIO_C1_OFFSET 0x080 +#define S5PC110_GPIO_D0_OFFSET 0x0A0 +#define S5PC110_GPIO_D1_OFFSET 0x0C0 +#define S5PC110_GPIO_E0_OFFSET 0x0E0 +#define S5PC110_GPIO_E1_OFFSET 0x110 +#define S5PC110_GPIO_F0_OFFSET 0x120 +#define S5PC110_GPIO_F1_OFFSET 0x140 +#define S5PC110_GPIO_F2_OFFSET 0x160 +#define S5PC110_GPIO_F3_OFFSET 0x180 +#define S5PC110_GPIO_G0_OFFSET 0x1A0 +#define S5PC110_GPIO_G1_OFFSET 0x1C0 +#define S5PC110_GPIO_G2_OFFSET 0x1E0 +#define S5PC110_GPIO_G3_OFFSET 0x200 +#define S5PC110_GPIO_I_OFFSET 0x220 +#define S5PC110_GPIO_J0_OFFSET 0x240 +#define S5PC110_GPIO_J1_OFFSET 0x260 +#define S5PC110_GPIO_J2_OFFSET 0x280 +#define S5PC110_GPIO_J3_OFFSET 0x2A0 +#define S5PC110_GPIO_J4_OFFSET 0x2C0 +#define S5PC110_GPIO_MP0_1_OFFSET 0x2E0 +#define S5PC110_GPIO_MP0_2_OFFSET 0x300 +#define S5PC110_GPIO_MP0_3_OFFSET 0x320 +#define S5PC110_GPIO_MP0_4_OFFSET 0x340 +#define S5PC110_GPIO_MP0_5_OFFSET 0x360 +#define S5PC110_GPIO_MP0_6_OFFSET 0x380 +#define S5PC110_GPIO_MP0_7_OFFSET 0x3A0 +#define S5PC110_GPIO_MP1_0_OFFSET 0x3C0 +#define S5PC110_GPIO_MP1_1_OFFSET 0x3E0 +#define S5PC110_GPIO_MP1_2_OFFSET 0x410 +#define S5PC110_GPIO_MP1_3_OFFSET 0x420 +#define S5PC110_GPIO_MP1_4_OFFSET 0x440 +#define S5PC110_GPIO_MP1_5_OFFSET 0x460 +#define S5PC110_GPIO_MP1_6_OFFSET 0x480 +#define S5PC110_GPIO_MP1_7_OFFSET 0x4A0 +#define S5PC110_GPIO_MP1_8_OFFSET 0x4C0 +#define S5PC110_GPIO_MP2_0_OFFSET 0x4E0 +#define S5PC110_GPIO_MP2_1_OFFSET 0x510 +#define S5PC110_GPIO_MP2_2_OFFSET 0x520 +#define S5PC110_GPIO_MP2_3_OFFSET 0x540 +#define S5PC110_GPIO_MP2_4_OFFSET 0x560 +#define S5PC110_GPIO_MP2_5_OFFSET 0x580 +#define S5PC110_GPIO_MP2_6_OFFSET 0x5A0 +#define S5PC110_GPIO_MP2_7_OFFSET 0x5C0 +#define S5PC110_GPIO_MP2_8_OFFSET 0x5E0 +#define S5PC110_GPIO_H0_OFFSET 0xC00 +#define S5PC110_GPIO_H1_OFFSET 0xC20 +#define S5PC110_GPIO_H2_OFFSET 0xC40 +#define S5PC110_GPIO_H3_OFFSET 0xC60 + +/* GPIO bank Offset */ +#define S5PC1XX_GPIO_CON_OFFSET 0x0 +#define S5PC1XX_GPIO_DAT_OFFSET 0x4 +#define S5PC1XX_GPIO_PULL_OFFSET 0x8 +#define S5PC1XX_GPIO_DRV_OFFSET 0xc +#define S5PC1XX_GPIO_PDNCON_OFFSET 0x10 +#define S5PC1XX_GPIO_PDNPULL_OFFSET 0x14 + +#endif diff --git a/include/asm-arm/arch-s5pc1xx/hardware.h b/include/asm-arm/arch-s5pc1xx/hardware.h new file mode 100644 index 0000000..ca95c3d --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/hardware.h @@ -0,0 +1,63 @@ +/* + * Originates from Samsung's u-boot 1.1.6 port to S3C6400 / SMDK6400 + * + * (C) Copyright 2008 + * Guennadi Liakhovetki, DENX Software Engineering, lg@denx.de + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ARCH_HARDWARE_H_ +#define _ARCH_HARDWARE_H_ + +#include <asm/sizes.h> + +#ifndef __ASSEMBLY__ +#define UData(Data) ((unsigned long)(Data)) + +#define __REG(x) (*(vu_long *)(x)) +#define __REGl(x) (*(vu_long *)(x)) +#define __REGw(x) (*(vu_short *)(x)) +#define __REGb(x) (*(vu_char *)(x)) +#define __REG2(x, y) (*(vu_long *)((x) + (y))) +#else +#define UData(Data) (Data) + +#define __REG(x) (x) +#define __REGl(x) (x) +#define __REGw(x) (x) +#define __REGb(x) (x) +#define __REG2(x, y) ((x) + (y)) +#endif + +#define Fld(Size, Shft) (((Size) << 16) + (Shft)) + +#define FSize(Field) ((Field) >> 16) +#define FShft(Field) ((Field) & 0x0000FFFF) +#define FMsk(Field) (((UData(1) << FSize(Field)) - 1) << FShft(Field)) +#define FAlnMsk(Field) ((UData(1) << FSize(Field)) - 1) +#define F1stBit(Field) (UData(1) << FShft(Field)) + +#define FClrBit(Data, Bit) (Data = (Data & ~(Bit))) +#define FClrFld(Data, Field) (Data = (Data & ~FMsk(Field))) + +#define FInsrt(Value, Field) \ + (UData(Value) << FShft(Field)) + +#define FExtr(Data, Field) \ + ((UData(Data) >> FShft(Field)) & FAlnMsk(Field)) + +#endif /* _ARCH_HARDWARE_H_ */ diff --git a/include/asm-arm/arch-s5pc1xx/i2c.h b/include/asm-arm/arch-s5pc1xx/i2c.h new file mode 100644 index 0000000..35a904a --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/i2c.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2009 Samsung Electronics + * Minkyu Kang mk7.kang@samsung.com + * Kyungnin Park kyungmin.park@samsung.com + * + * based on s3c24x0_i2c.c + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_I2C_H_ +#define __ASM_ARCH_I2C_H_ + +/* I2C */ +#define S5PC100_I2C0_BASE 0xEC100000 +#define S5PC100_I2C1_BASE 0xEC200000 +#define S5PC110_I2C0_BASE 0xE1800000 +#define S5PC110_I2C2_BASE 0xE1A00000 + +#ifndef __ASSEMBLY__ +typedef struct s5pc1xx_i2c { + volatile unsigned long IICCON; + volatile unsigned long IICSTAT; + volatile unsigned long IICADD; + volatile unsigned long IICDS; + volatile unsigned long IICLC; +} s5pc1xx_i2c_t; +#endif + +#endif diff --git a/include/asm-arm/arch-s5pc1xx/interrupt.h b/include/asm-arm/arch-s5pc1xx/interrupt.h new file mode 100644 index 0000000..a3c8680 --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/interrupt.h @@ -0,0 +1,40 @@ +/* + * (C) Copyright 2009 Samsung Electronics + * Minkyu Kang mk7.kang@samsung.com + * Heungjun Kim riverful.kim@samsung.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARM_ARCH_INTERRUPT_H_ +#define __ASM_ARM_ARCH_INTERRUPT_H_ + +/* Vector Interrupt Offset */ +#define VIC_IRQSTATUS_OFFSET 0x0 +#define VIC_FIQSTATUS_OFFSET 0x4 +#define VIC_RAWINTR_OFFSET 0x8 +#define VIC_INTSELECT_OFFSET 0xc +#define VIC_INTENABLE_OFFSET 0x10 +#define VIC_INTENCLEAR_OFFSET 0x14 +#define VIC_SOFTINT_OFFSET 0x18 +#define VIC_SOFTINTCLEAR_OFFSET 0x1c +#define VIC_PROTECTION_OFFSET 0x20 +#define VIC_SWPRIORITYMASK_OFFSET 0x24 +#define VIC_PRIORITYDAISY_OFFSET 0x28 +#define VIC_INTADDRESS_OFFSET 0xf00 + +#endif diff --git a/include/asm-arm/arch-s5pc1xx/keypad.h b/include/asm-arm/arch-s5pc1xx/keypad.h new file mode 100644 index 0000000..0437b5e --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/keypad.h @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2009 Samsung Electronics + * Kyungnin Park kyungmin.park@samsung.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_KEYPAD_H_ +#define __ASM_ARCH_KEYPAD_H_ + +#define S5PC100_KEYPAD_BASE 0xF3100000 +#define S5PC110_KEYPAD_BASE 0xE1600000 + +#define S5PC1XX_KEYIFCON_OFFSET (0x00) +#define S5PC1XX_KEYIFSTSCLR_OFFSET (0x04) +#define S5PC1XX_KEYIFCOL_OFFSET (0x08) +#define S5PC1XX_KEYIFROW_OFFSET (0x0C) +#define S5PC1XX_KEYIFFC_OFFSET (0x10) + +#endif diff --git a/include/asm-arm/arch-s5pc1xx/mem.h b/include/asm-arm/arch-s5pc1xx/mem.h new file mode 100644 index 0000000..4b06aaf --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/mem.h @@ -0,0 +1,58 @@ +/* + * (C) Copyright 2009 Samsung Electronics + * Minkyu Kang mk7.kang@samsung.com + * Heungjun Kim riverful.kim@samsung.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARM_ARCH_MEM_H_ +#define __ASM_ARM_ARCH_MEM_H_ + +/* + * SROMC Controller + */ +/* DRAM Memory Controller */ +#define S5PC100_DMC_BASE 0xE6000000 +#define S5PC110_DMC0_BASE 0xF0000000 +#define S5PC110_DMC1_BASE 0xF1400000 + +/* DMC offset */ +#define CONCONTROL_OFFSET 0x00 +#define MEMCONTROL_OFFSET 0x04 +#define MEMCONFIG0_OFFSET 0x08 +#define MEMCONFIG1_OFFSET 0x0c +#define DIRECTCMD_OFFSET 0x10 +#define PRECHCONFIG_OFFSET 0x14 +#define PHYCONTROL0_OFFSET 0x18 +#define PHYCONTROL1_OFFSET 0x1c +#define PHYCONTROL2_OFFSET 0x20 +#define PWRDNCONFIG_OFFSET 0x28 +#define TIMINGAREF_OFFSET 0x30 +#define TIMINGROW_OFFSET 0x34 +#define TIMINGDATA_OFFSET 0x38 +#define TIMINGPOWER_OFFSET 0x3c +#define PHYSTATUS0_OFFSET 0x40 +#define PHYSTATUS1_OFFSET 0x44 +#define CHIP0STATUS_OFFSET 0x48 +#define CHIP1STATUS_OFFSET 0x4c +#define AREFSTATUS_OFFSET 0x50 +#define MRSTATUS_OFFSET 0x54 +#define PHYTEST0_OFFSET 0x58 +#define PHYTEST1_OFFSET 0x5c + +#endif diff --git a/include/asm-arm/arch-s5pc1xx/power.h b/include/asm-arm/arch-s5pc1xx/power.h new file mode 100644 index 0000000..57e2a2b --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/power.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2009 Samsung Electronics + * Kyungmin Park kyungmin.park@samsung.com + * Minkyu Kang mk7.kang@samsung.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARM_ARCH_POWER_H_ +#define __ASM_ARM_ARCH_POWER_H_ + +/* + * Power control + */ +#define S5PC100_OTHERS 0xE0108200 +#define S5PC100_RST_STAT 0xE0108300 +#define S5PC100_SLEEP_WAKEUP (1 << 3) +#define S5PC100_WAKEUP_STAT 0xE0108304 +#define S5PC100_INFORM0 0xE0108400 + +#define S5PC110_RST_STAT 0xE010A000 +#define S5PC110_SLEEP_WAKEUP (1 << 3) +#define S5PC110_WAKEUP_STAT 0xE010C200 +#define S5PC110_OTHERS 0xE010E000 +#define S5PC110_USB_PHY_CON 0xE010E80C +#define S5PC110_INFORM0 0xE010F000 + +#endif diff --git a/include/asm-arm/arch-s5pc1xx/pwm.h b/include/asm-arm/arch-s5pc1xx/pwm.h new file mode 100644 index 0000000..6a6347e --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/pwm.h @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2009 Samsung Electronics + * Kyungmin Park kyungmin.park@samsung.com + * Minkyu Kang mk7.kang@samsung.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARM_ARCH_PWM_H_ +#define __ASM_ARM_ARCH_PWM_H_ + +/* + * PWM Timer + */ +#define S5PC100_PWMTIMER_BASE 0xEA000000 +#define S5PC110_PWMTIMER_BASE 0xE2500000 + +/* PWM timer addressing */ +#define S5PC100_TIMER_BASE S5PC100_PWMTIMER_BASE +#define S5PC110_TIMER_BASE S5PC110_PWMTIMER_BASE + +/* Interval mode(Auto Reload) of PWM Timer 4 */ +#define S5PC1XX_TCON4_AUTO_RELOAD (1 << 22) +/* Update TCNTB4 */ +#define S5PC1XX_TCON4_UPDATE (1 << 21) +/* start bit of PWM Timer 4 */ +#define S5PC1XX_TCON4_START (1 << 20) + +#ifndef __ASSEMBLY__ +typedef struct s5pc1xx_timer { + volatile unsigned long TCFG0; + volatile unsigned long TCFG1; + volatile unsigned long TCON; + volatile unsigned long TCNTB0; + volatile unsigned long TCMPB0; + volatile unsigned long TCNTO0; + volatile unsigned long TCNTB1; + volatile unsigned long TCMPB1; + volatile unsigned long TCNTO1; + volatile unsigned long TCNTB2; + volatile unsigned long TCMPB2; + volatile unsigned long TCNTO2; + volatile unsigned long TCNTB3; + volatile unsigned long res1; + volatile unsigned long TCNTO3; + volatile unsigned long TCNTB4; + volatile unsigned long TCNTO4; + volatile unsigned long TINTCSTAT; +} s5pc1xx_timers_t; +#endif /* __ASSEMBLY__ */ + +#endif diff --git a/include/asm-arm/arch-s5pc1xx/uart.h b/include/asm-arm/arch-s5pc1xx/uart.h new file mode 100644 index 0000000..189bbff --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/uart.h @@ -0,0 +1,72 @@ +/* + * (C) Copyright 2009 Samsung Electronics + * Minkyu Kang mk7.kang@samsung.com + * Heungjun Kim riverful.kim@samsung.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __ASM_ARCH_UART_H_ +#define __ASM_ARCH_UART_H_ + +/* + * UART + */ +/* uart base address */ +#define S5PC100_PA_UART 0xEC000000 +#define S5PC110_PA_UART 0xE2900000 + +#ifndef __ASSEMBLY__ +typedef struct s5pc1xx_uart { + volatile unsigned long ULCON; + volatile unsigned long UCON; + volatile unsigned long UFCON; + volatile unsigned long UMCON; + volatile unsigned long UTRSTAT; + volatile unsigned long UERSTAT; + volatile unsigned long UFSTAT; + volatile unsigned long UMSTAT; +#ifdef __BIG_ENDIAN + volatile unsigned char res1[3]; + volatile unsigned char UTXH; + volatile unsigned char res2[3]; + volatile unsigned char URXH; +#else /* Little Endian */ + volatile unsigned char UTXH; + volatile unsigned char res1[3]; + volatile unsigned char URXH; + volatile unsigned char res2[3]; +#endif + volatile unsigned long UBRDIV; +#ifdef __BIG_ENDIAN + volatile unsigned char res3[2]; + volatile unsigned short UDIVSLOT; +#else + volatile unsigned short UDIVSLOT; + volatile unsigned char res3[2]; +#endif +} s5pc1xx_uart_t; + +enum s5pc1xx_uarts_nr { + S5PC1XX_UART0, + S5PC1XX_UART1, + S5PC1XX_UART2, + S5PC1XX_UART3, +}; +#endif /* __ASSEMBLY__ */ + +#endif