Initial support for Taskit Stamp9261 board - based on an AT91SAM9261 SoC from Atmel.

Currently only a Stamp9261 with 64MB RAM fitted together with a Stamp-Adaptor on a Panel-Card EVB is supported.

Signed-off-by: Michael Roth mroth@nessie.de --- MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 3 + board/stamp9261/Makefile | 60 ++++++ board/stamp9261/config.mk | 2 + board/stamp9261/led.c | 77 ++++++++ board/stamp9261/lowlevel_init.S | 387 +++++++++++++++++++++++++++++++++++++++ board/stamp9261/stamp9261.c | 139 ++++++++++++++ include/configs/stamp9261.h | 199 ++++++++++++++++++++ 9 files changed, 872 insertions(+), 0 deletions(-) create mode 100644 board/stamp9261/Makefile create mode 100644 board/stamp9261/config.mk create mode 100644 board/stamp9261/led.c create mode 100644 board/stamp9261/lowlevel_init.S create mode 100644 board/stamp9261/stamp9261.c create mode 100644 include/configs/stamp9261.h

diff --git a/MAINTAINERS b/MAINTAINERS index 38feac8..59cd536 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -607,6 +607,10 @@ Stefan Roese sr@denx.de pdnb3 xscale scpu xscale

+Michael Roth mroth@nessie.de + + stamp9261 ARM926EJS (AT91SAM9261 SoC) + Alessandro Rubini rubini@unipv.it Nomadik Linux Team STN_WMM_nomadik_linux@list.st.com

diff --git a/MAKEALL b/MAKEALL index cf05133..7a5bbbf 100755 --- a/MAKEALL +++ b/MAKEALL @@ -573,6 +573,7 @@ LIST_at91=" \ kb9202 \ mp2usb \ m501sk \ + stamp9261 \ "

######################################################################### diff --git a/Makefile b/Makefile index 50c9975..20cccf0 100644 --- a/Makefile +++ b/Makefile @@ -2831,6 +2831,9 @@ smdk2400_config : unconfig smdk2410_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm920t smdk2410 samsung s3c24x0

+stamp9261_config: unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs stamp9261 NULL at91 + SX1_stdout_serial_config \ SX1_config: unconfig @mkdir -p $(obj)include diff --git a/board/stamp9261/Makefile b/board/stamp9261/Makefile new file mode 100644 index 0000000..68c43a1 --- /dev/null +++ b/board/stamp9261/Makefile @@ -0,0 +1,60 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop stelian.pop@leadtechdesign.com +# Lead Tech Design <www.leadtechdesign.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := stamp9261.o + +ECOBJS := led.o +ESOBJS := lowlevel_init.o + +SRCS := $(COBJS:.o=.c) $(ECOBJS:.o=.c) $(ESOBJS:.o=.S) +COBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(COBJS) + $(AR) $(ARFLAGS) $@ $(COBJS) + + +clean: + rm -f $(COBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### + + diff --git a/board/stamp9261/config.mk b/board/stamp9261/config.mk new file mode 100644 index 0000000..6d8135a --- /dev/null +++ b/board/stamp9261/config.mk @@ -0,0 +1,2 @@ +TEXT_BASE = 0x23f00000 +EXTRABOARDOBJS = lowlevel_init.o led.o diff --git a/board/stamp9261/led.c b/board/stamp9261/led.c new file mode 100644 index 0000000..367db20 --- /dev/null +++ b/board/stamp9261/led.c @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop stelian.pop@leadtechdesign.com + * Lead Tech Design <www.leadtechdesign.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/at91sam9261.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/io.h> + +#define RED_LED AT91_PIN_PA19 +#define GREEN_LED AT91_PIN_PA21 +#define YELLOW_LED AT91_PIN_PA20 + +void red_LED_on(void) +{ + at91_set_gpio_value(RED_LED, 0); +} + +void red_LED_off(void) +{ + at91_set_gpio_value(RED_LED, 1); +} + +void green_LED_on(void) +{ + at91_set_gpio_value(GREEN_LED, 0); +} + +void green_LED_off(void) +{ + at91_set_gpio_value(GREEN_LED, 1); +} + +void yellow_LED_on(void) +{ + at91_set_gpio_value(YELLOW_LED, 0); +} + +void yellow_LED_off(void) +{ + at91_set_gpio_value(YELLOW_LED, 1); +} + +void coloured_LED_init(void) +{ + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOA); + + at91_set_gpio_output(RED_LED, 1); + at91_set_gpio_output(GREEN_LED, 1); + at91_set_gpio_output(YELLOW_LED, 1); + + at91_set_gpio_value(RED_LED, 1); + at91_set_gpio_value(GREEN_LED, 1); + at91_set_gpio_value(YELLOW_LED, 1); +} diff --git a/board/stamp9261/lowlevel_init.S b/board/stamp9261/lowlevel_init.S new file mode 100644 index 0000000..0531091 --- /dev/null +++ b/board/stamp9261/lowlevel_init.S @@ -0,0 +1,387 @@ +/* + * Low Level Initialization for a Stamp9261 + * + * (C) Copyright 2009 Michael Roth mroth@nessie.de + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> + + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + + +#define SRAM_BASE 0x300000 /* Internal SRAM C */ + +#define SDRAM_BASE 0x20000000 /* External SDRAM */ + +#define SYS_BASE 0xffffea00 /* System Controller */ + +#define SDRAMC_OFFSET (0xffffea00 - SYS_BASE) +#define SDRAMC_MR_OFFSET (0xffffea00 - SDRAMC_OFFSET - SYS_BASE) +#define SDRAMC_TR_OFFSET (0xffffea04 - SDRAMC_OFFSET - SYS_BASE) +#define SDRAMC_CR_OFFSET (0xffffea08 - SDRAMC_OFFSET - SYS_BASE) + +#define SMC0_OFFSET (0xffffec00 - SYS_BASE) + +#define MATRIX_OFFSET (0xffffee00 - SYS_BASE) +#define MATRIX_SCFG3_OFFSET (0xffffee10 - MATRIX_OFFSET - SYS_BASE) +#define SLOT_CYCLE(a) ((a)<<0) +#define DEFMSTR_TYPE(a) ((a)<<16) +#define FIXED_DEFMSTR(a) ((a)<<18) +#define EBI_CSA_OFFSET (0xffffee30 - MATRIX_OFFSET - SYS_BASE) +#define EBI_CS1A(a) ((a)<<1) + +#define PIOC_OFFSET (0xfffff800 - SYS_BASE) +#define PIOC_PDR_OFFSET (0xfffff804 - PIOC_OFFSET - SYS_BASE) +#define PIOC_ASR_OFFSET (0xfffff870 - PIOC_OFFSET - SYS_BASE) + +#define PMC_OFFSET (0xfffffc00 - SYS_BASE) + +#define CKGR_MOR_OFFSET (0xfffffc20 - PMC_OFFSET - SYS_BASE) +#define OSCOUNT(a) ((a)<<8) +#define MOSCEN(a) ((a)<<0) + +#define CKGR_PLLAR_OFFSET (0xfffffc28 - PMC_OFFSET - SYS_BASE) +#define CKGR_PLLBR_OFFSET (0xfffffc2c - PMC_OFFSET - SYS_BASE) + +#define PMC_MCKR_OFFSET (0xfffffc30 - PMC_OFFSET - SYS_BASE) +#define MDIV(a) ((a)<<8) +#define CSS(a) ((a)<<0) + +#define PMC_SR_OFFSET (0xfffffc68 - PMC_OFFSET - SYS_BASE) +#define MOSCS(a) ((a)<<0) +#define LOCKA(a) ((a)<<1) +#define LOCKB(a) ((a)<<2) +#define MCKRDY(a) ((a)<<3) + +#define PLLICPR_OFFSET (0xfffffc80 - PMC_OFFSET - SYS_BASE) +#define ICPPLLA(a) ((a)<<0) +#define ICPPLLB(a) ((a)<<16) + +#define PMC_MCKR_OFFSET (0xfffffc30 - PMC_OFFSET - SYS_BASE) + +#define RSTC_OFFSET (0xfffffd00 - SYS_BASE) +#define RSTC_MR (0xfffffd08 - RSTC_OFFSET - SYS_BASE) +#define URSTEN(a) ((a)<<0) +#define KEY(a) ((a)<<24) + +#define WDT_OFFSET (0xfffffd40 - SYS_BASE) +#define WDT_MR_OFFSET (0xfffffd44 - WDT_OFFSET - SYS_BASE) +#define WDDIS(a) ((a)<<15) + + +/* + * Calculate PLL Configuration + */ +#if (AT91_CPU_CLOCK == 161938286) +# define DIVA 14 +# define MULA 122 +#elif (AT91_CPU_CLOCK == 199916308) +# define DIVA 13 +# define MULA 140 +#elif (AT91_CPU_CLOCK == 239616000) +# define DIVA 1 +# define MULA 12 +#else +# error Unsupported AT91_CPU_CLOCK +#endif + +#if (AT91_CPU_CLOCK > 195000000) +# define OUTA 2 +#else +# define OUTA 0 +#endif + +#define PLLACOUNT 0x3f + +#define CKGR_PLLAR_VALUE ((1<<29) | (MULA<<16) | (OUTA<<14) \ + | (PLLACOUNT<<8) | (DIVA)) + +#define CKGR_PLLBR_VALUE 0x10483F0E /* Fixed PLLB Settings */ + + +/* + * Calculate SDRAM Timings + */ +#define TICK_PERIOD ((1000000000) / (AT91_MASTER_CLOCK / 1000)) +#define TICKS(picosecs) ( ((picosecs)+TICK_PERIOD-1) / TICK_PERIOD ) + +#if (AT91_MASTER_CLOCK < 100000000) +# define SDRAM_CAS 2 +#else +# define SDRAM_CAS 3 +#endif + +#define SDRAM_NC 1 /* 9 Column Bits */ +#define SDRAM_NR 2 /* 13 Row Bits */ +#define SDRAM_NB 1 /* 4 banks */ +#define SDRAM_DBW 0 /* 32 Bits Data Bus */ +#define SDRAM_TWR 2 /* Last data in to row precharge */ +#define SDRAM_TRC TICKS(63000) /* Row cycle time */ +#define SDRAM_TRP TICKS(18000) /* Row precharge time */ +#define SDRAM_TRCD TICKS(18000) /* RAS to CAS delay */ +#define SDRAM_TRAS TICKS(45000) /* Row active time */ +#define SDRAM_TXSR (SDRAM_TRC + 1) /* Exit Self Refresh */ + + +#define SDRAMC_CR_VALUE ((SDRAM_TXSR<<28) | (SDRAM_TRAS<<24) \ + | (SDRAM_TRCD<<20) | (SDRAM_TRP<<16) | (SDRAM_TRC<<12) \ + | (SDRAM_TWR<<8) | (SDRAM_DBW<<7) | (SDRAM_CAS<<5) \ + | (SDRAM_NB<<4) | (SDRAM_NR<<2) | (SDRAM_NC<<0) ) + +#define SDRAMC_TR_VALUE (AT91_MASTER_CLOCK / 128000) /* Refresh Cycle */ + + + +/* + * Calculate NOR-Flash Timings + */ +#define FLASH_TRC TICKS(110000) /* Read Cycle */ +#define FLASH_TWC TICKS(110000) /* Write Cycle */ +#define FLASH_TCEH TICKS(35000) /* Chip Enable Hold Time */ +#define FLASH_TOEH TICKS(10000) /* Output Enable Hold Time */ +#define FLASH_TOE TICKS(35000) /* Output Enable to Output Delay */ +#define FLASH_TDS TICKS(45000 + TICK_PERIOD / 2) /* Data Setup Time */ +#define FLASH_TWPH TICKS(30000) /* Write Pulse Width High */ +#define FLASH_TDF TICKS(20000) /* Chip Enable to Output Tri-State */ + +#if ( (FLASH_TOE + FLASH_TOEH) >= FLASH_TRC ) +# define NCS_RD_SETUP 0 +# define NCS_RD_PULSE (FLASH_TOE + FLASH_TOEH) +# define NRD_CYCLE (FLASH_TOE + FLASH_TOEH) +# define NRD_SETUP FLASH_TOEH +# define NRD_PULSE FLASH_TOE +#else +# define NCS_RD_SETUP 0 +# define NCS_RD_PULSE FLASH_TRC +# define NRD_CYCLE FLASH_TRC +# define NRD_SETUP (FLASH_TOEH + (FLASH_TRC - FLASH_TOEH - FLASH_TOE) / 2) +# define NRD_PULSE (FLASH_TRC - NRD_SETUP) +#endif + +#if ( FLASH_TCEH >= (FLASH_TWPH - 1) ) +# define FLASH_HOLD FLASH_TCEH +#else +# define FLASH_HOLD (FLASH_TWPH - 1) +#endif + +#if ( (FLASH_TDS + 1 + FLASH_HOLD) >= FLASH_TWC ) +# define NCS_WR_SETUP 0 +# define NCS_WR_PULSE (FLASH_TDS + 1) +# define NWE_CYCLE (FLASH_TDS + 1 + FLASH_HOLD) +# define NWE_SETUP 0 +# define NWE_PULSE FLASH_TDS +#else +# define NCS_WR_SETUP 0 +# define NCS_WR_PULSE (FLASH_TDS + 1 + (FLASH_TWC - FLASH_TDS - 1 - FLASH_HOLD) / 2) +# define NWE_CYCLE FLASH_TWC +# define NWE_SETUP 0 +# define NWE_PULSE (NCS_WR_PULSE - 1) +#endif + +#define SMC0_SETUP_VALUE ((NCS_RD_SETUP<<24) | (NRD_SETUP<<16) \ + | (NCS_WR_SETUP<<8) | (NWE_SETUP<<0) ) + +#define SMC0_PULSE_VALUE ((NCS_RD_PULSE<<24) | (NRD_PULSE<<16) \ + | (NCS_WR_PULSE<<8) | (NWE_PULSE<<0) ) + +#define SMC0_CYCLE_VALUE ((NRD_CYCLE<<16) | (NWE_CYCLE<<0)) + +#define SMC0_MODE_VALUE ((FLASH_TDF<<16) | 0x00101103) + + +/* + * The Low Level Setup Code + */ + .globl lowlevel_init + .func lowlevel_init + +lowlevel_init: + + ldr r8, =SYS_BASE + + /* + * Step 1: Disable watchdog and enable user reset on NRST pin + */ + add r7, r8, #WDT_OFFSET + mov r0, #WDDIS(1) + str r0, [r7, #WDT_MR_OFFSET] + + add r7, r8, #RSTC_OFFSET + ldr r0, =KEY(0xa5) | URSTEN(1) + str r0, [r7, #RSTC_MR] + + + /* + * Step 2: Relocate to internal SRAM as mentioned in + * the datasheet because we change the chipselect timing. + */ + adr r9, relocate_start /* r9 <- start address */ + adr r10, relocate_end /* r10 <- stop address */ + mov r11, #SRAM_BASE /* r11 <- destination address */ +1: ldmia r9!, {r0-r7} /* read 8 words*/ + stmia r11!, {r0-r7} /* store 8 words */ + cmp r9, r10 /* done? */ + ble 1b + + mov pc, #SRAM_BASE /* jump to relocated code */ + + .ltorg + +relocate_start: + + /* + * Step 3: Enable the main oscillator + */ + add r7, r8, #PMC_OFFSET + ldr r0, =OSCOUNT(0x40) | MOSCEN(1) + str r0, [r7, #CKGR_MOR_OFFSET] + + /* Wait for the oscillator to stabilize */ +1: ldr r0, [r7, #PMC_SR_OFFSET] + ands r0, r0, #MOSCS(1) + beq 1b + + + /* + * Step 4: Enable PLLA and PLLB + */ + ldr r0, =ICPPLLA(1) | ICPPLLB(1) + str r0, [r7, #PLLICPR_OFFSET] + + ldr r0, =CKGR_PLLAR_VALUE + ldr r1, =CKGR_PLLBR_VALUE + str r0, [r7, #CKGR_PLLAR_OFFSET] + str r1, [r7, #CKGR_PLLBR_OFFSET] + + /* Wait until the PLLs are locked */ +1: ldr r0, [r7, #PMC_SR_OFFSET] + and r0, r0, #LOCKA(1)+LOCKB(1) + cmp r0, #LOCKA(1)+LOCKB(1) + bne 1b + + + /* + * Step 5: Switch the clocks + * + * Processor Clock = PLLA Clock / 1 + * Master Clock = Processor Clock / 2 + */ + + /* First, set master clock divider to 1/2 */ + mov r0, #MDIV(1) /* CSS=0, PRES=0, MDIV=1 */ + str r0, [r7, #PMC_MCKR_OFFSET] +1: ldr r1, [r7, #PMC_SR_OFFSET] + ands r1, r1, #MCKRDY(1) + beq 1b + + /* Second, switch to plla clock */ + orr r0, r0, #CSS(2) /* CSS=2, PRES=0, MDIV=1 */ + str r0, [r7, #PMC_MCKR_OFFSET] +1: ldr r1, [r7, #PMC_SR_OFFSET] + ands r1, r1, #MCKRDY(1) + beq 1b + + + /* + * Step 6: Configure NOR-Flash timings + */ + add r7, r8, #SMC0_OFFSET + adr r6, smc0_data /* address of configuration data */ + ldmia r6, {r0-r3} /* load 4 words configuration data */ + stmia r7, {r0-r3} /* and store them sequentially */ + + + /* + * Step 7: SDRAM Initialation + */ + + /* Enable D17 - D31 on PIO C */ + add r7, r8, #PIOC_OFFSET + ldr r0, =0xffff0000 + str r0, [r7, #PIOC_ASR_OFFSET] + str r0, [r7, #PIOC_PDR_OFFSET] + + /* Assign EBI Chip Select 1 to SDRAM */ + add r7, r8, #MATRIX_OFFSET + mov r0, #EBI_CS1A(1) + str r0, [r7, #EBI_CSA_OFFSET] + + /* Set EBI Slave Slot Cycle and Fixed Default Master to ARM926 Instruction */ + ldr r0, =SLOT_CYCLE(64) | DEFMSTR_TYPE(2) | FIXED_DEFMSTR(0) + str r0, [r7, #MATRIX_SCFG3_OFFSET] + + /* Configure SDRAM Timing */ + add r7, r8, #SDRAMC_OFFSET + ldr r0, =SDRAMC_CR_VALUE + str r0, [r7, #SDRAMC_CR_OFFSET] + + /* At least 200 us minimum delay required. We are conservative... */ + mov r0, #0x8000 +1: subs r0, r0, #1 + bne 1b + + /* Issue a NOP Command */ + mov r1, #SDRAM_BASE + mov r0, #1 /* NOP */ + str r0, [r7, #SDRAMC_MR_OFFSET] + str r0, [r1] /* do it */ + + /* Issue an "All Banks Precharge" */ + mov r0, #2 /* All Banks Precharge */ + str r0, [r7, #SDRAMC_MR_OFFSET] + str r0, [r1] /* do it */ + + /* Issue eight Auto Refresh Cycles */ + mov r0, #4 /* Auto Refresh */ + str r0, [r7, #SDRAMC_MR_OFFSET] + stmia r1, {r0-r7} /* do it eight times */ + + /* Issue an Load Mode Register */ + mov r0, #3 /* Load Mode Register */ + str r0, [r7, #SDRAMC_MR_OFFSET] + str r0, [r1] /* do it */ + + /* Switch to Normal Mode */ + mov r0, #0 /* Normal Mode */ + str r0, [r7, #SDRAMC_MR_OFFSET] + str r0, [r1] /* do it */ + + /* Configure SDRAM Refresh Cycle */ + ldr r0, =SDRAMC_TR_VALUE + str r0, [r7, #SDRAMC_TR_OFFSET] + + + /* + * Step 8: We are done. + */ + mov pc, lr + + .ltorg + +smc0_data: + .word SMC0_SETUP_VALUE + .word SMC0_PULSE_VALUE + .word SMC0_CYCLE_VALUE + .word SMC0_MODE_VALUE + +relocate_end: + + .endfunc + +#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */ diff --git a/board/stamp9261/stamp9261.c b/board/stamp9261/stamp9261.c new file mode 100644 index 0000000..51fe785 --- /dev/null +++ b/board/stamp9261/stamp9261.c @@ -0,0 +1,139 @@ +/* + * Board Initialization for Stamp9261 + * + * (C) Copyright 2009 Michael Roth mroth@nessie.de + * + * (C) Copyright 2007-2008 + * Stelian Pop stelian.pop@leadtechdesign.com + * Lead Tech Design <www.leadtechdesign.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/io.h> +#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000) +#include <net.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + + +/* + * Serial Port initialisation + */ +static void stamp9261_serial_init(void) +{ +#ifdef CONFIG_ATMEL_USART +#ifdef CONFIG_USART0 + at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */ + at91_set_A_periph(AT91_PIN_PC9, 0); /* RXD0 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0); +#endif +#ifdef CONFIG_USART1 + at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */ + at91_set_A_periph(AT91_PIN_PC13, 0); /* RXD1 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1); +#endif +#ifdef CONFIG_USART2 + at91_set_A_periph(AT91_PIN_PC14, 1); /* TXD2 */ + at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2); +#endif +#ifdef CONFIG_USART3 /* DBGU */ + at91_set_A_periph(AT91_PIN_PA10, 1); /* DTXD */ + at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); +#endif +#endif +} + + + +/* + * Ethernet initialisation + */ +static void stamp9261_dm9000_init(void) +{ +#ifdef CONFIG_DRIVER_DM9000 + /* Configure SMC CS2 for DM9000 */ + at91_sys_write(AT91_SMC_SETUP(2), + AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) | + AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0)); + at91_sys_write(AT91_SMC_PULSE(2), + AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) | + AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8)); + at91_sys_write(AT91_SMC_CYCLE(2), + AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16)); + at91_sys_write(AT91_SMC_MODE(2), + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_EXNWMODE_DISABLE | + AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 | + AT91_SMC_TDF_(1)); + + /* We don't use interrupts, so configure FIQ pin as gpio input */ + at91_set_gpio_input(AT91_PIN_PC11, 0); +#endif +} + + +int board_init(void) +{ + /* Enable Ctrlc */ + console_init_f(); + + /* arch number of Stamp9261 on Panel-Card EVB */ + gd->bd->bi_arch_number = 2056; /* FIXME: Change to MACH_TYPE_STAMP9261_PC_EVB as soon as include/asm-arm/mach-types.h is updated */ + + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + /* serial ports */ + stamp9261_serial_init(); + + /* ethernet */ + stamp9261_dm9000_init(); + + return 0; +} + + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + return 0; +} + + +#ifdef CONFIG_RESET_PHY_R +void reset_phy(void) +{ +#ifdef CONFIG_DRIVER_DM9000 + /* + * Initialize ethernet HW addr prior to starting Linux, + * needed for nfsroot + */ + eth_init(gd->bd); +#endif +} +#endif diff --git a/include/configs/stamp9261.h b/include/configs/stamp9261.h new file mode 100644 index 0000000..ab825e2 --- /dev/null +++ b/include/configs/stamp9261.h @@ -0,0 +1,199 @@ +/* + * Configuration for Stamp9261 + * + * (C) Copyright 2009 Michael Roth mroth@nessie.de + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + + +/* + * Clocks + * + * Supported values for AT91_CPU_CLOCK are: 161938286, 199916308, 239616000 + */ +#define AT91_SLOW_CLOCK 32768 +#define AT91_MAIN_CLOCK 18432000 +#define AT91_CPU_CLOCK 199916308 +#define AT91_MASTER_CLOCK (AT91_CPU_CLOCK / 2) + +#define CONFIG_SYS_HZ 1000000 + + +/* + * CPU & Board + */ +#define CONFIG_ARM926EJS /* This is an ARM926EJS Core */ +#define CONFIG_AT91SAM9261 /* It's an Atmel AT91SAM9261 SoC */ +#undef CONFIG_USE_IRQ /* don't use IRQ/FIQ stuff */ + + +/* + * ATAGs + */ +#define CONFIG_CMDLINE_TAG /* enable command line passing */ +#define CONFIG_SETUP_MEMORY_TAGS /* tells memory configuration to the kernel */ +#define CONFIG_INITRD_TAG /* tells where the initrd can be found */ + + +/* + * Serial Ports + */ +#define CONFIG_ATMEL_USART +#undef CONFIG_USART0 +#undef CONFIG_USART1 +#undef CONFIG_USART2 +#define CONFIG_USART3 /* USART 3 is DBGU */ + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } + + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_SEND_HOSTNAME + + +/* + * Command line configuration. + */ +#define CONFIG_CMD_ASKENV /* ask for env variable */ +#define CONFIG_CMD_AUTOSCRIPT /* Autoscript Support */ +#define CONFIG_CMD_BDI /* bdinfo */ +#define CONFIG_CMD_BOOTD /* bootd */ +#define CONFIG_CMD_CACHE /* icache, dcache */ +#define CONFIG_CMD_CONSOLE /* coninfo */ +#define CONFIG_CMD_DHCP /* DHCP Support */ +#define CONFIG_CMD_DIAG /* Diagnostics */ +#define CONFIG_CMD_ECHO /* echo arguments */ +#define CONFIG_CMD_ENV /* saveenv */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#define CONFIG_CMD_IMI /* iminfo */ +#define CONFIG_CMD_IMLS /* List all found images */ +#define CONFIG_CMD_ITEST /* Integer (and string) test */ +#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ +#define CONFIG_CMD_LOADB /* loadb */ +#define CONFIG_CMD_LOADS /* loads */ +#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ +#define CONFIG_CMD_MISC /* Misc functions like sleep etc */ +#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#define CONFIG_CMD_NFS /* NFS support */ +#define CONFIG_CMD_PING /* ping support */ +#define CONFIG_CMD_RUN /* run command in env variable */ +#define CONFIG_CMD_SAVES /* save S record dump */ +#define CONFIG_CMD_SETEXPR /* setexpr support */ +#define CONFIG_CMD_UNZIP /* unzip from memory to memory */ +#define CONFIG_CMD_USB /* USB Support */ +#define CONFIG_CMD_XIMG /* Load part of Multi Image */ + +#define CONFIG_AUTO_COMPLETE /* enable auto completion */ +#define CONFIG_CMDLINE_EDITING /* enable command line editing */ +#define CONFIG_SYS_LONGHELP /* include long help text */ + + +/* + * Boot Delay + */ +#define CONFIG_BOOTDELAY 3 + + +/* + * SDRAM + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 +#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ + + +/* + * Flash + */ +#define CONFIG_SYS_FLASH_BASE 0x10000000 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64 megs / 128 KB */ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_SHOW_PROGRESS 45 + + +/* + * Environment + */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_OFFSET 0x40000 /* third flash sector */ +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128 kilobytes */ + + +/* + * Ethernet + */ +#define CONFIG_DRIVER_DM9000 +#define CONFIG_DM9000_BASE 0x30000000 +#define DM9000_IO CONFIG_DM9000_BASE +#define DM9000_DATA (CONFIG_DM9000_BASE + 4) +#define CONFIG_DM9000_USE_16BIT +#define CONFIG_NET_RETRY_COUNT 20 +#undef CONFIG_RESET_PHY_R + + +/* + * USB + */ +#define CONFIG_USB_OHCI_NEW +#define LITTLEENDIAN +#define CONFIG_DOS_PARTITION +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */ +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE + + +/* + * Load Address and memory details + */ +#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END 0x23e00000 + + +/* + * Malloc, Stack and Misc + */ +#define CONFIG_SYS_MALLOC_LEN 0x80000 /* 512 kilobytes */ +#define CONFIG_STACKSIZE 0x8000 /* 32 kilobytes */ + +#define CONFIG_SYS_GBL_DATA_SIZE 128 +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + + +#endif /* __CONFIG_H */