At present the 'flight plan' for CPUs is passed into mp_init. But it is always the same. Move it into the mp_init file so everything is in one place. Also drop the SMI function since it does nothing. If we implement SMIs, more refactoring will be needed anyway.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Wolfgang Wallner wolfgang.wallner@br-automation.com Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

(no changes since v1)

arch/x86/cpu/i386/cpu.c | 24 +++++------------------- arch/x86/cpu/mp_init.c | 22 ++++++++++------------ arch/x86/include/asm/mp.h | 17 +---------------- 3 files changed, 16 insertions(+), 47 deletions(-)

diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c index a6a6afec8c..55a0907bc8 100644 --- a/arch/x86/cpu/i386/cpu.c +++ b/arch/x86/cpu/i386/cpu.c @@ -21,6 +21,7 @@ #include <common.h> #include <cpu_func.h> #include <init.h> +#include <log.h> #include <malloc.h> #include <spl.h> #include <asm/control_regs.h> @@ -631,29 +632,14 @@ int cpu_jump_to_64bit_uboot(ulong target) }

#ifdef CONFIG_SMP -static int enable_smis(struct udevice *cpu, void *unused) -{ - return 0; -} - -static struct mp_flight_record mp_steps[] = { - MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL), - /* Wait for APs to finish initialization before proceeding */ - MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL), -}; - int x86_mp_init(void) { - struct mp_params mp_params; - - mp_params.parallel_microcode_load = 0, - mp_params.flight_plan = &mp_steps[0]; - mp_params.num_records = ARRAY_SIZE(mp_steps); - mp_params.microcode_pointer = 0; + int ret;

- if (mp_init(&mp_params)) { + ret = mp_init(); + if (ret) { printf("Warning: MP init failure\n"); - return -EIO; + return log_ret(ret); }

return 0; diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c index c25d17c647..831fd7035d 100644 --- a/arch/x86/cpu/mp_init.c +++ b/arch/x86/cpu/mp_init.c @@ -41,6 +41,9 @@ struct saved_msr { uint32_t hi; } __packed;

+static struct mp_flight_record mp_steps[] = { + MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL), +};

struct mp_flight_plan { int num_records; @@ -372,7 +375,7 @@ static int start_aps(int ap_count, atomic_t *num_aps) return 0; }

-static int bsp_do_flight_plan(struct udevice *cpu, struct mp_params *mp_params) +static int bsp_do_flight_plan(struct udevice *cpu, struct mp_flight_plan *plan) { int i; int ret = 0; @@ -380,8 +383,8 @@ static int bsp_do_flight_plan(struct udevice *cpu, struct mp_params *mp_params) const int step_us = 100; int num_aps = num_cpus - 1;

- for (i = 0; i < mp_params->num_records; i++) { - struct mp_flight_record *rec = &mp_params->flight_plan[i]; + for (i = 0; i < plan->num_records; i++) { + struct mp_flight_record *rec = &plan->records[i];

/* Wait for APs if the record is not released */ if (atomic_read(&rec->barrier) == 0) { @@ -420,7 +423,7 @@ static int init_bsp(struct udevice **devp) return 0; }

-int mp_init(struct mp_params *p) +int mp_init(void) { int num_aps; atomic_t *ap_count; @@ -445,11 +448,6 @@ int mp_init(struct mp_params *p) return ret; }

- if (p == NULL || p->flight_plan == NULL || p->num_records < 1) { - printf("Invalid MP parameters\n"); - return -EINVAL; - } - num_cpus = cpu_get_count(cpu); if (num_cpus < 0) { debug("Cannot get number of CPUs: err=%d\n", num_cpus); @@ -464,8 +462,8 @@ int mp_init(struct mp_params *p) debug("Warning: Device tree does not describe all CPUs. Extra ones will not be started correctly\n");

/* Copy needed parameters so that APs have a reference to the plan */ - mp_info.num_records = p->num_records; - mp_info.records = p->flight_plan; + mp_info.num_records = ARRAY_SIZE(mp_steps); + mp_info.records = mp_steps;

/* Load the SIPI vector */ ret = load_sipi_vector(&ap_count, num_cpus); @@ -489,7 +487,7 @@ int mp_init(struct mp_params *p) }

/* Walk the flight plan for the BSP */ - ret = bsp_do_flight_plan(cpu, p); + ret = bsp_do_flight_plan(cpu, &mp_info); if (ret) { debug("CPU init failed: err=%d\n", ret); return ret; diff --git a/arch/x86/include/asm/mp.h b/arch/x86/include/asm/mp.h index 9dddf88b5a..db02904ecb 100644 --- a/arch/x86/include/asm/mp.h +++ b/arch/x86/include/asm/mp.h @@ -51,21 +51,6 @@ struct mp_flight_record { #define MP_FR_NOBLOCK_APS(ap_func, ap_arg, bsp_func, bsp_arg) \ MP_FLIGHT_RECORD(1, ap_func, ap_arg, bsp_func, bsp_arg)

-/* - * The mp_params structure provides the arguments to the mp subsystem - * for bringing up APs. - * - * At present this is overkill for U-Boot, but it may make it easier to add - * SMM support. - */ -struct mp_params { - int parallel_microcode_load; - const void *microcode_pointer; - /* Flight plan for APs and BSP */ - struct mp_flight_record *flight_plan; - int num_records; -}; - /* * mp_init() will set up the SIPI vector and bring up the APs according to * mp_params. Each flight record will be executed according to the plan. Note @@ -85,7 +70,7 @@ struct mp_params { * * mp_init() returns < 0 on error, 0 on success. */ -int mp_init(struct mp_params *params); +int mp_init(void);

/* Probes the CPU device */ int mp_init_cpu(struct udevice *cpu, void *unused);

These parameters are named differently from elsewhere in this file. Switch them to avoid confusion.

Also add comments to this function.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com Reviewed-by: Wolfgang Wallner wolfgang.wallner@br-automation.com ---

(no changes since v2)

Changes in v2: - Add comments to explain what start_aps() does

arch/x86/cpu/mp_init.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-)

diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c index e77d7f2cd6..8b00d57c88 100644 --- a/arch/x86/cpu/mp_init.c +++ b/arch/x86/cpu/mp_init.c @@ -308,13 +308,26 @@ static int apic_wait_timeout(int total_delay, const char *msg) return 0; }

-static int start_aps(int ap_count, atomic_t *num_aps) +/** + * start_aps() - Start up the APs and count how many we find + * + * This is called on the boot processor to start up all the other processors + * (here called APs). + * + * @num_aps: Number of APs we expect to find + * @ap_count: Initially zero. Incremented by this function for each AP found + * @return 0 if all APs were set up correctly or there are none to set up, + * -ENOSPC if the SIPI vector is too high in memory, + * -ETIMEDOUT if the ICR is busy or the second SIPI fails to complete + * -EIO if not all APs check in correctly + */ +static int start_aps(int num_aps, atomic_t *ap_count) { int sipi_vector; /* Max location is 4KiB below 1MiB */ const int max_vector_loc = ((1 << 20) - (1 << 12)) >> 12;

- if (ap_count == 0) + if (num_aps == 0) return 0;

/* The vector is sent as a 4k aligned address in one byte */ @@ -326,7 +339,7 @@ static int start_aps(int ap_count, atomic_t *num_aps) return -ENOSPC; }

- debug("Attempting to start %d APs\n", ap_count); + debug("Attempting to start %d APs\n", num_aps);

if (apic_wait_timeout(1000, "ICR not to be busy")) return -ETIMEDOUT; @@ -349,7 +362,7 @@ static int start_aps(int ap_count, atomic_t *num_aps) return -ETIMEDOUT;

/* Wait for CPUs to check in up to 200 us */ - wait_for_aps(num_aps, ap_count, 200, 15); + wait_for_aps(ap_count, num_aps, 200, 15);

/* Send 2nd SIPI */ if (apic_wait_timeout(1000, "ICR not to be busy")) @@ -362,9 +375,9 @@ static int start_aps(int ap_count, atomic_t *num_aps) return -ETIMEDOUT;

/* Wait for CPUs to check in */ - if (wait_for_aps(num_aps, ap_count, 10000, 50)) { + if (wait_for_aps(ap_count, num_aps, 10000, 50)) { debug("Not all APs checked in: %d/%d\n", - atomic_read(num_aps), ap_count); + atomic_read(ap_count), num_aps); return -EIO; }

Fix a typo in the command help.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Wolfgang Wallner wolfgang.wallner@br-automation.com Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

(no changes since v1)

cmd/x86/mtrr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/cmd/x86/mtrr.c b/cmd/x86/mtrr.c index 084d7315f4..5d25c5802a 100644 --- a/cmd/x86/mtrr.c +++ b/cmd/x86/mtrr.c @@ -135,5 +135,5 @@ U_BOOT_CMD( "set <reg> <type> <start> <size> - set a register\n" "\t<type> is Uncacheable, Combine, Through, Protect, Back\n" "disable <reg> - disable a register\n" - "ensable <reg> - enable a register" + "enable <reg> - enable a register" );

This function is misnamed since it does not actually init the BSP. Also it is convenient to adjust it to return a little more information.

Rename and update the function, to allow it to return the BSP CPU device and number, as well as the total number of CPUs.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Wolfgang Wallner wolfgang.wallner@br-automation.com Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

(no changes since v4)

Changes in v4: - Update get_bsp() to return zero when SMP is not inited

Changes in v2: - Drop change to include/dm/uclass.h - Mention error return in get_bsp()

arch/x86/cpu/mp_init.c | 36 +++++++++++++++++++++++------------- 1 file changed, 23 insertions(+), 13 deletions(-)

diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c index 6f6de49df0..9fdde7832a 100644 --- a/arch/x86/cpu/mp_init.c +++ b/arch/x86/cpu/mp_init.c @@ -421,9 +421,18 @@ static int bsp_do_flight_plan(struct udevice *cpu, struct mp_flight_plan *plan, return ret; }

-static int init_bsp(struct udevice **devp) +/** + * get_bsp() - Get information about the bootstrap processor + * + * @devp: If non-NULL, returns CPU device corresponding to the BSP + * @cpu_countp: If non-NULL, returns the total number of CPUs + * @return CPU number of the BSP, or -ve on error. If multiprocessing is not + * enabled, returns 0 + */ +static int get_bsp(struct udevice **devp, int *cpu_countp) { char processor_name[CPU_MAX_NAME_LEN]; + struct udevice *dev; int apic_id; int ret;

@@ -431,13 +440,20 @@ static int init_bsp(struct udevice **devp) debug("CPU: %s\n", processor_name);

apic_id = lapicid(); - ret = find_cpu_by_apic_id(apic_id, devp); - if (ret) { + ret = find_cpu_by_apic_id(apic_id, &dev); + if (ret < 0) { printf("Cannot find boot CPU, APIC ID %d\n", apic_id); return ret; } + ret = cpu_get_count(dev); + if (ret < 0) + return log_msg_ret("count", ret); + if (devp) + *devp = dev; + if (cpu_countp) + *cpu_countp = ret;

- return 0; + return dev->req_seq >= 0 ? dev->req_seq : 0; }

static int mp_init_cpu(struct udevice *cpu, void *unused) @@ -476,24 +492,18 @@ int mp_init(void) uclass_id_foreach_dev(UCLASS_CPU, cpu, uc) cpu->req_seq = dev_read_u32_default(cpu, "reg", -1);

- ret = init_bsp(&cpu); - if (ret) { + ret = get_bsp(&cpu, &num_cpus); + if (ret < 0) { debug("Cannot init boot CPU: err=%d\n", ret); return ret; }

- num_cpus = cpu_get_count(cpu); - if (num_cpus < 0) { - debug("Cannot get number of CPUs: err=%d\n", num_cpus); - return num_cpus; - } - if (num_cpus < 2) debug("Warning: Only 1 CPU is detected\n");

ret = check_cpu_devices(num_cpus); if (ret) - debug("Warning: Device tree does not describe all CPUs. Extra ones will not be started correctly\n"); + log_warning("Warning: Device tree does not describe all CPUs. Extra ones will not be started correctly\n");

/* Copy needed parameters so that APs have a reference to the plan */ mp_info.num_records = ARRAY_SIZE(mp_steps);

At present the APs (non-boot CPUs) are inited once and then parked ready for the OS to use them. However in some cases we want to send new requests through, such as to change MTRRs and keep them consistent across CPUs.

Change the last state of the flight plan to go into a wait loop, accepting instructions from the main CPU.

Drop cpu_map since it is not used.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Wolfgang Wallner wolfgang.wallner@br-automation.com ---

(no changes since v4)

Changes in v4: - Add a Kconfig to control this feature, enabled only on APL

Changes in v3: - s/slow/slot/ - Use C code instead of assembler to read/write callback pointers - Update commit message to mention dropping of cpu_map

Changes in v2: - Add more comments

arch/x86/Kconfig | 7 ++ arch/x86/cpu/apollolake/Kconfig | 1 + arch/x86/cpu/mp_init.c | 123 +++++++++++++++++++++++++++++--- arch/x86/include/asm/mp.h | 11 +++ 4 files changed, 134 insertions(+), 8 deletions(-)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 27295ef384..ff4f06ed79 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -603,6 +603,13 @@ config SMP only one CPU will be enabled regardless of the number of CPUs available.

+config SMP_AP_WORK + bool + depends on SMP + help + Allow APs to do other work after initialisation instead of going + to sleep. + config MAX_CPUS int "Maximum number of CPUs permitted" depends on SMP diff --git a/arch/x86/cpu/apollolake/Kconfig b/arch/x86/cpu/apollolake/Kconfig index 942f11f566..99d4e105c2 100644 --- a/arch/x86/cpu/apollolake/Kconfig +++ b/arch/x86/cpu/apollolake/Kconfig @@ -15,6 +15,7 @@ config INTEL_APOLLOLAKE select TPL_PCH_SUPPORT select PCH_SUPPORT select P2SB + select SMP_AP_WORK imply ENABLE_MRC_CACHE imply AHCI_PCI imply SCSI diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c index 9fdde7832a..787de92fa3 100644 --- a/arch/x86/cpu/mp_init.c +++ b/arch/x86/cpu/mp_init.c @@ -15,6 +15,7 @@ #include <asm/atomic.h> #include <asm/cpu.h> #include <asm/interrupt.h> +#include <asm/io.h> #include <asm/lapic.h> #include <asm/microcode.h> #include <asm/mp.h> @@ -43,13 +44,38 @@ struct mp_flight_plan { struct mp_flight_record *records; };

+/** + * struct mp_callback - Callback information for APs + * + * @func: Function to run + * @arg: Argument to pass to the function + * @logical_cpu_number: Either a CPU number (i.e. dev->req_seq) or a special + * value like MP_SELECT_BSP. It tells the AP whether it should process this + * callback + */ +struct mp_callback { + /** + * func() - Function to call on the AP + * + * @arg: Argument to pass + */ + void (*func)(void *arg); + void *arg; + int logical_cpu_number; +}; + static struct mp_flight_plan mp_info;

-struct cpu_map { - struct udevice *dev; - int apic_id; - int err_code; -}; +/* + * ap_callbacks - Callback mailbox array + * + * Array of callback, one entry for each available CPU, indexed by the CPU + * number, which is dev->req_seq. The entry for the main CPU is never used. + * When this is NULL, there is no pending work for the CPU to run. When + * non-NULL it points to the mp_callback structure. This is shared between all + * CPUs, so should only be written by the main CPU. + */ +static struct mp_callback **ap_callbacks;

static inline void barrier_wait(atomic_t *b) { @@ -147,11 +173,12 @@ static void ap_init(unsigned int cpu_index) debug("AP: slot %d apic_id %x, dev %s\n", cpu_index, apic_id, dev ? dev->name : "(apic_id not found)");

- /* Walk the flight plan */ + /* + * Walk the flight plan, which only returns if CONFIG_SMP_AP_WORK is not + * enabled + */ ap_do_flight_plan(dev);

- /* Park the AP */ - debug("parking\n"); done: stop_this_cpu(); } @@ -456,6 +483,81 @@ static int get_bsp(struct udevice **devp, int *cpu_countp) return dev->req_seq >= 0 ? dev->req_seq : 0; }

+/** + * read_callback() - Read the pointer in a callback slot + * + * This is called by APs to read their callback slot to see if there is a + * pointer to new instructions + * + * @slot: Pointer to the AP's callback slot + * @return value of that pointer + */ +static struct mp_callback *read_callback(struct mp_callback **slot) +{ + dmb(); + + return *slot; +} + +/** + * store_callback() - Store a pointer to the callback slot + * + * This is called by APs to write NULL into the callback slot when they have + * finished the work requested by the BSP. + * + * @slot: Pointer to the AP's callback slot + * @val: Value to write (e.g. NULL) + */ +static void store_callback(struct mp_callback **slot, struct mp_callback *val) +{ + *slot = val; + dmb(); +} + +/** + * ap_wait_for_instruction() - Wait for and process requests from the main CPU + * + * This is called by APs (here, everything other than the main boot CPU) to + * await instructions. They arrive in the form of a function call and argument, + * which is then called. This uses a simple mailbox with atomic read/set + * + * @cpu: CPU that is waiting + * @unused: Optional argument provided by struct mp_flight_record, not used here + * @return Does not return + */ +static int ap_wait_for_instruction(struct udevice *cpu, void *unused) +{ + struct mp_callback lcb; + struct mp_callback **per_cpu_slot; + + if (!IS_ENABLED(CONFIG_SMP_AP_WORK)) + return 0; + + per_cpu_slot = &ap_callbacks[cpu->req_seq]; + + while (1) { + struct mp_callback *cb = read_callback(per_cpu_slot); + + if (!cb) { + asm ("pause"); + continue; + } + + /* Copy to local variable before using the value */ + memcpy(&lcb, cb, sizeof(lcb)); + mfence(); + if (lcb.logical_cpu_number == MP_SELECT_ALL || + lcb.logical_cpu_number == MP_SELECT_APS || + cpu->req_seq == lcb.logical_cpu_number) + lcb.func(lcb.arg); + + /* Indicate we are finished */ + store_callback(per_cpu_slot, NULL); + } + + return 0; +} + static int mp_init_cpu(struct udevice *cpu, void *unused) { struct cpu_platdata *plat = dev_get_parent_platdata(cpu); @@ -468,6 +570,7 @@ static int mp_init_cpu(struct udevice *cpu, void *unused)

static struct mp_flight_record mp_steps[] = { MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL), + MP_FR_BLOCK_APS(ap_wait_for_instruction, NULL, NULL, NULL), };

int mp_init(void) @@ -505,6 +608,10 @@ int mp_init(void) if (ret) log_warning("Warning: Device tree does not describe all CPUs. Extra ones will not be started correctly\n");

+ ap_callbacks = calloc(num_cpus, sizeof(struct mp_callback *)); + if (!ap_callbacks) + return -ENOMEM; + /* Copy needed parameters so that APs have a reference to the plan */ mp_info.num_records = ARRAY_SIZE(mp_steps); mp_info.records = mp_steps; diff --git a/arch/x86/include/asm/mp.h b/arch/x86/include/asm/mp.h index 94af819ad9..41b1575f4b 100644 --- a/arch/x86/include/asm/mp.h +++ b/arch/x86/include/asm/mp.h @@ -11,6 +11,17 @@ #include <asm/atomic.h> #include <asm/cache.h>

+enum { + /* Indicates that the function should run on all CPUs */ + MP_SELECT_ALL = -1, + + /* Run on boot CPUs */ + MP_SELECT_BSP = -2, + + /* Run on non-boot CPUs */ + MP_SELECT_APS = -3, +}; + typedef int (*mp_callback_t)(struct udevice *cpu, void *arg);

/*

Allow keeping track of whether all CPUs have been enabled yet. This allows us to know whether other CPUs need to be considered when updating CPU-specific settings such as MTRRs on x86.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Wolfgang Wallner wolfgang.wallner@br-automation.com ---

(no changes since v3)

Changes in v3: - Rename flag to GD_FLG_SMP_READY

include/asm-generic/global_data.h | 1 + 1 file changed, 1 insertion(+)

diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index 8c78792cc9..d4a4e2215d 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -167,5 +167,6 @@ typedef struct global_data { #define GD_FLG_LOG_READY 0x08000 /* Log system is ready for use */ #define GD_FLG_WDT_READY 0x10000 /* Watchdog is ready for use */ #define GD_FLG_SKIP_LL_INIT 0x20000 /* Don't perform low-level init */ +#define GD_FLG_SMP_READY 0x40000 /* SMP init is complete */

#endif /* __ASM_GENERIC_GBL_DATA_H */

Set this flag so we can track when it is safe to use CPUs other than the main one.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Wolfgang Wallner wolfgang.wallner@br-automation.com Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

(no changes since v3)

Changes in v3: - Rename flag to GD_FLG_SMP_READY

arch/x86/cpu/mp_init.c | 1 + 1 file changed, 1 insertion(+)

diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c index 787de92fa3..69a23829b9 100644 --- a/arch/x86/cpu/mp_init.c +++ b/arch/x86/cpu/mp_init.c @@ -643,6 +643,7 @@ int mp_init(void) debug("CPU init failed: err=%d\n", ret); return ret; } + gd->flags |= GD_FLG_SMP_READY;

return 0; }

SMP should be set up in U-Boot where possible, not SPL. Disable it in SPL. For 64-bit U-Boot we should find a way to allow SMP operations in U-Boot, but this is somewhat more complicated. For now that is disabled too.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com Reviewed-by: Wolfgang Wallner wolfgang.wallner@br-automation.com ---

(no changes since v2)

Changes in v2: - Add a new patch to avoid enabling SMP in SPL

arch/x86/cpu/Makefile | 2 +- arch/x86/include/asm/mp.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index ee0499f5d7..16e67e3da2 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -60,7 +60,7 @@ ifndef CONFIG_SYS_COREBOOT obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += irq.o endif ifndef CONFIG_$(SPL_)X86_64 -obj-$(CONFIG_SMP) += mp_init.o +obj-$(CONFIG_$(SPL_)SMP) += mp_init.o endif obj-y += mtrr.o obj-$(CONFIG_PCI) += pci.o diff --git a/arch/x86/include/asm/mp.h b/arch/x86/include/asm/mp.h index 9379826b6b..ff49004222 100644 --- a/arch/x86/include/asm/mp.h +++ b/arch/x86/include/asm/mp.h @@ -93,7 +93,7 @@ int x86_mp_init(void); */ typedef void (*mp_run_func)(void *arg);

-#if defined(CONFIG_SMP) && !CONFIG_IS_ENABLED(X86_64) +#if CONFIG_IS_ENABLED(SMP) && !CONFIG_IS_ENABLED(X86_64) /** * mp_run_on_cpus() - Run a function on one or all CPUs *

When the boot CPU MTRRs are updated, perform the same update on all other CPUs so they are kept in sync.

This avoids kernel warnings about mismatched MTRRs.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Wolfgang Wallner wolfgang.wallner@br-automation.com ---

(no changes since v2)

Changes in v2: - Rename function to mtrr_write_all()

arch/x86/cpu/mtrr.c | 57 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+)

diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c index c9b4e7d06e..5c567551e5 100644 --- a/arch/x86/cpu/mtrr.c +++ b/arch/x86/cpu/mtrr.c @@ -74,10 +74,61 @@ void mtrr_read_all(struct mtrr_info *info) } }

+void mtrr_write_all(struct mtrr_info *info) +{ + struct mtrr_state state; + int i; + + for (i = 0; i < MTRR_COUNT; i++) { + mtrr_open(&state, true); + wrmsrl(MTRR_PHYS_BASE_MSR(i), info->mtrr[i].base); + wrmsrl(MTRR_PHYS_MASK_MSR(i), info->mtrr[i].mask); + mtrr_close(&state, true); + } +} + +static void write_mtrrs(void *arg) +{ + struct mtrr_info *info = arg; + + mtrr_write_all(info); +} + +static void read_mtrrs(void *arg) +{ + struct mtrr_info *info = arg; + + mtrr_read_all(info); +} + +/** + * mtrr_copy_to_aps() - Copy the MTRRs from the boot CPU to other CPUs + * + * @return 0 on success, -ve on failure + */ +static int mtrr_copy_to_aps(void) +{ + struct mtrr_info info; + int ret; + + ret = mp_run_on_cpus(MP_SELECT_BSP, read_mtrrs, &info); + if (ret == -ENXIO) + return 0; + else if (ret) + return log_msg_ret("bsp", ret); + + ret = mp_run_on_cpus(MP_SELECT_APS, write_mtrrs, &info); + if (ret) + return log_msg_ret("bsp", ret); + + return 0; +} + int mtrr_commit(bool do_caches) { struct mtrr_request *req = gd->arch.mtrr_req; struct mtrr_state state; + int ret; int i;

debug("%s: enabled=%d, count=%d\n", __func__, gd->arch.has_mtrr, @@ -99,6 +150,12 @@ int mtrr_commit(bool do_caches) mtrr_close(&state, do_caches); debug("mtrr done\n");

+ if (gd->flags & GD_FLG_RELOC) { + ret = mtrr_copy_to_aps(); + if (ret) + return log_msg_ret("copy", ret); + } + return 0; }

To enable support for the 'mtrr' command, add a way to perform MTRR operations on selected CPUs.

This works by setting up a little 'operation' structure and sending it around the CPUs for action.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com Reviewed-by: Wolfgang Wallner wolfgang.wallner@br-automation.com ---

(no changes since v2)

Changes in v2: - Keep things building by temporarily renaming the function in cmd/

arch/x86/cpu/mtrr.c | 81 +++++++++++++++++++++++++++++++++++++ arch/x86/include/asm/mtrr.h | 21 ++++++++++ cmd/x86/mtrr.c | 6 +-- 3 files changed, 105 insertions(+), 3 deletions(-)

diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c index 5c567551e5..2468d88a80 100644 --- a/arch/x86/cpu/mtrr.c +++ b/arch/x86/cpu/mtrr.c @@ -221,3 +221,84 @@ int mtrr_set_next_var(uint type, uint64_t start, uint64_t size)

return 0; } + +/** enum mtrr_opcode - supported operations for mtrr_do_oper() */ +enum mtrr_opcode { + MTRR_OP_SET, + MTRR_OP_SET_VALID, +}; + +/** + * struct mtrr_oper - An MTRR operation to perform on a CPU + * + * @opcode: Indicates operation to perform + * @reg: MTRR reg number to select (0-7, -1 = all) + * @valid: Valid value to write for MTRR_OP_SET_VALID + * @base: Base value to write for MTRR_OP_SET + * @mask: Mask value to write for MTRR_OP_SET + */ +struct mtrr_oper { + enum mtrr_opcode opcode; + int reg; + bool valid; + u64 base; + u64 mask; +}; + +static void mtrr_do_oper(void *arg) +{ + struct mtrr_oper *oper = arg; + u64 mask; + + switch (oper->opcode) { + case MTRR_OP_SET_VALID: + mask = native_read_msr(MTRR_PHYS_MASK_MSR(oper->reg)); + if (oper->valid) + mask |= MTRR_PHYS_MASK_VALID; + else + mask &= ~MTRR_PHYS_MASK_VALID; + wrmsrl(MTRR_PHYS_MASK_MSR(oper->reg), mask); + break; + case MTRR_OP_SET: + wrmsrl(MTRR_PHYS_BASE_MSR(oper->reg), oper->base); + wrmsrl(MTRR_PHYS_MASK_MSR(oper->reg), oper->mask); + break; + } +} + +static int mtrr_start_op(int cpu_select, struct mtrr_oper *oper) +{ + struct mtrr_state state; + int ret; + + mtrr_open(&state, true); + ret = mp_run_on_cpus(cpu_select, mtrr_do_oper, oper); + mtrr_close(&state, true); + if (ret) + return log_msg_ret("run", ret); + + return 0; +} + +int mtrr_set_valid(int cpu_select, int reg, bool valid) +{ + struct mtrr_oper oper; + + oper.opcode = MTRR_OP_SET_VALID; + oper.reg = reg; + oper.valid = valid; + + return mtrr_start_op(cpu_select, &oper); +} + +int mtrr_set(int cpu_select, int reg, u64 base, u64 mask) +{ + struct mtrr_oper oper; + + oper.opcode = MTRR_OP_SET; + oper.reg = reg; + oper.base = base; + oper.mask = mask; + + return mtrr_start_op(cpu_select, &oper); +} diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index e1f1a44643..48db1dd82f 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -159,6 +159,27 @@ int mtrr_set_next_var(uint type, uint64_t base, uint64_t size); */ void mtrr_read_all(struct mtrr_info *info);

+/** + * mtrr_set_valid() - Set the valid flag for a selected MTRR and CPU(s) + * + * @cpu_select: Selected CPUs (either a CPU number or MP_SELECT_...) + * @reg: MTRR register to write (0-7) + * @valid: Valid flag to write + * @return 0 on success, -ve on error + */ +int mtrr_set_valid(int cpu_select, int reg, bool valid); + +/** + * mtrr_set() - Set the valid flag for a selected MTRR and CPU(s) + * + * @cpu_select: Selected CPUs (either a CPU number or MP_SELECT_...) + * @reg: MTRR register to write (0-7) + * @base: Base address and MTRR_BASE_TYPE_MASK + * @mask: Mask and MTRR_PHYS_MASK_VALID + * @return 0 on success, -ve on error + */ +int mtrr_set(int cpu_select, int reg, u64 base, u64 mask); + #endif

#if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0) diff --git a/cmd/x86/mtrr.c b/cmd/x86/mtrr.c index f357f58767..46ef6a2830 100644 --- a/cmd/x86/mtrr.c +++ b/cmd/x86/mtrr.c @@ -96,7 +96,7 @@ static int do_mtrr_set(uint reg, int argc, char *const argv[]) return 0; }

-static int mtrr_set_valid(int reg, bool valid) +static int mtrr_set_valid_(int reg, bool valid) { struct mtrr_state state; uint64_t mask; @@ -134,9 +134,9 @@ static int do_mtrr(struct cmd_tbl *cmdtp, int flag, int argc, return CMD_RET_USAGE; } if (*cmd == 'e') - return mtrr_set_valid(reg, true); + return mtrr_set_valid_(reg, true); else if (*cmd == 'd') - return mtrr_set_valid(reg, false); + return mtrr_set_valid_(reg, false); else if (*cmd == 's') return do_mtrr_set(reg, argc - 1, argv + 1); else

At present do_mtrr() does the 'list' subcommand at the top and the rest below. Update it to do them all in the same place so we can (in a later patch) add parsing of the CPU number for all subcommands.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Wolfgang Wallner wolfgang.wallner@br-automation.com Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

(no changes since v1)

cmd/x86/mtrr.c | 55 +++++++++++++++++++++++++++++++++----------------- 1 file changed, 36 insertions(+), 19 deletions(-)

diff --git a/cmd/x86/mtrr.c b/cmd/x86/mtrr.c index b047a9897c..b51b1cd7e2 100644 --- a/cmd/x86/mtrr.c +++ b/cmd/x86/mtrr.c @@ -98,31 +98,48 @@ static int do_mtrr_set(int cpu_select, uint reg, int argc, char *const argv[]) static int do_mtrr(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { - const char *cmd; + int cmd; int cpu_select; uint reg; + int ret;

cpu_select = MP_SELECT_BSP; - cmd = argv[1]; - if (argc < 2 || *cmd == 'l') + argc--; + argv++; + cmd = argv[0] ? *argv[0] : 0; + if (argc < 1 || !cmd) { + cmd = 'l'; + reg = 0; + } else { + if (argc < 2) + return CMD_RET_USAGE; + reg = simple_strtoul(argv[1], NULL, 16); + if (reg >= MTRR_COUNT) { + printf("Invalid register number\n"); + return CMD_RET_USAGE; + } + } + if (cmd == 'l') { return do_mtrr_list(cpu_select); - argc -= 2; - argv += 2; - if (argc <= 0) - return CMD_RET_USAGE; - reg = simple_strtoul(argv[0], NULL, 16); - if (reg >= MTRR_COUNT) { - printf("Invalid register number\n"); - return CMD_RET_USAGE; + } else { + switch (cmd) { + case 'e': + ret = mtrr_set_valid(cpu_select, reg, true); + break; + case 'd': + ret = mtrr_set_valid(cpu_select, reg, false); + break; + case 's': + ret = do_mtrr_set(cpu_select, reg, argc - 2, argv + 2); + break; + default: + return CMD_RET_USAGE; + } + if (ret) { + printf("Operation failed (err=%d)\n", ret); + return CMD_RET_FAILURE; + } } - if (*cmd == 'e') - return mtrr_set_valid(cpu_select, reg, true); - else if (*cmd == 'd') - return mtrr_set_valid(cpu_select, reg, false); - else if (*cmd == 's') - return do_mtrr_set(cpu_select, reg, argc - 1, argv + 1); - else - return CMD_RET_USAGE;

return 0; }

Add a description of how this module works and also some missing function comments.

Reviewed-by: Wolfgang Wallner wolfgang.wallner@br-automation.com Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

(no changes since v3)

Changes in v3: - Remove stray asterisk from comments - Drop mention of cpu_map which was handled in a previous patch

Changes in v2: - Add a new patch with more comments

arch/x86/cpu/mp_init.c | 91 ++++++++++++++++++++++++++++++++++++++- arch/x86/include/asm/mp.h | 14 +++++- 2 files changed, 102 insertions(+), 3 deletions(-)

diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c index c373c3099a..d2f1ee38cf 100644 --- a/arch/x86/cpu/mp_init.c +++ b/arch/x86/cpu/mp_init.c @@ -32,13 +32,99 @@

DECLARE_GLOBAL_DATA_PTR;

+/* + * Setting up multiprocessing + * + * See https://www.intel.com/content/www/us/en/intelligent-systems/intel-boot-loade... + * + * Note that this file refers to the boot CPU (the one U-Boot is running on) as + * the BSP (BootStrap Processor) and the others as APs (Application Processors). + * + * This module works by loading some setup code into RAM at AP_DEFAULT_BASE and + * telling each AP to execute it. The code that each AP runs is in + * sipi_vector.S (see ap_start16) which includes a struct sipi_params at the + * end of it. Those parameters are set up by the C code. + + * Setting up is handled by load_sipi_vector(). It inits the common block of + * parameters (sipi_params) which tell the APs what to do. This block includes + * microcode and the MTTRs (Memory-Type-Range Registers) from the main CPU. + * There is also an ap_count which each AP increments as it starts up, so the + * BSP can tell how many checked in. + * + * The APs are started with a SIPI (Startup Inter-Processor Interrupt) which + * tells an AP to start executing at a particular address, in this case + * AP_DEFAULT_BASE which contains the code copied from ap_start16. This protocol + * is handled by start_aps(). + * + * After being started, each AP runs the code in ap_start16, switches to 32-bit + * mode, runs the code at ap_start, then jumps to c_handler which is ap_init(). + * This runs a very simple 'flight plan' described in mp_steps(). This sets up + * the CPU and waits for further instructions by looking at its entry in + * ap_callbacks[]. Note that the flight plan is only actually run for each CPU + * in bsp_do_flight_plan(): once the BSP completes each flight record, it sets + * mp_flight_record->barrier to 1 to allow the APs to executed the record one + * by one. + * + * CPUS are numbered sequentially from 0 using the device tree: + * + * cpus { + * u-boot,dm-pre-reloc; + * #address-cells = <1>; + * #size-cells = <0>; + * + * cpu@0 { + * u-boot,dm-pre-reloc; + * device_type = "cpu"; + * compatible = "intel,apl-cpu"; + * reg = <0>; + * intel,apic-id = <0>; + * }; + * + * cpu@1 { + * device_type = "cpu"; + * compatible = "intel,apl-cpu"; + * reg = <1>; + * intel,apic-id = <2>; + * }; + * + * Here the 'reg' property is the CPU number and then is placed in dev->req_seq + * so that we can index into ap_callbacks[] using that. The APIC ID is different + * and may not be sequential (it typically is if hyperthreading is supported). + * + * Once APs are inited they wait in ap_wait_for_instruction() for instructions. + * Instructions come in the form of a function to run. This logic is in + * mp_run_on_cpus() which supports running on any one AP, all APs, just the BSP + * or all CPUs. The BSP logic is handled directly in mp_run_on_cpus(), by + * calling the function. For the APs, callback information is stored in a + * single, common struct mp_callback and a pointer to this is written to each + * AP's slot in ap_callbacks[] by run_ap_work(). All APs get the message even + * if it is only for one of them. When an AP notices a message it checks whether + * it should call the function (see check in ap_wait_for_instruction()) and then + * does so if needed. After that it sets its slot to NULL to indicate it is + * done. + * + * While U-Boot is running it can use mp_run_on_cpus() to run code on the APs. + * An example of this is the 'mtrr' command which allows reading and changing + * the MTRRs on all CPUs. + * + * Before U-Boot exits it calls mp_park_aps() which tells all CPUs to halt by + * executing a 'hlt' instruction. That allows them to be used by Linux when it + * starts up. + */ + /* This also needs to match the sipi.S assembly code for saved MSR encoding */ -struct saved_msr { +struct __packed saved_msr { uint32_t index; uint32_t lo; uint32_t hi; -} __packed; +};

+/** + * struct mp_flight_plan - Holds the flight plan + * + * @num_records: Number of flight records + * @records: Pointer to each record + */ struct mp_flight_plan { int num_records; struct mp_flight_record *records; @@ -59,6 +145,7 @@ struct mp_callback { int logical_cpu_number; };

+/* Stores the flight plan so that APs can find it */ static struct mp_flight_plan mp_info;

/* diff --git a/arch/x86/include/asm/mp.h b/arch/x86/include/asm/mp.h index ff49004222..5f9b8c6564 100644 --- a/arch/x86/include/asm/mp.h +++ b/arch/x86/include/asm/mp.h @@ -36,6 +36,14 @@ typedef int (*mp_callback_t)(struct udevice *cpu, void *arg); * * Note that ap_call() and bsp_call() can be NULL. In the NULL case the * callback will just not be called. + * + * @barrier: Ensures that the BSP and AP don't run the flight record at the same + * time + * @cpus_entered: Counts the number of APs that have run this record + * @ap_call: Function for the APs to call + * @ap_arg: Argument to pass to @ap_call + * @bsp_call: Function for the BSP to call + * @bsp_arg: Argument to pass to @bsp_call */ struct mp_flight_record { atomic_t barrier; @@ -83,7 +91,11 @@ struct mp_flight_record { */ int mp_init(void);

-/* Set up additional CPUs */ +/** + * x86_mp_init() - Set up additional CPUs + * + * @returns < 0 on error, 0 on success. + */ int x86_mp_init(void);

/**