From: Takahiro Kuwano Takahiro.Kuwano@infineon.com

The correct 4KB erase opcode should be selected based on the address width currently used.

Fixes: 562d166a13 ("mtd: spi-nor-core: Add fixups for s25fs512s") Signed-off-by: Takahiro Kuwano Takahiro.Kuwano@infineon.com Reviewed-by: Pratyush Yadav pratyush@kernel.org Reviewed-by: Dhruva Gole d-gole@ti.com --- drivers/mtd/spi/spi-nor-core.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index aea611fef52..b633f3092b1 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -3349,8 +3349,10 @@ static int s25fs_s_quad_enable(struct spi_nor *nor)

static int s25fs_s_erase_non_uniform(struct spi_nor *nor, loff_t addr) { + u8 opcode = nor->addr_width == 4 ? SPINOR_OP_BE_4K_4B : SPINOR_OP_BE_4K; + /* Support 8 x 4KB sectors at bottom */ - return spansion_erase_non_uniform(nor, addr, SPINOR_OP_BE_4K_4B, 0, SZ_32K); + return spansion_erase_non_uniform(nor, addr, opcode, 0, SZ_32K); }

static int s25fs_s_setup(struct spi_nor *nor, const struct flash_info *info,

From: Takahiro Kuwano Takahiro.Kuwano@infineon.com

The S25FS064S, S25FS128S, and S25FS256S are the same family of SPI NOR Flash devices with S25FS512S. Some difference depending on the device densities are taken care in post SFDP fixup.

Signed-off-by: Takahiro Kuwano Takahiro.Kuwano@infineon.com Reviewed-by: Pratyush Yadav pratyush@kernel.org --- drivers/mtd/spi/spi-nor-core.c | 24 ++++++++++++++++++------ drivers/mtd/spi/spi-nor-ids.c | 3 +++ 2 files changed, 21 insertions(+), 6 deletions(-)

diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index b633f3092b1..e126fa37c16 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -3406,12 +3406,24 @@ static int s25fs_s_post_bfpt_fixup(struct spi_nor *nor, static void s25fs_s_post_sfdp_fixup(struct spi_nor *nor, struct spi_nor_flash_parameter *params) { - /* READ_1_1_2 is not supported */ - params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_2; - /* READ_1_1_4 is not supported */ - params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_4; - /* PP_1_1_4 is not supported */ - params->hwcaps.mask &= ~SNOR_HWCAPS_PP_1_1_4; + /* + * The S25FS064S(8MB) supports 1-1-2 and 1-1-4 commands, but params for + * read ops in SFDP are wrong. The other density parts do not support + * 1-1-2 and 1-1-4 commands. + */ + if (params->size == SZ_8M) { + spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_2], + 0, 8, SPINOR_OP_READ_1_1_2, + SNOR_PROTO_1_1_2); + spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_4], + 0, 8, SPINOR_OP_READ_1_1_4, + SNOR_PROTO_1_1_4); + } else { + params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_2; + params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_4; + params->hwcaps.mask &= ~SNOR_HWCAPS_PP_1_1_4; + } + /* Use volatile register to enable quad */ params->quad_enable = s25fs_s_quad_enable; } diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 17e0f84e9ee..9693c179b7e 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -342,6 +342,9 @@ const struct flash_info spi_nor_ids[] = { { INFO6("s25fl256s0", 0x010219, 0x4d0080, 256 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { INFO6("s25fl256s1", 0x010219, 0x4d0180, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, + { INFO6("s25fs064s", 0x010217, 0x4d0181, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, + { INFO6("s25fs128s", 0x012018, 0x4d0181, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, + { INFO6("s25fs256s", 0x010219, 0x4d0181, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { INFO("s25fl512s_256k", 0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { INFO("s25fl512s_64k", 0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },