From: Joseph Chen chenjh@rock-chips.com

Add dts to RK3588 board, which is a must for ARM platform.

Signed-off-by: Joseph Chen chenjh@rock-chips.com --- arch/arm/dts/rk3588-evb.dts | 31 + arch/arm/dts/rk3588-u-boot.dtsi | 250 ++ arch/arm/dts/rk3588-vccio3-pinctrl.dtsi | 453 ++++ arch/arm/dts/rk3588.dtsi | 518 ++++ arch/arm/dts/rk3588s-pinctrl.dtsi | 3009 +++++++++++++++++++++++ arch/arm/dts/rk3588s.dtsi | 2370 ++++++++++++++++++ 6 files changed, 6631 insertions(+) create mode 100644 arch/arm/dts/rk3588-evb.dts create mode 100644 arch/arm/dts/rk3588-u-boot.dtsi create mode 100644 arch/arm/dts/rk3588-vccio3-pinctrl.dtsi create mode 100644 arch/arm/dts/rk3588.dtsi create mode 100644 arch/arm/dts/rk3588s-pinctrl.dtsi create mode 100644 arch/arm/dts/rk3588s.dtsi

diff --git a/arch/arm/dts/rk3588-evb.dts b/arch/arm/dts/rk3588-evb.dts new file mode 100644 index 0000000000..ad750d5b74 --- /dev/null +++ b/arch/arm/dts/rk3588-evb.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd + * + */ + +/dts-v1/; +#include "rk3588.dtsi" +#include "rk3588-u-boot.dtsi" +#include <dt-bindings/input/input.h> + +/ { + model = "Rockchip RK3588 Evaluation Board"; + compatible = "rockchip,rk3588-evb", "rockchip,rk3588"; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + u-boot,dm-pre-reloc; + status = "okay"; + + volumeup-key { + u-boot,dm-pre-reloc; + linux,code = <KEY_VOLUMEUP>; + label = "volume up"; + press-threshold-microvolt = <1750>; + }; + }; +}; diff --git a/arch/arm/dts/rk3588-u-boot.dtsi b/arch/arm/dts/rk3588-u-boot.dtsi new file mode 100644 index 0000000000..a38a6dc57f --- /dev/null +++ b/arch/arm/dts/rk3588-u-boot.dtsi @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2021 Rockchip Electronics Co., Ltd + */ + +#include <dt-bindings/gpio/gpio.h> + +/ { + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = &uart2; + u-boot,spl-boot-order = &sdmmc, &sdhci, &spi_nand, &spi_nor; + }; + + secure-otp@fe3a0000 { + u-boot,dm-spl; + compatible = "rockchip,rk3588-secure-otp"; + reg = <0x0 0xfe3a0000 0x0 0x4000>; + }; +}; + +&firmware { + u-boot,dm-spl; +}; + +&gpio0 { + u-boot,dm-spl; + status = "okay"; +}; + +&gpio1 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&gpio2 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&gpio3 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&gpio4 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&scmi { + u-boot,dm-spl; +}; + +&scmi_clk { + u-boot,dm-spl; +}; + +&sram { + u-boot,dm-spl; +}; + +&scmi_shmem { + u-boot,dm-spl; +}; + +&xin24m { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&cru { + u-boot,dm-spl; + status = "okay"; +}; + +&psci { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&crypto { + u-boot,dm-spl; + status = "okay"; +}; + +&sys_grf { + u-boot,dm-spl; + status = "okay"; +}; + +&pcie30_phy_grf { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&php_grf { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&pipe_phy0_grf { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&pipe_phy1_grf { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&pipe_phy2_grf { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&uart2 { + u-boot,dm-spl; + status = "okay"; +}; + +&hw_decompress { + u-boot,dm-spl; + status = "okay"; +}; + +&rng { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&sfc { + u-boot,dm-spl; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + spi_nand: flash@0 { + u-boot,dm-spl; + compatible = "spi-nand"; + reg = <0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <80000000>; + }; + + spi_nor: flash@1 { + u-boot,dm-spl; + compatible = "jedec,spi-nor"; + label = "sfc_nor"; + reg = <0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <80000000>; + }; +}; + +&saradc { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + u-boot,dm-spl; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + u-boot,dm-spl; + mmc-hs400-1_8v; + non-removable; + status = "okay"; +}; + +/* Support SPL-PINCTRL: + * 1. ioc + * 2. pinctrl(sdmmc) + * 3. gpio if need + */ +&ioc { + u-boot,dm-spl; +}; + +&pinctrl { + u-boot,dm-spl; + /delete-node/ sdmmc; + sdmmc { + u-boot,dm-spl; + sdmmc_bus4: sdmmc-bus4 { + u-boot,dm-spl; + rockchip,pins = + /* sdmmc_d0 */ + <4 RK_PD0 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc_d1 */ + <4 RK_PD1 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc_d2 */ + <4 RK_PD2 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc_d3 */ + <4 RK_PD3 1 &pcfg_pull_up_drv_level_2>; + }; + + sdmmc_clk: sdmmc-clk { + u-boot,dm-spl; + rockchip,pins = + /* sdmmc_clk */ + <4 RK_PD5 1 &pcfg_pull_up_drv_level_2>; + }; + + sdmmc_cmd: sdmmc-cmd { + u-boot,dm-spl; + rockchip,pins = + /* sdmmc_cmd */ + <4 RK_PD4 1 &pcfg_pull_up_drv_level_2>; + }; + + sdmmc_det: sdmmc-det { + u-boot,dm-spl; + rockchip,pins = + /* sdmmc_det */ + <0 RK_PA4 1 &pcfg_pull_up>; + }; + + sdmmc_pwren: sdmmc-pwren { + u-boot,dm-spl; + rockchip,pins = + /* sdmmc_pwren */ + <0 RK_PA5 2 &pcfg_pull_none>; + }; + }; +}; + +&pcfg_pull_up_drv_level_2 { + u-boot,dm-spl; +}; + +&pcfg_pull_up { + u-boot,dm-spl; +}; + +&pcfg_pull_none +{ + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/rk3588-vccio3-pinctrl.dtsi b/arch/arm/dts/rk3588-vccio3-pinctrl.dtsi new file mode 100644 index 0000000000..4af6878a16 --- /dev/null +++ b/arch/arm/dts/rk3588-vccio3-pinctrl.dtsi @@ -0,0 +1,453 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include <dt-bindings/pinctrl/rockchip.h> + +/* + * This file is auto generated by pin2dts tool, please keep these code + * by adding changes at end of this file. + */ +&pinctrl { + clk32k { + clk32k_out1: clk32k-out1 { + rockchip,pins = + /* clk32k_out1 */ + <2 RK_PC5 1 &pcfg_pull_none>; + }; + + }; + + eth0 { + eth0_pins: eth0-pins { + rockchip,pins = + /* eth0_refclko_25m */ + <2 RK_PC3 1 &pcfg_pull_none>; + }; + + }; + + fspi { + fspim1_pins: fspim1-pins { + rockchip,pins = + /* fspi_clk_m1 */ + <2 RK_PB3 3 &pcfg_pull_none>, + /* fspi_cs0n_m1 */ + <2 RK_PB4 3 &pcfg_pull_none>, + /* fspi_d0_m1 */ + <2 RK_PA6 3 &pcfg_pull_none>, + /* fspi_d1_m1 */ + <2 RK_PA7 3 &pcfg_pull_none>, + /* fspi_d2_m1 */ + <2 RK_PB0 3 &pcfg_pull_none>, + /* fspi_d3_m1 */ + <2 RK_PB1 3 &pcfg_pull_none>; + }; + + fspim1_cs1: fspim1-cs1 { + rockchip,pins = + /* fspi_cs1n_m1 */ + <2 RK_PB5 3 &pcfg_pull_up>; + }; + }; + + gmac0 { + gmac0_miim: gmac0-miim { + rockchip,pins = + /* gmac0_mdc */ + <4 RK_PC4 1 &pcfg_pull_none>, + /* gmac0_mdio */ + <4 RK_PC5 1 &pcfg_pull_none>; + }; + + gmac0_clkinout: gmac0-clkinout { + rockchip,pins = + /* gmac0_mclkinout */ + <4 RK_PC3 1 &pcfg_pull_none>; + }; + + gmac0_rx_bus2: gmac0-rx-bus2 { + rockchip,pins = + /* gmac0_rxd0 */ + <2 RK_PC1 1 &pcfg_pull_none>, + /* gmac0_rxd1 */ + <2 RK_PC2 1 &pcfg_pull_none>, + /* gmac0_rxdv_crs */ + <4 RK_PC2 1 &pcfg_pull_none>; + }; + + gmac0_tx_bus2: gmac0-tx-bus2 { + rockchip,pins = + /* gmac0_txd0 */ + <2 RK_PB6 1 &pcfg_pull_none>, + /* gmac0_txd1 */ + <2 RK_PB7 1 &pcfg_pull_none>, + /* gmac0_txen */ + <2 RK_PC0 1 &pcfg_pull_none>; + }; + + gmac0_rgmii_clk: gmac0-rgmii-clk { + rockchip,pins = + /* gmac0_rxclk */ + <2 RK_PB0 1 &pcfg_pull_none>, + /* gmac0_txclk */ + <2 RK_PB3 1 &pcfg_pull_none>; + }; + + gmac0_rgmii_bus: gmac0-rgmii-bus { + rockchip,pins = + /* gmac0_rxd2 */ + <2 RK_PA6 1 &pcfg_pull_none>, + /* gmac0_rxd3 */ + <2 RK_PA7 1 &pcfg_pull_none>, + /* gmac0_txd2 */ + <2 RK_PB1 1 &pcfg_pull_none>, + /* gmac0_txd3 */ + <2 RK_PB2 1 &pcfg_pull_none>; + }; + + gmac0_ppsclk: gmac0-ppsclk { + rockchip,pins = + /* gmac0_ppsclk */ + <2 RK_PC4 1 &pcfg_pull_none>; + }; + + gmac0_ppstring: gmac0-ppstring { + rockchip,pins = + /* gmac0_ppstring */ + <2 RK_PB5 1 &pcfg_pull_none>; + }; + + gmac0_ptp_refclk: gmac0-ptp-refclk { + rockchip,pins = + /* gmac0_ptp_refclk */ + <2 RK_PB4 1 &pcfg_pull_none>; + }; + + gmac0_txer: gmac0-txer { + rockchip,pins = + /* gmac0_txer */ + <4 RK_PC6 1 &pcfg_pull_none>; + }; + + }; + + hdmi { + hdmim0_pins: hdmim0-pins { + rockchip,pins = + /* hdmi_tx1_cec_m0 */ + <2 RK_PC4 4 &pcfg_pull_none>, + /* hdmi_tx1_scl_m0 */ + <2 RK_PB5 4 &pcfg_pull_none>, + /* hdmi_tx1_sda_m0 */ + <2 RK_PB4 4 &pcfg_pull_none>; + }; + }; + + i2c0 { + i2c0m1_xfer: i2c0m1-xfer { + rockchip,pins = + /* i2c0_scl_m1 */ + <4 RK_PC5 9 &pcfg_pull_none_smt>, + /* i2c0_sda_m1 */ + <4 RK_PC6 9 &pcfg_pull_none_smt>; + }; + }; + + i2c2 { + i2c2m1_xfer: i2c2m1-xfer { + rockchip,pins = + /* i2c2_scl_m1 */ + <2 RK_PC1 9 &pcfg_pull_none_smt>, + /* i2c2_sda_m1 */ + <2 RK_PC0 9 &pcfg_pull_none_smt>; + }; + }; + + i2c3 { + i2c3m3_xfer: i2c3m3-xfer { + rockchip,pins = + /* i2c3_scl_m3 */ + <2 RK_PB2 9 &pcfg_pull_none_smt>, + /* i2c3_sda_m3 */ + <2 RK_PB3 9 &pcfg_pull_none_smt>; + }; + }; + + i2c4 { + i2c4m1_xfer: i2c4m1-xfer { + rockchip,pins = + /* i2c4_scl_m1 */ + <2 RK_PB5 9 &pcfg_pull_none_smt>, + /* i2c4_sda_m1 */ + <2 RK_PB4 9 &pcfg_pull_none_smt>; + }; + }; + + i2c5 { + i2c5m4_xfer: i2c5m4-xfer { + rockchip,pins = + /* i2c5_scl_m4 */ + <2 RK_PB6 9 &pcfg_pull_none_smt>, + /* i2c5_sda_m4 */ + <2 RK_PB7 9 &pcfg_pull_none_smt>; + }; + }; + + i2c6 { + i2c6m2_xfer: i2c6m2-xfer { + rockchip,pins = + /* i2c6_scl_m2 */ + <2 RK_PC3 9 &pcfg_pull_none_smt>, + /* i2c6_sda_m2 */ + <2 RK_PC2 9 &pcfg_pull_none_smt>; + }; + }; + + i2c7 { + i2c7m1_xfer: i2c7m1-xfer { + rockchip,pins = + /* i2c7_scl_m1 */ + <4 RK_PC3 9 &pcfg_pull_none_smt>, + /* i2c7_sda_m1 */ + <4 RK_PC4 9 &pcfg_pull_none_smt>; + }; + }; + + i2c8 { + i2c8m1_xfer: i2c8m1-xfer { + rockchip,pins = + /* i2c8_scl_m1 */ + <2 RK_PB0 9 &pcfg_pull_none_smt>, + /* i2c8_sda_m1 */ + <2 RK_PB1 9 &pcfg_pull_none_smt>; + }; + }; + + i2s2 { + i2s2m0_lrck: i2s2m0-lrck { + rockchip,pins = + /* i2s2m0_lrck */ + <2 RK_PC0 2 &pcfg_pull_none>; + }; + + i2s2m0_mclk: i2s2m0-mclk { + rockchip,pins = + /* i2s2m0_mclk */ + <2 RK_PB6 2 &pcfg_pull_none>; + }; + + i2s2m0_sclk: i2s2m0-sclk { + rockchip,pins = + /* i2s2m0_sclk */ + <2 RK_PB7 2 &pcfg_pull_none>; + }; + + i2s2m0_sdi: i2s2m0-sdi { + rockchip,pins = + /* i2s2m0_sdi */ + <2 RK_PC3 2 &pcfg_pull_none>; + }; + + i2s2m0_sdo: i2s2m0-sdo { + rockchip,pins = + /* i2s2m0_sdo */ + <4 RK_PC3 2 &pcfg_pull_none>; + }; + }; + + pwm2 { + pwm2m2_pins: pwm2m2-pins { + rockchip,pins = + /* pwm2_m2 */ + <4 RK_PC2 11 &pcfg_pull_none>; + }; + }; + + pwm4 { + pwm4m1_pins: pwm4m1-pins { + rockchip,pins = + /* pwm4_m1 */ + <4 RK_PC3 11 &pcfg_pull_none>; + }; + }; + + pwm5 { + pwm5m2_pins: pwm5m2-pins { + rockchip,pins = + /* pwm5_m2 */ + <4 RK_PC4 11 &pcfg_pull_none>; + }; + }; + + pwm6 { + pwm6m2_pins: pwm6m2-pins { + rockchip,pins = + /* pwm6_m2 */ + <4 RK_PC5 11 &pcfg_pull_none>; + }; + }; + + pwm7 { + pwm7m3_pins: pwm7m3-pins { + rockchip,pins = + /* pwm7_ir_m3 */ + <4 RK_PC6 11 &pcfg_pull_none>; + }; + }; + + sdio { + sdiom0_pins: sdiom0-pins { + rockchip,pins = + /* sdio_clk_m0 */ + <2 RK_PB3 2 &pcfg_pull_none>, + /* sdio_cmd_m0 */ + <2 RK_PB2 2 &pcfg_pull_none>, + /* sdio_d0_m0 */ + <2 RK_PA6 2 &pcfg_pull_none>, + /* sdio_d1_m0 */ + <2 RK_PA7 2 &pcfg_pull_none>, + /* sdio_d2_m0 */ + <2 RK_PB0 2 &pcfg_pull_none>, + /* sdio_d3_m0 */ + <2 RK_PB1 2 &pcfg_pull_none>; + }; + }; + + spi1 { + spi1m0_pins: spi1m0-pins { + rockchip,pins = + /* spi1_clk_m0 */ + <2 RK_PC0 8 &pcfg_pull_none>, + /* spi1_miso_m0 */ + <2 RK_PC1 8 &pcfg_pull_none>, + /* spi1_mosi_m0 */ + <2 RK_PC2 8 &pcfg_pull_none>; + }; + + spi1m0_cs0: spi1m0-cs0 { + rockchip,pins = + /* spi1_cs0_m0 */ + <2 RK_PC3 8 &pcfg_pull_none>; + }; + + spi1m0_cs1: spi1m0-cs1 { + rockchip,pins = + /* spi1_cs1_m0 */ + <2 RK_PC4 8 &pcfg_pull_none>; + }; + }; + + spi3 { + spi3m0_pins: spi3m0-pins { + rockchip,pins = + /* spi3_clk_m0 */ + <4 RK_PC6 8 &pcfg_pull_none>, + /* spi3_miso_m0 */ + <4 RK_PC4 8 &pcfg_pull_none>, + /* spi3_mosi_m0 */ + <4 RK_PC5 8 &pcfg_pull_none>; + }; + + spi3m0_cs0: spi3m0-cs0 { + rockchip,pins = + /* spi3_cs0_m0 */ + <4 RK_PC2 8 &pcfg_pull_none>; + }; + + spi3m0_cs1: spi3m0-cs1 { + rockchip,pins = + /* spi3_cs1_m0 */ + <4 RK_PC3 8 &pcfg_pull_none>; + }; + }; + + uart1 { + uart1m0_xfer: uart1m0-xfer { + rockchip,pins = + /* uart1_rx_m0 */ + <2 RK_PB6 10 &pcfg_pull_up>, + /* uart1_tx_m0 */ + <2 RK_PB7 10 &pcfg_pull_up>; + }; + + uart1m0_ctsn: uart1m0-ctsn { + rockchip,pins = + /* uart1m0_ctsn */ + <2 RK_PC1 10 &pcfg_pull_none>; + }; + + uart1m0_rtsn: uart1m0-rtsn { + rockchip,pins = + /* uart1m0_rtsn */ + <2 RK_PC0 10 &pcfg_pull_none>; + }; + }; + + uart6 { + uart6m0_xfer: uart6m0-xfer { + rockchip,pins = + /* uart6_rx_m0 */ + <2 RK_PA6 10 &pcfg_pull_up>, + /* uart6_tx_m0 */ + <2 RK_PA7 10 &pcfg_pull_up>; + }; + + uart6m0_ctsn: uart6m0-ctsn { + rockchip,pins = + /* uart6m0_ctsn */ + <2 RK_PB1 10 &pcfg_pull_none>; + }; + + uart6m0_rtsn: uart6m0-rtsn { + rockchip,pins = + /* uart6m0_rtsn */ + <2 RK_PB0 10 &pcfg_pull_none>; + }; + }; + + uart7 { + uart7m0_xfer: uart7m0-xfer { + rockchip,pins = + /* uart7_rx_m0 */ + <2 RK_PB4 10 &pcfg_pull_up>, + /* uart7_tx_m0 */ + <2 RK_PB5 10 &pcfg_pull_up>; + }; + + uart7m0_ctsn: uart7m0-ctsn { + rockchip,pins = + /* uart7m0_ctsn */ + <4 RK_PC6 10 &pcfg_pull_none>; + }; + + uart7m0_rtsn: uart7m0-rtsn { + rockchip,pins = + /* uart7m0_rtsn */ + <4 RK_PC2 10 &pcfg_pull_none>; + }; + }; + + uart9 { + uart9m0_xfer: uart9m0-xfer { + rockchip,pins = + /* uart9_rx_m0 */ + <2 RK_PC4 10 &pcfg_pull_up>, + /* uart9_tx_m0 */ + <2 RK_PC2 10 &pcfg_pull_up>; + }; + + uart9m0_ctsn: uart9m0-ctsn { + rockchip,pins = + /* uart9m0_ctsn */ + <4 RK_PC5 10 &pcfg_pull_none>; + }; + + uart9m0_rtsn: uart9m0-rtsn { + rockchip,pins = + /* uart9m0_rtsn */ + <4 RK_PC4 10 &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm/dts/rk3588.dtsi b/arch/arm/dts/rk3588.dtsi new file mode 100644 index 0000000000..3e1bcc83fe --- /dev/null +++ b/arch/arm/dts/rk3588.dtsi @@ -0,0 +1,518 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include <dt-bindings/phy/phy-snps-pcie3.h> +#include "rk3588s.dtsi" +#include "rk3588-vccio3-pinctrl.dtsi" + +/ { + aliases { + edp0 = &edp0; + edp1 = &edp1; + ethernet0 = &gmac0; + hdptx0 = &hdptxphy0; + hdptx1 = &hdptxphy1; + }; + + usbdrd3_1: usbdrd3_1 { + compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3"; + clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, + <&cru ACLK_USB3OTG1>; + clock-names = "ref", "suspend", "bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usbdrd_dwc3_1: usb@fc400000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfc400000 0x0 0x400000>; + interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&power RK3588_PD_USB>; + resets = <&cru SRST_A_USB3OTG1>; + reset-names = "usb3-otg"; + dr_mode = "host"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + status = "disabled"; + }; + }; + + pcie30_phy_grf: syscon@fd5b8000 { + compatible = "rockchip,pcie30-phy-grf", "syscon"; + reg = <0x0 0xfd5b8000 0x0 0x10000>; + }; + + pipe_phy1_grf: syscon@fd5c0000 { + compatible = "rockchip,pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5c0000 0x0 0x100>; + }; + + usbdpphy1_grf: syscon@fd5cc000 { + compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; + reg = <0x0 0xfd5cc000 0x0 0x4000>; + }; + + usb2phy1_grf: syscon@fd5d4000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", + "simple-mfd"; + reg = <0x0 0xfd5d4000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy1: usb2-phy@4000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x4000 0x10>; + interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + #clock-cells = <0>; + status = "disabled"; + + u2phy1_otg: otg-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + hdptxphy1_grf: syscon@fd5e4000 { + compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; + reg = <0x0 0xfd5e4000 0x0 0x100>; + }; + + spdif_tx5: spdif-tx@fddb8000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfddb8000 0x0 0x1000>; + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmac1 22>; + dma-names = "tx"; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF5_DP1>, <&cru HCLK_SPDIF5_DP1>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s8_8ch: i2s@fddc8000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddc8000 0x0 0x1000>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>; + clock-names = "mclk_tx", "hclk"; + dmas = <&dmac2 22>; + dma-names = "tx"; + resets = <&cru SRST_M_I2S8_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_tx4: spdif-tx@fdde8000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfdde8000 0x0 0x1000>; + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmac1 8>; + dma-names = "tx"; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF4>, <&cru HCLK_SPDIF4>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s6_8ch: i2s@fddf4000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf4000 0x0 0x1000>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>; + clock-names = "mclk_tx", "hclk"; + dmas = <&dmac2 4>; + dma-names = "tx"; + resets = <&cru SRST_M_I2S6_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s7_8ch: i2s@fddf8000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf8000 0x0 0x1000>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>; + clock-names = "mclk_rx", "hclk"; + dmas = <&dmac2 21>; + dma-names = "rx"; + resets = <&cru SRST_M_I2S7_8CH_RX>; + reset-names = "rx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s10_8ch: i2s@fde00000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfde00000 0x0 0x1000>; + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>; + clock-names = "mclk_rx", "hclk"; + dmas = <&dmac2 24>; + dma-names = "rx"; + resets = <&cru SRST_M_I2S10_8CH_RX>; + reset-names = "rx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_rx1: spdif-rx@fde10000 { + compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx"; + reg = <0x0 0xfde10000 0x0 0x1000>; + interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru MCLK_SPDIFRX1>, <&cru HCLK_SPDIFRX1>; + clock-names = "mclk", "hclk"; + dmas = <&dmac0 22>; + dma-names = "rx"; + resets = <&cru SRST_M_SPDIFRX1>; + reset-names = "spdifrx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_rx2: spdif-rx@fde18000 { + compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx"; + reg = <0x0 0xfde18000 0x0 0x1000>; + interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru MCLK_SPDIFRX2>, <&cru HCLK_SPDIFRX2>; + clock-names = "mclk", "hclk"; + dmas = <&dmac0 23>; + dma-names = "rx"; + resets = <&cru SRST_M_SPDIFRX2>; + reset-names = "spdifrx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + edp1: edp@fded0000 { + compatible = "rockchip,rk3588-edp"; + reg = <0x0 0xfded0000 0x0 0x1000>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru CLK_EDP1_24M>, <&cru PCLK_EDP1>, + <&cru CLK_EDP1_200M>; + clock-names = "dp", "pclk", "spdif"; + resets = <&cru SRST_EDP1_24M>, <&cru SRST_P_EDP1>; + reset-names = "dp", "apb"; + phys = <&hdptxphy1>; + phy-names = "dp"; + power-domains = <&power RK3588_PD_VO1>; + rockchip,grf = <&vo1_grf>; + status = "disabled"; + }; + + pcie3x4: pcie@fe150000 { + compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0x0f>; + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, + <&cru CLK_PCIE_AUX0>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux"; + device_type = "pci"; + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x4_intc 0>, + <0 0 0 2 &pcie3x4_intc 1>, + <0 0 0 3 &pcie3x4_intc 2>, + <0 0 0 4 &pcie3x4_intc 3>; + linux,pci-domain = <0>; + num-ib-windows = <16>; + num-ob-windows = <16>; + max-link-speed = <3>; + msi-map = <0x0000 &its 0x0000 0x1000>; + num-lanes = <4>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x00000800 0x0 0x80000000 0x9 0x00000000 0x0 0x800000 + 0x81000000 0x0 0x80800000 0x9 0x00800000 0x0 0x100000 + 0x83000000 0x0 0x80900000 0x9 0x00900000 0x0 0x3f700000>; + reg = <0xa 0x40000000 0x0 0x400000>, + <0x0 0xfe150000 0x0 0x10000>; + reg-names = "pcie-dbi", "pcie-apb"; + resets = <&cru SRST_PCIE0_POWER_UP>; + reset-names = "pipe"; + status = "disabled"; + + pcie3x4_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING>; + }; + }; + + pcie3x2: pcie@fe160000 { + compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x10 0x1f>; + clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, + <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, + <&cru CLK_PCIE_AUX1>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux"; + device_type = "pci"; + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, + <0 0 0 2 &pcie3x2_intc 1>, + <0 0 0 3 &pcie3x2_intc 2>, + <0 0 0 4 &pcie3x2_intc 3>; + linux,pci-domain = <1>; + num-ib-windows = <16>; + num-ob-windows = <16>; + max-link-speed = <3>; + msi-map = <0x1000 &its 0x1000 0x1000>; + num-lanes = <2>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PHP>; + ranges = <0x00000800 0x0 0x80000000 0x9 0x40000000 0x0 0x800000 + 0x81000000 0x0 0x80800000 0x9 0x40800000 0x0 0x100000 + 0x83000000 0x0 0x80900000 0x9 0x40900000 0x0 0x3f700000>; + reg = <0xa 0x40400000 0x0 0x400000>, + <0x0 0xfe160000 0x0 0x10000>; + reg-names = "pcie-dbi", "pcie-apb"; + resets = <&cru SRST_PCIE1_POWER_UP>; + reset-names = "pipe"; + status = "disabled"; + + pcie3x2_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING>; + }; + }; + + pcie2x1l0: pcie@fe170000 { + compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x20 0x2f>; + clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>, + <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>, + <&cru CLK_PCIE_AUX2>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux"; + device_type = "pci"; + interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>, + <0 0 0 2 &pcie2x1l0_intc 1>, + <0 0 0 3 &pcie2x1l0_intc 2>, + <0 0 0 4 &pcie2x1l0_intc 3>; + linux,pci-domain = <2>; + num-ib-windows = <8>; + num-ob-windows = <8>; + max-link-speed = <2>; + msi-map = <0x2000 &its 0x2000 0x1000>; + num-lanes = <1>; + phys = <&combphy1_ps PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PHP>; + ranges = <0x00000800 0x0 0x80000000 0x9 0x80000000 0x0 0x800000 + 0x81000000 0x0 0x80800000 0x9 0x80800000 0x0 0x100000 + 0x83000000 0x0 0x80900000 0x9 0x80900000 0x0 0x3f700000>; + reg = <0xa 0x40800000 0x0 0x400000>, + <0x0 0xfe170000 0x0 0x10000>; + reg-names = "pcie-dbi", "pcie-apb"; + resets = <&cru SRST_PCIE2_POWER_UP>; + reset-names = "pipe"; + status = "disabled"; + + pcie2x1l0_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>; + }; + }; + + gmac0: ethernet@fe1b0000 { + compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; + reg = <0x0 0xfe1b0000 0x0 0x10000>; + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_wake_irq"; + rockchip,grf = <&sys_grf>; + rockchip,php_grf = <&php_grf>; + clocks = <&cru CLK_GMAC0>, <&cru ACLK_GMAC0>, + <&cru PCLK_GMAC0>, <&cru CLK_GMAC0_PTP_REF>; + clock-names = "stmmaceth", "aclk_mac", + "pclk_mac", "ptp_ref"; + resets = <&cru SRST_A_GMAC0>; + reset-names = "stmmaceth"; + + snps,mixed-burst; + snps,tso; + + snps,axi-config = <&gmac0_stmmac_axi_setup>; + snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; + status = "disabled"; + + mdio0: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + gmac0_stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <8>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + gmac0_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <2>; + queue0 {}; + queue1 {}; + }; + + gmac0_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <2>; + queue0 {}; + queue1 {}; + }; + }; + + sata1: sata@fe220000 { + compatible = "snps,dwc-ahci"; + reg = <0 0xfe220000 0 0x1000>; + clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, + <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>; + clock-names = "sata", "pmalive", "rxoob", "ref"; + interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hostc"; + phys = <&combphy1_ps PHY_TYPE_SATA>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + power-domains = <&power RK3588_PD_PHP>; + status = "disabled"; + }; + + crypto: crypto@fe370000 { + compatible = "rockchip,rk3588-crypto"; + reg = <0x0 0xfe370000 0x0 0x4000>; + clocks = <&scmi_clk SCMI_CRYPTO_CORE>, <&scmi_clk SCMI_CRYPTO_PKA>; + clock-names = "sclk_crypto", "apkclk_crypto"; + clock-frequency = <350000000>, <350000000>; + status = "disabled"; + }; + + rng: rng@fe378000 { + compatible = "rockchip,trngv1"; + reg = <0x0 0xfe378000 0x0 0x200>; + status = "disabled"; + }; + + hdptxphy1: phy@fed70000 { + compatible = "rockchip,rk3588-hdptx-phy"; + reg = <0x0 0xfed70000 0x0 0x2000>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>; + clock-names = "ref", "apb"; + resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>, + <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>, + <&cru SRST_HDPTX1_LANE>, <&cru SRST_HDPTX1_ROPLL>, + <&cru SRST_HDPTX1_LCPLL>; + reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", + "lcpll"; + rockchip,grf = <&hdptxphy1_grf>; + #phy-cells = <0>; + status = "disabled"; + }; + + usbdp_phy1: phy@fed90000 { + compatible = "rockchip,rk3588-usbdp-phy"; + reg = <0x0 0xfed90000 0x0 0x10000>; + rockchip,usb-grf = <&usb_grf>; + rockchip,usbdpphy-grf = <&usbdpphy1_grf>; + rockchip,vo-grf = <&vo0_grf>; + clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, + <&cru CLK_USBDP_PHY1_IMMORTAL>, + <&cru PCLK_USBDPPHY1>; + clock-names = "refclk", "immortal", "pclk"; + resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>, + <&cru SRST_USBDP_COMBO_PHY1_CMN>, + <&cru SRST_USBDP_COMBO_PHY1_LANE>, + <&cru SRST_USBDP_COMBO_PHY1_PCS>, + <&cru SRST_P_USBDPPHY1>; + reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; + status = "disabled"; + + usbdp_phy1_dp: dp-port { + #phy-cells = <0>; + status = "disabled"; + }; + + usbdp_phy1_u3: u3-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + + combphy1_ps: phy@fee10000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee10000 0x0 0x100>; + #phy-cells = <1>; + clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>; + clock-names = "refclk", "apbclk"; + assigned-clocks = <&cru CLK_REF_PIPE_PHY1>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_P_PCIE2_PHY1>, <&cru SRST_REF_PIPE_PHY1>; + reset-names = "combphy-apb", "combphy"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy1_grf>; + rockchip,pcie1ln-sel-bits = <0x100 0 0 0>; + status = "disabled"; + }; + + pcie30phy: phy@fee80000 { + compatible = "rockchip,rk3588-pcie3-phy"; + reg = <0x0 0xfee80000 0x0 0x20000>; + #phy-cells = <0>; + clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>; + clock-names = "pclk"; + resets = <&cru SRST_PCIE30_PHY>; + reset-names = "phy"; + rockchip,pipe-grf = <&php_grf>; + rockchip,phy-grf = <&pcie30_phy_grf>; + status = "disabled"; + }; + +}; diff --git a/arch/arm/dts/rk3588s-pinctrl.dtsi b/arch/arm/dts/rk3588s-pinctrl.dtsi new file mode 100644 index 0000000000..64453012a8 --- /dev/null +++ b/arch/arm/dts/rk3588s-pinctrl.dtsi @@ -0,0 +1,3009 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include <dt-bindings/pinctrl/rockchip.h> +#include "rockchip-pinconf.dtsi" + +/* + * This file is auto generated by pin2dts tool, please keep these code + * by adding changes at end of this file. + */ +&pinctrl { + auddsm { + auddsm_pins: auddsm-pins { + rockchip,pins = + /* auddsm_ln */ + <3 RK_PA1 4 &pcfg_pull_none>, + /* auddsm_lp */ + <3 RK_PA2 4 &pcfg_pull_none>, + /* auddsm_rn */ + <3 RK_PA3 4 &pcfg_pull_none>, + /* auddsm_rp */ + <3 RK_PA4 4 &pcfg_pull_none>; + }; + }; + + bt1120 { + bt1120_pins: bt1120-pins { + rockchip,pins = + /* bt1120_clkout */ + <4 RK_PB0 2 &pcfg_pull_none>, + /* bt1120_d0 */ + <4 RK_PA0 2 &pcfg_pull_none>, + /* bt1120_d1 */ + <4 RK_PA1 2 &pcfg_pull_none>, + /* bt1120_d2 */ + <4 RK_PA2 2 &pcfg_pull_none>, + /* bt1120_d3 */ + <4 RK_PA3 2 &pcfg_pull_none>, + /* bt1120_d4 */ + <4 RK_PA4 2 &pcfg_pull_none>, + /* bt1120_d5 */ + <4 RK_PA5 2 &pcfg_pull_none>, + /* bt1120_d6 */ + <4 RK_PA6 2 &pcfg_pull_none>, + /* bt1120_d7 */ + <4 RK_PA7 2 &pcfg_pull_none>, + /* bt1120_d8 */ + <4 RK_PB2 2 &pcfg_pull_none>, + /* bt1120_d9 */ + <4 RK_PB3 2 &pcfg_pull_none>, + /* bt1120_d10 */ + <4 RK_PB4 2 &pcfg_pull_none>, + /* bt1120_d11 */ + <4 RK_PB5 2 &pcfg_pull_none>, + /* bt1120_d12 */ + <4 RK_PB6 2 &pcfg_pull_none>, + /* bt1120_d13 */ + <4 RK_PB7 2 &pcfg_pull_none>, + /* bt1120_d14 */ + <4 RK_PC0 2 &pcfg_pull_none>, + /* bt1120_d15 */ + <4 RK_PC1 2 &pcfg_pull_none>; + }; + }; + + can0 { + can0m0_pins: can0m0-pins { + rockchip,pins = + /* can0_rx_m0 */ + <0 RK_PC0 11 &pcfg_pull_none>, + /* can0_tx_m0 */ + <0 RK_PB7 11 &pcfg_pull_none>; + }; + + can0m1_pins: can0m1-pins { + rockchip,pins = + /* can0_rx_m1 */ + <4 RK_PD5 9 &pcfg_pull_none>, + /* can0_tx_m1 */ + <4 RK_PD4 9 &pcfg_pull_none>; + }; + }; + + can1 { + can1m0_pins: can1m0-pins { + rockchip,pins = + /* can1_rx_m0 */ + <3 RK_PB5 9 &pcfg_pull_none>, + /* can1_tx_m0 */ + <3 RK_PB6 9 &pcfg_pull_none>; + }; + + can1m1_pins: can1m1-pins { + rockchip,pins = + /* can1_rx_m1 */ + <4 RK_PB2 12 &pcfg_pull_none>, + /* can1_tx_m1 */ + <4 RK_PB3 12 &pcfg_pull_none>; + }; + }; + + can2 { + can2m0_pins: can2m0-pins { + rockchip,pins = + /* can2_rx_m0 */ + <3 RK_PC4 9 &pcfg_pull_none>, + /* can2_tx_m0 */ + <3 RK_PC5 9 &pcfg_pull_none>; + }; + + can2m1_pins: can2m1-pins { + rockchip,pins = + /* can2_rx_m1 */ + <0 RK_PD4 10 &pcfg_pull_none>, + /* can2_tx_m1 */ + <0 RK_PD5 10 &pcfg_pull_none>; + }; + }; + + cif { + cif_clk: cif-clk { + rockchip,pins = + /* cif_clkout */ + <4 RK_PB4 1 &pcfg_pull_none>; + }; + + cif_dvp_clk: cif-dvp-clk { + rockchip,pins = + /* cif_clkin */ + <4 RK_PB0 1 &pcfg_pull_none>, + /* cif_href */ + <4 RK_PB2 1 &pcfg_pull_none>, + /* cif_vsync */ + <4 RK_PB3 1 &pcfg_pull_none>; + }; + + cif_dvp_bus16: cif-dvp-bus16 { + rockchip,pins = + /* cif_d8 */ + <3 RK_PC4 1 &pcfg_pull_none>, + /* cif_d9 */ + <3 RK_PC5 1 &pcfg_pull_none>, + /* cif_d10 */ + <3 RK_PC6 1 &pcfg_pull_none>, + /* cif_d11 */ + <3 RK_PC7 1 &pcfg_pull_none>, + /* cif_d12 */ + <3 RK_PD0 1 &pcfg_pull_none>, + /* cif_d13 */ + <3 RK_PD1 1 &pcfg_pull_none>, + /* cif_d14 */ + <3 RK_PD2 1 &pcfg_pull_none>, + /* cif_d15 */ + <3 RK_PD3 1 &pcfg_pull_none>; + }; + + cif_dvp_bus8: cif-dvp-bus8 { + rockchip,pins = + /* cif_d0 */ + <4 RK_PA0 1 &pcfg_pull_none>, + /* cif_d1 */ + <4 RK_PA1 1 &pcfg_pull_none>, + /* cif_d2 */ + <4 RK_PA2 1 &pcfg_pull_none>, + /* cif_d3 */ + <4 RK_PA3 1 &pcfg_pull_none>, + /* cif_d4 */ + <4 RK_PA4 1 &pcfg_pull_none>, + /* cif_d5 */ + <4 RK_PA5 1 &pcfg_pull_none>, + /* cif_d6 */ + <4 RK_PA6 1 &pcfg_pull_none>, + /* cif_d7 */ + <4 RK_PA7 1 &pcfg_pull_none>; + }; + }; + + clk32k { + clk32k_in: clk32k-in { + rockchip,pins = + /* clk32k_in */ + <0 RK_PB2 1 &pcfg_pull_none>; + }; + + clk32k_out0: clk32k-out0 { + rockchip,pins = + /* clk32k_out0 */ + <0 RK_PB2 2 &pcfg_pull_none>; + }; + }; + + cpu { + cpu_pins: cpu-pins { + rockchip,pins = + /* cpu_big0_avs */ + <0 RK_PD1 2 &pcfg_pull_none>, + /* cpu_big1_avs */ + <0 RK_PD5 2 &pcfg_pull_none>; + }; + }; + + ddrphych0 { + ddrphych0_pins: ddrphych0-pins { + rockchip,pins = + /* ddrphych0_dtb0 */ + <4 RK_PA0 7 &pcfg_pull_none>, + /* ddrphych0_dtb1 */ + <4 RK_PA1 7 &pcfg_pull_none>, + /* ddrphych0_dtb2 */ + <4 RK_PA2 7 &pcfg_pull_none>, + /* ddrphych0_dtb3 */ + <4 RK_PA3 7 &pcfg_pull_none>; + }; + }; + + ddrphych1 { + ddrphych1_pins: ddrphych1-pins { + rockchip,pins = + /* ddrphych1_dtb0 */ + <4 RK_PA4 7 &pcfg_pull_none>, + /* ddrphych1_dtb1 */ + <4 RK_PA5 7 &pcfg_pull_none>, + /* ddrphych1_dtb2 */ + <4 RK_PA6 7 &pcfg_pull_none>, + /* ddrphych1_dtb3 */ + <4 RK_PA7 7 &pcfg_pull_none>; + }; + }; + + ddrphych2 { + ddrphych2_pins: ddrphych2-pins { + rockchip,pins = + /* ddrphych2_dtb0 */ + <4 RK_PB0 7 &pcfg_pull_none>, + /* ddrphych2_dtb1 */ + <4 RK_PB1 7 &pcfg_pull_none>, + /* ddrphych2_dtb2 */ + <4 RK_PB2 7 &pcfg_pull_none>, + /* ddrphych2_dtb3 */ + <4 RK_PB3 7 &pcfg_pull_none>; + }; + }; + + ddrphych3 { + ddrphych3_pins: ddrphych3-pins { + rockchip,pins = + /* ddrphych3_dtb0 */ + <4 RK_PB4 7 &pcfg_pull_none>, + /* ddrphych3_dtb1 */ + <4 RK_PB5 7 &pcfg_pull_none>, + /* ddrphych3_dtb2 */ + <4 RK_PB6 7 &pcfg_pull_none>, + /* ddrphych3_dtb3 */ + <4 RK_PB7 7 &pcfg_pull_none>; + }; + }; + + dp0 { + dp0m0_pins: dp0m0-pins { + rockchip,pins = + /* dp0_hpdin_m0 */ + <4 RK_PB4 5 &pcfg_pull_none>; + }; + + dp0m1_pins: dp0m1-pins { + rockchip,pins = + /* dp0_hpdin_m1 */ + <0 RK_PC4 10 &pcfg_pull_none>; + }; + + dp0m2_pins: dp0m2-pins { + rockchip,pins = + /* dp0_hpdin_m2 */ + <1 RK_PA0 5 &pcfg_pull_none>; + }; + }; + + dp1 { + dp1m0_pins: dp1m0-pins { + rockchip,pins = + /* dp1_hpdin_m0 */ + <3 RK_PD5 5 &pcfg_pull_none>; + }; + + dp1m1_pins: dp1m1-pins { + rockchip,pins = + /* dp1_hpdin_m1 */ + <0 RK_PC5 10 &pcfg_pull_none>; + }; + + dp1m2_pins: dp1m2-pins { + rockchip,pins = + /* dp1_hpdin_m2 */ + <1 RK_PA1 5 &pcfg_pull_none>; + }; + }; + + emmc { + emmc_rstnout: emmc-rstnout { + rockchip,pins = + /* emmc_rstn */ + <2 RK_PA3 1 &pcfg_pull_none>; + }; + + emmc_bus8: emmc-bus8 { + rockchip,pins = + /* emmc_d0 */ + <2 RK_PD0 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d1 */ + <2 RK_PD1 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d2 */ + <2 RK_PD2 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d3 */ + <2 RK_PD3 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d4 */ + <2 RK_PD4 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d5 */ + <2 RK_PD5 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d6 */ + <2 RK_PD6 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d7 */ + <2 RK_PD7 1 &pcfg_pull_up_drv_level_2>; + }; + + emmc_clk: emmc-clk { + rockchip,pins = + /* emmc_clkout */ + <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = + /* emmc_cmd */ + <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>; + }; + + emmc_data_strobe: emmc-data-strobe { + rockchip,pins = + /* emmc_data_strobe */ + <2 RK_PA2 1 &pcfg_pull_none>; + }; + }; + + eth1 { + eth1_pins: eth1-pins { + rockchip,pins = + /* eth1_refclko_25m */ + <3 RK_PA6 1 &pcfg_pull_none>; + }; + }; + + fspi { + fspim0_pins: fspim0-pins { + rockchip,pins = + /* fspi_clk_m0 */ + <2 RK_PA0 2 &pcfg_pull_none>, + /* fspi_cs0n_m0 */ + <2 RK_PD6 2 &pcfg_pull_none>, + /* fspi_d0_m0 */ + <2 RK_PD0 2 &pcfg_pull_none>, + /* fspi_d1_m0 */ + <2 RK_PD1 2 &pcfg_pull_none>, + /* fspi_d2_m0 */ + <2 RK_PD2 2 &pcfg_pull_none>, + /* fspi_d3_m0 */ + <2 RK_PD3 2 &pcfg_pull_none>; + }; + + fspim0_cs1: fspim0-cs1 { + rockchip,pins = + /* fspi_cs1n_m0 */ + <2 RK_PD7 2 &pcfg_pull_up>; + }; + + fspim2_pins: fspim2-pins { + rockchip,pins = + /* fspi_clk_m2 */ + <3 RK_PA5 5 &pcfg_pull_none>, + /* fspi_cs0n_m2 */ + <3 RK_PC4 2 &pcfg_pull_none>, + /* fspi_d0_m2 */ + <3 RK_PA0 5 &pcfg_pull_none>, + /* fspi_d1_m2 */ + <3 RK_PA1 5 &pcfg_pull_none>, + /* fspi_d2_m2 */ + <3 RK_PA2 5 &pcfg_pull_none>, + /* fspi_d3_m2 */ + <3 RK_PA3 5 &pcfg_pull_none>; + }; + + fspim2_cs1: fspim2-cs1 { + rockchip,pins = + /* fspi_cs1n_m2 */ + <3 RK_PC5 2 &pcfg_pull_up>; + }; + }; + + gmac1 { + gmac1_miim: gmac1-miim { + rockchip,pins = + /* gmac1_mdc */ + <3 RK_PC2 1 &pcfg_pull_none>, + /* gmac1_mdio */ + <3 RK_PC3 1 &pcfg_pull_none>; + }; + + gmac1_clkinout: gmac1-clkinout { + rockchip,pins = + /* gmac1_mclkinout */ + <3 RK_PB6 1 &pcfg_pull_none>; + }; + + gmac1_rx_bus2: gmac1-rx-bus2 { + rockchip,pins = + /* gmac1_rxd0 */ + <3 RK_PA7 1 &pcfg_pull_none>, + /* gmac1_rxd1 */ + <3 RK_PB0 1 &pcfg_pull_none>, + /* gmac1_rxdv_crs */ + <3 RK_PB1 1 &pcfg_pull_none>; + }; + + gmac1_tx_bus2: gmac1-tx-bus2 { + rockchip,pins = + /* gmac1_txd0 */ + <3 RK_PB3 1 &pcfg_pull_none>, + /* gmac1_txd1 */ + <3 RK_PB4 1 &pcfg_pull_none>, + /* gmac1_txen */ + <3 RK_PB5 1 &pcfg_pull_none>; + }; + + gmac1_rgmii_clk: gmac1-rgmii-clk { + rockchip,pins = + /* gmac1_rxclk */ + <3 RK_PA5 1 &pcfg_pull_none>, + /* gmac1_txclk */ + <3 RK_PA4 1 &pcfg_pull_none>; + }; + + gmac1_rgmii_bus: gmac1-rgmii-bus { + rockchip,pins = + /* gmac1_rxd2 */ + <3 RK_PA2 1 &pcfg_pull_none>, + /* gmac1_rxd3 */ + <3 RK_PA3 1 &pcfg_pull_none>, + /* gmac1_txd2 */ + <3 RK_PA0 1 &pcfg_pull_none>, + /* gmac1_txd3 */ + <3 RK_PA1 1 &pcfg_pull_none>; + }; + + gmac1_ppsclk: gmac1-ppsclk { + rockchip,pins = + /* gmac1_ppsclk */ + <3 RK_PC1 1 &pcfg_pull_none>; + }; + + gmac1_ppstrig: gmac1-ppstrig { + rockchip,pins = + /* gmac1_ppstrig */ + <3 RK_PC0 1 &pcfg_pull_none>; + }; + + gmac1_ptp_ref_clk: gmac1-ptp-ref-clk { + rockchip,pins = + /* gmac1_ptp_ref_clk */ + <3 RK_PB7 1 &pcfg_pull_none>; + }; + + gmac1_txer: gmac1-txer { + rockchip,pins = + /* gmac1_txer */ + <3 RK_PB2 1 &pcfg_pull_none>; + }; + }; + + gpu { + gpu_pins: gpu-pins { + rockchip,pins = + /* gpu_avs */ + <0 RK_PC5 2 &pcfg_pull_none>; + }; + }; + + hdmi { + hdmim0_pins: hdmim0-pins { + rockchip,pins = + /* hdmi_rx_cec_m0 */ + <4 RK_PB5 5 &pcfg_pull_none>, + /* hdmi_rx_hpdin_m0 */ + <4 RK_PB6 5 &pcfg_pull_none>, + /* hdmi_rx_scl_m0 */ + <0 RK_PD2 11 &pcfg_pull_none>, + /* hdmi_rx_sda_m0 */ + <0 RK_PD1 11 &pcfg_pull_none>, + /* hdmi_tx0_cec_m0 */ + <4 RK_PC1 5 &pcfg_pull_none>, + /* hdmi_tx0_hpd_m0 */ + <1 RK_PA5 5 &pcfg_pull_none>, + /* hdmi_tx0_scl_m0 */ + <4 RK_PB7 5 &pcfg_pull_none>, + /* hdmi_tx0_sda_m0 */ + <4 RK_PC0 5 &pcfg_pull_none>, + /* hdmi_tx1_hpd_m0 */ + <1 RK_PA6 5 &pcfg_pull_none>; + }; + + hdmim1_pins: hdmim1-pins { + rockchip,pins = + /* hdmi_rx_cec_m1 */ + <3 RK_PD1 5 &pcfg_pull_none>, + /* hdmi_rx_hpdin_m1 */ + <3 RK_PD4 5 &pcfg_pull_none>, + /* hdmi_rx_scl_m1 */ + <3 RK_PD2 5 &pcfg_pull_none>, + /* hdmi_rx_sda_m1 */ + <3 RK_PD3 5 &pcfg_pull_none>, + /* hdmi_tx0_cec_m1 */ + <0 RK_PD1 13 &pcfg_pull_none>, + /* hdmi_tx0_hpd_m1 */ + <3 RK_PD4 3 &pcfg_pull_none>, + /* hdmi_tx0_scl_m1 */ + <0 RK_PD5 11 &pcfg_pull_none>, + /* hdmi_tx0_sda_m1 */ + <0 RK_PD4 11 &pcfg_pull_none>, + /* hdmi_tx1_cec_m1 */ + <0 RK_PD2 13 &pcfg_pull_none>, + /* hdmi_tx1_hpd_m1 */ + <3 RK_PB7 5 &pcfg_pull_none>, + /* hdmi_tx1_scl_m1 */ + <3 RK_PC6 5 &pcfg_pull_none>, + /* hdmi_tx1_sda_m1 */ + <3 RK_PC5 5 &pcfg_pull_none>; + }; + + hdmim2_pins: hdmim2-pins { + rockchip,pins = + /* hdmi_rx_cec_m2 */ + <1 RK_PB7 5 &pcfg_pull_none>, + /* hdmi_rx_hpdin_m2 */ + <1 RK_PB6 5 &pcfg_pull_none>, + /* hdmi_rx_scl_m2 */ + <1 RK_PD6 5 &pcfg_pull_none>, + /* hdmi_rx_sda_m2 */ + <1 RK_PD7 5 &pcfg_pull_none>, + /* hdmi_tx0_scl_m2 */ + <3 RK_PC7 5 &pcfg_pull_none>, + /* hdmi_tx0_sda_m2 */ + <3 RK_PD0 5 &pcfg_pull_none>, + /* hdmi_tx1_cec_m2 */ + <3 RK_PC4 5 &pcfg_pull_none>, + /* hdmi_tx1_scl_m2 */ + <1 RK_PA4 5 &pcfg_pull_none>, + /* hdmi_tx1_sda_m2 */ + <1 RK_PA3 5 &pcfg_pull_none>; + }; + + hdmi_debug0: hdmi-debug0 { + rockchip,pins = + /* hdmi_debug0 */ + <1 RK_PA7 7 &pcfg_pull_none>; + }; + + hdmi_debug1: hdmi-debug1 { + rockchip,pins = + /* hdmi_debug1 */ + <1 RK_PB0 7 &pcfg_pull_none>; + }; + + hdmi_debug2: hdmi-debug2 { + rockchip,pins = + /* hdmi_debug2 */ + <1 RK_PB1 7 &pcfg_pull_none>; + }; + + hdmi_debug3: hdmi-debug3 { + rockchip,pins = + /* hdmi_debug3 */ + <1 RK_PB2 7 &pcfg_pull_none>; + }; + + hdmi_debug4: hdmi-debug4 { + rockchip,pins = + /* hdmi_debug4 */ + <1 RK_PB3 7 &pcfg_pull_none>; + }; + + hdmi_debug5: hdmi-debug5 { + rockchip,pins = + /* hdmi_debug5 */ + <1 RK_PB4 7 &pcfg_pull_none>; + }; + + hdmi_debug6: hdmi-debug6 { + rockchip,pins = + /* hdmi_debug6 */ + <1 RK_PA0 7 &pcfg_pull_none>; + }; + }; + + i2c0 { + i2c0m0_xfer: i2c0m0-xfer { + rockchip,pins = + /* i2c0_scl_m0 */ + <0 RK_PB3 2 &pcfg_pull_none_smt>, + /* i2c0_sda_m0 */ + <0 RK_PA6 2 &pcfg_pull_none_smt>; + }; + + i2c0m2_xfer: i2c0m2-xfer { + rockchip,pins = + /* i2c0_scl_m2 */ + <0 RK_PD1 3 &pcfg_pull_none_smt>, + /* i2c0_sda_m2 */ + <0 RK_PD2 3 &pcfg_pull_none_smt>; + }; + }; + + i2c1 { + i2c1m0_xfer: i2c1m0-xfer { + rockchip,pins = + /* i2c1_scl_m0 */ + <0 RK_PB5 9 &pcfg_pull_none_smt>, + /* i2c1_sda_m0 */ + <0 RK_PB6 9 &pcfg_pull_none_smt>; + }; + + i2c1m1_xfer: i2c1m1-xfer { + rockchip,pins = + /* i2c1_scl_m1 */ + <0 RK_PB0 2 &pcfg_pull_none_smt>, + /* i2c1_sda_m1 */ + <0 RK_PB1 2 &pcfg_pull_none_smt>; + }; + + i2c1m2_xfer: i2c1m2-xfer { + rockchip,pins = + /* i2c1_scl_m2 */ + <0 RK_PD4 9 &pcfg_pull_none_smt>, + /* i2c1_sda_m2 */ + <0 RK_PD5 9 &pcfg_pull_none_smt>; + }; + + i2c1m3_xfer: i2c1m3-xfer { + rockchip,pins = + /* i2c1_scl_m3 */ + <2 RK_PD4 9 &pcfg_pull_none_smt>, + /* i2c1_sda_m3 */ + <2 RK_PD5 9 &pcfg_pull_none_smt>; + }; + + i2c1m4_xfer: i2c1m4-xfer { + rockchip,pins = + /* i2c1_scl_m4 */ + <1 RK_PD2 9 &pcfg_pull_none_smt>, + /* i2c1_sda_m4 */ + <1 RK_PD3 9 &pcfg_pull_none_smt>; + }; + }; + + i2c2 { + i2c2m0_xfer: i2c2m0-xfer { + rockchip,pins = + /* i2c2_scl_m0 */ + <0 RK_PB7 9 &pcfg_pull_none_smt>, + /* i2c2_sda_m0 */ + <0 RK_PC0 9 &pcfg_pull_none_smt>; + }; + + i2c2m2_xfer: i2c2m2-xfer { + rockchip,pins = + /* i2c2_scl_m2 */ + <2 RK_PA3 9 &pcfg_pull_none_smt>, + /* i2c2_sda_m2 */ + <2 RK_PA2 9 &pcfg_pull_none_smt>; + }; + + i2c2m3_xfer: i2c2m3-xfer { + rockchip,pins = + /* i2c2_scl_m3 */ + <1 RK_PC5 9 &pcfg_pull_none_smt>, + /* i2c2_sda_m3 */ + <1 RK_PC4 9 &pcfg_pull_none_smt>; + }; + + i2c2m4_xfer: i2c2m4-xfer { + rockchip,pins = + /* i2c2_scl_m4 */ + <1 RK_PA1 9 &pcfg_pull_none_smt>, + /* i2c2_sda_m4 */ + <1 RK_PA0 9 &pcfg_pull_none_smt>; + }; + }; + + i2c3 { + i2c3m0_xfer: i2c3m0-xfer { + rockchip,pins = + /* i2c3_scl_m0 */ + <1 RK_PC1 9 &pcfg_pull_none_smt>, + /* i2c3_sda_m0 */ + <1 RK_PC0 9 &pcfg_pull_none_smt>; + }; + + i2c3m1_xfer: i2c3m1-xfer { + rockchip,pins = + /* i2c3_scl_m1 */ + <3 RK_PB7 9 &pcfg_pull_none_smt>, + /* i2c3_sda_m1 */ + <3 RK_PC0 9 &pcfg_pull_none_smt>; + }; + + i2c3m2_xfer: i2c3m2-xfer { + rockchip,pins = + /* i2c3_scl_m2 */ + <4 RK_PA4 9 &pcfg_pull_none_smt>, + /* i2c3_sda_m2 */ + <4 RK_PA5 9 &pcfg_pull_none_smt>; + }; + + i2c3m4_xfer: i2c3m4-xfer { + rockchip,pins = + /* i2c3_scl_m4 */ + <4 RK_PD0 9 &pcfg_pull_none_smt>, + /* i2c3_sda_m4 */ + <4 RK_PD1 9 &pcfg_pull_none_smt>; + }; + }; + + i2c4 { + i2c4m0_xfer: i2c4m0-xfer { + rockchip,pins = + /* i2c4_scl_m0 */ + <3 RK_PA6 9 &pcfg_pull_none_smt>, + /* i2c4_sda_m0 */ + <3 RK_PA5 9 &pcfg_pull_none_smt>; + }; + + i2c4m2_xfer: i2c4m2-xfer { + rockchip,pins = + /* i2c4_scl_m2 */ + <0 RK_PC5 9 &pcfg_pull_none_smt>, + /* i2c4_sda_m2 */ + <0 RK_PC4 9 &pcfg_pull_none_smt>; + }; + + i2c4m3_xfer: i2c4m3-xfer { + rockchip,pins = + /* i2c4_scl_m3 */ + <1 RK_PA3 9 &pcfg_pull_none_smt>, + /* i2c4_sda_m3 */ + <1 RK_PA2 9 &pcfg_pull_none_smt>; + }; + + i2c4m4_xfer: i2c4m4-xfer { + rockchip,pins = + /* i2c4_scl_m4 */ + <1 RK_PC7 9 &pcfg_pull_none_smt>, + /* i2c4_sda_m4 */ + <1 RK_PC6 9 &pcfg_pull_none_smt>; + }; + }; + + i2c5 { + i2c5m0_xfer: i2c5m0-xfer { + rockchip,pins = + /* i2c5_scl_m0 */ + <3 RK_PC7 9 &pcfg_pull_none_smt>, + /* i2c5_sda_m0 */ + <3 RK_PD0 9 &pcfg_pull_none_smt>; + }; + + i2c5m1_xfer: i2c5m1-xfer { + rockchip,pins = + /* i2c5_scl_m1 */ + <4 RK_PB6 9 &pcfg_pull_none_smt>, + /* i2c5_sda_m1 */ + <4 RK_PB7 9 &pcfg_pull_none_smt>; + }; + + i2c5m2_xfer: i2c5m2-xfer { + rockchip,pins = + /* i2c5_scl_m2 */ + <4 RK_PA6 9 &pcfg_pull_none_smt>, + /* i2c5_sda_m2 */ + <4 RK_PA7 9 &pcfg_pull_none_smt>; + }; + + i2c5m3_xfer: i2c5m3-xfer { + rockchip,pins = + /* i2c5_scl_m3 */ + <1 RK_PB6 9 &pcfg_pull_none_smt>, + /* i2c5_sda_m3 */ + <1 RK_PB7 9 &pcfg_pull_none_smt>; + }; + }; + + i2c6 { + i2c6m0_xfer: i2c6m0-xfer { + rockchip,pins = + /* i2c6_scl_m0 */ + <0 RK_PD0 9 &pcfg_pull_none_smt>, + /* i2c6_sda_m0 */ + <0 RK_PC7 9 &pcfg_pull_none_smt>; + }; + + i2c6m1_xfer: i2c6m1-xfer { + rockchip,pins = + /* i2c6_scl_m1 */ + <1 RK_PC3 9 &pcfg_pull_none_smt>, + /* i2c6_sda_m1 */ + <1 RK_PC2 9 &pcfg_pull_none_smt>; + }; + + i2c6m3_xfer: i2c6m3-xfer { + rockchip,pins = + /* i2c6_scl_m3 */ + <4 RK_PB1 9 &pcfg_pull_none_smt>, + /* i2c6_sda_m3 */ + <4 RK_PB0 9 &pcfg_pull_none_smt>; + }; + + i2c6m4_xfer: i2c6m4-xfer { + rockchip,pins = + /* i2c6_scl_m4 */ + <3 RK_PA1 9 &pcfg_pull_none_smt>, + /* i2c6_sda_m4 */ + <3 RK_PA0 9 &pcfg_pull_none_smt>; + }; + }; + + i2c7 { + i2c7m0_xfer: i2c7m0-xfer { + rockchip,pins = + /* i2c7_scl_m0 */ + <1 RK_PD0 9 &pcfg_pull_none_smt>, + /* i2c7_sda_m0 */ + <1 RK_PD1 9 &pcfg_pull_none_smt>; + }; + + i2c7m2_xfer: i2c7m2-xfer { + rockchip,pins = + /* i2c7_scl_m2 */ + <3 RK_PD2 9 &pcfg_pull_none_smt>, + /* i2c7_sda_m2 */ + <3 RK_PD3 9 &pcfg_pull_none_smt>; + }; + + i2c7m3_xfer: i2c7m3-xfer { + rockchip,pins = + /* i2c7_scl_m3 */ + <4 RK_PB2 9 &pcfg_pull_none_smt>, + /* i2c7_sda_m3 */ + <4 RK_PB3 9 &pcfg_pull_none_smt>; + }; + }; + + i2c8 { + i2c8m0_xfer: i2c8m0-xfer { + rockchip,pins = + /* i2c8_scl_m0 */ + <4 RK_PD2 9 &pcfg_pull_none_smt>, + /* i2c8_sda_m0 */ + <4 RK_PD3 9 &pcfg_pull_none_smt>; + }; + + i2c8m2_xfer: i2c8m2-xfer { + rockchip,pins = + /* i2c8_scl_m2 */ + <1 RK_PD6 9 &pcfg_pull_none_smt>, + /* i2c8_sda_m2 */ + <1 RK_PD7 9 &pcfg_pull_none_smt>; + }; + + i2c8m3_xfer: i2c8m3-xfer { + rockchip,pins = + /* i2c8_scl_m3 */ + <4 RK_PC0 9 &pcfg_pull_none_smt>, + /* i2c8_sda_m3 */ + <4 RK_PC1 9 &pcfg_pull_none_smt>; + }; + + i2c8m4_xfer: i2c8m4-xfer { + rockchip,pins = + /* i2c8_scl_m4 */ + <3 RK_PC2 9 &pcfg_pull_none_smt>, + /* i2c8_sda_m4 */ + <3 RK_PC3 9 &pcfg_pull_none_smt>; + }; + }; + + i2s0 { + i2s0_lrck: i2s0-lrck { + rockchip,pins = + /* i2s0_lrck */ + <1 RK_PC5 1 &pcfg_pull_none>; + }; + + i2s0_mclk: i2s0-mclk { + rockchip,pins = + /* i2s0_mclk */ + <1 RK_PC2 1 &pcfg_pull_none>; + }; + + i2s0_sclk: i2s0-sclk { + rockchip,pins = + /* i2s0_sclk */ + <1 RK_PC3 1 &pcfg_pull_none>; + }; + + i2s0_sdi0: i2s0-sdi0 { + rockchip,pins = + /* i2s0_sdi0 */ + <1 RK_PD4 2 &pcfg_pull_none>; + }; + + i2s0_sdi1: i2s0-sdi1 { + rockchip,pins = + /* i2s0_sdi1 */ + <1 RK_PD3 2 &pcfg_pull_none>; + }; + + i2s0_sdi2: i2s0-sdi2 { + rockchip,pins = + /* i2s0_sdi2 */ + <1 RK_PD2 2 &pcfg_pull_none>; + }; + + i2s0_sdi3: i2s0-sdi3 { + rockchip,pins = + /* i2s0_sdi3 */ + <1 RK_PD1 2 &pcfg_pull_none>; + }; + + i2s0_sdo0: i2s0-sdo0 { + rockchip,pins = + /* i2s0_sdo0 */ + <1 RK_PC7 1 &pcfg_pull_none>; + }; + + i2s0_sdo1: i2s0-sdo1 { + rockchip,pins = + /* i2s0_sdo1 */ + <1 RK_PD0 1 &pcfg_pull_none>; + }; + + i2s0_sdo2: i2s0-sdo2 { + rockchip,pins = + /* i2s0_sdo2 */ + <1 RK_PD1 1 &pcfg_pull_none>; + }; + + i2s0_sdo3: i2s0-sdo3 { + rockchip,pins = + /* i2s0_sdo3 */ + <1 RK_PD2 1 &pcfg_pull_none>; + }; + }; + + i2s1 { + i2s1m0_lrck: i2s1m0-lrck { + rockchip,pins = + /* i2s1m0_lrck */ + <4 RK_PA2 3 &pcfg_pull_none>; + }; + + i2s1m0_mclk: i2s1m0-mclk { + rockchip,pins = + /* i2s1m0_mclk */ + <4 RK_PA0 3 &pcfg_pull_none>; + }; + + i2s1m0_sclk: i2s1m0-sclk { + rockchip,pins = + /* i2s1m0_sclk */ + <4 RK_PA1 3 &pcfg_pull_none>; + }; + + i2s1m0_sdi0: i2s1m0-sdi0 { + rockchip,pins = + /* i2s1m0_sdi0 */ + <4 RK_PA5 3 &pcfg_pull_none>; + }; + + i2s1m0_sdi1: i2s1m0-sdi1 { + rockchip,pins = + /* i2s1m0_sdi1 */ + <4 RK_PA6 3 &pcfg_pull_none>; + }; + + i2s1m0_sdi2: i2s1m0-sdi2 { + rockchip,pins = + /* i2s1m0_sdi2 */ + <4 RK_PA7 3 &pcfg_pull_none>; + }; + + i2s1m0_sdi3: i2s1m0-sdi3 { + rockchip,pins = + /* i2s1m0_sdi3 */ + <4 RK_PB0 3 &pcfg_pull_none>; + }; + + i2s1m0_sdo0: i2s1m0-sdo0 { + rockchip,pins = + /* i2s1m0_sdo0 */ + <4 RK_PB1 3 &pcfg_pull_none>; + }; + + i2s1m0_sdo1: i2s1m0-sdo1 { + rockchip,pins = + /* i2s1m0_sdo1 */ + <4 RK_PB2 3 &pcfg_pull_none>; + }; + + i2s1m0_sdo2: i2s1m0-sdo2 { + rockchip,pins = + /* i2s1m0_sdo2 */ + <4 RK_PB3 3 &pcfg_pull_none>; + }; + + i2s1m0_sdo3: i2s1m0-sdo3 { + rockchip,pins = + /* i2s1m0_sdo3 */ + <4 RK_PB4 3 &pcfg_pull_none>; + }; + i2s1m1_lrck: i2s1m1-lrck { + rockchip,pins = + /* i2s1m1_lrck */ + <0 RK_PB7 1 &pcfg_pull_none>; + }; + + i2s1m1_mclk: i2s1m1-mclk { + rockchip,pins = + /* i2s1m1_mclk */ + <0 RK_PB5 1 &pcfg_pull_none>; + }; + + i2s1m1_sclk: i2s1m1-sclk { + rockchip,pins = + /* i2s1m1_sclk */ + <0 RK_PB6 1 &pcfg_pull_none>; + }; + + i2s1m1_sdi0: i2s1m1-sdi0 { + rockchip,pins = + /* i2s1m1_sdi0 */ + <0 RK_PC5 1 &pcfg_pull_none>; + }; + + i2s1m1_sdi1: i2s1m1-sdi1 { + rockchip,pins = + /* i2s1m1_sdi1 */ + <0 RK_PC6 1 &pcfg_pull_none>; + }; + + i2s1m1_sdi2: i2s1m1-sdi2 { + rockchip,pins = + /* i2s1m1_sdi2 */ + <0 RK_PC7 1 &pcfg_pull_none>; + }; + + i2s1m1_sdi3: i2s1m1-sdi3 { + rockchip,pins = + /* i2s1m1_sdi3 */ + <0 RK_PD0 1 &pcfg_pull_none>; + }; + + i2s1m1_sdo0: i2s1m1-sdo0 { + rockchip,pins = + /* i2s1m1_sdo0 */ + <0 RK_PD1 1 &pcfg_pull_none>; + }; + + i2s1m1_sdo1: i2s1m1-sdo1 { + rockchip,pins = + /* i2s1m1_sdo1 */ + <0 RK_PD2 1 &pcfg_pull_none>; + }; + + i2s1m1_sdo2: i2s1m1-sdo2 { + rockchip,pins = + /* i2s1m1_sdo2 */ + <0 RK_PD4 1 &pcfg_pull_none>; + }; + + i2s1m1_sdo3: i2s1m1-sdo3 { + rockchip,pins = + /* i2s1m1_sdo3 */ + <0 RK_PD5 1 &pcfg_pull_none>; + }; + }; + + i2s2 { + i2s2m1_lrck: i2s2m1-lrck { + rockchip,pins = + /* i2s2m1_lrck */ + <3 RK_PB6 3 &pcfg_pull_none>; + }; + + i2s2m1_mclk: i2s2m1-mclk { + rockchip,pins = + /* i2s2m1_mclk */ + <3 RK_PB4 3 &pcfg_pull_none>; + }; + + i2s2m1_sclk: i2s2m1-sclk { + rockchip,pins = + /* i2s2m1_sclk */ + <3 RK_PB5 3 &pcfg_pull_none>; + }; + + i2s2m1_sdi: i2s2m1-sdi { + rockchip,pins = + /* i2s2m1_sdi */ + <3 RK_PB2 3 &pcfg_pull_none>; + }; + + i2s2m1_sdo: i2s2m1-sdo { + rockchip,pins = + /* i2s2m1_sdo */ + <3 RK_PB3 3 &pcfg_pull_none>; + }; + }; + + i2s3 { + i2s3_lrck: i2s3-lrck { + rockchip,pins = + /* i2s3_lrck */ + <3 RK_PA2 3 &pcfg_pull_none>; + }; + + i2s3_mclk: i2s3-mclk { + rockchip,pins = + /* i2s3_mclk */ + <3 RK_PA0 3 &pcfg_pull_none>; + }; + + i2s3_sclk: i2s3-sclk { + rockchip,pins = + /* i2s3_sclk */ + <3 RK_PA1 3 &pcfg_pull_none>; + }; + + i2s3_sdi: i2s3-sdi { + rockchip,pins = + /* i2s3_sdi */ + <3 RK_PA4 3 &pcfg_pull_none>; + }; + + i2s3_sdo: i2s3-sdo { + rockchip,pins = + /* i2s3_sdo */ + <3 RK_PA3 3 &pcfg_pull_none>; + }; + }; + + jtag { + jtagm0_pins: jtagm0-pins { + rockchip,pins = + /* jtag_tck_m0 */ + <4 RK_PD2 5 &pcfg_pull_none>, + /* jtag_tms_m0 */ + <4 RK_PD3 5 &pcfg_pull_none>; + }; + + jtagm1_pins: jtagm1-pins { + rockchip,pins = + /* jtag_tck_m1 */ + <4 RK_PD0 5 &pcfg_pull_none>, + /* jtag_tms_m1 */ + <4 RK_PD1 5 &pcfg_pull_none>; + }; + + jtagm2_pins: jtagm2-pins { + rockchip,pins = + /* jtag_tck_m2 */ + <0 RK_PB5 2 &pcfg_pull_none>, + /* jtag_tms_m2 */ + <0 RK_PB6 2 &pcfg_pull_none>; + }; + }; + + litcpu { + litcpu_pins: litcpu-pins { + rockchip,pins = + /* litcpu_avs */ + <0 RK_PD3 1 &pcfg_pull_none>; + }; + }; + + mcu { + mcum0_pins: mcum0-pins { + rockchip,pins = + /* mcu_jtag_tck_m0 */ + <4 RK_PD4 5 &pcfg_pull_none>, + /* mcu_jtag_tms_m0 */ + <4 RK_PD5 5 &pcfg_pull_none>; + }; + + mcum1_pins: mcum1-pins { + rockchip,pins = + /* mcu_jtag_tck_m1 */ + <3 RK_PD4 6 &pcfg_pull_none>, + /* mcu_jtag_tms_m1 */ + <3 RK_PD5 6 &pcfg_pull_none>; + }; + }; + + mipi { + mipim0_pins: mipim0-pins { + rockchip,pins = + /* mipi_camera0_clk_m0 */ + <4 RK_PB1 1 &pcfg_pull_none>, + /* mipi_camera1_clk_m0 */ + <1 RK_PB6 2 &pcfg_pull_none>, + /* mipi_camera2_clk_m0 */ + <1 RK_PB7 2 &pcfg_pull_none>, + /* mipi_camera3_clk_m0 */ + <1 RK_PD6 2 &pcfg_pull_none>, + /* mipi_camera4_clk_m0 */ + <1 RK_PD7 2 &pcfg_pull_none>; + }; + + mipim1_pins: mipim1-pins { + rockchip,pins = + /* mipi_camera0_clk_m1 */ + <3 RK_PA5 4 &pcfg_pull_none>, + /* mipi_camera1_clk_m1 */ + <3 RK_PA6 4 &pcfg_pull_none>, + /* mipi_camera2_clk_m1 */ + <3 RK_PA7 4 &pcfg_pull_none>, + /* mipi_camera3_clk_m1 */ + <3 RK_PB0 4 &pcfg_pull_none>, + /* mipi_camera4_clk_m1 */ + <3 RK_PB1 4 &pcfg_pull_none>; + }; + + mipi_te0: mipi-te0 { + rockchip,pins = + /* mipi_te0 */ + <3 RK_PC2 2 &pcfg_pull_none>; + }; + + mipi_te1: mipi-te1 { + rockchip,pins = + /* mipi_te1 */ + <3 RK_PC3 2 &pcfg_pull_none>; + }; + }; + + npu { + npu_pins: npu-pins { + rockchip,pins = + /* npu_avs */ + <0 RK_PC6 2 &pcfg_pull_none>; + }; + }; + + pcie20x1 { + pcie20x1m0_pins: pcie20x1m0-pins { + rockchip,pins = + /* pcie20x1_2_clkreqn_m0 */ + <3 RK_PC7 4 &pcfg_pull_none>, + /* pcie20x1_2_perstn_m0 */ + <3 RK_PD1 4 &pcfg_pull_none>, + /* pcie20x1_2_waken_m0 */ + <3 RK_PD0 4 &pcfg_pull_none>; + }; + + pcie20x1m1_pins: pcie20x1m1-pins { + rockchip,pins = + /* pcie20x1_2_clkreqn_m1 */ + <4 RK_PB7 4 &pcfg_pull_none>, + /* pcie20x1_2_perstn_m1 */ + <4 RK_PC1 4 &pcfg_pull_none>, + /* pcie20x1_2_waken_m1 */ + <4 RK_PC0 4 &pcfg_pull_none>; + }; + + pcie20x1_2_button_rstn: pcie20x1-2-button-rstn { + rockchip,pins = + /* pcie20x1_2_button_rstn */ + <4 RK_PB3 4 &pcfg_pull_none>; + }; + }; + + pcie30phy { + pcie30phy_pins: pcie30phy-pins { + rockchip,pins = + /* pcie30phy_dtb0 */ + <1 RK_PC4 4 &pcfg_pull_none>, + /* pcie30phy_dtb1 */ + <1 RK_PD1 4 &pcfg_pull_none>; + }; + }; + + pcie30x1 { + pcie30x1m0_pins: pcie30x1m0-pins { + rockchip,pins = + /* pcie30x1_0_clkreqn_m0 */ + <0 RK_PC0 12 &pcfg_pull_none>, + /* pcie30x1_0_perstn_m0 */ + <0 RK_PC5 12 &pcfg_pull_none>, + /* pcie30x1_0_waken_m0 */ + <0 RK_PC4 12 &pcfg_pull_none>, + /* pcie30x1_1_clkreqn_m0 */ + <0 RK_PB5 12 &pcfg_pull_none>, + /* pcie30x1_1_perstn_m0 */ + <0 RK_PB7 12 &pcfg_pull_none>, + /* pcie30x1_1_waken_m0 */ + <0 RK_PB6 12 &pcfg_pull_none>; + }; + + pcie30x1m1_pins: pcie30x1m1-pins { + rockchip,pins = + /* pcie30x1_0_clkreqn_m1 */ + <4 RK_PA3 4 &pcfg_pull_none>, + /* pcie30x1_0_perstn_m1 */ + <4 RK_PA5 4 &pcfg_pull_none>, + /* pcie30x1_0_waken_m1 */ + <4 RK_PA4 4 &pcfg_pull_none>, + /* pcie30x1_1_clkreqn_m1 */ + <4 RK_PA0 4 &pcfg_pull_none>, + /* pcie30x1_1_perstn_m1 */ + <4 RK_PA2 4 &pcfg_pull_none>, + /* pcie30x1_1_waken_m1 */ + <4 RK_PA1 4 &pcfg_pull_none>; + }; + + pcie30x1m2_pins: pcie30x1m2-pins { + rockchip,pins = + /* pcie30x1_0_clkreqn_m2 */ + <1 RK_PB5 4 &pcfg_pull_none>, + /* pcie30x1_0_perstn_m2 */ + <1 RK_PB4 4 &pcfg_pull_none>, + /* pcie30x1_0_waken_m2 */ + <1 RK_PB3 4 &pcfg_pull_none>, + /* pcie30x1_1_clkreqn_m2 */ + <1 RK_PA0 4 &pcfg_pull_none>, + /* pcie30x1_1_perstn_m2 */ + <1 RK_PA7 4 &pcfg_pull_none>, + /* pcie30x1_1_waken_m2 */ + <1 RK_PA1 4 &pcfg_pull_none>; + }; + + pcie30x1_0_button_rstn: pcie30x1-0-button-rstn { + rockchip,pins = + /* pcie30x1_0_button_rstn */ + <4 RK_PB1 4 &pcfg_pull_none>; + }; + + pcie30x1_1_button_rstn: pcie30x1-1-button-rstn { + rockchip,pins = + /* pcie30x1_1_button_rstn */ + <4 RK_PB2 4 &pcfg_pull_none>; + }; + }; + + pcie30x2 { + pcie30x2m0_pins: pcie30x2m0-pins { + rockchip,pins = + /* pcie30x2_clkreqn_m0 */ + <0 RK_PD1 12 &pcfg_pull_none>, + /* pcie30x2_perstn_m0 */ + <0 RK_PD4 12 &pcfg_pull_none>, + /* pcie30x2_waken_m0 */ + <0 RK_PD2 12 &pcfg_pull_none>; + }; + + pcie30x2m1_pins: pcie30x2m1-pins { + rockchip,pins = + /* pcie30x2_clkreqn_m1 */ + <4 RK_PA6 4 &pcfg_pull_none>, + /* pcie30x2_perstn_m1 */ + <4 RK_PB0 4 &pcfg_pull_none>, + /* pcie30x2_waken_m1 */ + <4 RK_PA7 4 &pcfg_pull_none>; + }; + + pcie30x2m2_pins: pcie30x2m2-pins { + rockchip,pins = + /* pcie30x2_clkreqn_m2 */ + <3 RK_PD2 4 &pcfg_pull_none>, + /* pcie30x2_perstn_m2 */ + <3 RK_PD4 4 &pcfg_pull_none>, + /* pcie30x2_waken_m2 */ + <3 RK_PD3 4 &pcfg_pull_none>; + }; + + pcie30x2m3_pins: pcie30x2m3-pins { + rockchip,pins = + /* pcie30x2_clkreqn_m3 */ + <1 RK_PD7 4 &pcfg_pull_none>, + /* pcie30x2_perstn_m3 */ + <1 RK_PB7 4 &pcfg_pull_none>, + /* pcie30x2_waken_m3 */ + <1 RK_PB6 4 &pcfg_pull_none>; + }; + + pcie30x2_button_rstn: pcie30x2-button-rstn { + rockchip,pins = + /* pcie30x2_button_rstn */ + <3 RK_PC1 4 &pcfg_pull_none>; + }; + }; + + pcie30x4 { + pcie30x4m0_pins: pcie30x4m0-pins { + rockchip,pins = + /* pcie30x4_clkreqn_m0 */ + <0 RK_PC6 12 &pcfg_pull_none>, + /* pcie30x4_perstn_m0 */ + <0 RK_PD0 12 &pcfg_pull_none>, + /* pcie30x4_waken_m0 */ + <0 RK_PC7 12 &pcfg_pull_none>; + }; + + pcie30x4m1_pins: pcie30x4m1-pins { + rockchip,pins = + /* pcie30x4_clkreqn_m1 */ + <4 RK_PB4 4 &pcfg_pull_none>, + /* pcie30x4_perstn_m1 */ + <4 RK_PB6 4 &pcfg_pull_none>, + /* pcie30x4_waken_m1 */ + <4 RK_PB5 4 &pcfg_pull_none>; + }; + + pcie30x4m2_pins: pcie30x4m2-pins { + rockchip,pins = + /* pcie30x4_clkreqn_m2 */ + <3 RK_PC4 4 &pcfg_pull_none>, + /* pcie30x4_perstn_m2 */ + <3 RK_PC6 4 &pcfg_pull_none>, + /* pcie30x4_waken_m2 */ + <3 RK_PC5 4 &pcfg_pull_none>; + }; + + pcie30x4m3_pins: pcie30x4m3-pins { + rockchip,pins = + /* pcie30x4_clkreqn_m3 */ + <1 RK_PB0 4 &pcfg_pull_none>, + /* pcie30x4_perstn_m3 */ + <1 RK_PB2 4 &pcfg_pull_none>, + /* pcie30x4_waken_m3 */ + <1 RK_PB1 4 &pcfg_pull_none>; + }; + + pcie30x4_button_rstn: pcie30x4-button-rstn { + rockchip,pins = + /* pcie30x4_button_rstn */ + <3 RK_PD5 4 &pcfg_pull_none>; + }; + }; + + pdm0 { + pdm0m0_clk: pdm0m0-clk { + rockchip,pins = + /* pdm0_clk0_m0 */ + <1 RK_PC6 3 &pcfg_pull_none>; + }; + + pdm0m0_clk1: pdm0m0-clk1 { + rockchip,pins = + /* pdm0m0_clk1 */ + <1 RK_PC4 3 &pcfg_pull_none>; + }; + + pdm0m0_sdi0: pdm0m0-sdi0 { + rockchip,pins = + /* pdm0m0_sdi0 */ + <1 RK_PD5 3 &pcfg_pull_none>; + }; + + pdm0m0_sdi1: pdm0m0-sdi1 { + rockchip,pins = + /* pdm0m0_sdi1 */ + <1 RK_PD1 3 &pcfg_pull_none>; + }; + + pdm0m0_sdi2: pdm0m0-sdi2 { + rockchip,pins = + /* pdm0m0_sdi2 */ + <1 RK_PD2 3 &pcfg_pull_none>; + }; + + pdm0m0_sdi3: pdm0m0-sdi3 { + rockchip,pins = + /* pdm0m0_sdi3 */ + <1 RK_PD3 3 &pcfg_pull_none>; + }; + pdm0m1_clk: pdm0m1-clk { + rockchip,pins = + /* pdm0_clk0_m1 */ + <0 RK_PC0 2 &pcfg_pull_none>; + }; + + pdm0m1_clk1: pdm0m1-clk1 { + rockchip,pins = + /* pdm0m1_clk1 */ + <0 RK_PC4 2 &pcfg_pull_none>; + }; + + pdm0m1_sdi0: pdm0m1-sdi0 { + rockchip,pins = + /* pdm0m1_sdi0 */ + <0 RK_PC7 2 &pcfg_pull_none>; + }; + + pdm0m1_sdi1: pdm0m1-sdi1 { + rockchip,pins = + /* pdm0m1_sdi1 */ + <0 RK_PD0 2 &pcfg_pull_none>; + }; + + pdm0m1_sdi2: pdm0m1-sdi2 { + rockchip,pins = + /* pdm0m1_sdi2 */ + <0 RK_PD4 2 &pcfg_pull_none>; + }; + + pdm0m1_sdi3: pdm0m1-sdi3 { + rockchip,pins = + /* pdm0m1_sdi3 */ + <0 RK_PD6 2 &pcfg_pull_none>; + }; + }; + + pdm1 { + pdm1m0_clk: pdm1m0-clk { + rockchip,pins = + /* pdm1_clk0_m0 */ + <4 RK_PD5 2 &pcfg_pull_none>; + }; + + pdm1m0_clk1: pdm1m0-clk1 { + rockchip,pins = + /* pdm1m0_clk1 */ + <4 RK_PD4 2 &pcfg_pull_none>; + }; + + pdm1m0_sdi0: pdm1m0-sdi0 { + rockchip,pins = + /* pdm1m0_sdi0 */ + <4 RK_PD3 2 &pcfg_pull_none>; + }; + + pdm1m0_sdi1: pdm1m0-sdi1 { + rockchip,pins = + /* pdm1m0_sdi1 */ + <4 RK_PD2 2 &pcfg_pull_none>; + }; + + pdm1m0_sdi2: pdm1m0-sdi2 { + rockchip,pins = + /* pdm1m0_sdi2 */ + <4 RK_PD1 2 &pcfg_pull_none>; + }; + + pdm1m0_sdi3: pdm1m0-sdi3 { + rockchip,pins = + /* pdm1m0_sdi3 */ + <4 RK_PD0 2 &pcfg_pull_none>; + }; + pdm1m1_clk: pdm1m1-clk { + rockchip,pins = + /* pdm1_clk0_m1 */ + <1 RK_PB4 2 &pcfg_pull_none>; + }; + + pdm1m1_clk1: pdm1m1-clk1 { + rockchip,pins = + /* pdm1m1_clk1 */ + <1 RK_PB3 2 &pcfg_pull_none>; + }; + + pdm1m1_sdi0: pdm1m1-sdi0 { + rockchip,pins = + /* pdm1m1_sdi0 */ + <1 RK_PA7 2 &pcfg_pull_none>; + }; + + pdm1m1_sdi1: pdm1m1-sdi1 { + rockchip,pins = + /* pdm1m1_sdi1 */ + <1 RK_PB0 2 &pcfg_pull_none>; + }; + + pdm1m1_sdi2: pdm1m1-sdi2 { + rockchip,pins = + /* pdm1m1_sdi2 */ + <1 RK_PB1 2 &pcfg_pull_none>; + }; + + pdm1m1_sdi3: pdm1m1-sdi3 { + rockchip,pins = + /* pdm1m1_sdi3 */ + <1 RK_PB2 2 &pcfg_pull_none>; + }; + }; + + pmic { + pmic_pins: pmic-pins { + rockchip,pins = + /* pmic_int_l */ + <0 RK_PA7 1 &pcfg_pull_none>, + /* pmic_sleep1 */ + <0 RK_PA2 1 &pcfg_pull_none>, + /* pmic_sleep2 */ + <0 RK_PA3 1 &pcfg_pull_none>, + /* pmic_sleep3 */ + <0 RK_PC1 1 &pcfg_pull_none>, + /* pmic_sleep4 */ + <0 RK_PC2 1 &pcfg_pull_none>, + /* pmic_sleep5 */ + <0 RK_PC3 1 &pcfg_pull_none>, + /* pmic_sleep6 */ + <0 RK_PD6 1 &pcfg_pull_none>; + }; + }; + + pmu { + pmu_pins: pmu-pins { + rockchip,pins = + /* pmu_debug */ + <0 RK_PA5 3 &pcfg_pull_none>; + }; + }; + + pwm0 { + pwm0m0_pins: pwm0m0-pins { + rockchip,pins = + /* pwm0_m0 */ + <0 RK_PB7 3 &pcfg_pull_none>; + }; + + pwm0m1_pins: pwm0m1-pins { + rockchip,pins = + /* pwm0_m1 */ + <1 RK_PD2 11 &pcfg_pull_none>; + }; + + pwm0m2_pins: pwm0m2-pins { + rockchip,pins = + /* pwm0_m2 */ + <1 RK_PA2 11 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1m0_pins: pwm1m0-pins { + rockchip,pins = + /* pwm1_m0 */ + <0 RK_PC0 3 &pcfg_pull_none>; + }; + + pwm1m1_pins: pwm1m1-pins { + rockchip,pins = + /* pwm1_m1 */ + <1 RK_PD3 11 &pcfg_pull_none>; + }; + + pwm1m2_pins: pwm1m2-pins { + rockchip,pins = + /* pwm1_m2 */ + <1 RK_PA3 11 &pcfg_pull_none>; + }; + }; + + pwm2 { + pwm2m0_pins: pwm2m0-pins { + rockchip,pins = + /* pwm2_m0 */ + <0 RK_PC4 3 &pcfg_pull_none>; + }; + + pwm2m1_pins: pwm2m1-pins { + rockchip,pins = + /* pwm2_m1 */ + <3 RK_PB1 11 &pcfg_pull_none>; + }; + }; + + pwm3 { + pwm3m0_pins: pwm3m0-pins { + rockchip,pins = + /* pwm3_ir_m0 */ + <0 RK_PD4 3 &pcfg_pull_none>; + }; + + pwm3m1_pins: pwm3m1-pins { + rockchip,pins = + /* pwm3_ir_m1 */ + <3 RK_PB2 11 &pcfg_pull_none>; + }; + + pwm3m2_pins: pwm3m2-pins { + rockchip,pins = + /* pwm3_ir_m2 */ + <1 RK_PC2 11 &pcfg_pull_none>; + }; + + pwm3m3_pins: pwm3m3-pins { + rockchip,pins = + /* pwm3_ir_m3 */ + <1 RK_PA7 11 &pcfg_pull_none>; + }; + }; + + pwm4 { + pwm4m0_pins: pwm4m0-pins { + rockchip,pins = + /* pwm4_m0 */ + <0 RK_PC5 11 &pcfg_pull_none>; + }; + }; + + pwm5 { + pwm5m0_pins: pwm5m0-pins { + rockchip,pins = + /* pwm5_m0 */ + <0 RK_PB1 3 &pcfg_pull_none>; + }; + + pwm5m1_pins: pwm5m1-pins { + rockchip,pins = + /* pwm5_m1 */ + <0 RK_PC6 11 &pcfg_pull_none>; + }; + }; + + pwm6 { + pwm6m0_pins: pwm6m0-pins { + rockchip,pins = + /* pwm6_m0 */ + <0 RK_PC7 11 &pcfg_pull_none>; + }; + + pwm6m1_pins: pwm6m1-pins { + rockchip,pins = + /* pwm6_m1 */ + <4 RK_PC1 11 &pcfg_pull_none>; + }; + }; + + pwm7 { + pwm7m0_pins: pwm7m0-pins { + rockchip,pins = + /* pwm7_ir_m0 */ + <0 RK_PD0 11 &pcfg_pull_none>; + }; + + pwm7m1_pins: pwm7m1-pins { + rockchip,pins = + /* pwm7_ir_m1 */ + <4 RK_PD4 11 &pcfg_pull_none>; + }; + + pwm7m2_pins: pwm7m2-pins { + rockchip,pins = + /* pwm7_ir_m2 */ + <1 RK_PC3 11 &pcfg_pull_none>; + }; + }; + + pwm8 { + pwm8m0_pins: pwm8m0-pins { + rockchip,pins = + /* pwm8_m0 */ + <3 RK_PA7 11 &pcfg_pull_none>; + }; + + pwm8m1_pins: pwm8m1-pins { + rockchip,pins = + /* pwm8_m1 */ + <4 RK_PD0 11 &pcfg_pull_none>; + }; + + pwm8m2_pins: pwm8m2-pins { + rockchip,pins = + /* pwm8_m2 */ + <3 RK_PD0 11 &pcfg_pull_none>; + }; + }; + + pwm9 { + pwm9m0_pins: pwm9m0-pins { + rockchip,pins = + /* pwm9_m0 */ + <3 RK_PB0 11 &pcfg_pull_none>; + }; + + pwm9m1_pins: pwm9m1-pins { + rockchip,pins = + /* pwm9_m1 */ + <4 RK_PD1 11 &pcfg_pull_none>; + }; + + pwm9m2_pins: pwm9m2-pins { + rockchip,pins = + /* pwm9_m2 */ + <3 RK_PD1 11 &pcfg_pull_none>; + }; + }; + + pwm10 { + pwm10m0_pins: pwm10m0-pins { + rockchip,pins = + /* pwm10_m0 */ + <3 RK_PA0 11 &pcfg_pull_none>; + }; + + pwm10m1_pins: pwm10m1-pins { + rockchip,pins = + /* pwm10_m1 */ + <4 RK_PD3 11 &pcfg_pull_none>; + }; + + pwm10m2_pins: pwm10m2-pins { + rockchip,pins = + /* pwm10_m2 */ + <3 RK_PD3 11 &pcfg_pull_none>; + }; + }; + + pwm11 { + pwm11m0_pins: pwm11m0-pins { + rockchip,pins = + /* pwm11_ir_m0 */ + <3 RK_PA1 11 &pcfg_pull_none>; + }; + + pwm11m1_pins: pwm11m1-pins { + rockchip,pins = + /* pwm11_ir_m1 */ + <4 RK_PB4 11 &pcfg_pull_none>; + }; + + pwm11m2_pins: pwm11m2-pins { + rockchip,pins = + /* pwm11_ir_m2 */ + <1 RK_PC4 11 &pcfg_pull_none>; + }; + + pwm11m3_pins: pwm11m3-pins { + rockchip,pins = + /* pwm11_ir_m3 */ + <3 RK_PD5 11 &pcfg_pull_none>; + }; + }; + + pwm12 { + pwm12m0_pins: pwm12m0-pins { + rockchip,pins = + /* pwm12_m0 */ + <3 RK_PB5 11 &pcfg_pull_none>; + }; + + pwm12m1_pins: pwm12m1-pins { + rockchip,pins = + /* pwm12_m1 */ + <4 RK_PB5 11 &pcfg_pull_none>; + }; + }; + + pwm13 { + pwm13m0_pins: pwm13m0-pins { + rockchip,pins = + /* pwm13_m0 */ + <3 RK_PB6 11 &pcfg_pull_none>; + }; + + pwm13m1_pins: pwm13m1-pins { + rockchip,pins = + /* pwm13_m1 */ + <4 RK_PB6 11 &pcfg_pull_none>; + }; + + pwm13m2_pins: pwm13m2-pins { + rockchip,pins = + /* pwm13_m2 */ + <1 RK_PB7 11 &pcfg_pull_none>; + }; + }; + + pwm14 { + pwm14m0_pins: pwm14m0-pins { + rockchip,pins = + /* pwm14_m0 */ + <3 RK_PC2 11 &pcfg_pull_none>; + }; + + pwm14m1_pins: pwm14m1-pins { + rockchip,pins = + /* pwm14_m1 */ + <4 RK_PB2 11 &pcfg_pull_none>; + }; + + pwm14m2_pins: pwm14m2-pins { + rockchip,pins = + /* pwm14_m2 */ + <1 RK_PD6 11 &pcfg_pull_none>; + }; + }; + + pwm15 { + pwm15m0_pins: pwm15m0-pins { + rockchip,pins = + /* pwm15_ir_m0 */ + <3 RK_PC3 11 &pcfg_pull_none>; + }; + + pwm15m1_pins: pwm15m1-pins { + rockchip,pins = + /* pwm15_ir_m1 */ + <4 RK_PB3 11 &pcfg_pull_none>; + }; + + pwm15m2_pins: pwm15m2-pins { + rockchip,pins = + /* pwm15_ir_m2 */ + <1 RK_PC6 11 &pcfg_pull_none>; + }; + + pwm15m3_pins: pwm15m3-pins { + rockchip,pins = + /* pwm15_ir_m3 */ + <1 RK_PD7 11 &pcfg_pull_none>; + }; + }; + + refclk { + refclk_pins: refclk-pins { + rockchip,pins = + /* refclk_out */ + <0 RK_PA0 1 &pcfg_pull_none>; + }; + }; + + sata { + sata_pins: sata-pins { + rockchip,pins = + /* sata_cp_pod */ + <0 RK_PC6 13 &pcfg_pull_none>, + /* sata_cpdet */ + <0 RK_PD4 13 &pcfg_pull_none>, + /* sata_mp_switch */ + <0 RK_PD5 13 &pcfg_pull_none>; + }; + }; + + sata0 { + sata0m0_pins: sata0m0-pins { + rockchip,pins = + /* sata0_act_led_m0 */ + <4 RK_PB6 6 &pcfg_pull_none>; + }; + + sata0m1_pins: sata0m1-pins { + rockchip,pins = + /* sata0_act_led_m1 */ + <1 RK_PB3 6 &pcfg_pull_none>; + }; + }; + + sata1 { + sata1m0_pins: sata1m0-pins { + rockchip,pins = + /* sata1_act_led_m0 */ + <4 RK_PB5 6 &pcfg_pull_none>; + }; + + sata1m1_pins: sata1m1-pins { + rockchip,pins = + /* sata1_act_led_m1 */ + <1 RK_PA1 6 &pcfg_pull_none>; + }; + }; + + sata2 { + sata2m0_pins: sata2m0-pins { + rockchip,pins = + /* sata2_act_led_m0 */ + <4 RK_PB1 6 &pcfg_pull_none>; + }; + + sata2m1_pins: sata2m1-pins { + rockchip,pins = + /* sata2_act_led_m1 */ + <1 RK_PB7 6 &pcfg_pull_none>; + }; + }; + + sdio { + sdiom1_pins: sdiom1-pins { + rockchip,pins = + /* sdio_clk_m1 */ + <3 RK_PA5 2 &pcfg_pull_none>, + /* sdio_cmd_m1 */ + <3 RK_PA4 2 &pcfg_pull_none>, + /* sdio_d0_m1 */ + <3 RK_PA0 2 &pcfg_pull_none>, + /* sdio_d1_m1 */ + <3 RK_PA1 2 &pcfg_pull_none>, + /* sdio_d2_m1 */ + <3 RK_PA2 2 &pcfg_pull_none>, + /* sdio_d3_m1 */ + <3 RK_PA3 2 &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = + /* sdmmc_d0 */ + <4 RK_PD0 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc_d1 */ + <4 RK_PD1 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc_d2 */ + <4 RK_PD2 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc_d3 */ + <4 RK_PD3 1 &pcfg_pull_up_drv_level_2>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = + /* sdmmc_clk */ + <4 RK_PD5 1 &pcfg_pull_up_drv_level_2>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = + /* sdmmc_cmd */ + <4 RK_PD4 1 &pcfg_pull_up_drv_level_2>; + }; + + sdmmc_det: sdmmc-det { + rockchip,pins = + /* sdmmc_det */ + <0 RK_PA4 1 &pcfg_pull_up>; + }; + + sdmmc_pwren: sdmmc-pwren { + rockchip,pins = + /* sdmmc_pwren */ + <0 RK_PA5 2 &pcfg_pull_none>; + }; + }; + + spdif0 { + spdif0m0_tx: spdif0m0-tx { + rockchip,pins = + /* spdif0m0_tx */ + <1 RK_PB6 3 &pcfg_pull_none>; + }; + + spdif0m1_tx: spdif0m1-tx { + rockchip,pins = + /* spdif0m1_tx */ + <4 RK_PB4 6 &pcfg_pull_none>; + }; + }; + + spdif1 { + spdif1m0_tx: spdif1m0-tx { + rockchip,pins = + /* spdif1m0_tx */ + <1 RK_PB7 3 &pcfg_pull_none>; + }; + + spdif1m1_tx: spdif1m1-tx { + rockchip,pins = + /* spdif1m1_tx */ + <4 RK_PB1 2 &pcfg_pull_none>; + }; + + spdif1m2_tx: spdif1m2-tx { + rockchip,pins = + /* spdif1m2_tx */ + <4 RK_PC1 3 &pcfg_pull_none>; + }; + }; + + spi0 { + spi0m0_pins: spi0m0-pins { + rockchip,pins = + /* spi0_clk_m0 */ + <0 RK_PC6 8 &pcfg_pull_none>, + /* spi0_miso_m0 */ + <0 RK_PC7 8 &pcfg_pull_none>, + /* spi0_mosi_m0 */ + <0 RK_PC0 8 &pcfg_pull_none>; + }; + + spi0m0_cs0: spi0m0-cs0 { + rockchip,pins = + /* spi0_cs0_m0 */ + <0 RK_PD1 8 &pcfg_pull_none>; + }; + + spi0m0_cs1: spi0m0-cs1 { + rockchip,pins = + /* spi0_cs1_m0 */ + <0 RK_PB7 8 &pcfg_pull_none>; + }; + spi0m1_pins: spi0m1-pins { + rockchip,pins = + /* spi0_clk_m1 */ + <4 RK_PA2 8 &pcfg_pull_none>, + /* spi0_miso_m1 */ + <4 RK_PA0 8 &pcfg_pull_none>, + /* spi0_mosi_m1 */ + <4 RK_PA1 8 &pcfg_pull_none>; + }; + + spi0m1_cs0: spi0m1-cs0 { + rockchip,pins = + /* spi0_cs0_m1 */ + <4 RK_PB2 8 &pcfg_pull_none>; + }; + + spi0m1_cs1: spi0m1-cs1 { + rockchip,pins = + /* spi0_cs1_m1 */ + <4 RK_PB1 8 &pcfg_pull_none>; + }; + spi0m2_pins: spi0m2-pins { + rockchip,pins = + /* spi0_clk_m2 */ + <1 RK_PB3 8 &pcfg_pull_none>, + /* spi0_miso_m2 */ + <1 RK_PB1 8 &pcfg_pull_none>, + /* spi0_mosi_m2 */ + <1 RK_PB2 8 &pcfg_pull_none>; + }; + + spi0m2_cs0: spi0m2-cs0 { + rockchip,pins = + /* spi0_cs0_m2 */ + <1 RK_PB4 8 &pcfg_pull_none>; + }; + + spi0m2_cs1: spi0m2-cs1 { + rockchip,pins = + /* spi0_cs1_m2 */ + <1 RK_PB5 8 &pcfg_pull_none>; + }; + spi0m3_pins: spi0m3-pins { + rockchip,pins = + /* spi0_clk_m3 */ + <3 RK_PD3 8 &pcfg_pull_none>, + /* spi0_miso_m3 */ + <3 RK_PD1 8 &pcfg_pull_none>, + /* spi0_mosi_m3 */ + <3 RK_PD2 8 &pcfg_pull_none>; + }; + + spi0m3_cs0: spi0m3-cs0 { + rockchip,pins = + /* spi0_cs0_m3 */ + <3 RK_PD4 8 &pcfg_pull_none>; + }; + + spi0m3_cs1: spi0m3-cs1 { + rockchip,pins = + /* spi0_cs1_m3 */ + <3 RK_PD5 8 &pcfg_pull_none>; + }; + }; + + spi1 { + spi1m1_pins: spi1m1-pins { + rockchip,pins = + /* spi1_clk_m1 */ + <3 RK_PC1 8 &pcfg_pull_none>, + /* spi1_miso_m1 */ + <3 RK_PC0 8 &pcfg_pull_none>, + /* spi1_mosi_m1 */ + <3 RK_PB7 8 &pcfg_pull_none>; + }; + + spi1m1_cs0: spi1m1-cs0 { + rockchip,pins = + /* spi1_cs0_m1 */ + <3 RK_PC2 8 &pcfg_pull_none>; + }; + + spi1m1_cs1: spi1m1-cs1 { + rockchip,pins = + /* spi1_cs1_m1 */ + <3 RK_PC3 8 &pcfg_pull_none>; + }; + + spi1m2_pins: spi1m2-pins { + rockchip,pins = + /* spi1_clk_m2 */ + <1 RK_PD2 8 &pcfg_pull_none>, + /* spi1_miso_m2 */ + <1 RK_PD0 8 &pcfg_pull_none>, + /* spi1_mosi_m2 */ + <1 RK_PD1 8 &pcfg_pull_none>; + }; + + spi1m2_cs0: spi1m2-cs0 { + rockchip,pins = + /* spi1_cs0_m2 */ + <1 RK_PD3 8 &pcfg_pull_none>; + }; + + spi1m2_cs1: spi1m2-cs1 { + rockchip,pins = + /* spi1_cs1_m2 */ + <1 RK_PD5 8 &pcfg_pull_none>; + }; + }; + + spi2 { + spi2m0_pins: spi2m0-pins { + rockchip,pins = + /* spi2_clk_m0 */ + <1 RK_PA6 8 &pcfg_pull_none>, + /* spi2_miso_m0 */ + <1 RK_PA4 8 &pcfg_pull_none>, + /* spi2_mosi_m0 */ + <1 RK_PA5 8 &pcfg_pull_none>; + }; + + spi2m0_cs0: spi2m0-cs0 { + rockchip,pins = + /* spi2_cs0_m0 */ + <1 RK_PA7 8 &pcfg_pull_none>; + }; + + spi2m0_cs1: spi2m0-cs1 { + rockchip,pins = + /* spi2_cs1_m0 */ + <1 RK_PB0 8 &pcfg_pull_none>; + }; + + spi2m1_pins: spi2m1-pins { + rockchip,pins = + /* spi2_clk_m1 */ + <4 RK_PA6 8 &pcfg_pull_none>, + /* spi2_miso_m1 */ + <4 RK_PA4 8 &pcfg_pull_none>, + /* spi2_mosi_m1 */ + <4 RK_PA5 8 &pcfg_pull_none>; + }; + + spi2m1_cs0: spi2m1-cs0 { + rockchip,pins = + /* spi2_cs0_m1 */ + <4 RK_PA7 8 &pcfg_pull_none>; + }; + + spi2m1_cs1: spi2m1-cs1 { + rockchip,pins = + /* spi2_cs1_m1 */ + <4 RK_PB0 8 &pcfg_pull_none>; + }; + + spi2m2_pins: spi2m2-pins { + rockchip,pins = + /* spi2_clk_m2 */ + <0 RK_PA5 1 &pcfg_pull_none>, + /* spi2_miso_m2 */ + <0 RK_PB3 1 &pcfg_pull_none>, + /* spi2_mosi_m2 */ + <0 RK_PA6 1 &pcfg_pull_none>; + }; + + spi2m2_cs0: spi2m2-cs0 { + rockchip,pins = + /* spi2_cs0_m2 */ + <0 RK_PB1 1 &pcfg_pull_none>; + }; + + spi2m2_cs1: spi2m2-cs1 { + rockchip,pins = + /* spi2_cs1_m2 */ + <0 RK_PB0 1 &pcfg_pull_none>; + }; + }; + + spi3 { + spi3m1_pins: spi3m1-pins { + rockchip,pins = + /* spi3_clk_m1 */ + <4 RK_PB7 8 &pcfg_pull_none>, + /* spi3_miso_m1 */ + <4 RK_PB5 8 &pcfg_pull_none>, + /* spi3_mosi_m1 */ + <4 RK_PB6 8 &pcfg_pull_none>; + }; + + spi3m1_cs0: spi3m1-cs0 { + rockchip,pins = + /* spi3_cs0_m1 */ + <4 RK_PC0 8 &pcfg_pull_none>; + }; + + spi3m1_cs1: spi3m1-cs1 { + rockchip,pins = + /* spi3_cs1_m1 */ + <4 RK_PC1 8 &pcfg_pull_none>; + }; + + spi3m2_pins: spi3m2-pins { + rockchip,pins = + /* spi3_clk_m2 */ + <0 RK_PD3 8 &pcfg_pull_none>, + /* spi3_miso_m2 */ + <0 RK_PD0 8 &pcfg_pull_none>, + /* spi3_mosi_m2 */ + <0 RK_PD2 8 &pcfg_pull_none>; + }; + + spi3m2_cs0: spi3m2-cs0 { + rockchip,pins = + /* spi3_cs0_m2 */ + <0 RK_PD4 8 &pcfg_pull_none>; + }; + + spi3m2_cs1: spi3m2-cs1 { + rockchip,pins = + /* spi3_cs1_m2 */ + <0 RK_PD5 8 &pcfg_pull_none>; + }; + + spi3m3_pins: spi3m3-pins { + rockchip,pins = + /* spi3_clk_m3 */ + <3 RK_PD0 8 &pcfg_pull_none>, + /* spi3_miso_m3 */ + <3 RK_PC6 8 &pcfg_pull_none>, + /* spi3_mosi_m3 */ + <3 RK_PC7 8 &pcfg_pull_none>; + }; + + spi3m3_cs0: spi3m3-cs0 { + rockchip,pins = + /* spi3_cs0_m3 */ + <3 RK_PC4 8 &pcfg_pull_none>; + }; + + spi3m3_cs1: spi3m3-cs1 { + rockchip,pins = + /* spi3_cs1_m3 */ + <3 RK_PC5 8 &pcfg_pull_none>; + }; + }; + + spi4 { + spi4m0_pins: spi4m0-pins { + rockchip,pins = + /* spi4_clk_m0 */ + <1 RK_PC2 8 &pcfg_pull_none>, + /* spi4_miso_m0 */ + <1 RK_PC0 8 &pcfg_pull_none>, + /* spi4_mosi_m0 */ + <1 RK_PC1 8 &pcfg_pull_none>; + }; + + spi4m0_cs0: spi4m0-cs0 { + rockchip,pins = + /* spi4_cs0_m0 */ + <1 RK_PC3 8 &pcfg_pull_none>; + }; + + spi4m0_cs1: spi4m0-cs1 { + rockchip,pins = + /* spi4_cs1_m0 */ + <1 RK_PC4 8 &pcfg_pull_none>; + }; + + spi4m1_pins: spi4m1-pins { + rockchip,pins = + /* spi4_clk_m1 */ + <3 RK_PA2 8 &pcfg_pull_none>, + /* spi4_miso_m1 */ + <3 RK_PA0 8 &pcfg_pull_none>, + /* spi4_mosi_m1 */ + <3 RK_PA1 8 &pcfg_pull_none>; + }; + + spi4m1_cs0: spi4m1-cs0 { + rockchip,pins = + /* spi4_cs0_m1 */ + <3 RK_PA3 8 &pcfg_pull_none>; + }; + + spi4m1_cs1: spi4m1-cs1 { + rockchip,pins = + /* spi4_cs1_m1 */ + <3 RK_PA4 8 &pcfg_pull_none>; + }; + + spi4m2_pins: spi4m2-pins { + rockchip,pins = + /* spi4_clk_m2 */ + <1 RK_PA2 8 &pcfg_pull_none>, + /* spi4_miso_m2 */ + <1 RK_PA0 8 &pcfg_pull_none>, + /* spi4_mosi_m2 */ + <1 RK_PA1 8 &pcfg_pull_none>; + }; + + spi4m2_cs0: spi4m2-cs0 { + rockchip,pins = + /* spi4_cs0_m2 */ + <1 RK_PA3 8 &pcfg_pull_none>; + }; + }; + + tsadc { + tsadcm1_shut: tsadcm1-shut { + rockchip,pins = + /* tsadcm1_shut */ + <0 RK_PA2 2 &pcfg_pull_none>; + }; + + tsadc_shut: tsadc-shut { + rockchip,pins = + /* tsadc_shut */ + <0 RK_PA1 2 &pcfg_pull_none>; + }; + + tsadc_shut_org: tsadc-shut-org { + rockchip,pins = + /* tsadc_shut_org */ + <0 RK_PA1 1 &pcfg_pull_none>; + }; + }; + + uart0 { + uart0m0_xfer: uart0m0-xfer { + rockchip,pins = + /* uart0_rx_m0 */ + <0 RK_PC4 4 &pcfg_pull_up>, + /* uart0_tx_m0 */ + <0 RK_PC5 4 &pcfg_pull_up>; + }; + + uart0m1_xfer: uart0m1-xfer { + rockchip,pins = + /* uart0_rx_m1 */ + <0 RK_PB0 4 &pcfg_pull_up>, + /* uart0_tx_m1 */ + <0 RK_PB1 4 &pcfg_pull_up>; + }; + + uart0m2_xfer: uart0m2-xfer { + rockchip,pins = + /* uart0_rx_m2 */ + <4 RK_PA4 10 &pcfg_pull_up>, + /* uart0_tx_m2 */ + <4 RK_PA3 10 &pcfg_pull_up>; + }; + + uart0_ctsn: uart0-ctsn { + rockchip,pins = + /* uart0_ctsn */ + <0 RK_PD1 4 &pcfg_pull_none>; + }; + + uart0_rtsn: uart0-rtsn { + rockchip,pins = + /* uart0_rtsn */ + <0 RK_PC6 4 &pcfg_pull_none>; + }; + }; + + uart1 { + uart1m1_xfer: uart1m1-xfer { + rockchip,pins = + /* uart1_rx_m1 */ + <1 RK_PB7 10 &pcfg_pull_up>, + /* uart1_tx_m1 */ + <1 RK_PB6 10 &pcfg_pull_up>; + }; + + uart1m1_ctsn: uart1m1-ctsn { + rockchip,pins = + /* uart1m1_ctsn */ + <1 RK_PD7 10 &pcfg_pull_none>; + }; + + uart1m1_rtsn: uart1m1-rtsn { + rockchip,pins = + /* uart1m1_rtsn */ + <1 RK_PD6 10 &pcfg_pull_none>; + }; + + uart1m2_xfer: uart1m2-xfer { + rockchip,pins = + /* uart1_rx_m2 */ + <0 RK_PD2 10 &pcfg_pull_up>, + /* uart1_tx_m2 */ + <0 RK_PD1 10 &pcfg_pull_up>; + }; + + uart1m2_ctsn: uart1m2-ctsn { + rockchip,pins = + /* uart1m2_ctsn */ + <0 RK_PD0 10 &pcfg_pull_none>; + }; + + uart1m2_rtsn: uart1m2-rtsn { + rockchip,pins = + /* uart1m2_rtsn */ + <0 RK_PC7 10 &pcfg_pull_none>; + }; + }; + + uart2 { + uart2m0_xfer: uart2m0-xfer { + rockchip,pins = + /* uart2_rx_m0 */ + <0 RK_PB6 10 &pcfg_pull_up>, + /* uart2_tx_m0 */ + <0 RK_PB5 10 &pcfg_pull_up>; + }; + + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = + /* uart2_rx_m1 */ + <4 RK_PD1 10 &pcfg_pull_up>, + /* uart2_tx_m1 */ + <4 RK_PD0 10 &pcfg_pull_up>; + }; + + uart2m2_xfer: uart2m2-xfer { + rockchip,pins = + /* uart2_rx_m2 */ + <3 RK_PB2 10 &pcfg_pull_up>, + /* uart2_tx_m2 */ + <3 RK_PB1 10 &pcfg_pull_up>; + }; + + uart2_ctsn: uart2-ctsn { + rockchip,pins = + /* uart2_ctsn */ + <3 RK_PB4 10 &pcfg_pull_none>; + }; + + uart2_rtsn: uart2-rtsn { + rockchip,pins = + /* uart2_rtsn */ + <3 RK_PB3 10 &pcfg_pull_none>; + }; + }; + + uart3 { + uart3m0_xfer: uart3m0-xfer { + rockchip,pins = + /* uart3_rx_m0 */ + <1 RK_PC0 10 &pcfg_pull_up>, + /* uart3_tx_m0 */ + <1 RK_PC1 10 &pcfg_pull_up>; + }; + + uart3m1_xfer: uart3m1-xfer { + rockchip,pins = + /* uart3_rx_m1 */ + <3 RK_PB6 10 &pcfg_pull_up>, + /* uart3_tx_m1 */ + <3 RK_PB5 10 &pcfg_pull_up>; + }; + + uart3m2_xfer: uart3m2-xfer { + rockchip,pins = + /* uart3_rx_m2 */ + <4 RK_PA6 10 &pcfg_pull_up>, + /* uart3_tx_m2 */ + <4 RK_PA5 10 &pcfg_pull_up>; + }; + + uart3_ctsn: uart3-ctsn { + rockchip,pins = + /* uart3_ctsn */ + <1 RK_PC3 10 &pcfg_pull_none>; + }; + + uart3_rtsn: uart3-rtsn { + rockchip,pins = + /* uart3_rtsn */ + <1 RK_PC2 10 &pcfg_pull_none>; + }; + }; + + uart4 { + uart4m0_xfer: uart4m0-xfer { + rockchip,pins = + /* uart4_rx_m0 */ + <1 RK_PD3 10 &pcfg_pull_up>, + /* uart4_tx_m0 */ + <1 RK_PD2 10 &pcfg_pull_up>; + }; + + uart4m1_xfer: uart4m1-xfer { + rockchip,pins = + /* uart4_rx_m1 */ + <3 RK_PD0 10 &pcfg_pull_up>, + /* uart4_tx_m1 */ + <3 RK_PD1 10 &pcfg_pull_up>; + }; + + uart4m2_xfer: uart4m2-xfer { + rockchip,pins = + /* uart4_rx_m2 */ + <1 RK_PB2 10 &pcfg_pull_up>, + /* uart4_tx_m2 */ + <1 RK_PB3 10 &pcfg_pull_up>; + }; + + uart4_ctsn: uart4-ctsn { + rockchip,pins = + /* uart4_ctsn */ + <1 RK_PC7 10 &pcfg_pull_none>; + }; + + uart4_rtsn: uart4-rtsn { + rockchip,pins = + /* uart4_rtsn */ + <1 RK_PC5 10 &pcfg_pull_none>; + }; + }; + + uart5 { + uart5m0_xfer: uart5m0-xfer { + rockchip,pins = + /* uart5_rx_m0 */ + <4 RK_PD4 10 &pcfg_pull_up>, + /* uart5_tx_m0 */ + <4 RK_PD5 10 &pcfg_pull_up>; + }; + + uart5m0_ctsn: uart5m0-ctsn { + rockchip,pins = + /* uart5m0_ctsn */ + <4 RK_PD2 10 &pcfg_pull_none>; + }; + + uart5m0_rtsn: uart5m0-rtsn { + rockchip,pins = + /* uart5m0_rtsn */ + <4 RK_PD3 10 &pcfg_pull_none>; + }; + + uart5m1_xfer: uart5m1-xfer { + rockchip,pins = + /* uart5_rx_m1 */ + <3 RK_PC5 10 &pcfg_pull_up>, + /* uart5_tx_m1 */ + <3 RK_PC4 10 &pcfg_pull_up>; + }; + + uart5m1_ctsn: uart5m1-ctsn { + rockchip,pins = + /* uart5m1_ctsn */ + <2 RK_PA2 10 &pcfg_pull_none>; + }; + + uart5m1_rtsn: uart5m1-rtsn { + rockchip,pins = + /* uart5m1_rtsn */ + <2 RK_PA3 10 &pcfg_pull_none>; + }; + + uart5m2_xfer: uart5m2-xfer { + rockchip,pins = + /* uart5_rx_m2 */ + <2 RK_PD4 10 &pcfg_pull_up>, + /* uart5_tx_m2 */ + <2 RK_PD5 10 &pcfg_pull_up>; + }; + }; + + uart6 { + uart6m1_xfer: uart6m1-xfer { + rockchip,pins = + /* uart6_rx_m1 */ + <1 RK_PA0 10 &pcfg_pull_up>, + /* uart6_tx_m1 */ + <1 RK_PA1 10 &pcfg_pull_up>; + }; + + uart6m1_ctsn: uart6m1-ctsn { + rockchip,pins = + /* uart6m1_ctsn */ + <1 RK_PA3 10 &pcfg_pull_none>; + }; + + uart6m1_rtsn: uart6m1-rtsn { + rockchip,pins = + /* uart6m1_rtsn */ + <1 RK_PA2 10 &pcfg_pull_none>; + }; + + uart6m2_xfer: uart6m2-xfer { + rockchip,pins = + /* uart6_rx_m2 */ + <1 RK_PD1 10 &pcfg_pull_up>, + /* uart6_tx_m2 */ + <1 RK_PD0 10 &pcfg_pull_up>; + }; + }; + + uart7 { + uart7m1_xfer: uart7m1-xfer { + rockchip,pins = + /* uart7_rx_m1 */ + <3 RK_PC1 10 &pcfg_pull_up>, + /* uart7_tx_m1 */ + <3 RK_PC0 10 &pcfg_pull_up>; + }; + + uart7m1_ctsn: uart7m1-ctsn { + rockchip,pins = + /* uart7m1_ctsn */ + <3 RK_PC3 10 &pcfg_pull_none>; + }; + + uart7m1_rtsn: uart7m1-rtsn { + rockchip,pins = + /* uart7m1_rtsn */ + <3 RK_PC2 10 &pcfg_pull_none>; + }; + + uart7m2_xfer: uart7m2-xfer { + rockchip,pins = + /* uart7_rx_m2 */ + <1 RK_PB4 10 &pcfg_pull_up>, + /* uart7_tx_m2 */ + <1 RK_PB5 10 &pcfg_pull_up>; + }; + }; + + uart8 { + uart8m0_xfer: uart8m0-xfer { + rockchip,pins = + /* uart8_rx_m0 */ + <4 RK_PB1 10 &pcfg_pull_up>, + /* uart8_tx_m0 */ + <4 RK_PB0 10 &pcfg_pull_up>; + }; + + uart8m0_ctsn: uart8m0-ctsn { + rockchip,pins = + /* uart8m0_ctsn */ + <4 RK_PB3 10 &pcfg_pull_none>; + }; + + uart8m0_rtsn: uart8m0-rtsn { + rockchip,pins = + /* uart8m0_rtsn */ + <4 RK_PB2 10 &pcfg_pull_none>; + }; + + uart8m1_xfer: uart8m1-xfer { + rockchip,pins = + /* uart8_rx_m1 */ + <3 RK_PA3 10 &pcfg_pull_up>, + /* uart8_tx_m1 */ + <3 RK_PA2 10 &pcfg_pull_up>; + }; + + uart8m1_ctsn: uart8m1-ctsn { + rockchip,pins = + /* uart8m1_ctsn */ + <3 RK_PA5 10 &pcfg_pull_none>; + }; + + uart8m1_rtsn: uart8m1-rtsn { + rockchip,pins = + /* uart8m1_rtsn */ + <3 RK_PA4 10 &pcfg_pull_none>; + }; + + uart8_xfer: uart8-xfer { + rockchip,pins = + /* uart8_rx_ */ + <4 RK_PB1 10 &pcfg_pull_up>; + }; + }; + + uart9 { + uart9m1_xfer: uart9m1-xfer { + rockchip,pins = + /* uart9_rx_m1 */ + <4 RK_PB5 10 &pcfg_pull_up>, + /* uart9_tx_m1 */ + <4 RK_PB4 10 &pcfg_pull_up>; + }; + + uart9m1_ctsn: uart9m1-ctsn { + rockchip,pins = + /* uart9m1_ctsn */ + <4 RK_PA1 10 &pcfg_pull_none>; + }; + + uart9m1_rtsn: uart9m1-rtsn { + rockchip,pins = + /* uart9m1_rtsn */ + <4 RK_PA0 10 &pcfg_pull_none>; + }; + + uart9m2_xfer: uart9m2-xfer { + rockchip,pins = + /* uart9_rx_m2 */ + <3 RK_PD4 10 &pcfg_pull_up>, + /* uart9_tx_m2 */ + <3 RK_PD5 10 &pcfg_pull_up>; + }; + + uart9m2_ctsn: uart9m2-ctsn { + rockchip,pins = + /* uart9m2_ctsn */ + <3 RK_PD3 10 &pcfg_pull_none>; + }; + + uart9m2_rtsn: uart9m2-rtsn { + rockchip,pins = + /* uart9m2_rtsn */ + <3 RK_PD2 10 &pcfg_pull_none>; + }; + }; + + vop { + vop_pins: vop-pins { + rockchip,pins = + /* vop_post_empty */ + <1 RK_PA2 1 &pcfg_pull_none>; + }; + }; +}; + +/* + * This part is edited handly. + */ +&pinctrl { + gpio-func { + tsadc_gpio_func: tsadc-gpio-func { + rockchip,pins = + <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + spi0-hs { + spi0m0_pins_hs: spi0m0-pins { + rockchip,pins = + /* spi0_clk_m0 */ + <0 RK_PC6 8 &pcfg_pull_up_drv_level_1>, + /* spi0_miso_m0 */ + <0 RK_PC7 8 &pcfg_pull_up_drv_level_1>, + /* spi0_mosi_m0 */ + <0 RK_PC0 8 &pcfg_pull_up_drv_level_1>; + }; + + spi0m1_pins_hs: spi0m1-pins { + rockchip,pins = + /* spi0_clk_m1 */ + <4 RK_PA2 8 &pcfg_pull_up_drv_level_1>, + /* spi0_miso_m1 */ + <4 RK_PA0 8 &pcfg_pull_up_drv_level_1>, + /* spi0_mosi_m1 */ + <4 RK_PA1 8 &pcfg_pull_up_drv_level_1>; + }; + + spi0m2_pins_hs: spi0m2-pins { + rockchip,pins = + /* spi0_clk_m2 */ + <1 RK_PB3 8 &pcfg_pull_up_drv_level_1>, + /* spi0_miso_m2 */ + <1 RK_PB1 8 &pcfg_pull_up_drv_level_1>, + /* spi0_mosi_m2 */ + <1 RK_PB2 8 &pcfg_pull_up_drv_level_1>; + }; + + spi0m3_pins_hs: spi0m3-pins { + rockchip,pins = + /* spi0_clk_m3 */ + <3 RK_PD3 8 &pcfg_pull_up_drv_level_1>, + /* spi0_miso_m3 */ + <3 RK_PD1 8 &pcfg_pull_up_drv_level_1>, + /* spi0_mosi_m3 */ + <3 RK_PD2 8 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi1-hs { + spi1m1_pins_hs: spi1m1-pins { + rockchip,pins = + /* spi1_clk_m1 */ + <3 RK_PC1 8 &pcfg_pull_up_drv_level_1>, + /* spi1_miso_m1 */ + <3 RK_PC0 8 &pcfg_pull_up_drv_level_1>, + /* spi1_mosi_m1 */ + <3 RK_PB7 8 &pcfg_pull_up_drv_level_1>; + }; + + spi1m2_pins_hs: spi1m2-pins { + rockchip,pins = + /* spi1_clk_m2 */ + <1 RK_PD2 8 &pcfg_pull_up_drv_level_1>, + /* spi1_miso_m2 */ + <1 RK_PD0 8 &pcfg_pull_up_drv_level_1>, + /* spi1_mosi_m2 */ + <1 RK_PD1 8 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi2-hs { + spi2m0_pins_hs: spi2m0-pins { + rockchip,pins = + /* spi2_clk_m0 */ + <1 RK_PA6 8 &pcfg_pull_up_drv_level_1>, + /* spi2_miso_m0 */ + <1 RK_PA4 8 &pcfg_pull_up_drv_level_1>, + /* spi2_mosi_m0 */ + <1 RK_PA5 8 &pcfg_pull_up_drv_level_1>; + }; + + spi2m1_pins_hs: spi2m1-pins { + rockchip,pins = + /* spi2_clk_m1 */ + <4 RK_PA6 8 &pcfg_pull_up_drv_level_1>, + /* spi2_miso_m1 */ + <4 RK_PA4 8 &pcfg_pull_up_drv_level_1>, + /* spi2_mosi_m1 */ + <4 RK_PA5 8 &pcfg_pull_up_drv_level_1>; + }; + + spi2m2_pins_hs: spi2m2-pins { + rockchip,pins = + /* spi2_clk_m2 */ + <0 RK_PA5 1 &pcfg_pull_up_drv_level_1>, + /* spi2_miso_m2 */ + <0 RK_PB3 1 &pcfg_pull_up_drv_level_1>, + /* spi2_mosi_m2 */ + <0 RK_PA6 1 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi3-hs { + spi3m1_pins_hs: spi3m1-pins { + rockchip,pins = + /* spi3_clk_m1 */ + <4 RK_PB7 8 &pcfg_pull_up_drv_level_1>, + /* spi3_miso_m1 */ + <4 RK_PB5 8 &pcfg_pull_up_drv_level_1>, + /* spi3_mosi_m1 */ + <4 RK_PB6 8 &pcfg_pull_up_drv_level_1>; + }; + + spi3m2_pins_hs: spi3m2-pins { + rockchip,pins = + /* spi3_clk_m2 */ + <0 RK_PD3 8 &pcfg_pull_up_drv_level_1>, + /* spi3_miso_m2 */ + <0 RK_PD0 8 &pcfg_pull_up_drv_level_1>, + /* spi3_mosi_m2 */ + <0 RK_PD2 8 &pcfg_pull_up_drv_level_1>; + }; + + spi3m3_pins_hs: spi3m3-pins { + rockchip,pins = + /* spi3_clk_m3 */ + <3 RK_PD0 8 &pcfg_pull_up_drv_level_1>, + /* spi3_miso_m3 */ + <3 RK_PC6 8 &pcfg_pull_up_drv_level_1>, + /* spi3_mosi_m3 */ + <3 RK_PC7 8 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi4-hs { + spi4m0_pins_hs: spi4m0-pins { + rockchip,pins = + /* spi4_clk_m0 */ + <1 RK_PC2 8 &pcfg_pull_up_drv_level_1>, + /* spi4_miso_m0 */ + <1 RK_PC0 8 &pcfg_pull_up_drv_level_1>, + /* spi4_mosi_m0 */ + <1 RK_PC1 8 &pcfg_pull_up_drv_level_1>; + }; + + spi4m1_pins_hs: spi4m1-pins { + rockchip,pins = + /* spi4_clk_m1 */ + <3 RK_PA2 8 &pcfg_pull_up_drv_level_1>, + /* spi4_miso_m1 */ + <3 RK_PA0 8 &pcfg_pull_up_drv_level_1>, + /* spi4_mosi_m1 */ + <3 RK_PA1 8 &pcfg_pull_up_drv_level_1>; + }; + + spi4m2_pins_hs: spi4m2-pins { + rockchip,pins = + /* spi4_clk_m2 */ + <1 RK_PA2 8 &pcfg_pull_up_drv_level_1>, + /* spi4_miso_m2 */ + <1 RK_PA0 8 &pcfg_pull_up_drv_level_1>, + /* spi4_mosi_m2 */ + <1 RK_PA1 8 &pcfg_pull_up_drv_level_1>; + }; + }; +}; diff --git a/arch/arm/dts/rk3588s.dtsi b/arch/arm/dts/rk3588s.dtsi new file mode 100644 index 0000000000..0bef66b201 --- /dev/null +++ b/arch/arm/dts/rk3588s.dtsi @@ -0,0 +1,2370 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include <dt-bindings/clock/rk3588-cru.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/power/rk3588-power.h> +#include <dt-bindings/gpio/gpio.h> + +/ { + compatible = "rockchip,rk3588"; + + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet1 = &gmac1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &uart6; + serial7 = &uart7; + serial8 = &uart8; + serial9 = &uart9; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; + spi4 = &spi4; + spi5 = &sfc; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu_l0>; + }; + core1 { + cpu = <&cpu_l1>; + }; + core2 { + cpu = <&cpu_l2>; + }; + core3 { + cpu = <&cpu_l3>; + }; + }; + cluster1 { + core0 { + cpu = <&cpu_b0>; + }; + core1 { + cpu = <&cpu_b1>; + }; + }; + cluster2 { + core0 { + cpu = <&cpu_b2>; + }; + core1 { + cpu = <&cpu_b3>; + }; + }; + }; + + cpu_l0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <530>; + }; + + cpu_l1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <530>; + }; + + cpu_l2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + capacity-dmips-mhz = <530>; + }; + + cpu_l3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + capacity-dmips-mhz = <530>; + }; + + cpu_b0: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x400>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + }; + + cpu_b1: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x500>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + }; + + cpu_b2: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x600>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + }; + + cpu_b3: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x700>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + }; + }; + + arm_pmu: arm-pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_LOW>; + interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, <&cpu_l3>, + <&cpu_b0>, <&cpu_b1>, <&cpu_b2>, <&cpu_b3>; + }; + + firmware: firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + scmi: scmi { + compatible = "arm,scmi-smc"; + shmem = <&scmi_shmem>; + arm,smc-id = <0x82000010>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + + assigned-clocks = <&scmi_clk SCMI_SPLL>; + assigned-clock-rates = <700000000>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + sdei: sdei { + compatible = "arm,sdei-1.0"; + method = "smc"; + }; + }; + + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + spll: spll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <702000000>; + clock-output-names = "spll"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + }; + + xin24m: xin24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + }; + + sram: sram@10f000 { + compatible = "mmio-sram"; + reg = <0x0 0x0010f000 0x0 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x0010f000 0x100>; + + scmi_shmem: scmi_shmem@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x100>; + }; + }; + + usbdrd3_0: usbdrd3_0 { + compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3"; + clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, + <&cru ACLK_USB3OTG0>; + clock-names = "ref", "suspend", "bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usbdrd_dwc3_0: usb@fc000000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfc000000 0x0 0x400000>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&power RK3588_PD_USB>; + resets = <&cru SRST_A_USB3OTG0>; + reset-names = "usb3-otg"; + dr_mode = "otg"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + status = "disabled"; + }; + }; + + usb_host0_ehci: usb@fc800000 { + compatible = "generic-ehci"; + reg = <0x0 0xfc800000 0x0 0x40000>; + interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>; + clock-names = "usbhost", "arbiter"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host0_ohci: usb@fc840000 { + compatible = "generic-ohci"; + reg = <0x0 0xfc840000 0x0 0x40000>; + interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>; + clock-names = "usbhost", "arbiter"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host1_ehci: usb@fc880000 { + compatible = "generic-ehci"; + reg = <0x0 0xfc880000 0x0 0x40000>; + interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>; + clock-names = "usbhost", "arbiter"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host1_ohci: usb@fc8c0000 { + compatible = "generic-ohci"; + reg = <0x0 0xfc8c0000 0x0 0x40000>; + interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>; + clock-names = "usbhost", "arbiter"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + mmu600_pcie: iommu@fc900000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0xfc900000 0x0 0x200000>; + interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; + #iommu-cells = <1>; + status = "disabled"; + }; + + mmu600_php: iommu@fcb00000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0xfcb00000 0x0 0x200000>; + interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; + #iommu-cells = <1>; + status = "disabled"; + }; + + usbhost3_0: usbhost3_0 { + compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3"; + clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, + <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>; + clock-names = "ref", "suspend", "bus", "utmi"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usbhost_dwc3_0: usb@fcd00000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfcd00000 0x0 0x400000>; + interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&power RK3588_PD_PHP>; + resets = <&cru SRST_A_USB3OTG2>; + reset-names = "usb3-host"; + dr_mode = "host"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + status = "disabled"; + }; + }; + + sys_grf: syscon@fd58c000 { + compatible = "rockchip,rk3588-sys-grf", "syscon"; + reg = <0x0 0xfd58c000 0x0 0x1000>; + }; + + vo0_grf: syscon@fd5a6000 { + compatible = "rockchip,rk3588-vo-grf", "syscon"; + reg = <0x0 0xfd5a6000 0x0 0x2000>; + }; + + vo1_grf: syscon@fd5a8000 { + compatible = "rockchip,rk3588-vo-grf", "syscon"; + reg = <0x0 0xfd5a8000 0x0 0x100>; + }; + + usb_grf: syscon@fd5ac000 { + compatible = "rockchip,rk3588-usb-grf", "syscon"; + reg = <0x0 0xfd5ac000 0x0 0x4000>; + }; + + php_grf: syscon@fd5b0000 { + compatible = "rockchip,rk3588-php-grf", "syscon"; + reg = <0x0 0xfd5b0000 0x0 0x1000>; + }; + + pipe_phy0_grf: syscon@fd5bc000 { + compatible = "rockchip,pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5bc000 0x0 0x100>; + }; + + pipe_phy2_grf: syscon@fd5c4000 { + compatible = "rockchip,pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5c4000 0x0 0x100>; + }; + + usbdpphy0_grf: syscon@fd5c8000 { + compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; + reg = <0x0 0xfd5c8000 0x0 0x4000>; + }; + + usb2phy0_grf: syscon@fd5d0000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", + "simple-mfd"; + reg = <0x0 0xfd5d0000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy0: usb2-phy@0 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x0 0x10>; + interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + #clock-cells = <0>; + status = "disabled"; + + u2phy0_otg: otg-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + usb2phy2_grf: syscon@fd5d8000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", + "simple-mfd"; + reg = <0x0 0xfd5d8000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy2: usb2-phy@8000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x8000 0x10>; + interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + #clock-cells = <0>; + status = "disabled"; + + u2phy2_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + usb2phy3_grf: syscon@fd5dc000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", + "simple-mfd"; + reg = <0x0 0xfd5dc000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy3: usb2-phy@c000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0xc000 0x10>; + interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + #clock-cells = <0>; + status = "disabled"; + + u2phy3_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + hdptxphy0_grf: syscon@fd5e0000 { + compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; + reg = <0x0 0xfd5e0000 0x0 0x100>; + }; + + ioc: syscon@fd5f0000 { + compatible = "rockchip,rk3588-ioc", "syscon"; + reg = <0x0 0xfd5f0000 0x0 0x10000>; + }; + + syssram: sram@fd600000 { + compatible = "mmio-sram"; + reg = <0x0 0xfd600000 0x0 0x100000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xfd600000 0x100000>; + }; + + cru: clock-controller@fd7c0000 { + compatible = "rockchip,rk3588-cru"; + rockchip,grf = <&php_grf>; + reg = <0x0 0xfd7c0000 0x0 0x5c000>; + #clock-cells = <1>; + #reset-cells = <1>; + + assigned-clocks = + <&cru PLL_PPLL>, <&cru PLL_CPLL>, + <&cru PLL_NPLL>, <&cru PLL_GPLL>, + <&cru ARMCLK_L>, <&cru ARMCLK_B01>, + <&cru ACLK_CENTER_ROOT>, <&cru PCLK_CENTER_ROOT>, + <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, + <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, + <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, + <&cru HCLK_PMU_CM0_ROOT>; + assigned-clock-rates = + <100000000>, <1500000000>, + <850000000>, <1188000000>, + <816000000>, <1008000000>, + <600000000>, <200000000>, + <400000000>, <500000000>, + <800000000>, <100000000>, + <400000000>, <100000000>, + <200000000>; + }; + + i2c0: i2c@fd880000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfd880000 0x0 0x1000>; + clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart0: serial@fd890000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfd890000 0x0 0x100>; + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 6>, <&dmac0 7>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; + status = "disabled"; + }; + + pwm0: pwm@fd8b0000 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfd8b0000 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm0m0_pins>; + clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm1: pwm@fd8b0010 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfd8b0010 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm1m0_pins>; + clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm2: pwm@fd8b0020 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfd8b0020 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2m0_pins>; + clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm3: pwm@fd8b0030 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfd8b0030 0x0 0x10>; + interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm3m0_pins>; + clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pmu: power-management@fd8d8000 { + compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd"; + reg = <0x0 0xfd8d8000 0x0 0x400>; + + power: power-controller { + compatible = "rockchip,rk3588-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + /* These power domains are grouped by VD_NPU */ + power-domain@RK3588_PD_NPU { + reg = <RK3588_PD_NPU>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3588_PD_NPUTOP { + reg = <RK3588_PD_NPUTOP>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3588_PD_NPU1 { + reg = <RK3588_PD_NPU1>; + }; + power-domain@RK3588_PD_NPU2 { + reg = <RK3588_PD_NPU2>; + }; + }; + }; + /* These power domains are grouped by VD_GPU */ + power-domain@RK3588_PD_GPU { + reg = <RK3588_PD_GPU>; + }; + /* These power domains are grouped by VD_VCODEC */ + power-domain@RK3588_PD_VCODEC { + reg = <RK3588_PD_VCODEC>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3588_PD_RKVDEC0 { + reg = <RK3588_PD_RKVDEC0>; + }; + power-domain@RK3588_PD_RKVDEC1 { + reg = <RK3588_PD_RKVDEC1>; + }; + power-domain@RK3588_PD_VENC0 { + reg = <RK3588_PD_VENC0>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3588_PD_VENC1 { + reg = <RK3588_PD_VENC1>; + }; + }; + }; + /* These power domains are grouped by VD_LOGIC */ + power-domain@RK3588_PD_VDPU { + reg = <RK3588_PD_VDPU>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3588_PD_RGA30 { + reg = <RK3588_PD_RGA30>; + }; + power-domain@RK3588_PD_av1 { + reg = <RK3588_PD_AV1>; + }; + }; + power-domain@RK3588_PD_VOP { + reg = <RK3588_PD_VOP>; + }; + power-domain@RK3588_PD_VO0 { + reg = <RK3588_PD_VO0>; + }; + power-domain@RK3588_PD_VO1 { + reg = <RK3588_PD_VO1>; + }; + power-domain@RK3588_PD_VI { + reg = <RK3588_PD_VI>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3588_PD_ISP1 { + reg = <RK3588_PD_ISP1>; + }; + power-domain@RK3588_PD_FEC { + reg = <RK3588_PD_FEC>; + }; + }; + power-domain@RK3588_PD_RGA31 { + reg = <RK3588_PD_RGA31>; + }; + power-domain@RK3588_PD_USB { + reg = <RK3588_PD_USB>; + }; + power-domain@RK3588_PD_PHP { + reg = <RK3588_PD_PHP>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3588_PD_GMAC { + reg = <RK3588_PD_GMAC>; + }; + power-domain@RK3588_PD_PCIE { + reg = <RK3588_PD_PCIE>; + }; + }; + power-domain@RK3588_PD_NVM { + reg = <RK3588_PD_NVM>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3588_PD_NVM0 { + reg = <RK3588_PD_NVM0>; + }; + }; + power-domain@RK3588_PD_SDIO { + reg = <RK3588_PD_SDIO>; + }; + power-domain@RK3588_PD_AUDIO { + reg = <RK3588_PD_AUDIO>; + }; + power-domain@RK3588_PD_SDMMC { + reg = <RK3588_PD_SDMMC>; + }; + }; + }; + + pvtm@fda40000 { + compatible = "rockchip,rk3588-bigcore0-pvtm"; + reg = <0x0 0xfda40000 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + pvtm@0 { + reg = <0>; + clocks = <&cru CLK_BIGCORE0_PVTM>, <&cru PCLK_BIGCORE0_PVTM>; + clock-names = "clk", "pclk"; + }; + }; + + pvtm@fda50000 { + compatible = "rockchip,rk3588-bigcore1-pvtm"; + reg = <0x0 0xfda50000 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + pvtm@1 { + reg = <1>; + clocks = <&cru CLK_BIGCORE1_PVTM>, <&cru PCLK_BIGCORE1_PVTM>; + clock-names = "clk", "pclk"; + }; + }; + + pvtm@fda60000 { + compatible = "rockchip,rk3588-litcore-pvtm"; + reg = <0x0 0xfda60000 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + pvtm@2 { + reg = <2>; + clocks = <&cru CLK_LITCORE_PVTM>, <&cru PCLK_LITCORE_PVTM>; + clock-names = "clk", "pclk"; + }; + }; + + pvtm@fdaf0000 { + compatible = "rockchip,rk3588-npu-pvtm"; + reg = <0x0 0xfdaf0000 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + pvtm@3 { + reg = <3>; + clocks = <&cru CLK_NPU_PVTM>, <&cru PCLK_NPU_PVTM>; + clock-names = "clk", "pclk"; + resets = <&cru SRST_NPU_PVTM>, <&cru SRST_P_NPU_PVTM>; + reset-names = "rts", "rst-p"; + }; + }; + + pvtm@fdb30000 { + compatible = "rockchip,rk3588-gpu-pvtm"; + reg = <0x0 0xfdb30000 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + pvtm@4 { + reg = <4>; + clocks = <&cru CLK_GPU_PVTM>, <&cru PCLK_GPU_PVTM>; + clock-names = "clk", "pclk"; + resets = <&cru SRST_GPU_PVTM>, <&cru SRST_P_GPU_PVTM>; + reset-names = "rts", "rst-p"; + }; + }; + + npu0_mmu: iommu@fdab9000 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdab9000 0x0 0x100>, <0x0 0xfdaba000 0x0 0x100>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "npu0_mmu"; + clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_NPUTOP>; + #iommu-cells = <0>; + status = "disabled"; + }; + + npu1_mmu: iommu@fdaca000 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdaca000 0x0 0x100>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "npu1_mmu"; + clocks = <&cru ACLK_NPU1>, <&cru HCLK_NPU1>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_NPU1>; + #iommu-cells = <0>; + status = "disabled"; + }; + + npu2_mmu: iommu@fdada000 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdada000 0x0 0x100>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "npu2_mmu"; + clocks = <&cru ACLK_NPU2>, <&cru HCLK_NPU2>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_NPU2>; + #iommu-cells = <0>; + status = "disabled"; + }; + + vdpu_mmu: iommu@fdb50800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdb50800 0x0 0x40>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_vdpu_mmu"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_VDPU>; + #iommu-cells = <0>; + status = "disabled"; + }; + + rga3_0_mmu: iommu@fdb60f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdb60f00 0x0 0x100>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "rga3_0_mmu"; + clocks = <&cru ACLK_RGA3_0>, <&cru HCLK_RGA3_0>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_RGA30>; + #iommu-cells = <0>; + status = "disabled"; + }; + + rga3_1_mmu: iommu@fdb70f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdb70f00 0x0 0x100>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "rga3_1_mmu"; + clocks = <&cru ACLK_RGA3_1>, <&cru HCLK_RGA3_1>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_RGA31>; + #iommu-cells = <0>; + status = "disabled"; + }; + + jpegd_mmu: iommu@fdb90480 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdb90480 0x0 0x40>; + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_jpegd_mmu"; + clocks = <&cru ACLK_JPEG_DECODER>, <&cru HCLK_JPEG_DECODER>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_VDPU>; + #iommu-cells = <0>; + status = "disabled"; + }; + + jpege0_mmu: iommu@fdba0800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdba0800 0x0 0x40>; + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_jpege0_mmu"; + clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_VDPU>; + #iommu-cells = <0>; + status = "disabled"; + }; + + jpege1_mmu: iommu@fdba4800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdba4800 0x0 0x40>; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_jpege1_mmu"; + clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_VDPU>; + #iommu-cells = <0>; + status = "disabled"; + }; + + jpege2_mmu: iommu@fdba8800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdba8800 0x0 0x40>; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_jpege2_mmu"; + clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_VDPU>; + #iommu-cells = <0>; + status = "disabled"; + }; + + jpege3_mmu: iommu@fdbac800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdbac800 0x0 0x40>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_jpege3_mmu"; + clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_VDPU>; + #iommu-cells = <0>; + status = "disabled"; + }; + + iep_mmu: iommu@fdbb0800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdbb0800 0x0 0x100>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_iep_mmu"; + clocks = <&cru ACLK_IEP2P0>, <&cru HCLK_IEP2P0>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_VDPU>; + status = "disabled"; + }; + + rkvenc0_mmu: iommu@fdbdf000 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdbdf000 0x0 0x40>, <0x0 0xfdbdf040 0x0 0x40>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_rkvenc0_mmu0", "irq_rkvenc0_mmu1"; + clocks = <&cru ACLK_RKVENC0>, <&cru HCLK_RKVENC0>; + clock-names = "aclk", "iface"; + rockchip,disable-mmu-reset; + rockchip,enable-cmd-retry; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_VENC0>; + status = "disabled"; + }; + + rkvenc1_mmu: iommu@fdbef000 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdbef000 0x0 0x40>, <0x0 0xfdbef040 0x0 0x40>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_rkvenc1_mmu0", "irq_rkvenc1_mmu1"; + clocks = <&cru ACLK_RKVENC1>, <&cru HCLK_RKVENC1>; + lock-names = "aclk", "iface"; + rockchip,disable-mmu-reset; + rockchip,enable-cmd-retry; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_VENC1>; + status = "disabled"; + }; + + rkvdec0_mmu: iommu@fdc38700 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdc38700 0x0 0x40>, <0x0 0xfdc38740 0x0 0x40>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_rkvdec0_mmu"; + locks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>; + clock-names = "aclk", "iface"; + rockchip,disable-mmu-reset; + rockchip,enable-cmd-retry; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_RKVDEC0>; + status = "disabled"; + }; + + rkvdec1_mmu: iommu@fdc48700 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdc48700 0x0 0x40>, <0x0 0xfdc48740 0x0 0x40>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_rkvdec1_mmu"; + clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>; + clock-names = "aclk", "iface"; + rockchip,disable-mmu-reset; + rockchip,enable-cmd-retry; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_RKVDEC1>; + status = "disabled"; + }; + + isp0_mmu: iommu@fdcb7f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdcb7f00 0x0 0x100>; + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "isp0_mmu"; + clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_VI>; + #iommu-cells = <0>; + rockchip,disable-mmu-reset; + status = "disabled"; + }; + + isp1_mmu: iommu@fdcc7f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdcc7f00 0x0 0x100>; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "isp1_mmu"; + clocks = <&cru ACLK_ISP1>, <&cru HCLK_ISP1>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_ISP1>; + #iommu-cells = <0>; + rockchip,disable-mmu-reset; + status = "disabled"; + }; + + fec0_mmu: iommu@fdcd0f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdcd0f00 0x0 0x100>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "fec0_mmu"; + clocks = <&cru ACLK_FISHEYE0>, <&cru HCLK_FISHEYE0>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_FEC>; + #iommu-cells = <0>; + status = "disabled"; + }; + + fec1_mmu: iommu@fdcd8f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdcd8f00 0x0 0x100>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "fec1_mmu"; + clocks = <&cru ACLK_FISHEYE1>, <&cru HCLK_FISHEYE1>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_FEC>; + #iommu-cells = <0>; + status = "disabled"; + }; + + vop_mmu: iommu@fdd97e00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "vop_mmu"; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + rockchip,disable-device-link-resume; + status = "disabled"; + }; + + spdif_tx2: spdif-tx@fddb0000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfddb0000 0x0 0x1000>; + interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmac1 6>; + dma-names = "tx"; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF2_DP0>, <&cru HCLK_SPDIF2_DP0>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s4_8ch: i2s@fddc0000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddc0000 0x0 0x1000>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; + clock-names = "mclk_tx", "hclk"; + dmas = <&dmac2 0>; + dma-names = "tx"; + resets = <&cru SRST_M_I2S4_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_tx3: spdif-tx@fdde0000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfdde0000 0x0 0x1000>; + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmac1 7>; + dma-names = "tx"; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF3>, <&cru HCLK_SPDIF3>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s5_8ch: i2s@fddf0000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf0000 0x0 0x1000>; + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; + clock-names = "mclk_tx", "hclk"; + dmas = <&dmac2 2>; + dma-names = "tx"; + resets = <&cru SRST_M_I2S5_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s9_8ch: i2s@fddfc000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddfc000 0x0 0x1000>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; + clock-names = "mclk_rx", "hclk"; + dmas = <&dmac2 23>; + dma-names = "rx"; + resets = <&cru SRST_M_I2S9_8CH_RX>; + reset-names = "rx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_rx0: spdif-rx@fde08000 { + compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx"; + reg = <0x0 0xfde08000 0x0 0x1000>; + interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru MCLK_SPDIFRX0>, <&cru HCLK_SPDIFRX0>; + clock-names = "mclk", "hclk"; + dmas = <&dmac0 21>; + dma-names = "rx"; + resets = <&cru SRST_M_SPDIFRX0>; + reset-names = "spdifrx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + edp0: edp@fdec0000 { + compatible = "rockchip,rk3588-edp"; + reg = <0x0 0xfdec0000 0x0 0x1000>; + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru CLK_EDP0_24M>, <&cru PCLK_EDP0>, + <&cru CLK_EDP0_200M>; + clock-names = "dp", "pclk", "spdif"; + resets = <&cru SRST_EDP0_24M>, <&cru SRST_P_EDP0>; + reset-names = "dp", "apb"; + phys = <&hdptxphy0>; + phy-names = "dp"; + power-domains = <&power RK3588_PD_VO1>; + rockchip,grf = <&vo1_grf>; + status = "disabled"; + }; + + pcie2x1l1: pcie@fe180000 { + compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x30 0x3f>; + clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, + <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, + <&cru CLK_PCIE_AUX3>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux"; + device_type = "pci"; + interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, + <0 0 0 2 &pcie2x1l1_intc 1>, + <0 0 0 3 &pcie2x1l1_intc 2>, + <0 0 0 4 &pcie2x1l1_intc 3>; + linux,pci-domain = <3>; + num-ib-windows = <8>; + num-ob-windows = <8>; + max-link-speed = <2>; + msi-map = <0x3000 &its 0x3000 0x1000>; + num-lanes = <1>; + phys = <&combphy2_psu PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PHP>; + ranges = <0x00000800 0x0 0xc0000000 0x9 0xc0000000 0x0 0x100000 + 0x81000000 0x0 0xc0100000 0x9 0xc0100000 0x0 0x100000 + 0x83000000 0x0 0xc0200000 0x9 0xc0200000 0x0 0x3fe00000>; + reg = <0xa 0x40c00000 0x0 0x400000>, + <0x0 0xfe180000 0x0 0x10000>; + reg-names = "pcie-dbi", "pcie-apb"; + resets = <&cru SRST_PCIE3_POWER_UP>; + reset-names = "pipe"; + status = "disabled"; + + pcie2x1l1_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>; + }; + }; + + pcie2x1l2: pcie@fe190000 { + compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x40 0x4f>; + clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, + <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, + <&cru CLK_PCIE_AUX4>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux"; + device_type = "pci"; + interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, + <0 0 0 2 &pcie2x1l2_intc 1>, + <0 0 0 3 &pcie2x1l2_intc 2>, + <0 0 0 4 &pcie2x1l2_intc 3>; + linux,pci-domain = <4>; + num-ib-windows = <8>; + num-ob-windows = <8>; + max-link-speed = <2>; + msi-map = <0x4000 &its 0x4000 0x1000>; + num-lanes = <1>; + phys = <&combphy0_ps PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PHP>; + ranges = <0x00000800 0x0 0xe0000000 0xa 0x00000000 0x0 0x100000 + 0x81000000 0x0 0xe0100000 0xa 0x00100000 0x0 0x100000 + 0x83000000 0x0 0xe0200000 0xa 0x00200000 0x0 0x3fe00000>; + reg = <0xa 0x41000000 0x0 0x400000>, + <0x0 0xfe190000 0x0 0x10000>; + reg-names = "pcie-dbi", "pcie-apb"; + resets = <&cru SRST_PCIE4_POWER_UP>; + reset-names = "pipe"; + status = "disabled"; + + pcie2x1l2_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>; + }; + }; + + gmac1: ethernet@fe1c0000 { + compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; + reg = <0x0 0xfe1c0000 0x0 0x10000>; + interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_wake_irq"; + rockchip,grf = <&sys_grf>; + rockchip,php_grf = <&php_grf>; + clocks = <&cru CLK_GMAC1>, <&cru ACLK_GMAC1>, + <&cru PCLK_GMAC1>, <&cru CLK_GMAC1_PTP_REF>; + clock-names = "stmmaceth", "aclk_mac", + "pclk_mac", "ptp_ref"; + resets = <&cru SRST_A_GMAC1>; + reset-names = "stmmaceth"; + + snps,mixed-burst; + snps,tso; + + snps,axi-config = <&gmac1_stmmac_axi_setup>; + snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; + status = "disabled"; + + mdio1: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + gmac1_stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <8>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + gmac1_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <2>; + queue0 {}; + queue1 {}; + }; + + gmac1_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <2>; + queue0 {}; + queue1 {}; + }; + }; + + sata0: sata@fe210000 { + compatible = "snps,dwc-ahci"; + reg = <0 0xfe210000 0 0x1000>; + clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, + <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>; + clock-names = "sata", "pmalive", "rxoob", "ref"; + interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hostc"; + phys = <&combphy0_ps PHY_TYPE_SATA>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + power-domains = <&power RK3588_PD_PHP>; + status = "disabled"; + }; + + sata2: sata@fe230000 { + compatible = "snps,dwc-ahci"; + reg = <0 0xfe230000 0 0x1000>; + clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, + <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>; + clock-names = "sata", "pmalive", "rxoob", "ref"; + interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hostc"; + phys = <&combphy2_psu PHY_TYPE_SATA>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + power-domains = <&power RK3588_PD_PHP>; + status = "disabled"; + }; + + sfc: spi@fe2b0000 { + compatible = "rockchip,sfc"; + reg = <0x0 0xfe2b0000 0x0 0x4000>; + interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names = "clk_sfc", "hclk_sfc"; + assigned-clocks = <&cru SCLK_SFC>; + assigned-clock-rates = <100000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + sdmmc: mmc@fe2c0000 { + compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe2c0000 0x0 0x4000>; + interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk SCMI_CCLK_SD>, <&scmi_clk SCMI_HCLK_SD>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "ciu", "biu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; + status = "disabled"; + }; + + sdio: mmc@fe2d0000 { + compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe2d0000 0x0 0x4000>; + interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + status = "disabled"; + }; + + sdhci: mmc@fe2e0000 { + compatible = "rockchip,rk3588-dwcmshc", "rockchip,dwcmshc-sdhci"; + reg = <0x0 0xfe2e0000 0x0 0x10000>; + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; + assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>; + assigned-clock-rates = <200000000>, <24000000>; + clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, + <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, + <&cru TMCLK_EMMC>; + clock-names = "core", "bus", "axi", "block", "timer"; + max-frequency = <200000000>; + status = "disabled"; + }; + + i2s0_8ch: i2s@fe470000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfe470000 0x0 0x1000>; + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + dmas = <&dmac0 0>, <&dmac0 1>; + dma-names = "tx", "rx"; + resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; + reset-names = "tx-m", "rx-m"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdi1 + &i2s0_sdi2 + &i2s0_sdi3 + &i2s0_sdo0 + &i2s0_sdo1 + &i2s0_sdo2 + &i2s0_sdo3>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s1_8ch: i2s@fe480000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfe480000 0x0 0x1000>; + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + dmas = <&dmac0 2>, <&dmac0 3>; + dma-names = "tx", "rx"; + resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; + reset-names = "tx-m", "rx-m"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_lrck + &i2s1m0_sclk + &i2s1m0_sdi0 + &i2s1m0_sdi1 + &i2s1m0_sdi2 + &i2s1m0_sdi3 + &i2s1m0_sdo0 + &i2s1m0_sdo1 + &i2s1m0_sdo2 + &i2s1m0_sdo3>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s2_2ch: i2s@fe490000 { + compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xfe490000 0x0 0x1000>; + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <&dmac1 0>, <&dmac1 1>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s2m1_lrck + &i2s2m1_sclk + &i2s2m1_sdi + &i2s2m1_sdo>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s3_2ch: i2s@fe4a0000 { + compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xfe4a0000 0x0 0x1000>; + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <&dmac1 2>, <&dmac1 3>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s3_lrck + &i2s3_sclk + &i2s3_sdi + &i2s3_sdo>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + pdm0: pdm@fe4b0000 { + compatible = "rockchip,rk3588-pdm"; + reg = <0x0 0xfe4b0000 0x0 0x1000>; + clocks = <&cru MCLK_PDM0>, <&cru HCLK_PDM0>; + clock-names = "pdm_clk", "pdm_hclk"; + dmas = <&dmac0 4>; + dma-names = "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pdm0m0_clk + &pdm0m0_clk1 + &pdm0m0_sdi0 + &pdm0m0_sdi1 + &pdm0m0_sdi2 + &pdm0m0_sdi3>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + pdm1: pdm@fe4c0000 { + compatible = "rockchip,rk3588-pdm"; + reg = <0x0 0xfe4c0000 0x0 0x1000>; + clocks = <&cru MCLK_PDM1>, <&cru HCLK_PDM1>; + clock-names = "pdm_clk", "pdm_hclk"; + dmas = <&dmac1 4>; + dma-names = "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pdm1m0_clk + &pdm1m0_clk1 + &pdm1m0_sdi0 + &pdm1m0_sdi1 + &pdm1m0_sdi2 + &pdm1m0_sdi3>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + vad: vad@fe4d0000 { + compatible = "rockchip,rk3588-vad"; + reg = <0x0 0xfe4d0000 0x0 0x1000>; + reg-names = "vad"; + clocks = <&cru HCLK_VAD>; + clock-names = "hclk"; + interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; + rockchip,audio-src = <0>; + rockchip,det-channel = <0>; + rockchip,mode = <0>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_tx0: spdif-tx@fe4e0000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfe4e0000 0x0 0x1000>; + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmac0 5>; + dma-names = "tx"; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF0>, <&cru HCLK_SPDIF0>; + pinctrl-names = "default"; + pinctrl-0 = <&spdif0m0_tx>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_tx1: spdif-tx@fe4f0000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfe4f0000 0x0 0x1000>; + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmac1 5>; + dma-names = "tx"; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF1>, <&cru HCLK_SPDIF1>; + pinctrl-names = "default"; + pinctrl-0 = <&spdif1m0_tx>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + acdcdig_dsm: codec-digital@fe500000 { + compatible = "rockchip,rk3588-codec-digital", "rockchip,codec-digital-v1"; + reg = <0x0 0xfe500000 0x0 0x1000>; + clocks = <&cru CLK_DAC_ACDCDIG>, <&cru PCLK_ACDCDIG>; + clock-names = "dac", "pclk"; + resets = <&cru SRST_DAC_ACDCDIG>; + reset-names = "reset" ; + rockchip,grf = <&sys_grf>; + rockchip,pwm-output-mode; + pinctrl-names = "default"; + pinctrl-0 = <&auddsm_pins>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + hwlock: hwspinlock@fe5a0000 { + compatible = "rockchip,hwspinlock"; + reg = <0 0xfe5a0000 0 0x100>; + #hwlock-cells = <1>; + }; + + gic: interrupt-controller@fe600000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + + reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ + <0x0 0xfe680000 0 0x100000>; /* GICR */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + its: interrupt-controller@fe640000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x0 0xfe640000 0x0 0x20000>; + }; + }; + + dmac0: dma-controller@fea10000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfea10000 0x0 0x4000>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_DMAC0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + arm,pl330-periph-burst; + }; + + dmac1: dma-controller@fea30000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfea30000 0x0 0x4000>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_DMAC1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + arm,pl330-periph-burst; + }; + + can0: can@fea50000 { + compatible = "rockchip,canfd-1.0"; + reg = <0x0 0xfea50000 0x0 0x1000>; + iinterrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>; + clock-names = "baudclk", "apb_pclk"; + resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>; + reset-names = "can", "can-apb"; + pinctrl-names = "default"; + pinctrl-0 = <&can0m0_pins>; + tx-fifo-depth = <1>; + rx-fifo-depth = <6>; + status = "disabled"; + }; + + can1: can@fea60000 { + compatible = "rockchip,canfd-1.0"; + reg = <0x0 0xfea60000 0x0 0x1000>; + interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>; + clock-names = "baudclk", "apb_pclk"; + resets = <&cru SRST_CAN1>, <&cru SRST_P_CAN1>; + reset-names = "can", "can-apb"; + pinctrl-names = "default"; + pinctrl-0 = <&can1m0_pins>; + tx-fifo-depth = <1>; + rx-fifo-depth = <6>; + status = "disabled"; + }; + + can2: can@fea70000 { + compatible = "rockchip,canfd-1.0"; + reg = <0x0 0xfea70000 0x0 0x1000>; + interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>; + clock-names = "baudclk", "apb_pclk"; + resets = <&cru SRST_CAN2>, <&cru SRST_P_CAN2>; + reset-names = "can", "can-apb"; + pinctrl-names = "default"; + pinctrl-0 = <&can2m0_pins>; + tx-fifo-depth = <1>; + rx-fifo-depth = <6>; + status = "disabled"; + }; + + hw_decompress: decompress@fea80000 { + compatible = "rockchip,hw-decompress"; + reg = <0x0 0xfea80000 0x0 0x1000>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_DECOM>, <&cru DCLK_DECOM>, <&cru PCLK_DECOM>; + clock-names = "aclk", "dclk", "pclk"; + resets = <&cru SRST_D_DECOM>; + reset-names = "dresetn"; + status = "disabled"; + }; + + i2c1: i2c@fea90000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfea90000 0x0 0x1000>; + clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@feaa0000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfeaa0000 0x0 0x1000>; + clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@feab0000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfeab0000 0x0 0x1000>; + clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@feac0000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfeac0000 0x0 0x1000>; + clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@fead0000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfead0000 0x0 0x1000>; + clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rktimer: timer@feae0000 { + compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; + reg = <0x0 0xfeae0000 0x0 0x20>; + interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; + clock-names = "pclk", "timer"; + }; + + wdt: watchdog@feaf0000 { + compatible = "snps,dw-wdt"; + reg = <0x0 0xfeaf0000 0x0 0x100>; + clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; + clock-names = "tclk", "pclk"; + interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + spi0: spi@feb00000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x0 0xfeb00000 0x0 0x1000>; + interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 14>, <&dmac0 15>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "high_speed"; + pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; + pinctrl-1 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins_hs>; + num-cs = <2>; + status = "disabled"; + }; + + spi1: spi@feb10000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x0 0xfeb10000 0x0 0x1000>; + interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 16>, <&dmac0 17>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "high_speed"; + pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; + pinctrl-1 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins_hs>; + num-cs = <2>; + status = "disabled"; + }; + + spi2: spi@feb20000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x0 0xfeb20000 0x0 0x1000>; + interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac1 15>, <&dmac1 16>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "high_speed"; + pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>; + pinctrl-1 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins_hs>; + num-cs = <2>; + status = "disabled"; + }; + + spi3: spi@feb30000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x0 0xfeb30000 0x0 0x1000>; + interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac1 17>, <&dmac1 18>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "high_speed"; + pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; + pinctrl-1 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins_hs>; + num-cs = <2>; + status = "disabled"; + }; + + uart1: serial@feb40000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb40000 0x0 0x100>; + interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 8>, <&dmac0 9>; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer>; + status = "disabled"; + }; + + uart2: serial@feb50000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb50000 0x0 0x100>; + interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 10>, <&dmac0 11>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "disabled"; + }; + + uart3: serial@feb60000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb60000 0x0 0x100>; + interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 12>, <&dmac0 13>; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m0_xfer>; + status = "disabled"; + }; + + uart4: serial@feb70000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb70000 0x0 0x100>; + interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac1 9>, <&dmac1 10>; + pinctrl-names = "default"; + pinctrl-0 = <&uart4m0_xfer>; + status = "disabled"; + }; + + uart5: serial@feb80000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb80000 0x0 0x100>; + interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac1 11>, <&dmac1 12>; + pinctrl-names = "default"; + pinctrl-0 = <&uart5m0_xfer>; + status = "disabled"; + }; + + uart6: serial@feb90000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb90000 0x0 0x100>; + interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac1 13>, <&dmac1 14>; + pinctrl-names = "default"; + pinctrl-0 = <&uart6m0_xfer>; + status = "disabled"; + }; + + uart7: serial@feba0000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeba0000 0x0 0x100>; + interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac2 7>, <&dmac2 8>; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m0_xfer>; + status = "disabled"; + }; + + uart8: serial@febb0000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfebb0000 0x0 0x100>; + interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac2 9>, <&dmac2 10>; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m0_xfer>; + status = "disabled"; + }; + + uart9: serial@febc0000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfebc0000 0x0 0x100>; + interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac2 11>, <&dmac2 12>; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m0_xfer>; + status = "disabled"; + }; + + pwm4: pwm@febd0000 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebd0000 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm4m0_pins>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm5: pwm@febd0010 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebd0010 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm5m0_pins>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm6: pwm@febd0020 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebd0020 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm6m0_pins>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm7: pwm@febd0030 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebd0030 0x0 0x10>; + interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm7m0_pins>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm8: pwm@febe0000 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebe0000 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm8m0_pins>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm9: pwm@febe0010 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebe0010 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm9m0_pins>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm10: pwm@febe0020 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebe0020 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm10m0_pins>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm11: pwm@febe0030 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebe0030 0x0 0x10>; + interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm11m0_pins>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm12: pwm@febf0000 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebf0000 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm12m0_pins>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm13: pwm@febf0010 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebf0010 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm13m0_pins>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm14: pwm@febf0020 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebf0020 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm14m0_pins>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm15: pwm@febf0030 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebf0030 0x0 0x10>; + interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm15m0_pins>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + tsadc: tsadc@fec00000 { + compatible = "rockchip,rk3588-tsadc"; + reg = <0x0 0xfec00000 0x0 0x400>; + interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + assigned-clocks = <&cru CLK_TSADC>; + assigned-clock-rates = <2000000>; + resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>; + reset-names = "tsadc", "tsadc-apb"; + #thermal-sensor-cells = <1>; + rockchip,hw-tshut-temp = <120000>; + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + pinctrl-names = "gpio", "otpout"; + pinctrl-0 = <&tsadc_gpio_func>; + pinctrl-1 = <&tsadc_shut_org>; + status = "disabled"; + }; + + saradc: saradc@fec10000 { + compatible = "rockchip,rk3588-saradc"; + reg = <0x0 0xfec10000 0x0 0x10000>; + interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>; + #io-channel-cells = <1>; + clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_P_SARADC>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + mailbox0: mailbox@fec60000 { + compatible = "rockchip,rk3588-mailbox", + "rockchip,rk3368-mailbox"; + reg = <0x0 0xfec60000 0x0 0x200>; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_MAILBOX0>; + clock-names = "pclk_mailbox"; + #mbox-cells = <1>; + status = "disabled"; + }; + + mailbox1: mailbox@fec70000 { + compatible = "rockchip,rk3588-mailbox", + "rockchip,rk3368-mailbox"; + reg = <0x0 0xfec70000 0x0 0x200>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_MAILBOX1>; + clock-names = "pclk_mailbox"; + #mbox-cells = <1>; + status = "disabled"; + }; + + i2c6: i2c@fec80000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfec80000 0x0 0x1000>; + clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@fec90000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfec90000 0x0 0x1000>; + clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@feca0000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfeca0000 0x0 0x1000>; + clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@fecb0000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x0 0xfecb0000 0x0 0x1000>; + interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac2 13>, <&dmac2 14>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "high_speed"; + pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; + pinctrl-1 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins_hs>; + num-cs = <2>; + status = "disabled"; + }; + + otp: otp@fecc0000 { + compatible = "rockchip,rk3588-otp"; + reg = <0x0 0xfecc0000 0x0 0x400>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, + <&cru CLK_OTPC_ARB>, <&cru CLK_OTP_PHY_G>; + clock-names = "otpc", "apb", "arb", "phy"; + resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, + <&cru SRST_OTPC_ARB>; + reset-names = "otpc", "apb", "arb"; + }; + + mailbox2: mailbox@fece0000 { + compatible = "rockchip,rk3588-mailbox", + "rockchip,rk3368-mailbox"; + reg = <0x0 0xfece0000 0x0 0x200>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_MAILBOX2>; + clock-names = "pclk_mailbox"; + #mbox-cells = <1>; + status = "disabled"; + }; + + dmac2: dma-controller@fed10000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfed10000 0x0 0x4000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_DMAC2>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + arm,pl330-periph-burst; + }; + + hdptxphy0: phy@fed60000 { + compatible = "rockchip,rk3588-hdptx-phy"; + reg = <0x0 0xfed60000 0x0 0x2000>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; + clock-names = "ref", "apb"; + resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, + <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, + <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>, + <&cru SRST_HDPTX0_LCPLL>; + reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", + "lcpll"; + rockchip,grf = <&hdptxphy0_grf>; + #phy-cells = <0>; + status = "disabled"; + }; + + usbdp_phy0: phy@fed80000 { + compatible = "rockchip,rk3588-usbdp-phy"; + reg = <0x0 0xfed80000 0x0 0x10000>; + rockchip,usb-grf = <&usb_grf>; + rockchip,usbdpphy-grf = <&usbdpphy0_grf>; + rockchip,vo-grf = <&vo0_grf>; + clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, + <&cru CLK_USBDP_PHY0_IMMORTAL>, + <&cru PCLK_USBDPPHY0>; + clock-names = "refclk", "immortal", "pclk"; + resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, + <&cru SRST_USBDP_COMBO_PHY0_CMN>, + <&cru SRST_USBDP_COMBO_PHY0_LANE>, + <&cru SRST_USBDP_COMBO_PHY0_PCS>, + <&cru SRST_P_USBDPPHY0>; + reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; + status = "disabled"; + + usbdp_phy0_dp: dp-port { + #phy-cells = <0>; + status = "disabled"; + }; + + usbdp_phy0_u3: u3-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + + combphy0_ps: phy@fee00000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee00000 0x0 0x100>; + #phy-cells = <1>; + clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>; + clock-names = "refclk", "apbclk"; + assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_P_PCIE2_PHY0>, <&cru SRST_REF_PIPE_PHY0>; + reset-names = "combphy-apb", "combphy"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy0_grf>; + status = "disabled"; + }; + + combphy2_psu: phy@fee20000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee20000 0x0 0x100>; + #phy-cells = <1>; + clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>; + clock-names = "refclk", "apbclk"; + assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_P_PCIE2_PHY2>, <&cru SRST_REF_PIPE_PHY2>; + reset-names = "combphy-apb", "combphy"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy2_grf>; + rockchip,pcie1ln-sel-bits = <0x100 1 1 0>; + status = "disabled"; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3588-pinctrl"; + rockchip,grf = <&ioc>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio@fd8a0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfd8a0000 0x0 0x100>; + interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@fec20000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfec20000 0x0 0x100>; + interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 32 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@fec30000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfec30000 0x0 0x100>; + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 64 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@fec40000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfec40000 0x0 0x100>; + interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 96 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@fec50000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfec50000 0x0 0x100>; + interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 128 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +#include "rk3588s-pinctrl.dtsi"