From: Stefan Roese sr@denx.de

Use correct naming as done in the latest Marvell U-Boot version as well.

Signed-off-by: Stefan Roese sr@denx.de Signed-off-by: Igal Liberman igall@marvell.com --- arch/arm/dts/armada-8040-db.dts | 8 ++++---- arch/arm/dts/armada-8040-mcbin.dts | 10 +++++----- drivers/phy/marvell/comphy_core.c | 2 +- drivers/phy/marvell/comphy_cp110.c | 18 +++++++++--------- include/dt-bindings/comphy/comphy_data.h | 2 +- 5 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/arch/arm/dts/armada-8040-db.dts b/arch/arm/dts/armada-8040-db.dts index f1f196f..76fd004 100644 --- a/arch/arm/dts/armada-8040-db.dts +++ b/arch/arm/dts/armada-8040-db.dts @@ -205,7 +205,7 @@ * Serdes Configuration: * Lane 0: SGMII2 * Lane 1: USB3_HOST0 - * Lane 2: KR (10G) + * Lane 2: SFI (10G) * Lane 3: SATA1 * Lane 4: USB3_HOST1 * Lane 5: PEX2x1 @@ -220,7 +220,7 @@ };

phy2 { - phy-type = <PHY_TYPE_KR>; + phy-type = <PHY_TYPE_SFI>; };

phy3 { @@ -241,7 +241,7 @@ * Serdes Configuration: * Lane 0: SGMII2 * Lane 1: USB3_HOST0 - * Lane 2: KR (10G) + * Lane 2: SFI (10G) * Lane 3: SATA1 * Lane 4: Unconnected * Lane 5: PEX2x1 @@ -256,7 +256,7 @@ };

phy2 { - phy-type = <PHY_TYPE_KR>; + phy-type = <PHY_TYPE_SFI>; };

phy3 { diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts index e42b092..dde495a 100644 --- a/arch/arm/dts/armada-8040-mcbin.dts +++ b/arch/arm/dts/armada-8040-mcbin.dts @@ -99,7 +99,7 @@ * [54] 2.5G SFP LOS * [55] Micro SD card detect * [56-61] Micro SD - * [62] CP1 KR SFP FAULT + * [62] CP1 SFI SFP FAULT */ /* 0 1 2 3 4 5 6 7 8 9 */ pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff @@ -163,7 +163,7 @@ * Lane 1: PCIe0 (x4) * Lane 2: PCIe0 (x4) * Lane 3: PCIe0 (x4) - * Lane 4: KR (10G) + * Lane 4: SFI (10G) * Lane 5: SATA1 */ phy0 { @@ -179,7 +179,7 @@ phy-type = <PHY_TYPE_PEX0>; }; phy4 { - phy-type = <PHY_TYPE_KR>; + phy-type = <PHY_TYPE_SFI>; }; phy5 { phy-type = <PHY_TYPE_SATA1>; @@ -268,7 +268,7 @@ * Lane 1: SATA 0 * Lane 2: USB HOST 0 * Lane 3: SATA1 - * Lane 4: KR (10G) + * Lane 4: SFI (10G) * Lane 5: SGMII3 */ phy0 { @@ -285,7 +285,7 @@ phy-type = <PHY_TYPE_SATA1>; }; phy4 { - phy-type = <PHY_TYPE_KR>; + phy-type = <PHY_TYPE_SFI>; }; phy5 { phy-type = <PHY_TYPE_SGMII3>; diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c index caa1928..ac084a6 100644 --- a/drivers/phy/marvell/comphy_core.c +++ b/drivers/phy/marvell/comphy_core.c @@ -37,7 +37,7 @@ static char *get_type_string(u32 type) "SGMII1", "SGMII2", "SGMII3", "QSGMII", "USB3_HOST0", "USB3_HOST1", "USB3_DEVICE", "XAUI0", "XAUI1", "XAUI2", "XAUI3", - "RXAUI0", "RXAUI1", "KR"}; + "RXAUI0", "RXAUI1", "SFI"};

if (type < 0 || type > PHY_TYPE_MAX) return "invalid"; diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index 25c067d..cd3cf96 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -34,7 +34,7 @@ struct utmi_phy_data { * PIPE selector include USB and PCIe options. * PHY selector include the Ethernet and SATA options, every Ethernet * option has different options, for example: serdes lane2 had option - * Eth_port_0 that include (SGMII0, XAUI0, RXAUI0, KR) + * Eth_port_0 that include (SGMII0, XAUI0, RXAUI0, SFI) */ struct comphy_mux_data cp110_comphy_phy_mux_data[] = { {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 0 */ @@ -43,13 +43,13 @@ struct comphy_mux_data cp110_comphy_phy_mux_data[] = { {PHY_TYPE_XAUI3, 0x1}, {PHY_TYPE_SATA0, 0x4} } }, {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 2 */ {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, - {PHY_TYPE_KR, 0x1}, {PHY_TYPE_SATA0, 0x4} } }, + {PHY_TYPE_SFI, 0x1}, {PHY_TYPE_SATA0, 0x4} } }, {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 3 */ {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, - {PHY_TYPE_KR, 0x1}, {PHY_TYPE_XAUI1, 0x1}, + {PHY_TYPE_SFI, 0x1}, {PHY_TYPE_XAUI1, 0x1}, {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SATA1, 0x4} } }, {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, /* Lane 4 */ - {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_KR, 0x1}, + {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_SFI, 0x1}, {PHY_TYPE_SGMII2, 0x1}, {PHY_TYPE_XAUI2, 0x1} } }, {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_XAUI1, 0x1}, /* Lane 5 */ {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SGMII3, 0x1}, @@ -907,8 +907,8 @@ static int comphy_sgmii_power_up(u32 lane, u32 sgmii_speed, return ret; }

-static int comphy_kr_power_up(u32 lane, void __iomem *hpipe_base, - void __iomem *comphy_base) +static int comphy_sfi_power_up(u32 lane, void __iomem *hpipe_base, + void __iomem *comphy_base) { u32 mask, data, ret = 1; void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); @@ -1696,9 +1696,9 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, lane, ptr_comphy_map->speed, hpipe_base_addr, comphy_base_addr); break; - case PHY_TYPE_KR: - ret = comphy_kr_power_up(lane, hpipe_base_addr, - comphy_base_addr); + case PHY_TYPE_SFI: + ret = comphy_sfi_power_up(lane, hpipe_base_addr, + comphy_base_addr); break; case PHY_TYPE_RXAUI0: case PHY_TYPE_RXAUI1: diff --git a/include/dt-bindings/comphy/comphy_data.h b/include/dt-bindings/comphy/comphy_data.h index a3a6b40..8fd578a 100644 --- a/include/dt-bindings/comphy/comphy_data.h +++ b/include/dt-bindings/comphy/comphy_data.h @@ -42,7 +42,7 @@ #define PHY_TYPE_XAUI3 20 #define PHY_TYPE_RXAUI0 21 #define PHY_TYPE_RXAUI1 22 -#define PHY_TYPE_KR 23 +#define PHY_TYPE_SFI 23 #define PHY_TYPE_MAX 24 #define PHY_TYPE_INVALID 0xff

From: Stefan Roese sr@denx.de

The serdes was always configured in root complex mode. this patch add new entry in device tree (per serdes) which indicates whether the serdes is in end point mode. if so, it skips the root complex configuration.

Signed-off-by: Haim Boot hayim@marvell.com Signed-off-by: Stefan Roese sr@denx.de Signed-off-by: Igal Liberman igall@marvell.com --- drivers/phy/marvell/comphy.h | 1 + drivers/phy/marvell/comphy_core.c | 2 ++ drivers/phy/marvell/comphy_cp110.c | 16 ++++++++++------ 3 files changed, 13 insertions(+), 6 deletions(-)

diff --git a/drivers/phy/marvell/comphy.h b/drivers/phy/marvell/comphy.h index 0a15692..8b05757 100644 --- a/drivers/phy/marvell/comphy.h +++ b/drivers/phy/marvell/comphy.h @@ -86,6 +86,7 @@ struct comphy_map { u32 speed; u32 invert; bool clk_src; + bool end_point; };

struct chip_serdes_phy_config { diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c index ac084a6..db23bef 100644 --- a/drivers/phy/marvell/comphy_core.c +++ b/drivers/phy/marvell/comphy_core.c @@ -166,6 +166,8 @@ static int comphy_probe(struct udevice *dev) blob, subnode, "phy-invert", PHY_POLARITY_NO_INVERT); comphy_map_data[lane].clk_src = fdtdec_get_bool(blob, subnode, "clk-src"); + comphy_map_data[lane].end_point = fdtdec_get_bool(blob, subnode, + "end_point"); if (comphy_map_data[lane].type == PHY_TYPE_INVALID) { printf("no phy type for lane %d, setting lane as unconnected\n", lane + 1); diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index cd3cf96..70554fe 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -87,8 +87,8 @@ static u32 polling_with_timeout(void __iomem *addr, u32 val, return 0; }

-static int comphy_pcie_power_up(u32 lane, u32 pcie_width, - bool clk_src, void __iomem *hpipe_base, +static int comphy_pcie_power_up(u32 lane, u32 pcie_width, bool clk_src, + bool is_end_point, void __iomem *hpipe_base, void __iomem *comphy_base) { u32 mask, data, ret = 1; @@ -109,6 +109,7 @@ static int comphy_pcie_power_up(u32 lane, u32 pcie_width, * and SerDes Lane 0 got PCIe ref-clock #0 */ debug("PCIe clock = %x\n", pcie_clk); + debug("PCIe RC = %d\n", !is_end_point); debug("PCIe width = %d\n", pcie_width);

/* enable PCIe by4 and by2 */ @@ -384,10 +385,12 @@ static int comphy_pcie_power_up(u32 lane, u32 pcie_width, data |= 0x1 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET; reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask);

- /* Set phy in root complex mode */ - mask = HPIPE_CFG_PHY_RC_EP_MASK; - data = 0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET; - reg_set(hpipe_addr + HPIPE_LANE_EQU_CONFIG_0_REG, data, mask); + if (!is_end_point) { + /* Set phy in root complex mode */ + mask = HPIPE_CFG_PHY_RC_EP_MASK; + data = 0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET; + reg_set(hpipe_addr + HPIPE_LANE_EQU_CONFIG_0_REG, data, mask); + }

debug("stage: Comphy power up\n");

@@ -1667,6 +1670,7 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, case PHY_TYPE_PEX3: ret = comphy_pcie_power_up( lane, pcie_width, ptr_comphy_map->clk_src, + serdes_map->end_point, hpipe_base_addr, comphy_base_addr); break; case PHY_TYPE_SATA0:

From: Stefan Roese sr@denx.de

UTMI_PHY_TO_USB_HOST was used in USB3 UTMI dts node only, but there will be USB2 UTMI dts node for some SoCs that have got USB2 controller, so rename TO_USB_HOST to TO_USB3_HOST to distinguish TO_USB2_HOST in later on patches.

Signed-off-by: zachary zhangzg@marvell.com Signed-off-by: Stefan Roese sr@denx.de Signed-off-by: Igal Liberman igall@marvell.com --- arch/arm/dts/armada-cp110-master.dtsi | 4 ++-- arch/arm/dts/armada-cp110-slave.dtsi | 2 +- drivers/phy/marvell/comphy_cp110.c | 5 +++-- include/dt-bindings/comphy/comphy_data.h | 6 +++--- 4 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/arch/arm/dts/armada-cp110-master.dtsi b/arch/arm/dts/armada-cp110-master.dtsi index 229046f..b6c7dc5 100644 --- a/arch/arm/dts/armada-cp110-master.dtsi +++ b/arch/arm/dts/armada-cp110-master.dtsi @@ -253,7 +253,7 @@ reg = <0x580000 0x1000>, /* utmi-unit */ <0x440420 0x4>, /* usb-cfg */ <0x440440 0x4>; /* utmi-cfg */ - utmi-port = <UTMI_PHY_TO_USB_HOST0>; + utmi-port = <UTMI_PHY_TO_USB3_HOST0>; status = "disabled"; };

@@ -262,7 +262,7 @@ reg = <0x581000 0x1000>, /* utmi-unit */ <0x440420 0x4>, /* usb-cfg */ <0x440444 0x4>; /* utmi-cfg */ - utmi-port = <UTMI_PHY_TO_USB_HOST1>; + utmi-port = <UTMI_PHY_TO_USB3_HOST1>; status = "disabled"; };

diff --git a/arch/arm/dts/armada-cp110-slave.dtsi b/arch/arm/dts/armada-cp110-slave.dtsi index 5876391..0cdb3d3 100644 --- a/arch/arm/dts/armada-cp110-slave.dtsi +++ b/arch/arm/dts/armada-cp110-slave.dtsi @@ -254,7 +254,7 @@ reg = <0x580000 0x1000>, /* utmi-unit */ <0x440420 0x4>, /* usb-cfg */ <0x440440 0x4>; /* utmi-cfg */ - utmi-port = <UTMI_PHY_TO_USB_HOST0>; + utmi-port = <UTMI_PHY_TO_USB3_HOST0>; status = "disabled"; }; }; diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index 70554fe..8bec0ab 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -1304,7 +1304,7 @@ static void comphy_utmi_power_down(u32 utmi_index, void __iomem *utmi_base_addr, * If UTMI connected to USB Device, configure mux prior to PHY init * (Device can be connected to UTMI0 or to UTMI1) */ - if (utmi_phy_port == UTMI_PHY_TO_USB_DEVICE0) { + if (utmi_phy_port == UTMI_PHY_TO_USB3_DEVICE0) { debug("stage: UTMI %d - Enable Device mode and configure UTMI mux\n", utmi_index); /* USB3 Device UTMI enable */ @@ -1496,7 +1496,8 @@ static void comphy_utmi_phy_init(u32 utmi_phy_count, continue; } printf("UTMI PHY %d initialized to ", i); - if (cp110_utmi_data[i].utmi_phy_port == UTMI_PHY_TO_USB_DEVICE0) + if (cp110_utmi_data[i].utmi_phy_port == + UTMI_PHY_TO_USB3_DEVICE0) printf("USB Device\n"); else printf("USB Host%d\n", diff --git a/include/dt-bindings/comphy/comphy_data.h b/include/dt-bindings/comphy/comphy_data.h index 8fd578a..d127388 100644 --- a/include/dt-bindings/comphy/comphy_data.h +++ b/include/dt-bindings/comphy/comphy_data.h @@ -52,9 +52,9 @@ #define PHY_POLARITY_ALL_INVERT \ (PHY_POLARITY_TXD_INVERT | PHY_POLARITY_RXD_INVERT)

-#define UTMI_PHY_TO_USB_HOST0 0 -#define UTMI_PHY_TO_USB_HOST1 1 -#define UTMI_PHY_TO_USB_DEVICE0 2 +#define UTMI_PHY_TO_USB3_HOST0 0 +#define UTMI_PHY_TO_USB3_HOST1 1 +#define UTMI_PHY_TO_USB3_DEVICE0 2 #define UTMI_PHY_INVALID 0xff

#endif /* _COMPHY_DATA_H_ */

From: Stefan Roese sr@denx.de

This type tells u-boot to preserve the COMPHY settings as is it is usefull in situations where the COMPHY was initialized by earlier firmware. Note that IGNORE is different from UNCONNECTED since setting UNCONNECTED type will disconnect the COMPHY in the COMPHY MUX which is a desired behaviour

Signed-off-by: Yehuda Yitschak yehuday@marvell.com Signed-off-by: Stefan Roese sr@denx.de Signed-off-by: Igal Liberman igall@marvell.com --- drivers/phy/marvell/comphy_core.c | 2 +- drivers/phy/marvell/comphy_cp110.c | 1 + drivers/phy/marvell/comphy_mux.c | 7 +++++++ include/dt-bindings/comphy/comphy_data.h | 3 ++- 4 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c index db23bef..23e8c4b 100644 --- a/drivers/phy/marvell/comphy_core.c +++ b/drivers/phy/marvell/comphy_core.c @@ -37,7 +37,7 @@ static char *get_type_string(u32 type) "SGMII1", "SGMII2", "SGMII3", "QSGMII", "USB3_HOST0", "USB3_HOST1", "USB3_DEVICE", "XAUI0", "XAUI1", "XAUI2", "XAUI3", - "RXAUI0", "RXAUI1", "SFI"}; + "RXAUI0", "RXAUI1", "SFI", "IGNORE"};

if (type < 0 || type > PHY_TYPE_MAX) return "invalid"; diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index 8bec0ab..499aa68 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -1663,6 +1663,7 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, } switch (ptr_comphy_map->type) { case PHY_TYPE_UNCONNECTED: + case PHY_TYPE_IGNORE: continue; break; case PHY_TYPE_PEX0: diff --git a/drivers/phy/marvell/comphy_mux.c b/drivers/phy/marvell/comphy_mux.c index 1dc7426..b036fb1 100644 --- a/drivers/phy/marvell/comphy_mux.c +++ b/drivers/phy/marvell/comphy_mux.c @@ -27,6 +27,10 @@ static void comphy_mux_check_config(struct comphy_mux_data *mux_data,

for (lane = 0; lane < comphy_max_lanes; lane++, comphy_map_data++, mux_data++) { + /* Don't check ignored COMPHYs */ + if (comphy_map_data->type == PHY_TYPE_IGNORE) + continue; + mux_opt = mux_data->mux_values; for (opt = 0, valid = 0; opt < mux_data->max_lane_values; opt++, mux_opt++) { @@ -83,6 +87,9 @@ static void comphy_mux_reg_write(struct comphy_mux_data *mux_data,

for (lane = 0; lane < comphy_max_lanes; lane++, comphy_map_data++, mux_data++) { + if (comphy_map_data->type == PHY_TYPE_IGNORE) + continue; + offset = lane * bitcount; mask = (((1 << bitcount) - 1) << offset); value = (comphy_mux_get_mux_value(mux_data, diff --git a/include/dt-bindings/comphy/comphy_data.h b/include/dt-bindings/comphy/comphy_data.h index d127388..5eb32ef 100644 --- a/include/dt-bindings/comphy/comphy_data.h +++ b/include/dt-bindings/comphy/comphy_data.h @@ -43,7 +43,8 @@ #define PHY_TYPE_RXAUI0 21 #define PHY_TYPE_RXAUI1 22 #define PHY_TYPE_SFI 23 -#define PHY_TYPE_MAX 24 +#define PHY_TYPE_IGNORE 24 +#define PHY_TYPE_MAX 25 #define PHY_TYPE_INVALID 0xff

#define PHY_POLARITY_NO_INVERT 0

From: Stefan Roese sr@denx.de

This patch fixes the following: 1. KR/SFI on lane #4 mux selector is 0x2 and not 0x1 2. Comment typo

Signed-off-by: Rabeeh Khoury rabeeh@solid-run.com Signed-off-by: Stefan Roese sr@denx.de Signed-off-by: Igal Liberman igall@marvell.com --- drivers/phy/marvell/comphy_cp110.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index 499aa68..e90a913 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -49,7 +49,7 @@ struct comphy_mux_data cp110_comphy_phy_mux_data[] = { {PHY_TYPE_SFI, 0x1}, {PHY_TYPE_XAUI1, 0x1}, {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SATA1, 0x4} } }, {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, /* Lane 4 */ - {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_SFI, 0x1}, + {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_SFI, 0x2}, {PHY_TYPE_SGMII2, 0x1}, {PHY_TYPE_XAUI2, 0x1} } }, {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_XAUI1, 0x1}, /* Lane 5 */ {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SGMII3, 0x1}, @@ -1718,7 +1718,7 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, } if (ret == 0) { /* - * If interface wans't initialiuzed, set the lane to + * If interface wans't initialized, set the lane to * PHY_TYPE_UNCONNECTED state. */ ptr_comphy_map->type = PHY_TYPE_UNCONNECTED;

From: Igal Liberman igall@marvell.com

Add SATA analog parameters initialization values according to latest ETP.

Signed-off-by: Konstantin Porotchkin kostap@marvell.com Signed-off-by: Stefan Roese sr@denx.de Signed-off-by: Igal Liberman igall@marvell.com --- drivers/phy/marvell/comphy_cp110.c | 188 ++++++++++++++++++++++++++++++++++--- drivers/phy/marvell/comphy_hpipe.h | 179 +++++++++++++++++++++++++++++++---- 2 files changed, 336 insertions(+), 31 deletions(-)

diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index e90a913..a4dddb8 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -360,15 +360,15 @@ static int comphy_pcie_power_up(u32 lane, u32 pcie_width, bool clk_src, reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);

/* Configure initial and final coefficient value for receiver */ - mask = HPIPE_G3_RX_SELMUPI_MASK; - data = 0x1 << HPIPE_G3_RX_SELMUPI_OFFSET; + mask = HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK; + data = 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET;

- mask |= HPIPE_G3_RX_SELMUPF_MASK; - data |= 0x1 << HPIPE_G3_RX_SELMUPF_OFFSET; + mask |= HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK; + data |= 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET;

- mask |= HPIPE_G3_SETTING_BIT_MASK; - data |= 0x0 << HPIPE_G3_SETTING_BIT_OFFSET; - reg_set(hpipe_addr + HPIPE_G3_SETTINGS_1_REG, data, mask); + mask |= HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK; + data |= 0x0 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET; + reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask);

/* Trigger sampler enable pulse */ mask = HPIPE_SMAPLER_MASK; @@ -693,10 +693,176 @@ static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base, 0x2 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK);

debug("stage: Analog paramters from ETP(HW)\n"); - /* - * TODO: Set analog paramters from ETP(HW) - for now use the - * default datas - */ + /* Set analog parameters from ETP(HW) */ + /* G1 settings */ + mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; + data = 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; + mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; + data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; + mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK; + data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET; + mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK; + data |= 0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET; + mask |= HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK; + data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET; + reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); + + mask = HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK; + data = 0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET; + mask |= HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK; + data |= 0x2 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET; + mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK; + data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET; + mask |= HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK; + data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET; + mask |= HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK; + data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET; + reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); + + /* G2 settings */ + mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK; + data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET; + mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK; + data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET; + mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK; + data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET; + mask |= HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK; + data |= 0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET; + mask |= HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK; + data |= 0x1 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET; + reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask); + + /* G3 settings */ + mask = HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK; + data = 0x2 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET; + mask |= HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK; + data |= 0x2 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET; + mask |= HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK; + data |= 0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET; + mask |= HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK; + data |= 0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET; + mask |= HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK; + data |= 0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET; + mask |= HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK; + data |= 0x2 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET; + mask |= HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK; + data |= 0x0 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET; + reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask); + + /* DTL Control */ + mask = HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK; + data = 0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET; + mask |= HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK; + data |= 0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET; + mask |= HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; + data |= 0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; + mask |= HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK; + data |= 0x1 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET; + mask |= HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK; + data |= 0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET; + mask |= HPIPE_PWR_CTR_DTL_CLK_MODE_MASK; + data |= 0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET; + mask |= HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK; + data |= 0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET; + reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); + + /* Trigger sampler enable pulse (by toggleing the bit) */ + mask = HPIPE_SMAPLER_MASK; + data = 0x1 << HPIPE_SMAPLER_OFFSET; + reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); + mask = HPIPE_SMAPLER_MASK; + data = 0x0 << HPIPE_SMAPLER_OFFSET; + reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); + + /* VDD Calibration Control 3 */ + mask = HPIPE_EXT_SELLV_RXSAMPL_MASK; + data = 0x10 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET; + reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); + + /* DFE Resolution Control */ + mask = HPIPE_DFE_RES_FORCE_MASK; + data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET; + reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); + + /* DFE F3-F5 Coefficient Control */ + mask = HPIPE_DFE_F3_F5_DFE_EN_MASK; + data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET; + mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK; + data = 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET; + reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); + + /* G3 Setting 3 */ + mask = HPIPE_G3_FFE_CAP_SEL_MASK; + data = 0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET; + mask |= HPIPE_G3_FFE_RES_SEL_MASK; + data |= 0x4 << HPIPE_G3_FFE_RES_SEL_OFFSET; + mask |= HPIPE_G3_FFE_SETTING_FORCE_MASK; + data |= 0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET; + mask |= HPIPE_G3_FFE_DEG_RES_LEVEL_MASK; + data |= 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET; + mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK; + data |= 0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET; + reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask); + + /* G3 Setting 4 */ + mask = HPIPE_G3_DFE_RES_MASK; + data = 0x2 << HPIPE_G3_DFE_RES_OFFSET; + reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask); + + /* Offset Phase Control */ + mask = HPIPE_OS_PH_OFFSET_MASK; + data = 0x5c << HPIPE_OS_PH_OFFSET_OFFSET; + mask |= HPIPE_OS_PH_OFFSET_FORCE_MASK; + data |= 0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET; + reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); + mask = HPIPE_OS_PH_VALID_MASK; + data = 0x1 << HPIPE_OS_PH_VALID_OFFSET; + reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); + mask = HPIPE_OS_PH_VALID_MASK; + data = 0x0 << HPIPE_OS_PH_VALID_OFFSET; + reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); + + /* Set G1 TX amplitude and TX post emphasis value */ + mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK; + data = 0x8 << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET; + mask |= HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK; + data |= 0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET; + mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK; + data |= 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET; + mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK; + data |= 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET; + reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask); + + /* Set G2 TX amplitude and TX post emphasis value */ + mask = HPIPE_G2_SET_0_G2_TX_AMP_MASK; + data = 0xa << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET; + mask |= HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK; + data |= 0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET; + mask |= HPIPE_G2_SET_0_G2_TX_EMPH1_MASK; + data |= 0x2 << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET; + mask |= HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK; + data |= 0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET; + reg_set(hpipe_addr + HPIPE_G2_SET_0_REG, data, mask); + + /* Set G3 TX amplitude and TX post emphasis value */ + mask = HPIPE_G3_SET_0_G3_TX_AMP_MASK; + data = 0xe << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET; + mask |= HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK; + data |= 0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET; + mask |= HPIPE_G3_SET_0_G3_TX_EMPH1_MASK; + data |= 0x6 << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET; + mask |= HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK; + data |= 0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET; + mask |= HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK; + data |= 0x4 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET; + mask |= HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK; + data |= 0x0 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET; + reg_set(hpipe_addr + HPIPE_G3_SET_0_REG, data, mask); + + /* SERDES External Configuration 2 register */ + mask = SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK; + data = 0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET; + reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask);

/* DFE reset sequence */ reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, diff --git a/drivers/phy/marvell/comphy_hpipe.h b/drivers/phy/marvell/comphy_hpipe.h index 179e910..1857ffd 100644 --- a/drivers/phy/marvell/comphy_hpipe.h +++ b/drivers/phy/marvell/comphy_hpipe.h @@ -49,6 +49,9 @@ #define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET 4 #define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK \ (0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET) +#define SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET 7 +#define SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK \ + (0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET)

#define SD_EXTERNAL_STATUS0_REG 0x18 #define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET 2 @@ -105,9 +108,15 @@ #define HPIPE_G1_SET_0_G1_TX_AMP_OFFSET 1 #define HPIPE_G1_SET_0_G1_TX_AMP_MASK \ (0x1f << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET) +#define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET 6 +#define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK \ + (0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET) #define HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET 7 #define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK \ (0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET) +#define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET 11 +#define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK \ + (0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET)

#define HPIPE_G1_SET_1_REG 0x038 #define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0 @@ -116,22 +125,96 @@ #define HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET 3 #define HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK \ (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET) +#define HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET 6 +#define HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK \ + (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET) +#define HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET 8 +#define HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK \ + (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET) #define HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET 10 #define HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK \ (0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET)

-#define HPIPE_G2_SETTINGS_1_REG 0x040 - -#define HPIPE_G3_SETTINGS_1_REG 0x048 -#define HPIPE_G3_RX_SELMUPI_OFFSET 0 -#define HPIPE_G3_RX_SELMUPI_MASK \ - (0x7 << HPIPE_G3_RX_SELMUPI_OFFSET) -#define HPIPE_G3_RX_SELMUPF_OFFSET 3 -#define HPIPE_G3_RX_SELMUPF_MASK \ - (0x7 << HPIPE_G3_RX_SELMUPF_OFFSET) -#define HPIPE_G3_SETTING_BIT_OFFSET 13 -#define HPIPE_G3_SETTING_BIT_MASK \ - (0x1 << HPIPE_G3_SETTING_BIT_OFFSET) +#define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET 11 +#define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK \ + (0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET) + +#define HPIPE_G2_SET_0_REG 0x3c +#define HPIPE_G2_SET_0_G2_TX_AMP_OFFSET 1 +#define HPIPE_G2_SET_0_G2_TX_AMP_MASK \ + (0x1f << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET) +#define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET 6 +#define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK \ + (0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET) +#define HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET 7 +#define HPIPE_G2_SET_0_G2_TX_EMPH1_MASK \ + (0xf << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET) +#define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET 11 +#define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK \ + (0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET) + +#define HPIPE_G2_SET_1_REG 0x040 +#define HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET 0 +#define HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK \ + (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET) +#define HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET 3 +#define HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK \ + (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET) +#define HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET 6 +#define HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK \ + (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET) +#define HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET 8 +#define HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK \ + (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET) +#define HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET 10 +#define HPIPE_G2_SET_1_G2_RX_DFE_EN_MASK \ + (0x1 << HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET) +#define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET 11 +#define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK \ + (0x3 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET) + +#define HPIPE_G3_SET_0_REG 0x44 +#define HPIPE_G3_SET_0_G3_TX_AMP_OFFSET 1 +#define HPIPE_G3_SET_0_G3_TX_AMP_MASK \ + (0x1f << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET) +#define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET 6 +#define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK \ + (0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET) +#define HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET 7 +#define HPIPE_G3_SET_0_G3_TX_EMPH1_MASK \ + (0xf << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET) +#define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET 11 +#define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK \ + (0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET) +#define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET 12 +#define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK \ + (0x7 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET) +#define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET 15 +#define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK \ + (0x1 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET) + +#define HPIPE_G3_SET_1_REG 0x048 +#define HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET 0 +#define HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK \ + (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET) +#define HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET 3 +#define HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK \ + (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET) +#define HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET 6 +#define HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK \ + (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET) +#define HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET 8 +#define HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK \ + (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET) +#define HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET 10 +#define HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK \ + (0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET) +#define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET 11 +#define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK \ + (0x3 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET) +#define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET 13 +#define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK \ + (0x1 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET)

#define HPIPE_LOOPBACK_REG 0x08c #define HPIPE_LOOPBACK_SEL_OFFSET 1 @@ -166,6 +249,11 @@

#define HPIPE_VTHIMPCAL_CTRL_REG 0x104

+#define HPIPE_VDD_CAL_CTRL_REG 0x114 +#define HPIPE_EXT_SELLV_RXSAMPL_OFFSET 5 +#define HPIPE_EXT_SELLV_RXSAMPL_MASK \ + (0x1f << HPIPE_EXT_SELLV_RXSAMPL_OFFSET) + #define HPIPE_PCIE_REG0 0x120 #define HPIPE_PCIE_IDLE_SYNC_OFFSET 12 #define HPIPE_PCIE_IDLE_SYNC_MASK \ @@ -227,12 +315,39 @@ #define HPIPE_TX_REG1_SLC_EN_MASK \ (0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET)

-#define HPIPE_PWR_CTR_DTL_REG 0x184 -#define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2 -#define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK \ +#define HPIPE_PWR_CTR_DTL_REG 0x184 +#define HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET 0 +#define HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK \ + (0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET) +#define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET 1 +#define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK \ + (0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET) +#define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2 +#define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK \ (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET) - -#define HPIPE_RX_REG3 0x188 +#define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET 4 +#define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK \ + (0x7 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET) +#define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET 10 +#define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK \ + (0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET) +#define HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET 12 +#define HPIPE_PWR_CTR_DTL_CLK_MODE_MASK \ + (0x3 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET) +#define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET 14 +#define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK \ + (1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET) + +#define HPIPE_PHASE_CONTROL_REG 0x188 +#define HPIPE_OS_PH_OFFSET_OFFSET 0 +#define HPIPE_OS_PH_OFFSET_MASK \ + (0x7f << HPIPE_OS_PH_OFFSET_OFFSET) +#define HPIPE_OS_PH_OFFSET_FORCE_OFFSET 7 +#define HPIPE_OS_PH_OFFSET_FORCE_MASK \ + (0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET) +#define HPIPE_OS_PH_VALID_OFFSET 8 +#define HPIPE_OS_PH_VALID_MASK \ + (0x1 << HPIPE_OS_PH_VALID_OFFSET)

#define HPIPE_TX_TRAIN_CTRL_0_REG 0x268 #define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET 15 @@ -291,10 +406,25 @@ #define HPIPE_TX_SWEEP_PRESET_EN_MASK \ (0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET)

-#define HPIPE_G1_SETTINGS_3_REG 0x440 -#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET 9 -#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK \ +#define HPIPE_G1_SETTINGS_3_REG 0x440 +#define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET 0 +#define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK \ + (0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET) +#define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET 4 +#define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK \ + (0x7 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET) +#define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET 7 +#define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK \ + (0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET) +#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET 9 +#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK \ (0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET) +#define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET 12 +#define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK \ + (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET) +#define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET 14 +#define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK \ + (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET)

#define HPIPE_G1_SETTINGS_4_REG 0x444 #define HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET 8 @@ -305,6 +435,15 @@ #define HPIPE_G2_SETTINGS_4_REG 0x44C

#define HPIPE_G3_SETTING_3_REG 0x450 +#define HPIPE_G3_FFE_CAP_SEL_OFFSET 0 +#define HPIPE_G3_FFE_CAP_SEL_MASK \ + (0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET) +#define HPIPE_G3_FFE_RES_SEL_OFFSET 4 +#define HPIPE_G3_FFE_RES_SEL_MASK \ + (0x7 << HPIPE_G3_FFE_RES_SEL_OFFSET) +#define HPIPE_G3_FFE_SETTING_FORCE_OFFSET 7 +#define HPIPE_G3_FFE_SETTING_FORCE_MASK \ + (0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET) #define HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET 12 #define HPIPE_G3_FFE_DEG_RES_LEVEL_MASK \ (0x3 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET)

From: Stefan Roese sr@denx.de

Align PHY selectors register with Armada-CP-110 functional SPEC update all relevant device trees with this change.

Signed-off-by: Hanna Hawa hannah@marvell.com Signed-off-by: Stefan Roese sr@denx.de Signed-off-by: Igal Liberman igall@marvell.com --- arch/arm/dts/armada-7040-db.dts | 2 +- arch/arm/dts/armada-8040-mcbin.dts | 4 ++-- drivers/phy/marvell/comphy_cp110.c | 29 +++++++++++++---------------- 3 files changed, 16 insertions(+), 19 deletions(-)

diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts index 84e0dbd..5fa2876 100644 --- a/arch/arm/dts/armada-7040-db.dts +++ b/arch/arm/dts/armada-7040-db.dts @@ -158,7 +158,7 @@

&cpm_comphy { phy0 { - phy-type = <PHY_TYPE_SGMII2>; + phy-type = <PHY_TYPE_SGMII1>; phy-speed = <PHY_SPEED_1_25G>; };

diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts index dde495a..991ddc0 100644 --- a/arch/arm/dts/armada-8040-mcbin.dts +++ b/arch/arm/dts/armada-8040-mcbin.dts @@ -264,7 +264,7 @@ &cps_comphy { /* * CP1 Serdes Configuration: - * Lane 0: SGMII2 + * Lane 0: SGMII1 * Lane 1: SATA 0 * Lane 2: USB HOST 0 * Lane 3: SATA1 @@ -272,7 +272,7 @@ * Lane 5: SGMII3 */ phy0 { - phy-type = <PHY_TYPE_SGMII2>; + phy-type = <PHY_TYPE_SGMII1>; phy-speed = <PHY_SPEED_1_25G>; }; phy1 { diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index a4dddb8..6a6083b 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -37,23 +37,20 @@ struct utmi_phy_data { * Eth_port_0 that include (SGMII0, XAUI0, RXAUI0, SFI) */ struct comphy_mux_data cp110_comphy_phy_mux_data[] = { - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 0 */ - {PHY_TYPE_XAUI2, 0x1}, {PHY_TYPE_SATA1, 0x4} } }, - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII3, 0x1}, /* Lane 1 */ - {PHY_TYPE_XAUI3, 0x1}, {PHY_TYPE_SATA0, 0x4} } }, + {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII1, 0x1}, /* Lane 0 */ + {PHY_TYPE_SATA1, 0x4} } }, + {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 1 */ + {PHY_TYPE_SATA0, 0x4} } }, {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 2 */ - {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, - {PHY_TYPE_SFI, 0x1}, {PHY_TYPE_SATA0, 0x4} } }, - {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 3 */ - {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, - {PHY_TYPE_SFI, 0x1}, {PHY_TYPE_XAUI1, 0x1}, - {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SATA1, 0x4} } }, - {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, /* Lane 4 */ - {PHY_TYPE_XAUI0, 0x1}, {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_SFI, 0x2}, - {PHY_TYPE_SGMII2, 0x1}, {PHY_TYPE_XAUI2, 0x1} } }, - {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_XAUI1, 0x1}, /* Lane 5 */ - {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SGMII3, 0x1}, - {PHY_TYPE_XAUI3, 0x1}, {PHY_TYPE_SATA1, 0x4} } }, + {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_SFI, 0x1}, + {PHY_TYPE_SATA0, 0x4} } }, + {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, /* Lane 3 */ + {PHY_TYPE_SGMII1, 0x2}, {PHY_TYPE_SATA1, 0x4} } }, + {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 4 */ + {PHY_TYPE_RXAUI0, 0x2}, {PHY_TYPE_SFI, 0x2}, + {PHY_TYPE_SGMII1, 0x2} } }, + {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 5 */ + {PHY_TYPE_RXAUI1, 0x2}, {PHY_TYPE_SATA1, 0x4} } }, };

struct comphy_mux_data cp110_comphy_pipe_mux_data[] = {

From: Igal Liberman igall@marvell.com

This patch adds the option to configure a comphy to 5G XFI mode.

In order to configure the comphy to 5G XFI, update the comphy node in the device-tree: phy2 { phy-type = <PHY_TYPE_SFI>; phy-speed = <PHY_SPEED_5_15625G>; };

Signed-off-by: Igal Liberman igall@marvell.com Signed-off-by: Stefan Roese sr@denx.de --- drivers/phy/marvell/comphy_cp110.c | 44 +++++++++++++++++++++++++++----- drivers/phy/marvell/comphy_hpipe.h | 14 ++++++++++ include/dt-bindings/comphy/comphy_data.h | 9 ++++--- 3 files changed, 56 insertions(+), 11 deletions(-)

diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index 6a6083b..056de83 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -1074,7 +1074,7 @@ static int comphy_sgmii_power_up(u32 lane, u32 sgmii_speed, }

static int comphy_sfi_power_up(u32 lane, void __iomem *hpipe_base, - void __iomem *comphy_base) + void __iomem *comphy_base, u32 speed) { u32 mask, data, ret = 1; void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); @@ -1129,7 +1129,9 @@ static int comphy_sfi_power_up(u32 lane, void __iomem *hpipe_base, debug("stage: Comphy configuration\n"); /* set reference clock */ mask = HPIPE_MISC_ICP_FORCE_MASK; - data = 0x1 << HPIPE_MISC_ICP_FORCE_OFFSET; + data = (speed == PHY_SPEED_5_15625G) ? + (0x0 << HPIPE_MISC_ICP_FORCE_OFFSET) : + (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET); mask |= HPIPE_MISC_REFCLK_SEL_MASK; data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); @@ -1154,6 +1156,19 @@ static int comphy_sfi_power_up(u32 lane, void __iomem *hpipe_base, data = 0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask);

+ /* Transmitter/Receiver Speed Divider Force */ + if (speed == PHY_SPEED_5_15625G) { + mask = HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK; + data = 1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET; + mask |= HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK; + data |= 1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET; + mask |= HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK; + data |= 1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET; + mask |= HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK; + data |= 1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET; + reg_set(hpipe_addr + HPIPE_SPD_DIV_FORCE_REG, data, mask); + } + /* Set analog paramters from ETP(HW) */ debug("stage: Analog paramters from ETP(HW)\n"); /* SERDES External Configuration 2 */ @@ -1165,10 +1180,15 @@ static int comphy_sfi_power_up(u32 lane, void __iomem *hpipe_base, data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET; reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); /* 0xd-G1_Setting_0 */ - mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK; - data = 0x1c << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET; - mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK; - data |= 0xe << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET; + if (speed == PHY_SPEED_5_15625G) { + mask = HPIPE_G1_SET_0_G1_TX_EMPH1_MASK; + data = 0x6 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET; + } else { + mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK; + data = 0x1c << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET; + mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK; + data |= 0xe << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET; + } reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask); /* Genration 1 setting 2 (G1_Setting_2) */ mask = HPIPE_G1_SET_2_G1_TX_EMPH0_MASK; @@ -1214,6 +1234,15 @@ static int comphy_sfi_power_up(u32 lane, void __iomem *hpipe_base, /* Genration 1 setting 3 (G1_Setting_3) */ mask = HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK; data = 0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET; + if (speed == PHY_SPEED_5_15625G) { + /* Force FFE (Feed Forward Equalization) to 5G */ + mask |= HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK; + data |= 0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET; + mask |= HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK; + data |= 0x4 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET; + mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK; + data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET; + } reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);

debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n"); @@ -1867,7 +1896,8 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, break; case PHY_TYPE_SFI: ret = comphy_sfi_power_up(lane, hpipe_base_addr, - comphy_base_addr); + comphy_base_addr, + ptr_comphy_map->speed); break; case PHY_TYPE_RXAUI0: case PHY_TYPE_RXAUI1: diff --git a/drivers/phy/marvell/comphy_hpipe.h b/drivers/phy/marvell/comphy_hpipe.h index 1857ffd..1e294fb 100644 --- a/drivers/phy/marvell/comphy_hpipe.h +++ b/drivers/phy/marvell/comphy_hpipe.h @@ -300,6 +300,20 @@ #define HPIPE_PWR_CTR_SFT_RST_MASK \ (0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET)

+#define HPIPE_SPD_DIV_FORCE_REG 0x154 +#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET 8 +#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK \ + (0x3 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET) +#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET 10 +#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK \ + (0x1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET) +#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET 13 +#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK \ + (0x3 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET) +#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET 15 +#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK \ + (0x1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET) + #define HPIPE_PLLINTP_REG1 0x150

#define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C diff --git a/include/dt-bindings/comphy/comphy_data.h b/include/dt-bindings/comphy/comphy_data.h index 5eb32ef..0983116 100644 --- a/include/dt-bindings/comphy/comphy_data.h +++ b/include/dt-bindings/comphy/comphy_data.h @@ -13,10 +13,11 @@ #define PHY_SPEED_3G 3 #define PHY_SPEED_3_125G 4 #define PHY_SPEED_5G 5 -#define PHY_SPEED_6G 6 -#define PHY_SPEED_6_25G 7 -#define PHY_SPEED_10_3125G 8 -#define PHY_SPEED_MAX 9 +#define PHY_SPEED_5_15625G 6 +#define PHY_SPEED_6G 7 +#define PHY_SPEED_6_25G 8 +#define PHY_SPEED_10_3125G 9 +#define PHY_SPEED_MAX 10 #define PHY_SPEED_INVALID 0xff

#define PHY_TYPE_UNCONNECTED 0

From: Stefan Roese sr@denx.de

The comphy configuration is incorrect. Set the correct values for SGMII.

In addition, remove xaui from the comment as it is not supported.

Signed-off-by: Yoav Gvili ygvili@marvell.com Signed-off-by: Stefan Roese sr@denx.de Signed-off-by: Igal Liberman igall@marvell.com --- drivers/phy/marvell/comphy_cp110.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index 056de83..8ea5df2 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -34,7 +34,7 @@ struct utmi_phy_data { * PIPE selector include USB and PCIe options. * PHY selector include the Ethernet and SATA options, every Ethernet * option has different options, for example: serdes lane2 had option - * Eth_port_0 that include (SGMII0, XAUI0, RXAUI0, SFI) + * Eth_port_0 that include (SGMII0, RXAUI0, SFI) */ struct comphy_mux_data cp110_comphy_phy_mux_data[] = { {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII1, 0x1}, /* Lane 0 */ @@ -46,9 +46,9 @@ struct comphy_mux_data cp110_comphy_phy_mux_data[] = { {PHY_TYPE_SATA0, 0x4} } }, {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, /* Lane 3 */ {PHY_TYPE_SGMII1, 0x2}, {PHY_TYPE_SATA1, 0x4} } }, - {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 4 */ + {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, /* Lane 4 */ {PHY_TYPE_RXAUI0, 0x2}, {PHY_TYPE_SFI, 0x2}, - {PHY_TYPE_SGMII1, 0x2} } }, + {PHY_TYPE_SGMII1, 0x1} } }, {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 5 */ {PHY_TYPE_RXAUI1, 0x2}, {PHY_TYPE_SATA1, 0x4} } }, };

From: Stefan Roese sr@denx.de

since now the COMPHY can also be ignored, we must know the state of the COMPHY. we cannot assume anymore that a missing COMPHY is unconnected.

Signed-off-by: Yehuda Yitschak yehuday@marvell.com Signed-off-by: Stefan Roese sr@denx.de Signed-off-by: Igal Liberman igall@marvell.com --- drivers/phy/marvell/comphy_core.c | 3 --- 1 file changed, 3 deletions(-)

diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c index 23e8c4b..d7b02f4 100644 --- a/drivers/phy/marvell/comphy_core.c +++ b/drivers/phy/marvell/comphy_core.c @@ -90,9 +90,6 @@ void comphy_print(struct chip_serdes_phy_config *chip_cfg,

for (lane = 0; lane < chip_cfg->comphy_lanes_count; lane++, comphy_map_data++) { - if (comphy_map_data->type == PHY_TYPE_UNCONNECTED) - continue; - if (comphy_map_data->speed == PHY_SPEED_INVALID) { printf("Comphy-%d: %-13s\n", lane, get_type_string(comphy_map_data->type));

From: Igal Liberman igall@marvell.com

Add SFI analog parameters initialization values according to latest ETP.

Signed-off-by: Igal Liberman igall@marvell.com --- drivers/phy/marvell/comphy_cp110.c | 88 +++++++++++++++++++++++++++++++++++--- drivers/phy/marvell/comphy_hpipe.h | 40 +++++++++++++++++ 2 files changed, 121 insertions(+), 7 deletions(-)

diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index 8ea5df2..21de90c 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -1166,8 +1166,11 @@ static int comphy_sfi_power_up(u32 lane, void __iomem *hpipe_base, data |= 1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET; mask |= HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK; data |= 1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET; - reg_set(hpipe_addr + HPIPE_SPD_DIV_FORCE_REG, data, mask); + } else { + mask = HPIPE_TXDIGCK_DIV_FORCE_MASK; + data = 0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET; } + reg_set(hpipe_addr + HPIPE_SPD_DIV_FORCE_REG, data, mask);

/* Set analog paramters from ETP(HW) */ debug("stage: Analog paramters from ETP(HW)\n"); @@ -1213,13 +1216,27 @@ static int comphy_sfi_power_up(u32 lane, void __iomem *hpipe_base, data = 0 << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET; reg_set(hpipe_addr + HPIPE_G1_SETTING_5_REG, data, mask); /* 0xE-G1_Setting_1 */ - mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; - data = 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; - mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; - data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; - mask |= HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK; - data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET; + mask = HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK; + data = 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET; + if (speed == PHY_SPEED_5_15625G) { + mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; + data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; + mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; + data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; + } else { + mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; + data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; + mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; + data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; + mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK; + data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET; + mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK; + data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET; + mask |= HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK; + data |= 0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET; + } reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); + /* 0xA-DFE_Reg3 */ mask = HPIPE_DFE_F3_F5_DFE_EN_MASK; data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET; @@ -1245,6 +1262,63 @@ static int comphy_sfi_power_up(u32 lane, void __iomem *hpipe_base, } reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);

+ /* Connfigure RX training timer */ + mask = HPIPE_RX_TRAIN_TIMER_MASK; + data = 0x13 << HPIPE_RX_TRAIN_TIMER_OFFSET; + reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask); + + /* Enable TX train peak to peak hold */ + mask = HPIPE_TX_TRAIN_P2P_HOLD_MASK; + data = 0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET; + reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask); + + /* Configure TX preset index */ + mask = HPIPE_TX_PRESET_INDEX_MASK; + data = 0x2 << HPIPE_TX_PRESET_INDEX_OFFSET; + reg_set(hpipe_addr + HPIPE_TX_PRESET_INDEX_REG, data, mask); + + /* Disable pattern lock lost timeout */ + mask = HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK; + data = 0x0 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET; + reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask); + + /* Configure TX training pattern and TX training 16bit auto */ + mask = HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK; + data = 0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET; + mask |= HPIPE_TX_TRAIN_PAT_SEL_MASK; + data |= 0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET; + reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask); + + /* Configure Training patten number */ + mask = HPIPE_TRAIN_PAT_NUM_MASK; + data = 0x88 << HPIPE_TRAIN_PAT_NUM_OFFSET; + reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_0_REG, data, mask); + + /* Configure differencial manchester encoter to ethernet mode */ + mask = HPIPE_DME_ETHERNET_MODE_MASK; + data = 0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET; + reg_set(hpipe_addr + HPIPE_DME_REG, data, mask); + + /* Configure VDD Continuous Calibration */ + mask = HPIPE_CAL_VDD_CONT_MODE_MASK; + data = 0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET; + reg_set(hpipe_addr + HPIPE_VDD_CAL_0_REG, data, mask); + + /* Trigger sampler enable pulse (by toggleing the bit) */ + mask = HPIPE_RX_SAMPLER_OS_GAIN_MASK; + data = 0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET; + mask |= HPIPE_SMAPLER_MASK; + data |= 0x1 << HPIPE_SMAPLER_OFFSET; + reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); + mask = HPIPE_SMAPLER_MASK; + data = 0x0 << HPIPE_SMAPLER_OFFSET; + reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); + + /* Set External RX Regulator Control */ + mask = HPIPE_EXT_SELLV_RXSAMPL_MASK; + data = 0x1A << HPIPE_EXT_SELLV_RXSAMPL_OFFSET; + reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); + debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n"); /* SERDES External Configuration */ mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; diff --git a/drivers/phy/marvell/comphy_hpipe.h b/drivers/phy/marvell/comphy_hpipe.h index 1e294fb..5edd0ad 100644 --- a/drivers/phy/marvell/comphy_hpipe.h +++ b/drivers/phy/marvell/comphy_hpipe.h @@ -254,6 +254,11 @@ #define HPIPE_EXT_SELLV_RXSAMPL_MASK \ (0x1f << HPIPE_EXT_SELLV_RXSAMPL_OFFSET)

+#define HPIPE_VDD_CAL_0_REG 0x108 +#define HPIPE_CAL_VDD_CONT_MODE_OFFSET 15 +#define HPIPE_CAL_VDD_CONT_MODE_MASK \ + (0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET) + #define HPIPE_PCIE_REG0 0x120 #define HPIPE_PCIE_IDLE_SYNC_OFFSET 12 #define HPIPE_PCIE_IDLE_SYNC_MASK \ @@ -301,6 +306,9 @@ (0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET)

#define HPIPE_SPD_DIV_FORCE_REG 0x154 +#define HPIPE_TXDIGCK_DIV_FORCE_OFFSET 7 +#define HPIPE_TXDIGCK_DIV_FORCE_MASK \ + (0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET) #define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET 8 #define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK \ (0x3 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET) @@ -317,6 +325,9 @@ #define HPIPE_PLLINTP_REG1 0x150

#define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C +#define HPIPE_RX_SAMPLER_OS_GAIN_OFFSET 6 +#define HPIPE_RX_SAMPLER_OS_GAIN_MASK \ + (0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET) #define HPIPE_SMAPLER_OFFSET 12 #define HPIPE_SMAPLER_MASK \ (0x1 << HPIPE_SMAPLER_OFFSET) @@ -363,6 +374,21 @@ #define HPIPE_OS_PH_VALID_MASK \ (0x1 << HPIPE_OS_PH_VALID_OFFSET)

+#define HPIPE_FRAME_DETECT_CTRL_0_REG 0x214 +#define HPIPE_TRAIN_PAT_NUM_OFFSET 0x7 +#define HPIPE_TRAIN_PAT_NUM_MASK \ + (0x1FF << HPIPE_TRAIN_PAT_NUM_OFFSET) + +#define HPIPE_FRAME_DETECT_CTRL_3_REG 0x220 +#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET 12 +#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK \ + (0x1 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET) + +#define HPIPE_DME_REG 0x228 +#define HPIPE_DME_ETHERNET_MODE_OFFSET 7 +#define HPIPE_DME_ETHERNET_MODE_MASK \ + (0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET) + #define HPIPE_TX_TRAIN_CTRL_0_REG 0x268 #define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET 15 #define HPIPE_TX_TRAIN_P2P_HOLD_MASK \ @@ -388,6 +414,9 @@ #define HPIPE_PCIE_REG3 0x290

#define HPIPE_TX_TRAIN_CTRL_5_REG 0x2A4 +#define HPIPE_RX_TRAIN_TIMER_OFFSET 0 +#define HPIPE_RX_TRAIN_TIMER_MASK \ + (0x3ff << HPIPE_RX_TRAIN_TIMER_OFFSET) #define HPIPE_TX_TRAIN_START_SQ_EN_OFFSET 11 #define HPIPE_TX_TRAIN_START_SQ_EN_MASK \ (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET) @@ -408,6 +437,12 @@ #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7 #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK \ (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET) +#define HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET 8 +#define HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK \ + (0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET) +#define HPIPE_TX_TRAIN_PAT_SEL_OFFSET 9 +#define HPIPE_TX_TRAIN_PAT_SEL_MASK \ + (0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET)

#define HPIPE_TX_TRAIN_CTRL_11_REG 0x438 #define HPIPE_TX_STATUS_CHECK_MODE_OFFSET 6 @@ -470,6 +505,11 @@ #define HPIPE_G3_DFE_RES_MASK \ (0x3 << HPIPE_G3_DFE_RES_OFFSET)

+#define HPIPE_TX_PRESET_INDEX_REG 0x468 +#define HPIPE_TX_PRESET_INDEX_OFFSET 0 +#define HPIPE_TX_PRESET_INDEX_MASK \ + (0xf << HPIPE_TX_PRESET_INDEX_OFFSET) + #define HPIPE_DFE_CTRL_28_REG 0x49C #define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7 #define HPIPE_DFE_CTRL_28_PIPE4_MASK \

From: Igal Liberman igall@marvell.com

No functional change. The variable name "comphy_index" is misleading, it represents cp index and not comphy index.

Signed-off-by: Igal Liberman igall@marvell.com --- drivers/phy/marvell/comphy.h | 2 +- drivers/phy/marvell/comphy_core.c | 8 ++++---- drivers/phy/marvell/comphy_cp110.c | 6 +++--- 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/phy/marvell/comphy.h b/drivers/phy/marvell/comphy.h index 8b05757..c9b94a4 100644 --- a/drivers/phy/marvell/comphy.h +++ b/drivers/phy/marvell/comphy.h @@ -97,7 +97,7 @@ struct chip_serdes_phy_config { void __iomem *hpipe3_base_addr; u32 comphy_lanes_count; u32 comphy_mux_bitcount; - u32 comphy_index; + u32 cp_index; };

/* Register helper functions */ diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c index d7b02f4..1cf0821 100644 --- a/drivers/phy/marvell/comphy_core.c +++ b/drivers/phy/marvell/comphy_core.c @@ -173,13 +173,13 @@ static int comphy_probe(struct udevice *dev) lane++; }

- /* Save comphy index for MultiCP devices (A8K) */ - chip_cfg->comphy_index = dev->seq; + /* Save CP index for MultiCP devices (A8K) */ + chip_cfg->cp_index = dev->seq; /* PHY power UP sequence */ chip_cfg->ptr_comphy_chip_init(chip_cfg, comphy_map_data); /* PHY print SerDes status */ if (of_machine_is_compatible("marvell,armada8040")) - printf("Comphy chip #%d:\n", chip_cfg->comphy_index); + printf("Comphy chip #%d:\n", chip_cfg->cp_index); comphy_print(chip_cfg, comphy_map_data);

/* @@ -188,7 +188,7 @@ static int comphy_probe(struct udevice *dev) if (of_machine_is_compatible("marvell,armada8040")) last_idx = 1;

- if (chip_cfg->comphy_index == last_idx) { + if (chip_cfg->cp_index == last_idx) { /* Initialize dedicated PHYs (not muxed SerDes lanes) */ comphy_dedicated_phys_init(); } diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index 21de90c..df60571 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -582,7 +582,7 @@ static int comphy_usb3_power_up(u32 lane, void __iomem *hpipe_base, }

static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base, - void __iomem *comphy_base, int comphy_index) + void __iomem *comphy_base, int cp_index) { u32 mask, data, i, ret = 1; void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); @@ -601,7 +601,7 @@ static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base, * In order to parse each CPs SATA node, fdt_node_offset_by_compatible * must be called again (according to the CP id) */ - for (i = 0; i < (comphy_index + 1); i++) + for (i = 0; i < (cp_index + 1); i++) sata_node = fdt_node_offset_by_compatible( gd->fdt_blob, sata_node, "marvell,armada-8k-ahci");

@@ -1947,7 +1947,7 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, case PHY_TYPE_SATA3: ret = comphy_sata_power_up( lane, hpipe_base_addr, comphy_base_addr, - ptr_chip_cfg->comphy_index); + ptr_chip_cfg->cp_index); break; case PHY_TYPE_USB3_HOST0: case PHY_TYPE_USB3_HOST1:

From: Igal Liberman igall@marvell.com

Add PCIE analog parameters initialization values according to latest ETP.

Signed-off-by: Igal Liberman igall@marvell.com --- drivers/phy/marvell/comphy_cp110.c | 66 ++++++++++++++++++++++++++++++++++++-- drivers/phy/marvell/comphy_hpipe.h | 44 ++++++++++++++++++++++++- 2 files changed, 106 insertions(+), 4 deletions(-)

diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index df60571..3ac405a 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -232,6 +232,8 @@ static int comphy_pcie_power_up(u32 lane, u32 pcie_width, bool clk_src, mask |= HPIPE_MISC_REFCLK_SEL_MASK; data |= 0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET; } + mask |= HPIPE_MISC_ICP_FORCE_MASK; + data |= 0x1 << HPIPE_MISC_ICP_FORCE_OFFSET; reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); if (pcie_clk) { /* output */ /* Set reference frequcency select - 0x2 for 25MHz*/ @@ -267,6 +269,9 @@ static int comphy_pcie_power_up(u32 lane, u32 pcie_width, bool clk_src, /* Set Maximal PHY Generation Setting(8Gbps) */ mask = HPIPE_INTERFACE_GEN_MAX_MASK; data = 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET; + /* Bypass frame detection and sync detection for RX DATA */ + mask = HPIPE_INTERFACE_DET_BYPASS_MASK; + data = 0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET; /* Set Link Train Mode (Tx training control pins are used) */ mask |= HPIPE_INTERFACE_LINK_TRAIN_MASK; data |= 0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET; @@ -351,9 +356,9 @@ static int comphy_pcie_power_up(u32 lane, u32 pcie_width, bool clk_src, data = 0x3 << HPIPE_G3_DFE_RES_OFFSET; reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask);

- /* Force DFE resolution (use GEN table value) */ + /* Use TX/RX training result for DFE */ mask = HPIPE_DFE_RES_FORCE_MASK; - data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET; + data = 0x0 << HPIPE_DFE_RES_FORCE_OFFSET; reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);

/* Configure initial and final coefficient value for receiver */ @@ -379,9 +384,64 @@ static int comphy_pcie_power_up(u32 lane, u32 pcie_width, bool clk_src, data = 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET;

mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK; - data |= 0x1 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET; + data |= 0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET; reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask);

+ /* Pattern lock lost timeout disable */ + mask = HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK; + data = 0x0 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET; + reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask); + + /* Configure DFE adaptations */ + mask = HPIPE_CDR_MAX_DFE_ADAPT_1_MASK; + data = 0x1 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET; + mask |= HPIPE_CDR_MAX_DFE_ADAPT_0_MASK; + data |= 0x0 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET; + mask |= HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK; + data |= 0x0 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET; + reg_set(hpipe_addr + HPIPE_CDR_CONTROL_REG, data, mask); + mask = HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK; + data = 0x0 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET; + reg_set(hpipe_addr + HPIPE_DFE_CONTROL_REG, data, mask); + + /* Genration 2 setting 1*/ + mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK; + data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET; + mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK; + data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET; + mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK; + data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET; + reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask); + + /* DFE enable */ + mask = HPIPE_G2_DFE_RES_MASK; + data = 0x3 << HPIPE_G2_DFE_RES_OFFSET; + reg_set(hpipe_addr + HPIPE_G2_SETTINGS_4_REG, data, mask); + + /* Configure DFE Resolution */ + mask = HPIPE_LANE_CFG4_DFE_EN_SEL_MASK; + data = 0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET; + reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask); + + /* VDD calibration control */ + mask = HPIPE_EXT_SELLV_RXSAMPL_MASK; + data = 0x16 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET; + reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); + + /* Set PLL Charge-pump Current Control */ + mask = HPIPE_G3_SETTING_5_G3_ICP_MASK; + data = 0x4 << HPIPE_G3_SETTING_5_G3_ICP_OFFSET; + reg_set(hpipe_addr + HPIPE_G3_SETTING_5_REG, data, mask); + + /* Set lane rqualization remote setting */ + mask = HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK; + data = 0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET; + mask |= HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK; + data |= 0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET; + mask |= HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK; + data |= 0x2 << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET; + reg_set(hpipe_addr + HPIPE_LANE_EQ_REMOTE_SETTING_REG, data, mask); + if (!is_end_point) { /* Set phy in root complex mode */ mask = HPIPE_CFG_PHY_RC_EP_MASK; diff --git a/drivers/phy/marvell/comphy_hpipe.h b/drivers/phy/marvell/comphy_hpipe.h index 5edd0ad..fbceb2a 100644 --- a/drivers/phy/marvell/comphy_hpipe.h +++ b/drivers/phy/marvell/comphy_hpipe.h @@ -227,6 +227,9 @@ #define HPIPE_INTERFACE_GEN_MAX_OFFSET 10 #define HPIPE_INTERFACE_GEN_MAX_MASK \ (0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET) +#define HPIPE_INTERFACE_DET_BYPASS_OFFSET 12 +#define HPIPE_INTERFACE_DET_BYPASS_MASK \ + (0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET) #define HPIPE_INTERFACE_LINK_TRAIN_OFFSET 14 #define HPIPE_INTERFACE_LINK_TRAIN_MASK \ (0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET) @@ -444,6 +447,17 @@ #define HPIPE_TX_TRAIN_PAT_SEL_MASK \ (0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET)

+#define HPIPE_CDR_CONTROL_REG 0x418 +#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET 12 +#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK \ + (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET) +#define HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET 9 +#define HPIPE_CDR_MAX_DFE_ADAPT_0_MASK \ + (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET) +#define HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET 6 +#define HPIPE_CDR_MAX_DFE_ADAPT_1_MASK \ + (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET) + #define HPIPE_TX_TRAIN_CTRL_11_REG 0x438 #define HPIPE_TX_STATUS_CHECK_MODE_OFFSET 6 #define HPIPE_TX_TX_STATUS_CHECK_MODE_MASK \ @@ -481,7 +495,11 @@ (0x3 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET)

#define HPIPE_G2_SETTINGS_3_REG 0x448 -#define HPIPE_G2_SETTINGS_4_REG 0x44C + +#define HPIPE_G2_SETTINGS_4_REG 0x44c +#define HPIPE_G2_DFE_RES_OFFSET 8 +#define HPIPE_G2_DFE_RES_MASK \ + (0x3 << HPIPE_G2_DFE_RES_OFFSET)

#define HPIPE_G3_SETTING_3_REG 0x450 #define HPIPE_G3_FFE_CAP_SEL_OFFSET 0 @@ -510,6 +528,11 @@ #define HPIPE_TX_PRESET_INDEX_MASK \ (0xf << HPIPE_TX_PRESET_INDEX_OFFSET)

+#define HPIPE_DFE_CONTROL_REG 0x470 +#define HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET 14 +#define HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK \ + (0x3 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET) + #define HPIPE_DFE_CTRL_28_REG 0x49C #define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7 #define HPIPE_DFE_CTRL_28_PIPE4_MASK \ @@ -520,6 +543,11 @@ #define HPIPE_G1_SETTING_5_G1_ICP_MASK \ (0xf << HPIPE_G1_SETTING_5_G1_ICP_OFFSET)

+#define HPIPE_G3_SETTING_5_REG 0x548 +#define HPIPE_G3_SETTING_5_G3_ICP_OFFSET 0 +#define HPIPE_G3_SETTING_5_G3_ICP_MASK \ + (0xf << HPIPE_G3_SETTING_5_G3_ICP_OFFSET) + #define HPIPE_LANE_CONFIG0_REG 0x600 #define HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET 0 #define HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK \ @@ -542,6 +570,9 @@ #define HPIPE_LANE_CFG4_DFE_CTRL_OFFSET 0 #define HPIPE_LANE_CFG4_DFE_CTRL_MASK \ (0x7 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET) +#define HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET 3 +#define HPIPE_LANE_CFG4_DFE_EN_SEL_MASK \ + (0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET) #define HPIPE_LANE_CFG4_DFE_OVER_OFFSET 6 #define HPIPE_LANE_CFG4_DFE_OVER_MASK \ (0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET) @@ -559,6 +590,17 @@ #define HPIPE_CFG_UPDATE_POLARITY_MASK \ (0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET)

+#define HPIPE_LANE_EQ_REMOTE_SETTING_REG 0x6f8 +#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET 0 +#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK \ + (0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET) +#define HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET 1 +#define HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK \ + (0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET) +#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET 2 +#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK \ + (0xf << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET) + #define HPIPE_RST_CLK_CTRL_REG 0x704 #define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0 #define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK \