[U-Boot] [PATCH 1/7] x86: qemu: Remove call to vgabios execution
The call to pci_run_vga_bios() is not needed as this is handled in the vesa_fb driver.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
arch/x86/cpu/qemu/pci.c | 19 +------------------ 1 file changed, 1 insertion(+), 18 deletions(-)
diff --git a/arch/x86/cpu/qemu/pci.c b/arch/x86/cpu/qemu/pci.c index 2e94456..8515d10 100644 --- a/arch/x86/cpu/qemu/pci.c +++ b/arch/x86/cpu/qemu/pci.c @@ -6,7 +6,6 @@
#include <common.h> #include <pci.h> -#include <pci_rom.h> #include <asm/pci.h> #include <asm/arch/device.h> #include <asm/arch/qemu.h> @@ -51,11 +50,8 @@ void board_pci_setup_hose(struct pci_controller *hose)
int board_pci_post_scan(struct pci_controller *hose) { - int ret = 0; u16 device, xbcs; int pam, i; - pci_dev_t vga; - ulong start;
/* * i440FX and Q35 chipset have different PAM register offset, but with @@ -96,20 +92,7 @@ int board_pci_post_scan(struct pci_controller *hose) CONFIG_PCIE_ECAM_BASE | BAR_EN); }
- /* - * QEMU emulated graphic card shows in the PCI configuration space with - * PCI vendor id and device id as an artificial pair 0x1234:0x1111. - * It is on PCI bus 0, function 0, but device number is not consistent - * for the two x86 targets it supports. For i440FX and PIIX chipset - * board, it shows as device 2, while for Q35 and ICH9 chipset board, - * it shows as device 1. - */ - vga = i440fx ? I440FX_VGA : Q35_VGA; - start = get_timer(0); - ret = pci_run_vga_bios(vga, NULL, PCI_ROM_USE_NATIVE); - debug("BIOS ran in %lums\n", get_timer(start)); - - return ret; + return 0; }
#ifdef CONFIG_GENERATE_MP_TABLE
Move chipset-specific codes such as PAM init, PCIe ECAM and MP table from pci.c to qemu.c, to prepare for DM PCI conversion.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
arch/x86/cpu/qemu/pci.c | 72 ---------------------------------------- arch/x86/cpu/qemu/qemu.c | 82 ++++++++++++++++++++++++++++++++++++++++++++++ include/configs/qemu-x86.h | 2 ++ 3 files changed, 84 insertions(+), 72 deletions(-)
diff --git a/arch/x86/cpu/qemu/pci.c b/arch/x86/cpu/qemu/pci.c index 8515d10..d50ab75 100644 --- a/arch/x86/cpu/qemu/pci.c +++ b/arch/x86/cpu/qemu/pci.c @@ -6,14 +6,9 @@
#include <common.h> #include <pci.h> -#include <asm/pci.h> -#include <asm/arch/device.h> -#include <asm/arch/qemu.h>
DECLARE_GLOBAL_DATA_PTR;
-static bool i440fx; - void board_pci_setup_hose(struct pci_controller *hose) { hose->first_busno = 0; @@ -50,72 +45,5 @@ void board_pci_setup_hose(struct pci_controller *hose)
int board_pci_post_scan(struct pci_controller *hose) { - u16 device, xbcs; - int pam, i; - - /* - * i440FX and Q35 chipset have different PAM register offset, but with - * the same bitfield layout. Here we determine the offset based on its - * PCI device ID. - */ - device = x86_pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID); - i440fx = (device == PCI_DEVICE_ID_INTEL_82441); - pam = i440fx ? I440FX_PAM : Q35_PAM; - - /* - * Initialize Programmable Attribute Map (PAM) Registers - * - * Configure legacy segments C/D/E/F to system RAM - */ - for (i = 0; i < PAM_NUM; i++) - x86_pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW); - - if (i440fx) { - /* - * Enable legacy IDE I/O ports decode - * - * Note: QEMU always decode legacy IDE I/O port on PIIX chipset. - * However Linux ata_piix driver does sanity check on these two - * registers to see whether legacy ports decode is turned on. - * This is to make Linux ata_piix driver happy. - */ - x86_pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN); - x86_pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN); - - /* Enable I/O APIC */ - xbcs = x86_pci_read_config16(PIIX_ISA, XBCS); - xbcs |= APIC_EN; - x86_pci_write_config16(PIIX_ISA, XBCS, xbcs); - } else { - /* Configure PCIe ECAM base address */ - x86_pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR, - CONFIG_PCIE_ECAM_BASE | BAR_EN); - } - return 0; } - -#ifdef CONFIG_GENERATE_MP_TABLE -int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq) -{ - u8 irq; - - if (i440fx) { - /* - * Not like most x86 platforms, the PIRQ[A-D] on PIIX3 are not - * connected to I/O APIC INTPIN#16-19. Instead they are routed - * to an irq number controled by the PIRQ routing register. - */ - irq = x86_pci_read_config8(PCI_BDF(bus, dev, func), - PCI_INTERRUPT_LINE); - } else { - /* - * ICH9's PIRQ[A-H] are not consecutive numbers from 0 to 7. - * PIRQ[A-D] still maps to [0-3] but PIRQ[E-H] maps to [8-11]. - */ - irq = pirq < 8 ? pirq + 16 : pirq + 12; - } - - return irq; -} -#endif diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c index 7c03e02..84fb082 100644 --- a/arch/x86/cpu/qemu/qemu.c +++ b/arch/x86/cpu/qemu/qemu.c @@ -6,8 +6,58 @@
#include <common.h> #include <asm/irq.h> +#include <asm/pci.h> #include <asm/post.h> #include <asm/processor.h> +#include <asm/arch/device.h> +#include <asm/arch/qemu.h> + +static bool i440fx; + +static void qemu_chipset_init(void) +{ + u16 device, xbcs; + int pam, i; + + /* + * i440FX and Q35 chipset have different PAM register offset, but with + * the same bitfield layout. Here we determine the offset based on its + * PCI device ID. + */ + device = x86_pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID); + i440fx = (device == PCI_DEVICE_ID_INTEL_82441); + pam = i440fx ? I440FX_PAM : Q35_PAM; + + /* + * Initialize Programmable Attribute Map (PAM) Registers + * + * Configure legacy segments C/D/E/F to system RAM + */ + for (i = 0; i < PAM_NUM; i++) + x86_pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW); + + if (i440fx) { + /* + * Enable legacy IDE I/O ports decode + * + * Note: QEMU always decode legacy IDE I/O port on PIIX chipset. + * However Linux ata_piix driver does sanity check on these two + * registers to see whether legacy ports decode is turned on. + * This is to make Linux ata_piix driver happy. + */ + x86_pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN); + x86_pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN); + + /* Enable I/O APIC */ + xbcs = x86_pci_read_config16(PIIX_ISA, XBCS); + xbcs |= APIC_EN; + x86_pci_write_config16(PIIX_ISA, XBCS, xbcs); + } else { + /* Configure PCIe ECAM base address */ + x86_pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR, + CONFIG_PCIE_ECAM_BASE | BAR_EN); + } +}
int arch_cpu_init(void) { @@ -39,7 +89,39 @@ void reset_cpu(ulong addr) x86_full_reset(); }
+int arch_early_init_r(void) +{ + qemu_chipset_init(); + + return 0; +} + int arch_misc_init(void) { return pirq_init(); } + +#ifdef CONFIG_GENERATE_MP_TABLE +int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq) +{ + u8 irq; + + if (i440fx) { + /* + * Not like most x86 platforms, the PIRQ[A-D] on PIIX3 are not + * connected to I/O APIC INTPIN#16-19. Instead they are routed + * to an irq number controled by the PIRQ routing register. + */ + irq = x86_pci_read_config8(PCI_BDF(bus, dev, func), + PCI_INTERRUPT_LINE); + } else { + /* + * ICH9's PIRQ[A-H] are not consecutive numbers from 0 to 7. + * PIRQ[A-D] still maps to [0-3] but PIRQ[E-H] maps to [8-11]. + */ + irq = pirq < 8 ? pirq + 16 : pirq + 12; + } + + return irq; +} +#endif diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86.h index 1b544c1..ac09032 100644 --- a/include/configs/qemu-x86.h +++ b/include/configs/qemu-x86.h @@ -15,6 +15,7 @@
#define CONFIG_SYS_MONITOR_LEN (1 << 20) #define CONFIG_ARCH_MISC_INIT +#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_PCI_MEM_BUS 0xc0000000 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS @@ -28,6 +29,7 @@ #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS #define CONFIG_PCI_IO_SIZE 0xe000
+#define CONFIG_SYS_EARLY_PCI_INIT #define CONFIG_PCI_PNP
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,vga\0" \
On 4 November 2015 at 05:50, Bin Meng bmeng.cn@gmail.com wrote:
Move chipset-specific codes such as PAM init, PCIe ECAM and MP table from pci.c to qemu.c, to prepare for DM PCI conversion.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/cpu/qemu/pci.c | 72 ---------------------------------------- arch/x86/cpu/qemu/qemu.c | 82 ++++++++++++++++++++++++++++++++++++++++++++++ include/configs/qemu-x86.h | 2 ++ 3 files changed, 84 insertions(+), 72 deletions(-)
Acked-by: Simon Glass sjg@chromium.org
Move to driver model for pci on QEMU.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
arch/x86/cpu/qemu/Makefile | 1 - arch/x86/cpu/qemu/pci.c | 49 ---------------------------------------------- configs/qemu-x86_defconfig | 1 + include/configs/qemu-x86.h | 12 ------------ 4 files changed, 1 insertion(+), 62 deletions(-) delete mode 100644 arch/x86/cpu/qemu/pci.c
diff --git a/arch/x86/cpu/qemu/Makefile b/arch/x86/cpu/qemu/Makefile index 1c00d1d..3f3958a 100644 --- a/arch/x86/cpu/qemu/Makefile +++ b/arch/x86/cpu/qemu/Makefile @@ -9,4 +9,3 @@ obj-y += car.o dram.o endif obj-y += qemu.o obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o dsdt.o -obj-$(CONFIG_PCI) += pci.o diff --git a/arch/x86/cpu/qemu/pci.c b/arch/x86/cpu/qemu/pci.c deleted file mode 100644 index d50ab75..0000000 --- a/arch/x86/cpu/qemu/pci.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (C) 2015, Bin Meng bmeng.cn@gmail.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <pci.h> - -DECLARE_GLOBAL_DATA_PTR; - -void board_pci_setup_hose(struct pci_controller *hose) -{ - hose->first_busno = 0; - hose->last_busno = 0; - - /* PCI memory space */ - pci_set_region(hose->regions + 0, - CONFIG_PCI_MEM_BUS, - CONFIG_PCI_MEM_PHYS, - CONFIG_PCI_MEM_SIZE, - PCI_REGION_MEM); - - /* PCI IO space */ - pci_set_region(hose->regions + 1, - CONFIG_PCI_IO_BUS, - CONFIG_PCI_IO_PHYS, - CONFIG_PCI_IO_SIZE, - PCI_REGION_IO); - - pci_set_region(hose->regions + 2, - CONFIG_PCI_PREF_BUS, - CONFIG_PCI_PREF_PHYS, - CONFIG_PCI_PREF_SIZE, - PCI_REGION_PREFETCH); - - pci_set_region(hose->regions + 3, - 0, - 0, - gd->ram_size, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - hose->region_count = 4; -} - -int board_pci_post_scan(struct pci_controller *hose) -{ - return 0; -} diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index f4cc862..62ac76e 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -17,6 +17,7 @@ CONFIG_CPU=y CONFIG_SPI_FLASH=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_DM_PCI=y CONFIG_DM_RTC=y CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86.h index ac09032..32b2271 100644 --- a/include/configs/qemu-x86.h +++ b/include/configs/qemu-x86.h @@ -17,18 +17,6 @@ #define CONFIG_ARCH_MISC_INIT #define CONFIG_ARCH_EARLY_INIT_R
-#define CONFIG_PCI_MEM_BUS 0xc0000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_PREF_BUS 0xd0000000 -#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS -#define CONFIG_PCI_PREF_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x2000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0xe000 - #define CONFIG_SYS_EARLY_PCI_INIT #define CONFIG_PCI_PNP
On 4 November 2015 at 05:50, Bin Meng bmeng.cn@gmail.com wrote:
Move to driver model for pci on QEMU.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/cpu/qemu/Makefile | 1 - arch/x86/cpu/qemu/pci.c | 49 ---------------------------------------------- configs/qemu-x86_defconfig | 1 + include/configs/qemu-x86.h | 12 ------------ 4 files changed, 1 insertion(+), 62 deletions(-) delete mode 100644 arch/x86/cpu/qemu/pci.c
Acked-by: Simon Glass sjg@chromium.org
Move to driver model for USB on QEMU.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
---
configs/qemu-x86_defconfig | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index 62ac76e..7d814d8 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -19,6 +19,8 @@ CONFIG_NETDEVICES=y CONFIG_E1000=y CONFIG_DM_PCI=y CONFIG_DM_RTC=y +CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_111=y
On 4 November 2015 at 05:50, Bin Meng bmeng.cn@gmail.com wrote:
Move to driver model for USB on QEMU.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
configs/qemu-x86_defconfig | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index 62ac76e..7d814d8 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -19,6 +19,8 @@ CONFIG_NETDEVICES=y CONFIG_E1000=y CONFIG_DM_PCI=y CONFIG_DM_RTC=y +CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_111=y -- 1.8.2.1
Acked-by: Simon Glass sjg@chromium.org
These are leftover when converted to use driver model pci.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
include/configs/crownbay.h | 12 ------------ 1 file changed, 12 deletions(-)
diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h index 7f91fff..184169d 100644 --- a/include/configs/crownbay.h +++ b/include/configs/crownbay.h @@ -20,18 +20,6 @@
#define CONFIG_SMSC_LPC47M
-#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x80000000 - -#define CONFIG_PCI_PREF_BUS 0xc0000000 -#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS -#define CONFIG_PCI_PREF_SIZE 0x20000000 - -#define CONFIG_PCI_IO_BUS 0x2000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0xe000 - #define CONFIG_SYS_EARLY_PCI_INIT #define CONFIG_PCI_PNP
On 4 November 2015 at 05:50, Bin Meng bmeng.cn@gmail.com wrote:
These are leftover when converted to use driver model pci.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
include/configs/crownbay.h | 12 ------------ 1 file changed, 12 deletions(-)
Acked-by: Simon Glass sjg@chromium.org
Now that we have converted all x86 boards to use driver model pci, remove these legacy pci codes.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
arch/x86/cpu/pci.c | 45 ------------------------------------------- arch/x86/include/asm/pci.h | 21 -------------------- arch/x86/lib/fsp/fsp_common.c | 5 ----- 3 files changed, 71 deletions(-)
diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c index d2ec45a..7a31260 100644 --- a/arch/x86/cpu/pci.c +++ b/arch/x86/cpu/pci.c @@ -19,51 +19,6 @@
DECLARE_GLOBAL_DATA_PTR;
-static struct pci_controller x86_hose; - -int pci_early_init_hose(struct pci_controller **hosep) -{ - struct pci_controller *hose; - - hose = calloc(1, sizeof(struct pci_controller)); - if (!hose) - return -ENOMEM; - - board_pci_setup_hose(hose); - pci_setup_type1(hose); - hose->last_busno = pci_hose_scan(hose); - gd->hose = hose; - *hosep = hose; - - return 0; -} - -__weak int board_pci_pre_scan(struct pci_controller *hose) -{ - return 0; -} - -__weak int board_pci_post_scan(struct pci_controller *hose) -{ - return 0; -} - -void pci_init_board(void) -{ - struct pci_controller *hose = &x86_hose; - - /* Stop using the early hose */ - gd->hose = NULL; - - board_pci_setup_hose(hose); - pci_setup_type1(hose); - pci_register_hose(hose); - - board_pci_pre_scan(hose); - hose->last_busno = pci_hose_scan(hose); - board_pci_post_scan(hose); -} - static struct pci_controller *get_hose(void) { if (gd->hose) diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h index f7e968e..a2945f1 100644 --- a/arch/x86/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h @@ -25,27 +25,6 @@ struct pci_controller;
void pci_setup_type1(struct pci_controller *hose);
-/** - * board_pci_setup_hose() - Set up the PCI hose - * - * This is called by the common x86 PCI code to set up the PCI controller - * hose. It may be called when no memory/BSS is available so should just - * store things in 'hose' and not in BSS variables. - */ -void board_pci_setup_hose(struct pci_controller *hose); - -/** - * pci_early_init_hose() - Set up PCI host before relocation - * - * This allocates memory for, sets up and returns the PCI hose. It can be - * called before relocation. The hose will be stored in gd->hose for - * later use, but will become invalid one DRAM is available. - */ -int pci_early_init_hose(struct pci_controller **hosep); - -int board_pci_pre_scan(struct pci_controller *hose); -int board_pci_post_scan(struct pci_controller *hose); - /* * Simple PCI access routines - these work from either the early PCI hose * or the 'real' one, created after U-Boot has memory available diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c index c78df94..5276ce6 100644 --- a/arch/x86/lib/fsp/fsp_common.c +++ b/arch/x86/lib/fsp/fsp_common.c @@ -35,11 +35,6 @@ int fsp_init_phase_pci(void) return status ? -EPERM : 0; }
-int board_pci_post_scan(struct pci_controller *hose) -{ - return fsp_init_phase_pci(); -} - void board_final_cleanup(void) { u32 status;
On 4 November 2015 at 05:50, Bin Meng bmeng.cn@gmail.com wrote:
Now that we have converted all x86 boards to use driver model pci, remove these legacy pci codes.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/cpu/pci.c | 45 ------------------------------------------- arch/x86/include/asm/pci.h | 21 -------------------- arch/x86/lib/fsp/fsp_common.c | 5 ----- 3 files changed, 71 deletions(-)
Acked-by: Simon Glass sjg@chromium.org
CONFIG_SYS_EARLY_PCI_INIT is not needed any more since with driver model, PCI enumeration is automatically triggered.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
include/configs/bayleybay.h | 1 - include/configs/crownbay.h | 1 - include/configs/galileo.h | 1 - include/configs/minnowmax.h | 1 - include/configs/qemu-x86.h | 1 - include/configs/som-6896.h | 1 - include/configs/x86-chromebook.h | 1 - 7 files changed, 7 deletions(-)
diff --git a/include/configs/bayleybay.h b/include/configs/bayleybay.h index 1ba2998..b102c68 100644 --- a/include/configs/bayleybay.h +++ b/include/configs/bayleybay.h @@ -16,7 +16,6 @@ #define CONFIG_SYS_MONITOR_LEN (1 << 20) #define CONFIG_ARCH_MISC_INIT
-#define CONFIG_SYS_EARLY_PCI_INIT #define CONFIG_PCI_PNP
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,vga,usbkbd\0" \ diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h index 184169d..54a2905 100644 --- a/include/configs/crownbay.h +++ b/include/configs/crownbay.h @@ -20,7 +20,6 @@
#define CONFIG_SMSC_LPC47M
-#define CONFIG_SYS_EARLY_PCI_INIT #define CONFIG_PCI_PNP
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,vga,usbkbd\0" \ diff --git a/include/configs/galileo.h b/include/configs/galileo.h index ba6c8f1..eb16a5e 100644 --- a/include/configs/galileo.h +++ b/include/configs/galileo.h @@ -21,7 +21,6 @@ /* ns16550 UART is memory-mapped in Quark SoC */ #undef CONFIG_SYS_NS16550_PORT_MAPPED
-#define CONFIG_SYS_EARLY_PCI_INIT #define CONFIG_PCI_PNP
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h index 53d86a2..a20552e 100644 --- a/include/configs/minnowmax.h +++ b/include/configs/minnowmax.h @@ -19,7 +19,6 @@
#define CONFIG_SMSC_LPC47M
-#define CONFIG_SYS_EARLY_PCI_INIT #define CONFIG_PCI_PNP #define CONFIG_RTL8169 #define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \ diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86.h index 32b2271..ecb385c 100644 --- a/include/configs/qemu-x86.h +++ b/include/configs/qemu-x86.h @@ -17,7 +17,6 @@ #define CONFIG_ARCH_MISC_INIT #define CONFIG_ARCH_EARLY_INIT_R
-#define CONFIG_SYS_EARLY_PCI_INIT #define CONFIG_PCI_PNP
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,vga\0" \ diff --git a/include/configs/som-6896.h b/include/configs/som-6896.h index 300e9df..43a9623 100644 --- a/include/configs/som-6896.h +++ b/include/configs/som-6896.h @@ -20,7 +20,6 @@ #define CONFIG_SCSI_DEV_LIST \ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_AHCI}
-#define CONFIG_SYS_EARLY_PCI_INIT #define CONFIG_PCI_PNP
#define VIDEO_IO_OFFSET 0 diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h index 2be8850..b0aa875 100644 --- a/include/configs/x86-chromebook.h +++ b/include/configs/x86-chromebook.h @@ -35,7 +35,6 @@ #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS #define CONFIG_PCI_IO_SIZE 0xefff
-#define CONFIG_SYS_EARLY_PCI_INIT #define CONFIG_PCI_PNP
#define CONFIG_BIOSEMU
On 4 November 2015 at 05:50, Bin Meng bmeng.cn@gmail.com wrote:
CONFIG_SYS_EARLY_PCI_INIT is not needed any more since with driver model, PCI enumeration is automatically triggered.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
include/configs/bayleybay.h | 1 - include/configs/crownbay.h | 1 - include/configs/galileo.h | 1 - include/configs/minnowmax.h | 1 - include/configs/qemu-x86.h | 1 - include/configs/som-6896.h | 1 - include/configs/x86-chromebook.h | 1 - 7 files changed, 7 deletions(-)
Acked-by: Simon Glass sjg@chromium.org
On 4 November 2015 at 05:50, Bin Meng bmeng.cn@gmail.com wrote:
The call to pci_run_vga_bios() is not needed as this is handled in the vesa_fb driver.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/cpu/qemu/pci.c | 19 +------------------ 1 file changed, 1 insertion(+), 18 deletions(-)
Acked-by: Simon Glass sjg@chromium.org
participants (2)
-
Bin Meng -
Simon Glass