From: T Karthik Reddy t.karthik.reddy@xilinx.com

Support has been added for DDR PHY mode in both DLL bypass mode and master DLL mode.

To switch the OSPI controller from SDR to DDR mode, Rx DLL tuning involves adjusting the TX delay, incrementing the RX delay, and verifying correct flash IDs by reading from the flash.

Moreover, support has been extended to enable DDR mode for Micron flash. In the spi_nor_micron_octal_dtr_enable function, the cmd->buf is utilized to read the flash ID during RX DLL tuning.

Signed-off-by: Ashok Reddy Soma ashok.reddy.soma@amd.com Signed-off-by: T Karthik Reddy t.karthik.reddy@xilinx.com Co-developed-by: Tejas Bhumkar tejas.arvind.bhumkar@amd.com Signed-off-by: Tejas Bhumkar tejas.arvind.bhumkar@amd.com --- drivers/mtd/spi/spi-nor-core.c | 50 +++-- drivers/spi/cadence_ospi_versal.c | 25 +++ drivers/spi/cadence_qspi.c | 300 ++++++++++++++++++++++++++++++ drivers/spi/cadence_qspi.h | 50 +++++ drivers/spi/cadence_qspi_apb.c | 33 +++- include/spi.h | 3 + 6 files changed, 436 insertions(+), 25 deletions(-)

diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index faf02c7778..5895b5de09 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -1511,8 +1511,10 @@ static const struct flash_info *spi_nor_read_id(struct spi_nor *nor) info = spi_nor_ids; for (; info->name; info++) { if (info->id_len) { - if (!memcmp(info->id, id, info->id_len)) + if ((!memcmp(info->id, id, info->id_len)) && + memcpy(nor->spi->device_id, id, SPI_NOR_MAX_ID_LEN)) { return info; + } } }

@@ -3944,7 +3946,7 @@ static struct spi_nor_fixups s28hx_t_fixups = { static int spi_nor_micron_octal_dtr_enable(struct spi_nor *nor) { struct spi_mem_op op; - u8 buf; + u8 *buf = nor->cmd_buf; u8 addr_width = 3; int ret;

@@ -3953,12 +3955,12 @@ static int spi_nor_micron_octal_dtr_enable(struct spi_nor *nor) if (ret) return ret;

- buf = 20; + *buf = 20; op = (struct spi_mem_op) SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1), SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_MT_CFR1V, 1), SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(1, &buf, 1)); + SPI_MEM_OP_DATA_OUT(1, buf, 1)); ret = spi_mem_exec_op(nor->spi, &op); if (ret) return ret; @@ -3973,18 +3975,33 @@ static int spi_nor_micron_octal_dtr_enable(struct spi_nor *nor) if (ret) return ret;

- buf = SPINOR_MT_OCT_DTR; + *buf = SPINOR_MT_OCT_DTR; op = (struct spi_mem_op) SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1), SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_MT_CFR0V, 1), SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(1, &buf, 1)); + SPI_MEM_OP_DATA_OUT(1, buf, 1)); ret = spi_mem_exec_op(nor->spi, &op); if (ret) { dev_err(nor->dev, "Failed to enable octal DTR mode\n"); return ret; }

+ /* Read flash ID to make sure the switch was successful. */ + op = (struct spi_mem_op) + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 0), + SPI_MEM_OP_ADDR(0, 0, 0), + SPI_MEM_OP_DUMMY(8, 0), + SPI_MEM_OP_DATA_IN(SPI_NOR_MAX_ID_LEN, buf, 0)); + + spi_nor_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); + + ret = spi_mem_exec_op(nor->spi, &op); + if (ret) + return ret; + + nor->reg_proto = SNOR_PROTO_8_8_8_DTR; + return 0; }

@@ -3996,18 +4013,19 @@ static void mt35xu512aba_default_init(struct spi_nor *nor) static void mt35xu512aba_post_sfdp_fixup(struct spi_nor *nor, struct spi_nor_flash_parameter *params) { - /* Set the Fast Read settings. */ - params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR; - spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_8_8_8_DTR], - 0, 20, SPINOR_OP_MT_DTR_RD, - SNOR_PROTO_8_8_8_DTR); - - params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR; + if (params->hwcaps.mask & SNOR_HWCAPS_READ_8_8_8_DTR) { + /* Set the Fast Read settings. */ + params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR; + spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_8_8_8_DTR], + 0, 20, SPINOR_OP_MT_DTR_RD, + SNOR_PROTO_8_8_8_DTR);

- nor->cmd_ext_type = SPI_NOR_EXT_REPEAT; - params->rdsr_dummy = 8; - params->rdsr_addr_nbytes = 0; + params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR;

+ nor->cmd_ext_type = SPI_NOR_EXT_REPEAT; + params->rdsr_dummy = 8; + params->rdsr_addr_nbytes = 0; + } /* * The BFPT quad enable field is set to a reserved value so the quad * enable function is ignored by spi_nor_parse_bfpt(). Make sure we diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c index c2be307f1d..70682490e6 100644 --- a/drivers/spi/cadence_ospi_versal.c +++ b/drivers/spi/cadence_ospi_versal.c @@ -15,6 +15,7 @@ #include <cpu_func.h> #include <zynqmp_firmware.h> #include <asm/arch/hardware.h> +#include <soc.h> #include "cadence_qspi.h" #include <dt-bindings/power/xlnx-versal-power.h>

@@ -126,6 +127,30 @@ int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_priv *priv) return 0; }

+static const struct soc_attr matches[] = { + { .family = "Versal", .revision = "v2" }, + { } +}; + +/* + * cadence_qspi_versal_set_dll_mode checks for silicon version + * and set the DLL mode. + * Returns 0 in case of success, -ENOTSUPP in case of failure. + */ +int cadence_qspi_versal_set_dll_mode(struct udevice *dev) +{ + struct cadence_spi_priv *priv = dev_get_priv(dev); + const struct soc_attr *attr; + + attr = soc_device_match(matches); + if (attr) { + priv->dll_mode = CQSPI_DLL_MODE_MASTER; + return 0; + } + + return -ENOTSUPP; +} + #if defined(CONFIG_DM_GPIO) int cadence_qspi_versal_flash_reset(struct udevice *dev) { diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index f4593c47b8..0a1257352a 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -194,6 +194,20 @@ static int cadence_spi_set_speed(struct udevice *bus, uint hz) return 0; }

+static int cadence_spi_child_pre_probe(struct udevice *bus) +{ + struct spi_slave *slave = dev_get_parent_priv(bus); + + slave->bytemode = SPI_4BYTE_MODE; + + return 0; +} + +__weak int cadence_qspi_versal_set_dll_mode(struct udevice *dev) +{ + return -ENOTSUPP; +} + static int cadence_spi_probe(struct udevice *bus) { struct cadence_spi_plat *plat = dev_get_plat(bus); @@ -250,6 +264,14 @@ static int cadence_spi_probe(struct udevice *bus) priv->qspi_is_init = 1; }

+ priv->edge_mode = CQSPI_EDGE_MODE_SDR; + priv->dll_mode = CQSPI_DLL_MODE_BYPASS; + + /* Select dll mode */ + ret = cadence_qspi_versal_set_dll_mode(bus); + if (ret == -ENOTSUPP) + debug("DLL mode set to bypass mode : %x\n", ret); + priv->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, priv->ref_clk_hz);

/* Versal and Versal-NET use spi calibration to set read delay */ @@ -293,6 +315,280 @@ static int cadence_spi_set_mode(struct udevice *bus, uint mode) return 0; }

+static int cadence_qspi_rx_dll_tuning(struct spi_slave *spi, const struct spi_mem_op *op, + u32 txtap, u8 extra_dummy) +{ + struct udevice *bus = spi->dev->parent; + struct cadence_spi_priv *priv = dev_get_priv(bus); + void *regbase = priv->regbase; + int ret, i, j; + u8 *id = op->data.buf.in; + u8 min_rxtap = 0, max_rxtap = 0, avg_rxtap, + max_tap, windowsize, dummy_flag = 0, max_index = 0, min_index = 0; + unsigned int reg; + s8 max_windowsize = -1; + bool id_matched, rxtapfound = false; + + /* Return if octal-spi disabled */ + reg = readl(regbase + CQSPI_REG_CONFIG); + reg &= CQSPI_REG_CONFIG_ENABLE; + if (!reg) + return 0; + + max_tap = CQSPI_MAX_DLL_TAPS; + /* + * Rx dll tuning is done by setting tx delay and increment rx + * delay and check for correct flash id's by reading from flash. + */ + for (i = 0; i <= max_tap; i++) { + /* Set DLL reset bit */ + writel((txtap | i | CQSPI_REG_PHY_CONFIG_RESET_FLD_MASK), + regbase + CQSPI_REG_PHY_CONFIG); + /* + * Re-synchronisation delay lines to update them + * with values from TX DLL Delay and RX DLL Delay fields + */ + writel((CQSPI_REG_PHY_CONFIG_RESYNC_FLD_MASK | txtap | i | + CQSPI_REG_PHY_CONFIG_RESET_FLD_MASK), + regbase + CQSPI_REG_PHY_CONFIG); + /* Check lock of loopback */ + if (priv->dll_mode == CQSPI_DLL_MODE_MASTER) { + ret = wait_for_bit_le32 + (regbase + CQSPI_REG_DLL_LOWER, + CQSPI_REG_DLL_LOWER_LPBK_LOCK_MASK, 1, + CQSPI_TIMEOUT_MS, 0); + if (ret) { + printf("LOWER_DLL_LOCK bit err: %i\n", ret); + return ret; + } + } + + ret = cadence_qspi_apb_command_read_setup(priv, op); + if (!ret) { + ret = cadence_qspi_apb_command_read(priv, op); + if (ret < 0) { + printf("error %d reading JEDEC ID\n", ret); + return ret; + } + } + + id_matched = true; + for (j = 0; j < op->data.nbytes; j++) { + if (spi->device_id[j] != id[j]) { + id_matched = false; + break; + } + } + + if (id_matched && !rxtapfound) { + if (priv->dll_mode == CQSPI_DLL_MODE_MASTER) { + min_rxtap = + readl(regbase + CQSPI_REG_DLL_OBSVBLE_UPPER) & + CQSPI_REG_DLL_UPPER_RX_FLD_MASK; + max_rxtap = min_rxtap; + max_index = i; + min_index = i; + } else { + min_rxtap = i; + max_rxtap = i; + } + rxtapfound = true; + } + + if (id_matched && rxtapfound) { + if (priv->dll_mode == CQSPI_DLL_MODE_MASTER) { + max_rxtap = + readl(regbase + + CQSPI_REG_DLL_OBSVBLE_UPPER) & + CQSPI_REG_DLL_UPPER_RX_FLD_MASK; + max_index = i; + } else { + max_rxtap = i; + } + } + + if ((!id_matched || i == max_tap) && rxtapfound) { + windowsize = max_rxtap - min_rxtap + 1; + if (windowsize > max_windowsize) { + dummy_flag = extra_dummy; + max_windowsize = windowsize; + if (priv->dll_mode == CQSPI_DLL_MODE_MASTER) + avg_rxtap = (max_index + min_index); + else + avg_rxtap = (max_rxtap + min_rxtap); + avg_rxtap /= 2; + } + + if (windowsize >= 3) + i = max_tap; + + rxtapfound = false; + } + } + + if (!extra_dummy) { + rxtapfound = false; + min_rxtap = 0; + max_rxtap = 0; + } + + if (!dummy_flag) + priv->extra_dummy = false; + + if (max_windowsize < 3) + return -EINVAL; + + return avg_rxtap; +} + +static int cadence_spi_setdlldelay(struct spi_slave *spi, const struct spi_mem_op *op) +{ + struct udevice *bus = spi->dev->parent; + struct cadence_spi_priv *priv = dev_get_priv(bus); + void *regbase = priv->regbase; + u32 txtap; + int ret, rxtap; + u8 extra_dummy; + + ret = wait_for_bit_le32(regbase + CQSPI_REG_CONFIG, + 1 << CQSPI_REG_CONFIG_IDLE_LSB, + 1, CQSPI_TIMEOUT_MS, 0); + if (ret) { + printf("spi_wait_idle error : 0x%x\n", ret); + return ret; + } + + if (priv->dll_mode == CQSPI_DLL_MODE_MASTER) { + /* Drive DLL reset bit to low */ + writel(0, regbase + CQSPI_REG_PHY_CONFIG); + + /* Set initial delay value */ + writel(CQSPI_REG_PHY_INITIAL_DLY, + regbase + CQSPI_REG_PHY_MASTER_CTRL); + /* Set DLL reset bit */ + writel(CQSPI_REG_PHY_CONFIG_RESET_FLD_MASK, + regbase + CQSPI_REG_PHY_CONFIG); + + /* Check for loopback lock */ + ret = wait_for_bit_le32(regbase + CQSPI_REG_DLL_LOWER, + CQSPI_REG_DLL_LOWER_LPBK_LOCK_MASK, + 1, CQSPI_TIMEOUT_MS, 0); + if (ret) { + printf("Loopback lock bit error (%i)\n", ret); + return ret; + } + + /* Re-synchronize slave DLLs */ + writel(CQSPI_REG_PHY_CONFIG_RESET_FLD_MASK, + regbase + CQSPI_REG_PHY_CONFIG); + writel(CQSPI_REG_PHY_CONFIG_RESET_FLD_MASK | + CQSPI_REG_PHY_CONFIG_RESYNC_FLD_MASK, + regbase + CQSPI_REG_PHY_CONFIG); + + txtap = CQSPI_TX_TAP_MASTER << + CQSPI_REG_PHY_CONFIG_TX_DLL_DLY_LSB; + } + + priv->extra_dummy = false; + for (extra_dummy = 0; extra_dummy <= 1; extra_dummy++) { + if (extra_dummy) + priv->extra_dummy = true; + + rxtap = cadence_qspi_rx_dll_tuning(spi, op, txtap, extra_dummy); + if (extra_dummy && rxtap < 0) { + printf("Failed RX dll tuning\n"); + return rxtap; + } + } + debug("RXTAP: %d\n", rxtap); + + writel((txtap | rxtap | CQSPI_REG_PHY_CONFIG_RESET_FLD_MASK), + regbase + CQSPI_REG_PHY_CONFIG); + writel((CQSPI_REG_PHY_CONFIG_RESYNC_FLD_MASK | txtap | rxtap | + CQSPI_REG_PHY_CONFIG_RESET_FLD_MASK), + regbase + CQSPI_REG_PHY_CONFIG); + + if (priv->dll_mode == CQSPI_DLL_MODE_MASTER) { + ret = wait_for_bit_le32(regbase + CQSPI_REG_DLL_LOWER, + CQSPI_REG_DLL_LOWER_LPBK_LOCK_MASK, + 1, CQSPI_TIMEOUT_MS, 0); + if (ret) { + printf("LOWER_DLL_LOCK bit err: %i\n", ret); + return ret; + } + } + + return 0; +} + +static int priv_setup_ddrmode(struct udevice *bus) +{ + struct cadence_spi_priv *priv = dev_get_priv(bus); + void *regbase = priv->regbase; + int ret; + + ret = wait_for_bit_le32(regbase + CQSPI_REG_CONFIG, + 1 << CQSPI_REG_CONFIG_IDLE_LSB, + 1, CQSPI_TIMEOUT_MS, 0); + if (ret) { + printf("spi_wait_idle error : 0x%x\n", ret); + return ret; + } + + /* Disable QSPI */ + cadence_qspi_apb_controller_disable(regbase); + + /* Disable DAC mode */ + if (priv->use_dac_mode) { + clrbits_le32(regbase + CQSPI_REG_CONFIG, + CQSPI_REG_CONFIG_DIRECT); + priv->use_dac_mode = false; + } + + setbits_le32(regbase + CQSPI_REG_CONFIG, + CQSPI_REG_CONFIG_PHY_ENABLE_MASK); + + /* Program POLL_CNT */ + clrsetbits_le32(regbase + CQSPI_REG_WRCOMPLETION, + CQSPI_REG_WRCOMPLETION_POLLCNT_MASK, + CQSPI_REG_WRCOMPLETION_POLLCNT << + CQSPI_REG_WRCOMPLETION_POLLCNY_LSB); + + setbits_le32(regbase + CQSPI_REG_CONFIG, + CQSPI_REG_CONFIG_DTR_PROT_EN_MASK); + + clrsetbits_le32(regbase + CQSPI_REG_RD_DATA_CAPTURE, + (CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK << + CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB), + CQSPI_REG_READCAPTURE_DQS_ENABLE); + + /* Enable QSPI */ + cadence_qspi_apb_controller_enable(regbase); + + return 0; +} + +static int cadence_spi_setup_ddrmode(struct spi_slave *spi, const struct spi_mem_op *op) +{ + struct udevice *bus = spi->dev->parent; + struct cadence_spi_priv *priv = dev_get_priv(bus); + int ret; + + ret = priv_setup_ddrmode(bus); + if (ret) + return ret; + + priv->edge_mode = CQSPI_EDGE_MODE_DDR; + ret = cadence_spi_setdlldelay(spi, op); + if (ret) { + printf("DDR tuning failed with error %d\n", ret); + return ret; + } + priv->ddr_init = 1; + + return 0; +} + static int cadence_spi_mem_exec_op(struct spi_slave *spi, const struct spi_mem_op *op) { @@ -353,6 +649,9 @@ static int cadence_spi_mem_exec_op(struct spi_slave *spi, break; }

+ if (op->cmd.dtr) + err = cadence_spi_setup_ddrmode(spi, op); + return err; }

@@ -469,6 +768,7 @@ U_BOOT_DRIVER(cadence_spi) = { .plat_auto = sizeof(struct cadence_spi_plat), .priv_auto = sizeof(struct cadence_spi_priv), .probe = cadence_spi_probe, + .child_pre_probe = cadence_spi_child_pre_probe, .remove = cadence_spi_remove, .flags = DM_FLAG_OS_PREPARE, }; diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 693474a287..6d7e31da50 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -10,6 +10,7 @@ #include <reset.h> #include <linux/mtd/spi-nor.h> #include <spi-mem.h> +#include <wait_bit.h>

#define CQSPI_IS_ADDR(cmd_len) (cmd_len > 1 ? 1 : 0)

@@ -21,6 +22,8 @@ #define CQSPI_REG_RETRY 10000 #define CQSPI_POLL_IDLE_RETRY 3

+#define CQSPI_TIMEOUT_MS 1000 + /* Transfer mode */ #define CQSPI_INST_TYPE_SINGLE 0 #define CQSPI_INST_TYPE_DUAL 1 @@ -37,6 +40,22 @@ #define CMD_4BYTE_OCTAL_READ 0x7c #define CMD_4BYTE_READ 0x13

+#define CQSPI_TX_TAP_MASTER 0x1E +#define CQSPI_MAX_DLL_TAPS 127 + +#define CQSPI_DLL_MODE_MASTER 0 +#define CQSPI_DLL_MODE_BYPASS 1 + +#define CQSPI_EDGE_MODE_SDR 0 +#define CQSPI_EDGE_MODE_DDR 1 + +#define SILICON_VER_MASK 0xFF +#define SILICON_VER_1 0x10 + +#define CQSPI_READ_ID 0x9F +#define CQSPI_READID_LOOP_MAX 10 +#define TERA_MACRO 1000000000000l + /**************************************************************************** * Controller's configuration and status register (offset from QSPI_BASE) ****************************************************************************/ @@ -69,6 +88,7 @@ #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3 #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F +#define CQSPI_REG_RD_INSTR_DDR_ENABLE BIT(10)

#define CQSPI_REG_WR_INSTR 0x08 #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0 @@ -113,9 +133,14 @@

#define CQSPI_REG_WR_COMPLETION_CTRL 0x38 #define CQSPI_REG_WR_DISABLE_AUTO_POLL BIT(14) +#define CQSPI_REG_WRCOMPLETION 0x38 +#define CQSPI_REG_WRCOMPLETION_POLLCNT_MASK 0xFF0000 +#define CQSPI_REG_WRCOMPLETION_POLLCNY_LSB 16 +#define CQSPI_REG_WRCOMPLETION_POLLCNT 3

#define CQSPI_REG_IRQSTATUS 0x40 #define CQSPI_REG_IRQMASK 0x44 +#define CQSPI_REG_ECO 0x48

#define CQSPI_REG_INDIRECTRD 0x60 #define CQSPI_REG_INDIRECTRD_START BIT(0) @@ -166,7 +191,31 @@ #define CQSPI_REG_OP_EXT_STIG_LSB 0

#define CQSPI_REG_PHY_CONFIG 0xB4 +#define CQSPI_REG_PHY_CONFIG_RESYNC_FLD_MASK 0x80000000 #define CQSPI_REG_PHY_CONFIG_RESET_FLD_MASK 0x40000000 +#define CQSPI_REG_PHY_CONFIG_TX_DLL_DLY_LSB 16 + +#define CQSPI_REG_PHY_MASTER_CTRL 0xB8 +#define CQSPI_REG_PHY_INITIAL_DLY 0x4 +#define CQSPI_REG_DLL_LOWER 0xBC +#define CQSPI_REG_DLL_LOWER_LPBK_LOCK_MASK 0x8000 +#define CQSPI_REG_DLL_LOWER_DLL_LOCK_MASK 0x1 + +#define CQSPI_REG_DLL_OBSVBLE_UPPER 0xC0 +#define CQSPI_REG_DLL_UPPER_RX_FLD_MASK 0x7F + +#define CQSPI_REG_EXT_OP_LOWER 0xE0 +#define CQSPI_REG_EXT_STIG_OP_MASK 0xFF +#define CQSPI_REG_EXT_READ_OP_MASK 0xFF000000 +#define CQSPI_REG_EXT_READ_OP_SHIFT 24 +#define CQSPI_REG_EXT_WRITE_OP_MASK 0xFF0000 +#define CQSPI_REG_EXT_WRITE_OP_SHIFT 16 +#define CQSPI_REG_DMA_SRC_ADDR 0x1000 +#define CQSPI_REG_DMA_DST_ADDR 0x1800 +#define CQSPI_REG_DMA_DST_SIZE 0x1804 +#define CQSPI_REG_DMA_DST_STS 0x1808 +#define CQSPI_REG_DMA_DST_CTRL 0x180C +#define CQSPI_REG_DMA_DST_CTRL_VAL 0xF43FFA00

#define CQSPI_DMA_DST_ADDR_REG 0x1800 #define CQSPI_DMA_DST_SIZE_REG 0x1804 @@ -309,6 +358,7 @@ int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_priv *priv); int cadence_qspi_apb_exec_flash_cmd(void *reg_base, unsigned int reg); int cadence_qspi_versal_flash_reset(struct udevice *dev); ofnode cadence_qspi_get_subnode(struct udevice *dev); +int cadence_qspi_versal_set_dll_mode(struct udevice *dev); void cadence_qspi_apb_enable_linear_mode(bool enable);

#endif /* __CADENCE_QSPI_H__ */ diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index fb90532217..4404b0ba07 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -464,6 +464,9 @@ int cadence_qspi_apb_command_read(struct cadence_spi_priv *priv, unsigned int dummy_clk; u8 opcode;

+ if (priv->dtr) + rxlen = ((rxlen % 2) != 0) ? (rxlen + 1) : rxlen; + if (priv->dtr) opcode = op->cmd.opcode >> 8; else @@ -479,6 +482,9 @@ int cadence_qspi_apb_command_read(struct cadence_spi_priv *priv, if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) return -ENOTSUPP;

+ if (priv->extra_dummy) + dummy_clk++; + if (dummy_clk) reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK) << CQSPI_REG_CMDCTRL_DUMMY_LSB; @@ -555,6 +561,9 @@ int cadence_qspi_apb_command_write(struct cadence_spi_priv *priv, void *reg_base = priv->regbase; u8 opcode;

+ if (priv->dtr) + txlen = ((txlen % 2) != 0) ? (txlen + 1) : txlen; + if (priv->dtr) opcode = op->cmd.opcode >> 8; else @@ -611,7 +620,6 @@ int cadence_qspi_apb_command_write(struct cadence_spi_priv *priv, int cadence_qspi_apb_read_setup(struct cadence_spi_priv *priv, const struct spi_mem_op *op) { - unsigned int reg; unsigned int rd_reg; unsigned int dummy_clk; unsigned int dummy_bytes = op->dummy.nbytes; @@ -649,6 +657,9 @@ int cadence_qspi_apb_read_setup(struct cadence_spi_priv *priv, if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) return -ENOTSUPP;

+ if (priv->extra_dummy) + dummy_clk++; + if (dummy_clk) rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK) << CQSPI_REG_RD_INSTR_DUMMY_LSB; @@ -657,10 +668,10 @@ int cadence_qspi_apb_read_setup(struct cadence_spi_priv *priv, writel(rd_reg, priv->regbase + CQSPI_REG_RD_INSTR);

/* set device size */ - reg = readl(priv->regbase + CQSPI_REG_SIZE); - reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; - reg |= (op->addr.nbytes - 1); - writel(reg, priv->regbase + CQSPI_REG_SIZE); + clrsetbits_le32(priv->regbase + CQSPI_REG_SIZE, + CQSPI_REG_SIZE_ADDRESS_MASK, + op->addr.nbytes - 1); + return 0; }

@@ -830,10 +841,10 @@ int cadence_qspi_apb_write_setup(struct cadence_spi_priv *priv, writel(reg, priv->regbase + CQSPI_REG_WR_COMPLETION_CTRL); }

- reg = readl(priv->regbase + CQSPI_REG_SIZE); - reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; - reg |= (op->addr.nbytes - 1); - writel(reg, priv->regbase + CQSPI_REG_SIZE); + clrsetbits_le32(priv->regbase + CQSPI_REG_SIZE, + CQSPI_REG_SIZE_ADDRESS_MASK, + op->addr.nbytes - 1); + return 0; }

@@ -848,6 +859,10 @@ cadence_qspi_apb_indirect_write_execute(struct cadence_spi_priv *priv, unsigned int write_bytes; int ret;

+ if (priv->edge_mode == CQSPI_EDGE_MODE_DDR && (n_tx % 2) != 0) + n_tx++; + remaining = n_tx; + /* * Use bounce buffer for non 32 bit aligned txbuf to avoid data * aborts diff --git a/include/spi.h b/include/spi.h index ee0f86fd3d..ab51c8428b 100644 --- a/include/spi.h +++ b/include/spi.h @@ -50,6 +50,8 @@ /* Max no. of CS supported per spi device */ #define SPI_CS_CNT_MAX 2

+#define SPI_MEM_DEV_MAX_ID_LEN 6 + /** * struct dm_spi_bus - SPI bus info * @@ -157,6 +159,7 @@ struct spi_slave { unsigned int bus; unsigned int cs; #endif + u8 device_id[SPI_MEM_DEV_MAX_ID_LEN]; uint mode; unsigned int wordlen; unsigned int max_read_size;

From: T Karthik Reddy t.karthik.reddy@xilinx.com

Set cmd, address & data buswidth to octal. Handle dummy clock cycles incase of reads & writes. Convert odd bytes to even bytes lengths in ddr mode, as we cannot rx/tx odd data in ddr mode.

Disable the DMA once the transfer is done to avoid disabling it at other places.

Signed-off-by: T Karthik Reddy t.karthik.reddy@xilinx.com Signed-off-by: Tejas Bhumkar tejas.arvind.bhumkar@amd.com --- drivers/spi/cadence_ospi_versal.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-)

diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c index 30abb7b431..2c5bdd5f26 100644 --- a/drivers/spi/cadence_ospi_versal.c +++ b/drivers/spi/cadence_ospi_versal.c @@ -23,7 +23,7 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, const struct spi_mem_op *op) { u32 reg, ret, rx_rem, n_rx, bytes_to_dma, data; - u8 opcode, addr_bytes, *rxbuf, dummy_cycles; + u8 opcode, addr_bytes, *rxbuf, dummy_cycles, unaligned_byte;

n_rx = op->data.nbytes; rxbuf = op->data.buf.in; @@ -67,13 +67,14 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, writel(CQSPI_REG_INDIRECTRD_DONE, priv->regbase + CQSPI_REG_INDIRECTRD); rxbuf += bytes_to_dma; - }

- if (rx_rem) { + /* Disable DMA on completion */ reg = readl(priv->regbase + CQSPI_REG_CONFIG); reg &= ~CQSPI_REG_CONFIG_ENBL_DMA; writel(reg, priv->regbase + CQSPI_REG_CONFIG); + }

+ if (rx_rem) { reg = readl(priv->regbase + CQSPI_REG_INDIRECTRDSTARTADDR); reg += bytes_to_dma; writel(reg, priv->regbase + CQSPI_REG_CMDADDRESS); @@ -81,10 +82,10 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, addr_bytes = readl(priv->regbase + CQSPI_REG_SIZE) & CQSPI_REG_SIZE_ADDRESS_MASK;

- opcode = CMD_4BYTE_FAST_READ; - dummy_cycles = 8; - writel((dummy_cycles << CQSPI_REG_RD_INSTR_DUMMY_LSB) | opcode, - priv->regbase + CQSPI_REG_RD_INSTR); + opcode = (u8)readl(priv->regbase + CQSPI_REG_RD_INSTR); + if (opcode == CMD_4BYTE_OCTAL_READ && + priv->edge_mode != CQSPI_EDGE_MODE_DDR) + opcode = CMD_4BYTE_FAST_READ;

reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB); @@ -96,7 +97,12 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, CQSPI_REG_RD_INSTR_DUMMY_MASK; reg |= (dummy_cycles & CQSPI_REG_CMDCTRL_DUMMY_MASK) << CQSPI_REG_CMDCTRL_DUMMY_LSB; - reg |= (((rx_rem - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) << + if (priv->edge_mode == CQSPI_EDGE_MODE_DDR && (rx_rem % 2) != 0) + unaligned_byte = 1; + else + unaligned_byte = 0; + reg |= (((rx_rem - 1 + unaligned_byte) & + CQSPI_REG_CMDCTRL_RD_BYTES_MASK) << CQSPI_REG_CMDCTRL_RD_BYTES_LSB); ret = cadence_qspi_apb_exec_flash_cmd(priv->regbase, reg); if (ret)

From: Ashok Reddy Soma ashok.reddy.soma@xilinx.com

This patch cleans up the cadence qspi registers in the init. The register contents may be invalid if this controller is used in previous boot and comes to uboot after a softreset (no power on reset). This may cause issues in uboot.

Signed-off-by: Ashok Reddy Soma ashok.reddy.soma@xilinx.com Signed-off-by: Tejas Bhumkar tejas.arvind.bhumkar@amd.com --- drivers/spi/cadence_qspi_apb.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 7576dacfb0..35a21a2727 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -340,12 +340,34 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_priv *priv) /* Configure the remap address register, no remap */ writel(0, priv->regbase + CQSPI_REG_REMAP);

+ /* Clear instruction read config register */ + writel(0, priv->regbase + CQSPI_REG_RD_INSTR); + + /* Reset the Delay lines */ + writel(CQSPI_REG_PHY_CONFIG_RESET_FLD_MASK, + priv->regbase + CQSPI_REG_PHY_CONFIG); + + reg = readl(priv->regbase + CQSPI_REG_RD_DATA_CAPTURE); + reg &= ~CQSPI_REG_READCAPTURE_DQS_ENABLE; + reg &= ~(CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK + << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB); + writel(reg, priv->regbase + CQSPI_REG_RD_DATA_CAPTURE); + /* Indirect mode configurations */ writel(priv->fifo_depth / 2, priv->regbase + CQSPI_REG_SRAMPARTITION);

/* Disable all interrupts */ writel(0, priv->regbase + CQSPI_REG_IRQMASK);

+ reg = readl(priv->regbase + CQSPI_REG_CONFIG); + reg &= ~CQSPI_REG_CONFIG_DTR_PROT_EN_MASK; + reg &= ~CQSPI_REG_CONFIG_PHY_ENABLE_MASK; + reg &= ~CQSPI_REG_CONFIG_DIRECT; + reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK + << CQSPI_REG_CONFIG_CHIPSELECT_LSB); + + writel(reg, priv->regbase + CQSPI_REG_CONFIG); + cadence_qspi_apb_controller_enable(priv->regbase); }

From: Ashok Reddy Soma ashok.reddy.soma@amd.com

Enable mt35xu512aba_fixups for all mt35 series flashes to work in DTR mode, and return after nor->fixups is updated, otherwise it will get overwritten with macronix_octal_fixups. This flash works in DTR mode only if CONFIG_SPI_FLASH_MT35XU is enabled and SPI_NOR_OCTAL_DTR_READ flag is set in id table.

Additionally, a new flag, "SPI_XFER_SET_DDR," has been introduced to instruct the Ospi controller driver to switch to DDR mode.

Signed-off-by: Ashok Reddy Soma ashok.reddy.soma@amd.com Co-developed-by: Tejas Bhumkar tejas.arvind.bhumkar@amd.com Signed-off-by: Tejas Bhumkar tejas.arvind.bhumkar@amd.com --- drivers/mtd/spi/spi-nor-core.c | 8 +++++++- drivers/spi/cadence_qspi.c | 2 +- include/spi.h | 1 + 3 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 5895b5de09..e8640cbf07 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -3975,6 +3975,7 @@ static int spi_nor_micron_octal_dtr_enable(struct spi_nor *nor) if (ret) return ret;

+ nor->spi->flags |= SPI_XFER_SET_DDR; *buf = SPINOR_MT_OCT_DTR; op = (struct spi_mem_op) SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1), @@ -4302,8 +4303,13 @@ void spi_nor_set_fixups(struct spi_nor *nor) #endif

#ifdef CONFIG_SPI_FLASH_MT35XU - if (!strcmp(nor->info->name, "mt35xu512aba")) + if (!strcmp(nor->info->name, "mt35xu512aba") || + !strcmp(nor->info->name, "mt35xl512aba") || + !strcmp(nor->info->name, "mt35xu01g") || + !strcmp(nor->info->name, "mt35xu02g")) { nor->fixups = &mt35xu512aba_fixups; + return; + } #endif

#if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX) diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index dd6aef9ab5..d312bafd90 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -702,7 +702,7 @@ static int cadence_spi_mem_exec_op(struct spi_slave *spi, break; }

- if (op->cmd.dtr) + if ((spi->flags & SPI_XFER_SET_DDR) && op->cmd.dtr) err = cadence_spi_setup_ddrmode(spi, op);

return err; diff --git a/include/spi.h b/include/spi.h index ab51c8428b..ade30fab73 100644 --- a/include/spi.h +++ b/include/spi.h @@ -172,6 +172,7 @@ struct spi_slave { #define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END) #define SPI_XFER_U_PAGE BIT(4) #define SPI_XFER_STACKED BIT(5) +#define SPI_XFER_SET_DDR BIT(6) /* * Flag indicating that the spi-controller has multi chip select * capability and can assert/de-assert more than one chip select

From: Venkatesh Yadav Abbarapu venkatesh.abbarapu@amd.com

The block protection flags for Gigadevice, Spansion, and ISSI flash memory have been modified. Additionally, new flags for SPI_NOR_OCTAL_DTR_READ and octal DTR page programming have been introduced for Micron OSPI flashes. Furthermore, the flashes mt35xu01g and mt35xu02g have been incorporated into the CONFIG_SPI_FLASH_MT35XU configuration, so that in driver mt35xu512aba_fixups will be applied.

Signed-off-by: Venkatesh Yadav Abbarapu venkatesh.abbarapu@amd.com Signed-off-by: Tejas Bhumkar tejas.arvind.bhumkar@amd.com --- drivers/mtd/spi/spi-nor-ids.c | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-)

diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 4e83b8c94c..f8ef87783e 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -123,9 +123,9 @@ const struct flash_info spi_nor_ids[] = { {INFO("gd25b256", 0xc84019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES) }, {INFO("gd25b512", 0xc8471A, 0, 64 * 1024, 1024, SECT_4K | - SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES | SPI_NOR_HAS_TB)}, {INFO("gd55b01g", 0xc8471B, 0, 64 * 1024, 2048, SECT_4K | - SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES | SPI_NOR_HAS_TB)}, {INFO("gd55b02g", 0xc8471C, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, {INFO("gd25f64", 0xc84317, 0, 64 * 1024, 128, SECT_4K | @@ -218,11 +218,11 @@ const struct flash_info spi_nor_ids[] = { { INFO("is25lp128", 0x9d6018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ) }, { INFO("is25lp256", 0x9d6019, 0, 64 * 1024, 512, - SECT_4K | SPI_NOR_DUAL_READ) }, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_HAS_TB) }, { INFO("is25lp512", 0x9d601a, 0, 64 * 1024, 1024, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_TB) }, { INFO("is25lp01g", 0x9d601b, 0, 64 * 1024, 2048, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_TB) }, { INFO("is25wp008", 0x9d7014, 0, 64 * 1024, 16, SPI_NOR_QUAD_READ) }, { INFO("is25wp016", 0x9d7015, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ) }, { INFO("is25wp032", 0x9d7016, 0, 64 * 1024, 64, @@ -326,11 +326,15 @@ const struct flash_info spi_nor_ids[] = { { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { INFO("mt25ql02g", 0x20ba22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE | SPI_NOR_4B_OPCODES) }, #ifdef CONFIG_SPI_FLASH_MT35XU - { INFO("mt35xl512aba", 0x2c5a1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) }, - { INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) }, + { INFO("mt35xl512aba", 0x2c5a1a, 0, 128 * 1024, 512, + USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP) }, + { INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, + USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP) }, + { INFO6("mt35xu01g", 0x2c5b1b, 0x104100, 128 * 1024, 1024, + USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP) }, + { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, + USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP) }, #endif /* CONFIG_SPI_FLASH_MT35XU */ - { INFO6("mt35xu01g", 0x2c5b1b, 0x104100, 128 * 1024, 1024, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, - { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, #endif #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ /* Spansion/Cypress -- single (large) sector size only, at least @@ -339,8 +343,8 @@ const struct flash_info spi_nor_ids[] = { { INFO("s25sl032p", 0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("s25sl064p", 0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("s25fl256s0", 0x010219, 0x4d00, 256 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, - { INFO("s25fl256s1", 0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, - { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, + { INFO("s25fl256s1", 0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR | SPI_NOR_HAS_TB) }, + { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR | SPI_NOR_HAS_TB) }, { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { INFO("s25fl512s_256k", 0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { INFO("s25fl512s_64k", 0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, @@ -348,7 +352,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("s70fs01gs_256k", 0x010221, 0x4d00, 256 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("s25sl12800", 0x012018, 0x0300, 256 * 1024, 64, 0) }, { INFO("s25sl12801", 0x012018, 0x0301, 64 * 1024, 256, 0) }, - { INFO6("s25fl128s", 0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, + { INFO6("s25fl128s", 0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR | SPI_NOR_HAS_TB) }, { INFO("s25fl129p0", 0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { INFO("s25fl129p1", 0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { INFO("s25sl008a", 0x010213, 0, 64 * 1024, 16, 0) },

From: T Karthik Reddy t.karthik.reddy@xilinx.com

In DDR mode, current default spi_mem_dtr_supports_op() function does not allow mixed DTR operation functionality. So implement cadence specific cadence_spi_mem_dtr_supports_op() function to verifying only the command buswidth and command opcode bytes which satisfies the DTR protocol.

Signed-off-by: T Karthik Reddy t.karthik.reddy@xilinx.com Signed-off-by: Tejas Bhumkar tejas.arvind.bhumkar@amd.com --- drivers/spi/cadence_qspi.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index d312bafd90..f1c8efe59c 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -708,6 +708,21 @@ static int cadence_spi_mem_exec_op(struct spi_slave *spi, return err; }

+static bool cadence_spi_mem_dtr_supports_op(struct spi_slave *slave, + const struct spi_mem_op *op) +{ + /* + * In DTR mode, except op->cmd all other parameters like address, + * dummy and data could be 0. + * So lets only check if the cmd buswidth and number of opcode bytes + * are true for DTR to support. + */ + if (op->cmd.buswidth == 8 && op->cmd.nbytes % 2) + return false; + + return true; +} + static bool cadence_spi_mem_supports_op(struct spi_slave *slave, const struct spi_mem_op *op) { @@ -730,7 +745,7 @@ static bool cadence_spi_mem_supports_op(struct spi_slave *slave, return false;

if (all_true) - return spi_mem_dtr_supports_op(slave, op); + return cadence_spi_mem_dtr_supports_op(slave, op); else return spi_mem_default_supports_op(slave, op); }

From: Ashok Reddy Soma ashok.reddy.soma@xilinx.com

In a dual parallel configuration, halve the read offset. Determine whether the read offset points to the lower or upper flash in a dual stacked configuration and set the corresponding flags accordingly.

Include support for cases where the read involves an odd number of bytes.

Extend support for cross-die reads in flash memory devices that contain multiple dies within them.

Signed-off-by: Ashok Reddy Soma ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com Signed-off-by: Tejas Bhumkar tejas.arvind.bhumkar@amd.com --- drivers/mtd/spi/spi-nor-core.c | 42 ++++++++++++++++++++++++++++++---- include/spi.h | 3 ++- 2 files changed, 39 insertions(+), 6 deletions(-)

diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index e0398a7a29..ffb9a48316 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -1528,11 +1528,9 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, { struct spi_nor *nor = mtd_to_spi_nor(mtd); int ret; - loff_t offset = from; - u32 read_len = 0; - u32 rem_bank_len = 0; - u8 bank; - bool is_ofst_odd = false; + u32 offset = from; + u32 bank_size, stack_shift = 0, read_len = 0, rem_bank_len = 0; + u8 bank, cur_bank, nxt_bank, is_ofst_odd = 0;

dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);

@@ -1565,6 +1563,40 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, } }

+ if (nor->addr_width == 4) { + /* + * Some flash devices like N25Q512 have multiple dies + * in it. Read operation in these devices is bounded + * by its die segment. In a continuous read, across + * multiple dies, when the last byte of the selected + * die segment is read, the next byte read is the + * first byte of the same die segment. This is Die + * cross over issue. So to handle this issue, split + * a read transaction, that spans across multiple + * banks, into one read per bank. Bank size is 16MB + * for single and dual stacked mode and 32MB for dual + * parallel mode. + */ + if (nor->spi && nor->spi->multi_die) { + bank_size = SZ_16M; + if (nor->flags & SNOR_F_HAS_PARALLEL) + bank_size <<= 1; + cur_bank = offset / bank_size; + nxt_bank = (offset + len) / bank_size; + if (cur_bank != nxt_bank) + rem_bank_len = (bank_size * + (cur_bank + 1)) - + offset; + else + rem_bank_len = (mtd->size >> + stack_shift) - + offset; + } else { + rem_bank_len = (mtd->size >> stack_shift) - + offset; + } + } + if (nor->flags & SNOR_F_HAS_PARALLEL) offset /= 2;

diff --git a/include/spi.h b/include/spi.h index ade30fab73..7b6c49cfc5 100644 --- a/include/spi.h +++ b/include/spi.h @@ -166,7 +166,7 @@ struct spi_slave { unsigned int max_write_size; void *memory_map;

- u8 flags; + u32 flags; #define SPI_XFER_BEGIN BIT(0) /* Assert CS before transfer */ #define SPI_XFER_END BIT(1) /* Deassert CS after transfer */ #define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END) @@ -180,6 +180,7 @@ struct spi_slave { */ bool multi_cs_cap; u32 bytemode; + bool multi_die; /* flash with multiple dies */ };

/**

From: T Karthik Reddy t.karthik.reddy@xilinx.com

Some flash devices have multiple dies in it & has die cross over issue. When SPI_NOR_MULTI_DIE flag is set in flash id table use it to enable split reads to avoid above issue. Define SPI_NOR_MULTI_DIE new flag to flash id flags. Remove SPI_FLASH_SPLIT_READ config and related code from the zynq and zynqmp qspi drivers as it is redundant.

Signed-off-by: T Karthik Reddy t.karthik.reddy@xilinx.com Signed-off-by: Ashok Reddy Soma ashok.reddy.soma@xilinx.com Signed-off-by: Tejas Bhumkar tejas.arvind.bhumkar@amd.com --- drivers/mtd/spi/sf_internal.h | 1 + drivers/mtd/spi/spi-nor-core.c | 3 +++ 2 files changed, 4 insertions(+)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 9c09f97ce2..2cbdea60b0 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -70,6 +70,7 @@ struct flash_info { #define SPI_NOR_OCTAL_READ BIT(16) /* Flash supports Octal Read */ #define SPI_NOR_OCTAL_DTR_READ BIT(17) /* Flash supports Octal DTR Read */ #define SPI_NOR_OCTAL_DTR_PP BIT(18) /* Flash supports Octal DTR page program */ +#define SPI_NOR_MULTI_DIE BIT(19) /* Flash has multi dies & need split reads*/ };

extern const struct flash_info spi_nor_ids[]; diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 8a3cff94db..f1dbeb4725 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -4470,6 +4470,9 @@ int spi_nor_scan(struct spi_nor *nor) if (info->flags & SPI_NOR_NO_ERASE) mtd->flags |= MTD_NO_ERASE;

+ if (info->flags & SPI_NOR_MULTI_DIE) + nor->spi->multi_die = true; + nor->page_size = params.page_size; mtd->writebufsize = nor->page_size;

Enable the utilization of mt35xu512aba_fixups for ISSI octal flash to operate in DDR mode.

Signed-off-by: Tejas Bhumkar tejas.arvind.bhumkar@amd.com --- drivers/mtd/spi/spi-nor-core.c | 10 +++++++++- drivers/mtd/spi/spi-nor-ids.c | 4 ++-- 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index f1dbeb4725..27579cbf15 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -3977,7 +3977,7 @@ static struct spi_nor_fixups s28hx_t_fixups = { }; #endif /* CONFIG_SPI_FLASH_S28HX_T */

-#ifdef CONFIG_SPI_FLASH_MT35XU +#if defined(CONFIG_SPI_FLASH_MT35XU) || defined(CONFIG_SPI_FLASH_ISSI) static int spi_nor_micron_octal_dtr_enable(struct spi_nor *nor) { struct spi_mem_op op; @@ -4348,6 +4348,14 @@ void spi_nor_set_fixups(struct spi_nor *nor) } #endif

+#if defined(CONFIG_SPI_FLASH_ISSI) + if (!strcmp(nor->info->name, "is25wx256") || + !strcmp(nor->info->name, "is25lx512")) { + nor->fixups = &mt35xu512aba_fixups; + return; + } +#endif + #if CONFIG_IS_ENABLED(SPI_FLASH_MACRONIX) nor->fixups = &macronix_octal_fixups; #endif /* SPI_FLASH_MACRONIX */ diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index f8ef87783e..c5c46c1a0c 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -239,9 +239,9 @@ const struct flash_info spi_nor_ids[] = { { INFO("is25wp01g", 0x9d701b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("is25wx256", 0x9d5b19, 0, 128 * 1024, 256, - SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, + SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP) }, { INFO("is25lx512", 0x9d5a1a, 0, 64 * 1024, 1024, - SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES | SPI_NOR_HAS_TB) }, + SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES | SPI_NOR_HAS_TB | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP) }, #endif #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ /* Macronix */

Added SFDP fixups for Macronix octal flash, with the requirement of the Invert Dual-byte opcode in Octal DDR mode.

Reference: linux-xlnx@08cf794

Signed-off-by: Tejas Bhumkar tejas.arvind.bhumkar@amd.com --- drivers/mtd/spi/spi-nor-core.c | 49 +++++++++++++++++++++++++++++----- drivers/mtd/spi/spi-nor-ids.c | 2 ++ 2 files changed, 45 insertions(+), 6 deletions(-)

diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 6b396ce681..9c2d70585a 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -4089,18 +4089,18 @@ static int spi_nor_macronix_octal_dtr_enable(struct spi_nor *nor) { struct spi_mem_op op; int ret; - u8 buf; + u8 *buf = nor->cmd_buf;

ret = write_enable(nor); if (ret) return ret;

- buf = SPINOR_REG_MXIC_DC_20; + *buf = SPINOR_REG_MXIC_DC_20; op = (struct spi_mem_op) SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_CR2, 1), SPI_MEM_OP_ADDR(4, SPINOR_REG_MXIC_CR2_DC, 1), SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(1, &buf, 1)); + SPI_MEM_OP_DATA_OUT(1, buf, 1));

ret = spi_mem_exec_op(nor->spi, &op); if (ret) @@ -4115,18 +4115,33 @@ static int spi_nor_macronix_octal_dtr_enable(struct spi_nor *nor) if (ret) return ret;

- buf = SPINOR_REG_MXIC_OPI_DTR_EN; + nor->spi->flags |= SPI_XFER_SET_DDR; + *buf = SPINOR_REG_MXIC_OPI_DTR_EN; op = (struct spi_mem_op) SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_CR2, 1), SPI_MEM_OP_ADDR(4, SPINOR_REG_MXIC_CR2_MODE, 1), SPI_MEM_OP_NO_DUMMY, - SPI_MEM_OP_DATA_OUT(1, &buf, 1)); + SPI_MEM_OP_DATA_OUT(1, buf, 1));

ret = spi_mem_exec_op(nor->spi, &op); if (ret) { dev_err(nor->dev, "Failed to enable octal DTR mode\n"); return ret; } + + /* Read flash ID to make sure the switch was successful. */ + op = (struct spi_mem_op) + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1), + SPI_MEM_OP_ADDR(4, 0, 1), + SPI_MEM_OP_DUMMY(4, 1), + SPI_MEM_OP_DATA_IN(round_up(nor->info->id_len, 2), buf, 1)); + + spi_nor_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); + + ret = spi_mem_exec_op(nor->spi, &op); + if (ret) + return ret; + nor->reg_proto = SNOR_PROTO_8_8_8_DTR;

return 0; @@ -4134,6 +4149,20 @@ static int spi_nor_macronix_octal_dtr_enable(struct spi_nor *nor)

static void macronix_octal_default_init(struct spi_nor *nor) { + u8 id_byte1, id_byte2; + /* + * Macronix Read Id bytes are always output in STR mode. Since tuning + * is based on Read Id command, adjust the Read Id bytes that will + * match the Read Id output in DTR mode. + */ + id_byte1 = nor->spi->device_id[1]; + id_byte2 = nor->spi->device_id[2]; + nor->spi->device_id[1] = nor->spi->device_id[0]; + nor->spi->device_id[2] = id_byte1; + nor->spi->device_id[3] = id_byte1; + nor->spi->device_id[4] = id_byte2; + nor->spi->device_id[5] = id_byte2; + nor->octal_dtr_enable = spi_nor_macronix_octal_dtr_enable; }

@@ -4144,8 +4173,16 @@ static void macronix_octal_post_sfdp_fixup(struct spi_nor *nor, * Adding SNOR_HWCAPS_PP_8_8_8_DTR in hwcaps.mask when * SPI_NOR_OCTAL_DTR_READ flag exists. */ - if (params->hwcaps.mask & SNOR_HWCAPS_READ_8_8_8_DTR) + if (params->hwcaps.mask & SNOR_HWCAPS_READ_8_8_8_DTR) { params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR; + spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_8_8_8_DTR], + 0, 20, SPINOR_OP_MXIC_DTR_RD, + SNOR_PROTO_8_8_8_DTR); + nor->cmd_ext_type = SPI_NOR_EXT_INVERT; + nor->flags |= SNOR_F_IO_MODE_EN_VOLATILE; + params->rdsr_dummy = 8; + params->rdsr_addr_nbytes = 0; + } }

static struct spi_nor_fixups macronix_octal_fixups = { diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 34fba49592..cd3fcda70c 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -275,6 +275,8 @@ const struct flash_info spi_nor_ids[] = { { INFO("mx66l2g45g", 0xc2201c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) }, { INFO("mx25r6435f", 0xc22817, 0, 64 * 1024, 128, SECT_4K) }, + { INFO("mx25um51345g", 0xc2813a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP) }, + { INFO("mx66um2g45g", 0xc2803c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP) }, { INFO("mx66uw2g345gx0", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx66lm1g45g", 0xc2853b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx25lm51245g", 0xc2853a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },