[U-Boot] MII register display
Why is "speed selection = 10 Mbps" when both sides support 100Mb? Is uboot decoding this register correctly?
uboot> mii dump 0 0 0. (1000) -- PHY control register -- (8000:0000) 0.15 = 0 reset (4000:0000) 0.14 = 0 loopback (2040:0000) 0. 6,13 = b00 speed selection = 10 Mbps (1000:1000) 0.12 = 1 A/N enable (0800:0000) 0.11 = 0 power-down (0400:0000) 0.10 = 0 isolate (0200:0000) 0. 9 = 0 restart A/N (0100:0000) 0. 8 = 0 duplex = half (0080:0000) 0. 7 = 0 collision test enable (003f:0000) 0. 5- 0 = 0 (reserved)
Definition from Linux:
/* Basic mode control register. */ #define BMCR_RESV 0x003f /* Unused... */ #define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ #define BMCR_CTST 0x0080 /* Collision test */ #define BMCR_FULLDPLX 0x0100 /* Full duplex */ #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ #define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */ #define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */ #define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ #define BMCR_SPEED100 0x2000 /* Select 100Mbps */ #define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ #define BMCR_RESET 0x8000 /* Reset the DP83840 */
uboot> mii dump 0 1 1. (786d) -- PHY status register -- (8000:0000) 1.15 = 0 100BASE-T4 able (4000:4000) 1.14 = 1 100BASE-X full duplex able (2000:2000) 1.13 = 1 100BASE-X half duplex able (1000:1000) 1.12 = 1 10 Mbps full duplex able (0800:0800) 1.11 = 1 10 Mbps half duplex able (0400:0000) 1.10 = 0 100BASE-T2 full duplex able (0200:0000) 1. 9 = 0 100BASE-T2 half duplex able (0100:0000) 1. 8 = 0 extended status (0080:0000) 1. 7 = 0 (reserved) (0040:0040) 1. 6 = 1 MF preamble suppression (0020:0020) 1. 5 = 1 A/N complete (0010:0000) 1. 4 = 0 remote fault (0008:0008) 1. 3 = 1 A/N able (0004:0004) 1. 2 = 1 link status (0002:0000) 1. 1 = 0 jabber detect (0001:0001) 1. 0 = 1 extended capabilities
uboot> mii dump 0 2 2. (0022) -- PHY ID 1 register -- (ffff:0022) 2.15- 0 = 34 OUI portion
uboot> mii dump 0 3 3. (161a) -- PHY ID 2 register -- (fc00:1400) 3.15-10 = 5 OUI portion (03f0:0210) 3. 9- 4 = 33 manufacturer part number (000f:000a) 3. 3- 0 = 10 manufacturer rev. number
uboot> mii dump 0 4 4. (01e1) -- Autonegotiation advertisement register -- (8000:0000) 4.15 = 0 next page able (4000:0000) 4.14 = 0 reserved (2000:0000) 4.13 = 0 remote fault (1000:0000) 4.12 = 0 reserved (0800:0000) 4.11 = 0 asymmetric pause (0400:0000) 4.10 = 0 pause enable (0200:0000) 4. 9 = 0 100BASE-T4 able (0100:0100) 4. 8 = 1 100BASE-TX full duplex able (0080:0080) 4. 7 = 1 100BASE-TX able (0040:0040) 4. 6 = 1 10BASE-T full duplex able (0020:0020) 4. 5 = 1 10BASE-T able (001f:0001) 4. 4- 0 = 1 selector = IEEE 802.3
uboot> mii dump 0 5 5. (c5e1) -- Autonegotiation partner abilities register -- (8000:8000) 5.15 = 1 next page able (4000:4000) 5.14 = 1 acknowledge (2000:0000) 5.13 = 0 remote fault (1000:0000) 5.12 = 0 (reserved) (0800:0000) 5.11 = 0 asymmetric pause able (0400:0400) 5.10 = 1 pause able (0200:0000) 5. 9 = 0 100BASE-T4 able (0100:0100) 5. 8 = 1 100BASE-X full duplex able (0080:0080) 5. 7 = 1 100BASE-TX able (0040:0040) 5. 6 = 1 10BASE-T full duplex able (0020:0020) 5. 5 = 1 10BASE-T able (001f:0001) 5. 4- 0 = 1 selector = IEEE 802.3
uboot>
On Wed, May 6, 2009 at 2:57 PM, Jon Smirl jonsmirl@gmail.com wrote:
Why is "speed selection = 10 Mbps" when both sides support 100Mb? Is uboot decoding this register correctly?
uboot> mii dump 0 0 0. (1000) -- PHY control register -- (8000:0000) 0.15 = 0 reset (4000:0000) 0.14 = 0 loopback (2040:0000) 0. 6,13 = b00 speed selection = 10 Mbps
This b00 here is confusing. b is a valid hex character, I thought this was reporting the register value as 0xb00. Instead it appears to be trying to indicate that the two bits are binary?
(1000:1000) 0.12 = 1 A/N enable (0800:0000) 0.11 = 0 power-down (0400:0000) 0.10 = 0 isolate (0200:0000) 0. 9 = 0 restart A/N (0100:0000) 0. 8 = 0 duplex = half (0080:0000) 0. 7 = 0 collision test enable (003f:0000) 0. 5- 0 = 0 (reserved)
Definition from Linux:
/* Basic mode control register. */ #define BMCR_RESV 0x003f /* Unused... */ #define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ #define BMCR_CTST 0x0080 /* Collision test */ #define BMCR_FULLDPLX 0x0100 /* Full duplex */ #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ #define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */ #define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */ #define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ #define BMCR_SPEED100 0x2000 /* Select 100Mbps */ #define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ #define BMCR_RESET 0x8000 /* Reset the DP83840 */
uboot> mii dump 0 1
- (786d) -- PHY status register --
(8000:0000) 1.15 = 0 100BASE-T4 able (4000:4000) 1.14 = 1 100BASE-X full duplex able (2000:2000) 1.13 = 1 100BASE-X half duplex able (1000:1000) 1.12 = 1 10 Mbps full duplex able (0800:0800) 1.11 = 1 10 Mbps half duplex able (0400:0000) 1.10 = 0 100BASE-T2 full duplex able (0200:0000) 1. 9 = 0 100BASE-T2 half duplex able (0100:0000) 1. 8 = 0 extended status (0080:0000) 1. 7 = 0 (reserved) (0040:0040) 1. 6 = 1 MF preamble suppression (0020:0020) 1. 5 = 1 A/N complete (0010:0000) 1. 4 = 0 remote fault (0008:0008) 1. 3 = 1 A/N able (0004:0004) 1. 2 = 1 link status (0002:0000) 1. 1 = 0 jabber detect (0001:0001) 1. 0 = 1 extended capabilities
uboot> mii dump 0 2 2. (0022) -- PHY ID 1 register -- (ffff:0022) 2.15- 0 = 34 OUI portion
uboot> mii dump 0 3 3. (161a) -- PHY ID 2 register -- (fc00:1400) 3.15-10 = 5 OUI portion (03f0:0210) 3. 9- 4 = 33 manufacturer part number (000f:000a) 3. 3- 0 = 10 manufacturer rev. number
uboot> mii dump 0 4 4. (01e1) -- Autonegotiation advertisement register -- (8000:0000) 4.15 = 0 next page able (4000:0000) 4.14 = 0 reserved (2000:0000) 4.13 = 0 remote fault (1000:0000) 4.12 = 0 reserved (0800:0000) 4.11 = 0 asymmetric pause (0400:0000) 4.10 = 0 pause enable (0200:0000) 4. 9 = 0 100BASE-T4 able (0100:0100) 4. 8 = 1 100BASE-TX full duplex able (0080:0080) 4. 7 = 1 100BASE-TX able (0040:0040) 4. 6 = 1 10BASE-T full duplex able (0020:0020) 4. 5 = 1 10BASE-T able (001f:0001) 4. 4- 0 = 1 selector = IEEE 802.3
uboot> mii dump 0 5 5. (c5e1) -- Autonegotiation partner abilities register -- (8000:8000) 5.15 = 1 next page able (4000:4000) 5.14 = 1 acknowledge (2000:0000) 5.13 = 0 remote fault (1000:0000) 5.12 = 0 (reserved) (0800:0000) 5.11 = 0 asymmetric pause able (0400:0400) 5.10 = 1 pause able (0200:0000) 5. 9 = 0 100BASE-T4 able (0100:0100) 5. 8 = 1 100BASE-X full duplex able (0080:0080) 5. 7 = 1 100BASE-TX able (0040:0040) 5. 6 = 1 10BASE-T full duplex able (0020:0020) 5. 5 = 1 10BASE-T able (001f:0001) 5. 4- 0 = 1 selector = IEEE 802.3
uboot>
-- Jon Smirl jonsmirl@gmail.com
On Wednesday 06 May 2009 21:53:21 Jon Smirl wrote:
On Wed, May 6, 2009 at 2:57 PM, Jon Smirl jonsmirl@gmail.com wrote:
Why is "speed selection = 10 Mbps" when both sides support 100Mb? Is uboot decoding this register correctly?
uboot> mii dump 0 0 0. (1000) -- PHY control register -- (8000:0000) 0.15 = 0 reset (4000:0000) 0.14 = 0 loopback (2040:0000) 0. 6,13 = b00 speed selection = 10 Mbps
This b00 here is confusing. b is a valid hex character, I thought this was reporting the register value as 0xb00. Instead it appears to be trying to indicate that the two bits are binary?
looks that way. it's showing bit6 and bit13. -mike
On Wed, May 6, 2009 at 10:03 PM, Mike Frysinger vapier@gentoo.org wrote:
On Wednesday 06 May 2009 21:53:21 Jon Smirl wrote:
On Wed, May 6, 2009 at 2:57 PM, Jon Smirl jonsmirl@gmail.com wrote:
Why is "speed selection = 10 Mbps" when both sides support 100Mb? Is uboot decoding this register correctly?
uboot> mii dump 0 0 0. (1000) -- PHY control register -- (8000:0000) 0.15 = 0 reset (4000:0000) 0.14 = 0 loopback (2040:0000) 0. 6,13 = b00 speed selection = 10 Mbps
This b00 here is confusing. b is a valid hex character, I thought this was reporting the register value as 0xb00. Instead it appears to be trying to indicate that the two bits are binary?
looks that way. it's showing bit6 and bit13.
It's in the source that way. It just confused me when trying to figure out what is wrong with the new PHY we're having hardware trouble with.
I still haven't figure out why speed selection is 10Mb when the auto-negotiate came up with 100Mb.
if ((regno == 0) && (pdesc->lo == 6)) { ushort speed_bits = regval & PHY_BMCR_SPEED_MASK; printf("%2u,%2u = b%u%u speed selection = %s Mbps", 6, 13, (regval >> 6) & 1, (regval >> 13) & 1, speed_bits == PHY_BMCR_1000_MBPS ? "1000" : speed_bits == PHY_BMCR_100_MBPS ? "100" : speed_bits == PHY_BMCR_10_MBPS ? "10" : "???"); return 1; }
-mike
On Wednesday 06 May 2009 22:06:46 Jon Smirl wrote:
On Wed, May 6, 2009 at 10:03 PM, Mike Frysinger vapier@gentoo.org wrote:
On Wednesday 06 May 2009 21:53:21 Jon Smirl wrote:
On Wed, May 6, 2009 at 2:57 PM, Jon Smirl jonsmirl@gmail.com wrote:
Why is "speed selection = 10 Mbps" when both sides support 100Mb? Is uboot decoding this register correctly?
uboot> mii dump 0 0 0. (1000) -- PHY control register -- (8000:0000) 0.15 = 0 reset (4000:0000) 0.14 = 0 loopback (2040:0000) 0. 6,13 = b00 speed selection = 10 Mbps
This b00 here is confusing. b is a valid hex character, I thought this was reporting the register value as 0xb00. Instead it appears to be trying to indicate that the two bits are binary?
looks that way. it's showing bit6 and bit13.
It's in the source that way. It just confused me when trying to figure out what is wrong with the new PHY we're having hardware trouble with.
enable debugging in the PHY driver then ... sometimes it outputs something that is only obvious when you see explicit statements as to what it's doing -mike
Hi Jon,
Jon Smirl wrote:
On Wed, May 6, 2009 at 2:57 PM, Jon Smirl jonsmirl@gmail.com wrote:
Why is "speed selection = 10 Mbps" when both sides support 100Mb? Is uboot decoding this register correctly?
uboot> mii dump 0 0 0. (1000) -- PHY control register -- (8000:0000) 0.15 = 0 reset (4000:0000) 0.14 = 0 loopback (2040:0000) 0. 6,13 = b00 speed selection = 10 Mbps
This b00 here is confusing. b is a valid hex character, I thought this was reporting the register value as 0xb00. Instead it appears to be trying to indicate that the two bits are binary?
Yes. The display confusion is rooted and aggravated by the fact that the two bits are not adjacent in the register (bits 6 and 13).
Looking at the rest of your dump, it isn't obvious to me why your PHY is running 10bT. Mike's suggestion of turning on (and possibly adding) debug is a good one.
Since you mention you are trying to debug new PHY problems, I would be suspicious of the PHY signal integrity (hardware problem) or a PHY non-standard register problem (software).
WRT hardware / signal integrity, note that the autonegotiation communications is done using the "fast link pulses" which are *not* fast and do not require anywhere near the signal integrity that 10/100/1000bT requires. Autonegotiation can work over bailing wire.
WRT software, the MII standard is a poster child for the saying "the beauty of standards is that there are so many novel ways to implement them." :-/
[snip]
Best regards, gvb
participants (3)
-
Jerry Van Baren -
Jon Smirl -
Mike Frysinger