Hello, I'm half way (probably less) through porting u-boot to trizeps3 K&K cpu module that has PXA255, 32MB flash, 64MB sdram, OTG TD242Lp, DM9000 ETh and UCB1400 onboard.

I'm stuck with DM9000 ethernet chip. Every packet that is recieved by the chip is supposed to be errornous. My DM9000 is at 0x08000000 and its IO port is at 0x08000000, while data port is at 0x08008000 (confirmed and working under supplied bootloader and linux). When I issue tftboot command in u-boot following is outputed if I enable debug; ... $ tftpboot a0100000 uImage eth_halt phy_write(reg:0, value:32768) eth_init() resetting dm9000 i/o: 0x8000000, id: 0x90000a46 MAC: 00:50:c2:0e:cc:ba 00:50:c2:0e:cc:ba: operating at 100M full duplex mode TFTP from server 192.168.0.77; our IP address is 192.168.0.97 Filename 'uImage'. Load address: 0xa0100000 Loading: *^Heth_send: length: 42

Send: 0x00: ff ff ff ff ff ff 00 50 Send: 0x08: c2 0e cc ba 08 06 00 01 Send: 0x10: 08 00 06 04 00 01 00 50 Send: 0x18: c2 0e cc ba c0 a8 00 61 Send: 0x20: 00 00 00 00 00 00 c0 a8 Send: 0x28: 00 4d transmit done

receiving packet rx status: 0x8000 rx len: 64 eth_rx: length/4: 16

Recv: 0x00: 0ec29000 40009acc deee8d45 01008608 04068008 40008200 deee8d45 4d0088c0 Recv: 0x08: 0ec29000 a8c09acc 00008100 00008000 00008000 00008000 00008000 bc178107 rx length error ...

The funny thing is that every recieved packet has bit 15 set to one (compared to ethereal dump)! It looks like address of data port is mixed in with data lines - dm9000 data port is offseted for 0x8000 on my board. This seems to happen when 32 bit access is used (for data transfer) while other register access is done in 8bit mode and that seems to function well.

I have following defines for DM9000 (probably nothing special here, anyway): /* LAN is on nCS2 */ #define CONFIG_DRIVER_DM9000 1 #define CONFIG_DM9000_BASE 0x08000000 #define DM9000_IO (CONFIG_DM9000_BASE) #define DM9000_DATA (CONFIG_DM9000_BASE + 0x8000) #define CONFIG_DM9000_USE_32BIT

Any comments?

reagrds, hinko k