[PATCH 0/2] Initial support for PXA1908 and samsung-coreprimevelte
Hello,
This series adds initial support for Marvell's PXA1908 ARM64 SoC and Samsung's Galaxy Core Prime VE LTE, a smartphone based on said SoC.
On this board, U-Boot is used as a secondary bootloader to work around certain quirks of the factory S-Boot.
Signed-off-by: Duje Mihanović duje.mihanovic@skole.hr --- Duje Mihanović (2): arm: mmp: add initial support for PXA1908 SoC board: samsung: add initial support for coreprimevelte board
MAINTAINERS | 8 ++ arch/arm/Kconfig | 11 +++ arch/arm/Makefile | 1 + arch/arm/dts/Makefile | 2 + arch/arm/dts/pxa1908-samsung-coreprimevelte.dts | 74 +++++++++++++++++ arch/arm/dts/pxa1908.dtsi | 106 ++++++++++++++++++++++++ arch/arm/mach-mmp/Kconfig | 12 +++ arch/arm/mach-mmp/Makefile | 1 + arch/arm/mach-mmp/board.c | 82 ++++++++++++++++++ arch/arm/mach-mmp/mmu.c | 30 +++++++ board/samsung/coreprimevelte/Kconfig | 12 +++ board/samsung/coreprimevelte/MAINTAINERS | 6 ++ configs/coreprimevelte_defconfig | 20 +++++ include/configs/pxa1908.h | 12 +++ 14 files changed, 377 insertions(+) --- base-commit: 3391587e3fe22db6c71882f652e13543a4501694 change-id: 20241226-coreprimevelte-1c26acfb58db
Best regards,
Add initial support for Marvell PXA1908. The SoC has 4 Cortex-A53 cores, a GC7000UL GPU and a variety of peripheral controllers.
Signed-off-by: Duje Mihanović duje.mihanovic@skole.hr --- MAINTAINERS | 8 ++++ arch/arm/Kconfig | 11 +++++ arch/arm/Makefile | 1 + arch/arm/dts/pxa1908.dtsi | 106 +++++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-mmp/Kconfig | 6 +++ arch/arm/mach-mmp/Makefile | 1 + arch/arm/mach-mmp/board.c | 82 +++++++++++++++++++++++++++++++++++ arch/arm/mach-mmp/mmu.c | 30 +++++++++++++ include/configs/pxa1908.h | 12 +++++ 9 files changed, 257 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS index 8c6c0c2a4bc8ea9e1cce80b1b5803dba46829f8d..2e08cd5598374275d7631917226898fac6b0ad53 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -386,6 +386,14 @@ T: git https://source.denx.de/u-boot/custodians/u-boot-marvell.git F: drivers/pci/pci-aardvark.c F: drivers/pci/pci_mvebu.c
+ARM MARVELL PXA1908 +M: Duje Mihanović duje.mihanovic@skole.hr +S: Maintained +T: git git://git.dujemihanovic.xyz/u-boot.git +F: arch/arm/dts/pxa1908* +F: arch/arm/mach-mmp/ +F: include/configs/pxa1908.h + ARM MARVELL SERIAL DRIVERS M: Pali Rohár pali@kernel.org M: Stefan Roese sr@denx.de diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7282c4123b08fab50c1ce3de125a19a4faf5cf1f..14732a52753d329128b923fd5b3e75a348362b30 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -841,6 +841,15 @@ config ARCH_MEDIATEK Support for the MediaTek SoCs family developed by MediaTek Inc. Please refer to doc/README.mediatek for more information.
+config ARCH_MMP + bool "Marvell MMP" + select ARM64 + select DM + select DM_SERIAL + select OF_CONTROL + select SAVE_PREV_BL_FDT_ADDR + select SAVE_PREV_BL_INITRAMFS_START_ADDR + config ARCH_LPC32XX bool "NXP LPC32xx platform" select CPU_ARM926EJS @@ -2320,6 +2329,8 @@ source "arch/arm/mach-meson/Kconfig"
source "arch/arm/mach-mediatek/Kconfig"
+source "arch/arm/mach-mmp/Kconfig" + source "arch/arm/mach-qemu/Kconfig"
source "arch/arm/mach-rockchip/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index cb87a68475406890713ad356024ee16b53ae464e..7334e79965f1f4701cf1d2aed13ccb24d2138507 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -69,6 +69,7 @@ machine-$(CONFIG_ARCH_KIRKWOOD) += kirkwood machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx machine-$(CONFIG_ARCH_MEDIATEK) += mediatek machine-$(CONFIG_ARCH_MESON) += meson +machine-$(CONFIG_ARCH_MMP) += mmp machine-$(CONFIG_ARCH_MVEBU) += mvebu machine-$(CONFIG_ARCH_NEXELL) += nexell machine-$(CONFIG_ARCH_NPCM) += npcm diff --git a/arch/arm/dts/pxa1908.dtsi b/arch/arm/dts/pxa1908.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..41ffe0ea898ff8a741096ea6b990489368f333fe --- /dev/null +++ b/arch/arm/dts/pxa1908.dtsi @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0-only +/dts-v1/; + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + model = "Marvell Armada PXA1908"; + compatible = "marvell,pxa1908"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0 0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0 1>; + enable-method = "psci"; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0 2>; + enable-method = "psci"; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0 3>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@d1df9000 { + compatible = "arm,gic-400"; + reg = <0 0xd1df9000 0 0x1000>, + <0 0xd1dfa000 0 0x2000>, + /* The subsequent registers are guesses. */ + <0 0xd1dfc000 0 0x2000>, + <0 0xd1dfe000 0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + apb@d4000000 { + compatible = "simple-bus"; + reg = <0 0xd4000000 0 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xd4000000 0x200000>; + + uart0: serial@17000 { + compatible = "ns16550"; + reg = <0x17000 0x1000>; + clock-frequency = <14745600>; + reg-shift = <2>; + }; + + uart1: serial@18000 { + compatible = "ns16550"; + reg = <0x18000 0x1000>; + clock-frequency = <14745600>; + reg-shift = <2>; + }; + + uart2: serial@36000 { + compatible = "ns16550"; + reg = <0x36000 0x1000>; + clock-frequency = <117000000>; + reg-shift = <2>; + }; + }; + }; +}; diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..b9438c6facb2e7f29f608bc72e97657d97a0d7dc --- /dev/null +++ b/arch/arm/mach-mmp/Kconfig @@ -0,0 +1,6 @@ +if ARCH_MMP + +config LNX_KRNL_IMG_TEXT_OFFSET_BASE + default TEXT_BASE + +endif diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..99beaed05c2493b55610f1012383755015c62958 --- /dev/null +++ b/arch/arm/mach-mmp/Makefile @@ -0,0 +1 @@ +obj-y += board.o mmu.o diff --git a/arch/arm/mach-mmp/board.c b/arch/arm/mach-mmp/board.c new file mode 100644 index 0000000000000000000000000000000000000000..47e4b503ca19eff6fc1b26a9283d9ec4e005b0da --- /dev/null +++ b/arch/arm/mach-mmp/board.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2024 + * Duje Mihanović duje.mihanovic@skole.hr + */ +#include <init.h> +#include <fdt_support.h> +#include <asm/io.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Timer constants */ +#define APBC_COUNTER_CLK_SEL 0xd4015064 +#define COUNTER_BASE 0xd4101000 +#define COUNTER_EN BIT(0) +#define COUNTER_HALT_ON_DEBUG BIT(1) + +int timer_init(void) +{ + u32 tmp = readl(APBC_COUNTER_CLK_SEL); + + if ((tmp >> 16) != 0x319) + return -1; + + /* Set timer frequency to 26MHz */ + writel(tmp | 1, APBC_COUNTER_CLK_SEL); + writel(COUNTER_EN | COUNTER_HALT_ON_DEBUG, COUNTER_BASE); + + gd->arch.timer_rate_hz = 26000000; + + return 0; +} + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + if (fdtdec_setup_mem_size_base() != 0) + puts("fdtdec_setup_mem_size_base() has failed\n"); + + return 0; +} + +#ifndef CONFIG_SYSRESET +void reset_cpu(void) +{ +} +#endif + +/* Stolen from arch/arm/mach-snapdragon/board.c */ +void *board_fdt_blob_setup(int *err) +{ + struct fdt_header *fdt; + bool internal_valid, external_valid; + + *err = 0; + fdt = (struct fdt_header *)get_prev_bl_fdt_addr(); + external_valid = fdt && !fdt_check_header(fdt); + internal_valid = !fdt_check_header(gd->fdt_blob); + + /* + * There is no point returning an error here, U-Boot can't do anything useful in this situation. + * Bail out while we can still print a useful error message. + */ + if (!internal_valid && !external_valid) + panic("Internal FDT is invalid and no external FDT was provided! (fdt=%#llx)\n", + (phys_addr_t)fdt); + + if (internal_valid) { + debug("Using built in FDT\n"); + } else { + debug("Using external FDT\n"); + /* So we can use it before returning */ + gd->fdt_blob = fdt; + } + + return (void *)gd->fdt_blob; +} diff --git a/arch/arm/mach-mmp/mmu.c b/arch/arm/mach-mmp/mmu.c new file mode 100644 index 0000000000000000000000000000000000000000..ad2f1e3d994ba21bc63d05f3b33586d0bfffe702 --- /dev/null +++ b/arch/arm/mach-mmp/mmu.c @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2024 + * Duje Mihanović duje.mihanovic@skole.hr + */ +#include <asm/armv8/mmu.h> +#include <linux/sizes.h> + +static struct mm_region pxa1908_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 2UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, + { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 2UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { + 0, + } +}; + +struct mm_region *mem_map = pxa1908_mem_map; diff --git a/include/configs/pxa1908.h b/include/configs/pxa1908.h new file mode 100644 index 0000000000000000000000000000000000000000..1071c32bfa2dc0b49e0f12341b6405d63ea4bcd5 --- /dev/null +++ b/include/configs/pxa1908.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2024 + * Duje Mihanović duje.mihanovic@skole.hr + */ +#define CFG_SYS_SDRAM_BASE 0x1000000 +#define CFG_SYS_INIT_RAM_ADDR 0x10000000 +#define CFG_SYS_INIT_RAM_SIZE 0x4000 +#define CFG_SYS_NS16550_IER 0x40 +#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } +#define CFG_EXTRA_ENV_SETTINGS \ + "bootcmd=bootm $prevbl_initrd_start_addr\0"
Samsung Galaxy Core Prime VE LTE is an entry-level PXA1908-based smartphone. It has 1GB of DRAM, 8GB eMMC and USB connectivity.
Signed-off-by: Duje Mihanović duje.mihanovic@skole.hr --- arch/arm/dts/Makefile | 2 + arch/arm/dts/pxa1908-samsung-coreprimevelte.dts | 74 +++++++++++++++++++++++++ arch/arm/mach-mmp/Kconfig | 6 ++ board/samsung/coreprimevelte/Kconfig | 12 ++++ board/samsung/coreprimevelte/MAINTAINERS | 6 ++ configs/coreprimevelte_defconfig | 20 +++++++ 6 files changed, 120 insertions(+)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 6ad59aeed5f684959845833d708bf1b37937f135..ea2c3e80962d08802d364efd25a1b8626225aa4d 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1283,6 +1283,8 @@ dtb-$(CONFIG_ARCH_QEMU) += qemu-arm.dtb qemu-arm64.dtb dtb-$(CONFIG_TARGET_CORSTONE1000) += corstone1000-mps3.dtb \ corstone1000-fvp.dtb
+dtb-$(CONFIG_TARGET_COREPRIMEVELTE) += pxa1908-samsung-coreprimevelte.dtb + include $(srctree)/scripts/Makefile.dts
# Add any required device tree compiler flags here diff --git a/arch/arm/dts/pxa1908-samsung-coreprimevelte.dts b/arch/arm/dts/pxa1908-samsung-coreprimevelte.dts new file mode 100644 index 0000000000000000000000000000000000000000..588e39e92650f9217e02bb332dcdcd5f74cc7fce --- /dev/null +++ b/arch/arm/dts/pxa1908-samsung-coreprimevelte.dts @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include "pxa1908.dtsi" + +/ { + pxa,rev-id = <3928 2>; + model = "Samsung Galaxy Core Prime VE LTE"; + compatible = "samsung,coreprimevelte", "marvell,pxa1908"; + + aliases { + serial0 = &uart0; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "serial0:115200n8"; + + /* S-Boot places the initramfs here */ + linux,initrd-start = <0x4d70000>; + linux,initrd-end = <0x5000000>; + + fb0: framebuffer@17177000 { + compatible = "simple-framebuffer"; + reg = <0 0x17177000 0 (480 * 800 * 4)>; + width = <480>; + height = <800>; + stride = <(480 * 4)>; + format = "a8r8g8b8"; + }; + }; + + memory { + device_type = "memory"; + reg = <0 0x1000000 0 0x3f000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer@17000000 { + reg = <0 0x17000000 0 0x1800000>; + no-map; + }; + + gpu@9000000 { + reg = <0 0x9000000 0 0x1000000>; + }; + + /* Communications processor, aka modem */ + cp@5000000 { + reg = <0 0x5000000 0 0x3000000>; + }; + + cm3@a000000 { + reg = <0 0xa000000 0 0x80000>; + }; + + seclog@8000000 { + reg = <0 0x8000000 0 0x100000>; + }; + + ramoops@8100000 { + compatible = "ramoops"; + reg = <0 0x8100000 0 0x40000>; + record-size = <0x8000>; + console-size = <0x20000>; + max-reason = <5>; + }; + }; +}; diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig index b9438c6facb2e7f29f608bc72e97657d97a0d7dc..889f127fe82b8110e16c8fdef2908842e1635ebb 100644 --- a/arch/arm/mach-mmp/Kconfig +++ b/arch/arm/mach-mmp/Kconfig @@ -1,6 +1,12 @@ if ARCH_MMP
+config TARGET_COREPRIMEVELTE + bool "Support coreprimevelte" + select LINUX_KERNEL_IMAGE_HEADER + config LNX_KRNL_IMG_TEXT_OFFSET_BASE default TEXT_BASE
+source "board/samsung/coreprimevelte/Kconfig" + endif diff --git a/board/samsung/coreprimevelte/Kconfig b/board/samsung/coreprimevelte/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..78a803796054ae9c43374eabebc14361d8561211 --- /dev/null +++ b/board/samsung/coreprimevelte/Kconfig @@ -0,0 +1,12 @@ +if TARGET_COREPRIMEVELTE + +config SYS_BOARD + default "coreprimevelte" + +config SYS_VENDOR + default "samsung" + +config SYS_CONFIG_NAME + default "pxa1908" + +endif diff --git a/board/samsung/coreprimevelte/MAINTAINERS b/board/samsung/coreprimevelte/MAINTAINERS new file mode 100644 index 0000000000000000000000000000000000000000..0902117e8b3dc9da782e61728ad9b10ee077229c --- /dev/null +++ b/board/samsung/coreprimevelte/MAINTAINERS @@ -0,0 +1,6 @@ +Samsung Galaxy Core Prime VE LTE support +M: Duje Mihanović duje.mihanovic@skole.hr +S: Maintained +T: git git://git.dujemihanovic.xyz/u-boot.git +F: board/samsung/coreprimevelte/ +F: configs/coreprimevelte_defconfig diff --git a/configs/coreprimevelte_defconfig b/configs/coreprimevelte_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..3815bb09fee552dad88f77c7a5fe62d381f1be60 --- /dev/null +++ b/configs/coreprimevelte_defconfig @@ -0,0 +1,20 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=26000000 +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_MMP=y +CONFIG_TEXT_BASE=0x1000000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_DEFAULT_DEVICE_TREE="pxa1908-samsung-coreprimevelte" +CONFIG_TARGET_COREPRIMEVELTE=y +CONFIG_SYS_LOAD_ADDR=0x1000000 +CONFIG_ARMV8_PSCI=y +CONFIG_FIT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +CONFIG_CMD_DM=y +CONFIG_OF_BOARD=y +CONFIG_CPU=y +CONFIG_CPU_ARMV8=y +CONFIG_SYS_NS16550=y +CONFIG_SYS_NS16550_MEM32=y
On Fri, Dec 27, 2024 at 10:22:14PM +0100, Duje Mihanović wrote:
Hello,
This series adds initial support for Marvell's PXA1908 ARM64 SoC and Samsung's Galaxy Core Prime VE LTE, a smartphone based on said SoC.
On this board, U-Boot is used as a secondary bootloader to work around certain quirks of the factory S-Boot.
Signed-off-by: Duje Mihanović duje.mihanovic@skole.hr
What is the status of getting these dtsi files upstream? Thanks.
On Friday 27 December 2024 22:53:27 Central European Standard Time Tom Rini wrote:
On Fri, Dec 27, 2024 at 10:22:14PM +0100, Duje Mihanović wrote:
Hello,
This series adds initial support for Marvell's PXA1908 ARM64 SoC and Samsung's Galaxy Core Prime VE LTE, a smartphone based on said SoC.
On this board, U-Boot is used as a secondary bootloader to work around certain quirks of the factory S-Boot.
Signed-off-by: Duje Mihanović duje.mihanovic@skole.hr
What is the status of getting these dtsi files upstream? Thanks.
They are the last component of PXA1908 support waiting to be merged, see https://lore.kernel.org/all/20241104-pxa1908-lkml-v13-0-e050609b8d6c@skole.h... .
In case you're asking this to see whether the board could use OF_UPSTREAM, I should note that the dtsi files in this set differ from the ones waiting to be merged into Linux differ by being slimmed down, having different compatibles in a few places (CPU and serial ports specifically) and the coreprimevelte dts also has an extra property `pxa,rev-id` which the stock bootloader requires for booting. Could all this be handled in a `pxa1908-samsung-coreprimevelte-u- boot.dtsi` and `pxa1908-u-boot.dtsi` once they are upstreamed?
Regards,
On Sat, Dec 28, 2024 at 12:10:49PM +0100, Duje Mihanović wrote:
On Friday 27 December 2024 22:53:27 Central European Standard Time Tom Rini wrote:
On Fri, Dec 27, 2024 at 10:22:14PM +0100, Duje Mihanović wrote:
Hello,
This series adds initial support for Marvell's PXA1908 ARM64 SoC and Samsung's Galaxy Core Prime VE LTE, a smartphone based on said SoC.
On this board, U-Boot is used as a secondary bootloader to work around certain quirks of the factory S-Boot.
Signed-off-by: Duje Mihanović duje.mihanovic@skole.hr
What is the status of getting these dtsi files upstream? Thanks.
They are the last component of PXA1908 support waiting to be merged, see https://lore.kernel.org/all/20241104-pxa1908-lkml-v13-0-e050609b8d6c@skole.h... .
In case you're asking this to see whether the board could use OF_UPSTREAM, I should note that the dtsi files in this set differ from the ones waiting to be merged into Linux differ by being slimmed down, having different compatibles in a few places (CPU and serial ports specifically) and the coreprimevelte dts also has an extra property `pxa,rev-id` which the stock bootloader requires for booting. Could all this be handled in a `pxa1908-samsung-coreprimevelte-u- boot.dtsi` and `pxa1908-u-boot.dtsi` once they are upstreamed?
Yes, this is about moving to OF_UPSTREAM. Strictly and only with respect to things that we have to deal with due to other bootloaders can we deal with problems like that in the -u-boot.dtsi file. Otherwise we need to match compatibles, etc, with upstream. Thanks!
On Monday 30 December 2024 16:25:33 Central European Standard Time Tom Rini wrote:
Yes, this is about moving to OF_UPSTREAM. Strictly and only with respect to things that we have to deal with due to other bootloaders can we deal with problems like that in the -u-boot.dtsi file. Otherwise we need to match compatibles, etc, with upstream. Thanks!
Fair enough. For v2 I can add "intel,xscale-uart" to NS16550's compatible array and the U-Boot dts if that's the right way to do it.
Regards,
On Tue, Dec 31, 2024 at 12:16:28PM +0100, Duje Mihanović wrote:
On Monday 30 December 2024 16:25:33 Central European Standard Time Tom Rini wrote:
Yes, this is about moving to OF_UPSTREAM. Strictly and only with respect to things that we have to deal with due to other bootloaders can we deal with problems like that in the -u-boot.dtsi file. Otherwise we need to match compatibles, etc, with upstream. Thanks!
Fair enough. For v2 I can add "intel,xscale-uart" to NS16550's compatible array and the U-Boot dts if that's the right way to do it.
Sounds like the right track yes, thanks!
participants (2)
-
Duje Mihanović -
Tom Rini