This patch adds the read_mpidr() function which returns the MPIDR_EL1 register value

Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com ---

Changes in v3: None Changes in v2: None

arch/arm/include/asm/system.h | 11 +++++++++++ 1 file changed, 11 insertions(+)

diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 868ea54..323c43e 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -71,6 +71,17 @@ static inline void set_sctlr(unsigned int val) asm volatile("isb"); }

+static inline unsigned long read_mpidr(void) +{ + unsigned long val; + + asm volatile("mrs %0, mpidr_el1" : "=r" (val)); + + return val; +} + +#define BSP_COREID 0 + void __asm_flush_dcache_all(void); void __asm_invalidate_dcache_all(void); void __asm_flush_dcache_range(u64 start, u64 end);

This patch adds code which sets up 2-level page tables on ARM64 thus extending available VA space. CPUs implementing 64k translation granule are able to use direct PA-VA mapping of the whole 48 bit address space. It also adds the ability to reset the SCTRL register at the very beginning of execution to avoid interference from stale mappings set up by early firmware/loaders/etc.

Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com

---

Changes in v3: - Reduced code duplication - Renamed CONFIG_SYS_PTL1_BITS to CONFIG_SYS_PTL2_BITS - Moved 'reset_sctrl' call to the 'reset' label - Rebased to the actual upstream tree - Documented newly added config options

Changes in v2: - Changed code licensing - Completed the patchset

arch/arm/cpu/armv8/cache_v8.c | 80 +++++++++++++++++++++++++++++++++++++- arch/arm/cpu/armv8/start.S | 36 +++++++++++++++++ arch/arm/include/asm/armv8/mmu.h | 79 ++++++++++++++++++++++++++++++++++--- arch/arm/include/asm/global_data.h | 1 + arch/arm/include/asm/system.h | 7 ++++ arch/arm/lib/board.c | 6 ++- doc/README.arm64 | 35 ++++++++++++++--- 7 files changed, 229 insertions(+), 15 deletions(-)

diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index c22f7b6..00778f2 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -12,6 +12,69 @@ DECLARE_GLOBAL_DATA_PTR;

#ifndef CONFIG_SYS_DCACHE_OFF + +#ifdef CONFIG_SYS_FULL_VA +static void set_ptl1_entry(u64 index, u64 ptl2_entry) +{ + u64 *pgd = (u64 *)gd->arch.tlb_addr; + u64 value; + + value = ptl2_entry | PTL1_TYPE_TABLE; + pgd[index] = value; +} + +static void set_ptl2_block(u64 ptl1, u64 bfn, u64 address, u64 memory_type) +{ + u64 *pmd = (u64 *)ptl1; + u64 value; + + value = address | PTL2_TYPE_BLOCK | PTL2_BLOCK_AF; + value |= PMD_ATTRINDX(memory_type); + pmd[bfn] = value; +} + +static struct mm_region mem_map[] = CONFIG_SYS_MEM_MAP; + +#define PTL1_ENTRIES CONFIG_SYS_PTL1_ENTRIES +#define PTL2_ENTRIES CONFIG_SYS_PTL2_ENTRIES + +static void setup_pgtables(void) +{ + int l1_e, l2_e; + unsigned long pmd = 0; + unsigned long address; + + /* Setup the PMD pointers */ + for (l1_e = 0; l1_e < CONFIG_SYS_MEM_MAP_SIZE; l1_e++) { + gd->arch.pmd_addr[l1_e] = gd->arch.tlb_addr + + PTL1_ENTRIES * sizeof(u64); + gd->arch.pmd_addr[l1_e] += PTL2_ENTRIES * sizeof(u64) * l1_e; + gd->arch.pmd_addr[l1_e] += 0xffffUL; + gd->arch.pmd_addr[l1_e] &= ~0xffffUL; + } + + /* Setup the page tables */ + for (l1_e = 0; l1_e < PTL1_ENTRIES; l1_e++) { + if (mem_map[pmd].base == + (uintptr_t)l1_e << PTL2_BITS) { + set_ptl1_entry(l1_e, gd->arch.pmd_addr[pmd]); + + for (l2_e = 0; l2_e < PTL2_ENTRIES; l2_e++) { + address = mem_map[pmd].base + + (uintptr_t)l2_e * BLOCK_SIZE; + set_ptl2_block(gd->arch.pmd_addr[pmd], l2_e, + address, mem_map[pmd].attrs); + } + + pmd++; + } else { + set_ptl1_entry(l1_e, 0); + } + } +} + +#else + void set_pgtable_section(u64 *page_table, u64 index, u64 section, u64 memory_type) { @@ -22,13 +85,25 @@ void set_pgtable_section(u64 *page_table, u64 index, u64 section, page_table[index] = value; }

+#endif + + /* to activate the MMU we need to set up virtual memory */ static void mmu_setup(void) { +#ifndef CONFIG_SYS_FULL_VA bd_t *bd = gd->bd; u64 *page_table = (u64 *)gd->arch.tlb_addr, i, j; +#endif int el;

+#ifdef CONFIG_SYS_FULL_VA + unsigned long coreid = read_mpidr() & CONFIG_COREID_MASK; + + /* Set up page tables only on BSP */ + if (coreid == BSP_COREID) + setup_pgtables(); +#else /* Setup an identity-mapping for all spaces */ for (i = 0; i < (PGTABLE_SIZE >> 3); i++) { set_pgtable_section(page_table, i, i << SECTION_SHIFT, @@ -45,7 +120,7 @@ static void mmu_setup(void) MT_NORMAL); } } - +#endif /* load TTBR0 */ el = current_el(); if (el == 1) { @@ -145,6 +220,7 @@ u64 *__weak arch_get_page_table(void) { return NULL; }

+#ifndef CONFIG_SYS_FULL_VA void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, enum dcache_option option) { @@ -170,6 +246,8 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, flush_dcache_range(start, end); asm volatile("dsb sy"); } +#endif + #else /* CONFIG_SYS_DCACHE_OFF */

void invalidate_dcache_all(void) diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index e70bed4..a7dfe23 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -43,6 +43,9 @@ _bss_end_ofs: .quad __bss_end - _start

reset: +#ifdef CONFIG_SYS_RESET_SCTRL + bl reset_sctrl +#endif /* * Could be EL3/EL2/EL1, Initial State: * Little Endian, MMU Disabled, i/dCache Disabled @@ -97,6 +100,39 @@ master_cpu:

bl _main

+#ifdef CONFIG_SYS_RESET_SCTRL +reset_sctrl: + switch_el x1, 3f, 2f, 1f +3: + mrs x0, sctlr_el3 + b 0f +2: + mrs x0, sctlr_el2 + b 0f +1: + mrs x0, sctlr_el1 + +0: + ldr x1, =0xfdfffffa + and x0, x0, x1 + + switch_el x1, 6f, 5f, 4f +6: + msr sctlr_el3, x0 + b 7f +5: + msr sctlr_el2, x0 + b 7f +4: + msr sctlr_el1, x0 + +7: + dsb sy + isb + b __asm_invalidate_tlb_all + ret +#endif + /*-----------------------------------------------------------------------*/

WEAK(apply_core_errata) diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 04fa0be..fee13e8 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -21,7 +21,13 @@ * The following definitions are related each other, shoud be * calculated specifically. */ + +#ifndef CONFIG_SYS_FULL_VA #define VA_BITS (42) /* 42 bits virtual address */ +#else +#define VA_BITS CONFIG_SYS_VA_BITS +#define PTL2_BITS CONFIG_SYS_PTL2_BITS +#endif

/* PAGE_SHIFT determines the page size */ #undef PAGE_SIZE @@ -30,11 +36,18 @@ #define PAGE_MASK (~(PAGE_SIZE-1))

/* - * section address mask and size definitions. + * block/section address mask and size definitions. */ +#ifndef CONFIG_SYS_FULL_VA #define SECTION_SHIFT 29 #define SECTION_SIZE (UL(1) << SECTION_SHIFT) #define SECTION_MASK (~(SECTION_SIZE-1)) +#else +#define BLOCK_SHIFT CONFIG_SYS_BLOCK_SHIFT +#define BLOCK_SIZE (UL(1) << BLOCK_SHIFT) +#define BLOCK_MASK (~(BLOCK_SIZE-1)) +#endif + /***************************************************************/

/* @@ -46,15 +59,51 @@ #define MT_NORMAL_NC 3 #define MT_NORMAL 4

-#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE*8)) | \ - (0x04 << (MT_DEVICE_NGNRE*8)) | \ - (0x0c << (MT_DEVICE_GRE*8)) | \ - (0x44 << (MT_NORMAL_NC*8)) | \ - (UL(0xff) << (MT_NORMAL*8))) +#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE * 8)) | \ + (0x04 << (MT_DEVICE_NGNRE * 8)) | \ + (0x0c << (MT_DEVICE_GRE * 8)) | \ + (0x44 << (MT_NORMAL_NC * 8)) | \ + (UL(0xff) << (MT_NORMAL * 8)))

/* * Hardware page table definitions. * + */ + +#ifdef CONFIG_SYS_FULL_VA +/* + * Level 1 descriptor (PGD). + */ + +#define PTL1_TYPE_MASK (3 << 0) +#define PTL1_TYPE_TABLE (3 << 0) + +#define PTL1_TABLE_PXN (1UL << 59) +#define PTL1_TABLE_XN (1UL << 60) +#define PTL1_TABLE_AP (1UL << 61) +#define PTL1_TABLE_NS (1UL << 63) + + +/* + * Level 2 descriptor (PMD). + */ + +#define PTL2_TYPE_MASK (3 << 0) +#define PTL2_TYPE_FAULT (0 << 0) +#define PTL2_TYPE_TABLE (3 << 0) +#define PTL2_TYPE_BLOCK (1 << 0) + +/* + * Block + */ +#define PTL2_BLOCK_S (3 << 8) +#define PTL2_BLOCK_AF (1 << 10) +#define PTL2_BLOCK_NG (1 << 11) +#define PTL2_BLOCK_PXN (UL(1) << 53) +#define PTL2_BLOCK_UXN (UL(1) << 54) + +#else +/* * Level 2 descriptor (PMD). */ #define PMD_TYPE_MASK (3 << 0) @@ -72,6 +121,8 @@ #define PMD_SECT_PXN (UL(1) << 53) #define PMD_SECT_UXN (UL(1) << 54)

+#endif + /* * AttrIndx[2:0] */ @@ -98,9 +149,16 @@ #define TCR_TG0_4K (0 << 14) #define TCR_TG0_64K (1 << 14) #define TCR_TG0_16K (2 << 14) + +#ifndef CONFIG_SYS_FULL_VA #define TCR_EL1_IPS_BITS (UL(3) << 32) /* 42 bits physical address */ #define TCR_EL2_IPS_BITS (3 << 16) /* 42 bits physical address */ #define TCR_EL3_IPS_BITS (3 << 16) /* 42 bits physical address */ +#else +#define TCR_EL1_IPS_BITS CONFIG_SYS_TCR_EL1_IPS_BITS +#define TCR_EL2_IPS_BITS CONFIG_SYS_TCR_EL2_IPS_BITS +#define TCR_EL3_IPS_BITS CONFIG_SYS_TCR_EL3_IPS_BITS +#endif

/* PTWs cacheable, inner/outer WBWA and non-shareable */ #define TCR_FLAGS (TCR_TG0_64K | \ @@ -110,8 +168,10 @@ TCR_T0SZ(VA_BITS))

#ifndef __ASSEMBLY__ +#ifndef CONFIG_SYS_FULL_VA void set_pgtable_section(u64 *page_table, u64 index, u64 section, u64 memory_type); +#endif static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) { asm volatile("dsb sy"); @@ -132,5 +192,12 @@ static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) } asm volatile("isb"); } + +struct mm_region { + u64 base; + u64 size; + u64 attrs; +}; #endif + #endif /* _ASM_ARMV8_MMU_H_ */ diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 4e3ea55..723539c 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -38,6 +38,7 @@ struct arch_global_data { unsigned long long timer_reset_value; #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) unsigned long tlb_addr; + unsigned long pmd_addr[CONFIG_SYS_PTL1_ENTRIES]; unsigned long tlb_size; #endif

diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 323c43e..9288541 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -14,7 +14,12 @@ #define CR_WXN (1 << 19) /* Write Permision Imply XN */ #define CR_EE (1 << 25) /* Exception (Big) Endian */

+#ifndef CONFIG_SYS_FULL_VA #define PGTABLE_SIZE (0x10000) +#else +#define PGTABLE_SIZE CONFIG_SYS_PGTABLE_SIZE +#endif + /* 2MB granularity */ #define MMU_SECTION_SHIFT 21

@@ -147,7 +152,9 @@ void flush_l3_cache(void); #define CR_AFE (1 << 29) /* Access flag enable */ #define CR_TE (1 << 30) /* Thumb exception enable */

+#ifndef PGTABLE_SIZE #define PGTABLE_SIZE (4096 * 4) +#endif

/* * This is used to ensure the compiler did actually allocate the register we diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index 37ea6e9..0c9c66a 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -327,10 +327,12 @@ void board_init_f(ulong bootflag) #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) /* reserve TLB table */ gd->arch.tlb_size = PGTABLE_SIZE; - addr -= gd->arch.tlb_size; + gd->arch.tlb_size += 0xffff; + gd->arch.tlb_size &= ~(0x10000 - 1);

- /* round down to next 64 kB limit */ + addr -= gd->arch.tlb_size; addr &= ~(0x10000 - 1); + /* round down to next 64 kB limit */

gd->arch.tlb_addr = addr; debug("TLB table from %08lx to %08lx\n", addr, addr + gd->arch.tlb_size); diff --git a/doc/README.arm64 b/doc/README.arm64 index 75586db..f32108f 100644 --- a/doc/README.arm64 +++ b/doc/README.arm64 @@ -36,11 +36,34 @@ Notes 6. CONFIG_ARM64 instead of CONFIG_ARMV8 is used to distinguish aarch64 and aarch32 specific codes.

+7. CONFIG_SYS_FULL_VA is used to enable 2-level page tables. For cores + supporting 64k pages it allows usage of full 48+ virtual/physical addresses + + Enabling this option requires the following ones to be defined: + - CONFIG_SYS_MEM_MAP - an array of 'struct mm_region' describing the + system memory map (start, length, attributes) + - CONFIG_SYS_MEM_MAP_SIZE - number of entries in CONFIG_SYS_MEM_MAP + - CONFIG_SYS_PTL1_ENTRIES - number of 1st level page table entries + - CONFIG_SYS_PTL2_ENTRIES - number of 1nd level page table entries + for the largest CONFIG_SYS_MEM_MAP entry + - CONFIG_COREID_MASK - the mask value used to get the core from the + MPIDR_EL1 register + - CONFIG_SYS_PTL2_BITS - number of bits addressed by the 2nd level + page tables + - CONFIG_SYS_BLOCK_SHIFT - number of bits addressed by a single block + entry from L2 page tables + - CONFIG_SYS_PGTABLE_SIZE - total size of the page table + - CONFIG_SYS_TCR_EL{1,2,3}_IPS_BITS - the IPS field of the TCR_EL{1,2,3} + + + + Contributor =========== - Tom Rini trini@ti.com - Scott Wood scottwood@freescale.com - York Sun yorksun@freescale.com - Simon Glass sjg@chromium.org - Sharma Bhupesh bhupesh.sharma@freescale.com - Rob Herring robherring2@gmail.com + Tom Rini trini@ti.com + Scott Wood scottwood@freescale.com + York Sun yorksun@freescale.com + Simon Glass sjg@chromium.org + Sharma Bhupesh bhupesh.sharma@freescale.com + Rob Herring robherring2@gmail.com + Sergey Temerkhanov s.temerkhanov@gmail.com

This commit adds the psci.h header file from Linux kernel which contains definitions related to the PSCI interface provided by firmware

Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com ---

Changes in v3: None Changes in v2: None

include/linux/psci.h | 90 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 include/linux/psci.h

diff --git a/include/linux/psci.h b/include/linux/psci.h new file mode 100644 index 0000000..310d83e --- /dev/null +++ b/include/linux/psci.h @@ -0,0 +1,90 @@ +/* + * ARM Power State and Coordination Interface (PSCI) header + * + * This header holds common PSCI defines and macros shared + * by: ARM kernel, ARM64 kernel, KVM ARM/ARM64 and user space. + * + * Copyright (C) 2014 Linaro Ltd. + * Author: Anup Patel anup.patel@linaro.org + */ + +#ifndef _UAPI_LINUX_PSCI_H +#define _UAPI_LINUX_PSCI_H + +/* + * PSCI v0.1 interface + * + * The PSCI v0.1 function numbers are implementation defined. + * + * Only PSCI return values such as: SUCCESS, NOT_SUPPORTED, + * INVALID_PARAMS, and DENIED defined below are applicable + * to PSCI v0.1. + */ + +/* PSCI v0.2 interface */ +#define PSCI_0_2_FN_BASE 0x84000000 +#define PSCI_0_2_FN(n) (PSCI_0_2_FN_BASE + (n)) +#define PSCI_0_2_64BIT 0x40000000 +#define PSCI_0_2_FN64_BASE \ + (PSCI_0_2_FN_BASE + PSCI_0_2_64BIT) +#define PSCI_0_2_FN64(n) (PSCI_0_2_FN64_BASE + (n)) + +#define PSCI_0_2_FN_PSCI_VERSION PSCI_0_2_FN(0) +#define PSCI_0_2_FN_CPU_SUSPEND PSCI_0_2_FN(1) +#define PSCI_0_2_FN_CPU_OFF PSCI_0_2_FN(2) +#define PSCI_0_2_FN_CPU_ON PSCI_0_2_FN(3) +#define PSCI_0_2_FN_AFFINITY_INFO PSCI_0_2_FN(4) +#define PSCI_0_2_FN_MIGRATE PSCI_0_2_FN(5) +#define PSCI_0_2_FN_MIGRATE_INFO_TYPE PSCI_0_2_FN(6) +#define PSCI_0_2_FN_MIGRATE_INFO_UP_CPU PSCI_0_2_FN(7) +#define PSCI_0_2_FN_SYSTEM_OFF PSCI_0_2_FN(8) +#define PSCI_0_2_FN_SYSTEM_RESET PSCI_0_2_FN(9) + +#define PSCI_0_2_FN64_CPU_SUSPEND PSCI_0_2_FN64(1) +#define PSCI_0_2_FN64_CPU_ON PSCI_0_2_FN64(3) +#define PSCI_0_2_FN64_AFFINITY_INFO PSCI_0_2_FN64(4) +#define PSCI_0_2_FN64_MIGRATE PSCI_0_2_FN64(5) +#define PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU PSCI_0_2_FN64(7) + +/* PSCI v0.2 power state encoding for CPU_SUSPEND function */ +#define PSCI_0_2_POWER_STATE_ID_MASK 0xffff +#define PSCI_0_2_POWER_STATE_ID_SHIFT 0 +#define PSCI_0_2_POWER_STATE_TYPE_SHIFT 16 +#define PSCI_0_2_POWER_STATE_TYPE_MASK \ + (0x1 << PSCI_0_2_POWER_STATE_TYPE_SHIFT) +#define PSCI_0_2_POWER_STATE_AFFL_SHIFT 24 +#define PSCI_0_2_POWER_STATE_AFFL_MASK \ + (0x3 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) + +/* PSCI v0.2 affinity level state returned by AFFINITY_INFO */ +#define PSCI_0_2_AFFINITY_LEVEL_ON 0 +#define PSCI_0_2_AFFINITY_LEVEL_OFF 1 +#define PSCI_0_2_AFFINITY_LEVEL_ON_PENDING 2 + +/* PSCI v0.2 multicore support in Trusted OS returned by MIGRATE_INFO_TYPE */ +#define PSCI_0_2_TOS_UP_MIGRATE 0 +#define PSCI_0_2_TOS_UP_NO_MIGRATE 1 +#define PSCI_0_2_TOS_MP 2 + +/* PSCI version decoding (independent of PSCI version) */ +#define PSCI_VERSION_MAJOR_SHIFT 16 +#define PSCI_VERSION_MINOR_MASK \ + ((1U << PSCI_VERSION_MAJOR_SHIFT) - 1) +#define PSCI_VERSION_MAJOR_MASK ~PSCI_VERSION_MINOR_MASK +#define PSCI_VERSION_MAJOR(ver) \ + (((ver) & PSCI_VERSION_MAJOR_MASK) >> PSCI_VERSION_MAJOR_SHIFT) +#define PSCI_VERSION_MINOR(ver) \ + ((ver) & PSCI_VERSION_MINOR_MASK) + +/* PSCI return values (inclusive of all PSCI versions) */ +#define PSCI_RET_SUCCESS 0 +#define PSCI_RET_NOT_SUPPORTED -1 +#define PSCI_RET_INVALID_PARAMS -2 +#define PSCI_RET_DENIED -3 +#define PSCI_RET_ALREADY_ON -4 +#define PSCI_RET_ON_PENDING -5 +#define PSCI_RET_INTERNAL_FAILURE -6 +#define PSCI_RET_NOT_PRESENT -7 +#define PSCI_RET_DISABLED -8 + +#endif /* _UAPI_LINUX_PSCI_H */

This commit adds basic Cavium ThunderX 88xx board definitions and support.

Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com

---

Changes in v3: - Fixed formatting - Added MAINTAINERS - Moved command definitions to defconfig

Changes in v2: None

arch/arm/Kconfig | 4 + board/cavium/thunderx/Kconfig | 19 +++++ board/cavium/thunderx/MAINTAINERS | 6 ++ board/cavium/thunderx/Makefile | 8 ++ board/cavium/thunderx/thunderx.c | 59 +++++++++++++++ configs/thunderx_88xx_defconfig | 24 ++++++ include/configs/thunderx_88xx.h | 154 ++++++++++++++++++++++++++++++++++++++ 7 files changed, 274 insertions(+) create mode 100644 board/cavium/thunderx/Kconfig create mode 100644 board/cavium/thunderx/MAINTAINERS create mode 100644 board/cavium/thunderx/Makefile create mode 100644 board/cavium/thunderx/thunderx.c create mode 100644 configs/thunderx_88xx_defconfig create mode 100644 include/configs/thunderx_88xx.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8b8269f..0c9f939 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -815,6 +815,9 @@ config TARGET_STM32F429_DISCOVERY bool "Support STM32F429 Discovery" select CPU_V7M

+config TARGET_THUNDERX_88XX + bool "Support ThunderX 88xx" + endchoice

source "arch/arm/mach-at91/Kconfig" @@ -984,6 +987,7 @@ source "board/woodburn/Kconfig" source "board/work-microwave/work_92105/Kconfig" source "board/xaeniax/Kconfig" source "board/zipitz2/Kconfig" +source "board/cavium/thunderx/Kconfig"

source "arch/arm/Kconfig.debug"

diff --git a/board/cavium/thunderx/Kconfig b/board/cavium/thunderx/Kconfig new file mode 100644 index 0000000..3e62abf --- /dev/null +++ b/board/cavium/thunderx/Kconfig @@ -0,0 +1,19 @@ +if TARGET_THUNDERX_88XX + +config SYS_CPU + string + default "armv8" + +config SYS_BOARD + string + default "thunderx" + +config SYS_VENDOR + string + default "cavium" + +config SYS_CONFIG_NAME + string + default "thunderx_88xx" + +endif diff --git a/board/cavium/thunderx/MAINTAINERS b/board/cavium/thunderx/MAINTAINERS new file mode 100644 index 0000000..c84d3b5 --- /dev/null +++ b/board/cavium/thunderx/MAINTAINERS @@ -0,0 +1,6 @@ +THUNDERX BOARD +M: Sergey Temerkhanov s.temerkhanov@gmail.com +S: Maintained +F: board/cavium/thunderx/ +F: include/configs/thunderx_88xx.h +F: configs/thunderx_88xx_defconfig diff --git a/board/cavium/thunderx/Makefile b/board/cavium/thunderx/Makefile new file mode 100644 index 0000000..306044a --- /dev/null +++ b/board/cavium/thunderx/Makefile @@ -0,0 +1,8 @@ +# +# +# (C) Copyright 2014, Cavium Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := thunderx.o diff --git a/board/cavium/thunderx/thunderx.c b/board/cavium/thunderx/thunderx.c new file mode 100644 index 0000000..5a5e259 --- /dev/null +++ b/board/cavium/thunderx/thunderx.c @@ -0,0 +1,59 @@ +/** + * (C) Copyright 2014, Cavium Inc. + * + * SPDX-License-Identifier: GPL-2.0+ +**/ + +#include <common.h> +#include <malloc.h> +#include <errno.h> +#include <linux/compiler.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + /* + * Clear spin table so that secondary processors + * observe the correct value after waken up from wfe. + */ + *(unsigned long *)CPU_RELEASE_ADDR = 0; + + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +int timer_init(void) +{ + return 0; +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(ulong addr) +{ +} + +/* + * Board specific ethernet initialization routine. + */ +int board_eth_init(bd_t *bis) +{ + int rc = 0; + + return rc; +} + +#ifdef CONFIG_PCI +void pci_init_board(void) +{ + printf("DEBUG: PCI Init TODO *****\n"); +} +#endif + diff --git a/configs/thunderx_88xx_defconfig b/configs/thunderx_88xx_defconfig new file mode 100644 index 0000000..b17329a --- /dev/null +++ b/configs/thunderx_88xx_defconfig @@ -0,0 +1,24 @@ +CONFIG_SYS_EXTRA_OPTIONS="ARM64" +CONFIG_ARM=y +CONFIG_TARGET_THUNDERX_88XX=y + + +CONFIG_CMD_CACHE=y +CONFIG_CMD_BDI=y +CONFIG_CMD_DIAG=y +CONFIG_CMD_ENV=y +CONFIG_CMD_IMI=y +CONFIG_CMD_MEMORY=y +CONFIG_CMD_RUN=y +CONFIG_CMD_BOOTD=y +CONFIG_CMD_ECHO=y +CONFIG_CMD_SOURCE=y + +CONFIG_CMD_LOADB=y +CONFIG_CMD_LOADS=y +CONFIG_CMD_SAVES=y + +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_IMLS is not set + +CONFIG_CMD_ATF=y diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h new file mode 100644 index 0000000..98609b7 --- /dev/null +++ b/include/configs/thunderx_88xx.h @@ -0,0 +1,154 @@ +/** + * (C) Copyright 2014, Cavium Inc. + * + * SPDX-License-Identifier: GPL-2.0+ +**/ + +#ifndef __THUNDERX_88XX_H__ +#define __THUNDERX_88XX_H__ + +#define CONFIG_REMAKE_ELF + +/*#define CONFIG_GICV3*/ + +/*#define CONFIG_ARMV8_SWITCH_TO_EL1*/ + +#define CONFIG_SYS_GENERIC_BOARD + +#define CONFIG_SYS_64BIT + +#define CONFIG_SYS_NO_FLASH + +/*#define CONFIG_SUPPORT_RAW_INITRD */ + + +#define CONFIG_IDENT_STRING \ + " for Cavium Thunder CN88XX ARM v8 Multi-Core" +#define CONFIG_BOOTP_VCI_STRING "Diagnostics" + +#define MEM_BASE 0x00500000 + +#define CONFIG_COREID_MASK 0xffffff + +#define CONFIG_SYS_FULL_VA + +#define CONFIG_SYS_MEM_MAP {{0x000000000000UL, 0x40000000000UL, \ + MT_NORMAL}, \ + {0x800000000000UL, 0x40000000000UL, \ + MT_DEVICE_NGNRNE}, \ + {0x840000000000UL, 0x40000000000UL, \ + MT_DEVICE_NGNRNE}, \ + {0xffffffffffffUL, 0xfffffffffffUL, \ + MT_DEVICE_NGNRNE},} + +#define CONFIG_SYS_MEM_MAP_SIZE 3 + +#define CONFIG_SYS_VA_BITS 48 +#define CONFIG_SYS_PTL2_BITS 42 +#define CONFIG_SYS_BLOCK_SHIFT 29 +#define CONFIG_SYS_PTL1_ENTRIES 64 +#define CONFIG_SYS_PTL2_ENTRIES 8192 + +#define CONFIG_SYS_PGTABLE_SIZE \ + ((CONFIG_SYS_PTL1_ENTRIES + \ + CONFIG_SYS_MEM_MAP_SIZE * CONFIG_SYS_PTL2_ENTRIES) * 8) +#define CONFIG_SYS_TCR_EL1_IPS_BITS (5UL << 32) +#define CONFIG_SYS_TCR_EL2_IPS_BITS (5 << 16) +#define CONFIG_SYS_TCR_EL3_IPS_BITS (5 << 16) + +/* Link Definitions */ +#define CONFIG_SYS_TEXT_BASE 0x00500000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_LIBFDT + +/* SMP Spin Table Definitions */ +#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) + + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ + + +#define CONFIG_SYS_MEMTEST_START MEM_BASE +#define CONFIG_SYS_MEMTEST_END (MEM_BASE + PHYS_SDRAM_1_SIZE) + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) + +/* PL011 Serial Configuration */ + +#define CONFIG_PL011_SERIAL +#define CONFIG_PL011_CLOCK 24000000 +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1} +#define CONFIG_CONS_INDEX 0 + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE (0x801000000000) +#define GICR_BASE (0x801000002000) +#define CONFIG_SYS_SERIAL0 0x87e024000000 +#define CONFIG_SYS_SERIAL1 0x87e025000000 + +#define CONFIG_PL010_SERIAL_PREINIT +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* Command line configuration */ +#define CONFIG_MENU + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_PXE +#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LOAD_ADDR (MEM_BASE) + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE (0x80000000-MEM_BASE) /* 2048 MB */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + + +/* Initial environment variables */ +#define UBOOT_IMG_HEAD_SIZE 0x40 +/* C80000 - 0x40 */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "kernel_addr=08007ffc0\0" \ + "fdt_addr=0x94C00000\0" \ + "fdt_high=0x9fffffff\0" + +#define CONFIG_BOOTARGS \ + "console=ttyAMA0,115200n8 " \ + "earlycon=pl011,0x87e024000000 " \ + "debug maxcpus=48 rootwait rw "\ + "root=/dev/sda2 coherent_pool=16M" +#define CONFIG_BOOTDELAY 5 + +/* Do not preserve environment */ +#define CONFIG_ENV_IS_NOWHERE 1 +#define CONFIG_ENV_SIZE 0x1000 + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PROMPT "ThunderX_88XX> " +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_SYS_MAXARGS 64 /* max command args */ +#define CONFIG_NO_RELOCATION 1 +#define CONFIG_LIB_RAND +#define PLL_REF_CLK 50000000 /* 50 MHz */ +#define NS_PER_REF_CLK_TICK (1000000000/PLL_REF_CLK) + +#endif /* __THUNDERX_88XX_H__ */

Change the dram_init() function on ThunderX to query ATF services for the real installed DRAM size

Signed-off-by: Sergey Temerkhanov s.temerkhanov@gmail.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com ---

Changes in v3: None Changes in v2: None

board/cavium/thunderx/Makefile | 2 +- board/cavium/thunderx/dram.c | 35 +++++++++++++++++++++++++++++++++++ board/cavium/thunderx/thunderx.c | 12 ------------ 3 files changed, 36 insertions(+), 13 deletions(-) create mode 100644 board/cavium/thunderx/dram.c

diff --git a/board/cavium/thunderx/Makefile b/board/cavium/thunderx/Makefile index c78c414..9200dd6 100644 --- a/board/cavium/thunderx/Makefile +++ b/board/cavium/thunderx/Makefile @@ -5,4 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ #

-obj-y := thunderx.o atf.o +obj-y := thunderx.o atf.o dram.o diff --git a/board/cavium/thunderx/dram.c b/board/cavium/thunderx/dram.c new file mode 100644 index 0000000..858699d --- /dev/null +++ b/board/cavium/thunderx/dram.c @@ -0,0 +1,35 @@ +/** + * (C) Copyright 2014, Cavium Inc. + * + * SPDX-License-Identifier: GPL-2.0+ +**/ + +#include <common.h> +#include <cavium/atf.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + ssize_t node_count = atf_node_count(); + ssize_t dram_size; + int node; + + printf("Initializing\nNodes in system: %zd\n", node_count); + + gd->ram_size = 0; + + for (node = 0; node < node_count; node++) { + dram_size = atf_dram_size(node); + printf("Node %d: %zd MBytes of DRAM\n", node, dram_size >> 20); + gd->ram_size += dram_size; + } + + gd->ram_size -= MEM_BASE; + + *(unsigned long *)CPU_RELEASE_ADDR = 0; + + puts("DRAM size:"); + + return 0; +} diff --git a/board/cavium/thunderx/thunderx.c b/board/cavium/thunderx/thunderx.c index 5a5e259..a5cf7c5 100644 --- a/board/cavium/thunderx/thunderx.c +++ b/board/cavium/thunderx/thunderx.c @@ -16,18 +16,6 @@ int board_init(void) return 0; }

-int dram_init(void) -{ - /* - * Clear spin table so that secondary processors - * observe the correct value after waken up from wfe. - */ - *(unsigned long *)CPU_RELEASE_ADDR = 0; - - gd->ram_size = PHYS_SDRAM_1_SIZE; - return 0; -} - int timer_init(void) { return 0;