[U-Boot] [PATCH 1/3] mx7_common: use psci 1.0 instead of 0.1
Use PSCI 1.0 instead of 0.1 to support more power management feature like system reset, power off etc..
Signed-off-by: Anson Huang Anson.Huang@nxp.com --- include/configs/mx7_common.h | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index 16e4d95..7861712 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -62,6 +62,8 @@
#define CONFIG_ARMV7_SECURE_BASE 0x00900000
+#define CONFIG_ARMV7_PSCI_1_0 + /* Secure boot (HAB) support */ #ifdef CONFIG_SECURE_BOOT #define CONFIG_CSF_SIZE 0x2000
Add i.MX7 PSCI system reset support, linux kernel can use "reboot" command to reset system even wdog driver is disabled in kernel.
Signed-off-by: Anson Huang Anson.Huang@nxp.com --- arch/arm/mach-imx/mx7/psci-mx7.c | 5 +++++ arch/arm/mach-imx/mx7/psci.S | 7 +++++++ 2 files changed, 12 insertions(+)
diff --git a/arch/arm/mach-imx/mx7/psci-mx7.c b/arch/arm/mach-imx/mx7/psci-mx7.c index 7f429b0..66f6db6 100644 --- a/arch/arm/mach-imx/mx7/psci-mx7.c +++ b/arch/arm/mach-imx/mx7/psci-mx7.c @@ -74,3 +74,8 @@ __secure int imx_cpu_off(int cpu) writel(0, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D + 4); return 0; } + +__secure void imx_system_reset(void) +{ + writew(1 << 2, WDOG1_BASE_ADDR); +} diff --git a/arch/arm/mach-imx/mx7/psci.S b/arch/arm/mach-imx/mx7/psci.S index fc5eb34..59f98cd 100644 --- a/arch/arm/mach-imx/mx7/psci.S +++ b/arch/arm/mach-imx/mx7/psci.S @@ -43,4 +43,11 @@ psci_cpu_off: 1: wfi b 1b
+.globl psci_system_reset +psci_system_reset: + b imx_system_reset + +2: wfi + b 2b + .popsection
Add i.MX7 PSCI system power off support, linux kernel can use "poweroff" command to power off system via SNVS, PMIC power will be disabled.
Signed-off-by: Anson Huang Anson.Huang@nxp.com --- arch/arm/mach-imx/mx7/psci-mx7.c | 18 ++++++++++++++++++ arch/arm/mach-imx/mx7/psci.S | 7 +++++++ 2 files changed, 25 insertions(+)
diff --git a/arch/arm/mach-imx/mx7/psci-mx7.c b/arch/arm/mach-imx/mx7/psci-mx7.c index 66f6db6..0e515f0 100644 --- a/arch/arm/mach-imx/mx7/psci-mx7.c +++ b/arch/arm/mach-imx/mx7/psci-mx7.c @@ -26,6 +26,12 @@ #define BP_SRC_A7RCR0_A7_CORE_RESET0 0 #define BP_SRC_A7RCR1_A7_CORE1_ENABLE 1
+#define SNVS_LPCR 0x38 +#define BP_SNVS_LPCR_DP_EN 0x20 +#define BP_SNVS_LPCR_TOP 0x40 + +#define CCM_CCGR_SNVS 0x4250 + static inline void imx_gpcv2_set_m_core_pgc(bool enable, u32 offset) { writel(enable, GPC_IPS_BASE_ADDR + offset); @@ -79,3 +85,15 @@ __secure void imx_system_reset(void) { writew(1 << 2, WDOG1_BASE_ADDR); } + +__secure void imx_system_off(void) +{ + u32 val; + + /* make sure SNVS clock is enabled */ + writel(0x3, CCM_BASE_ADDR + CCM_CCGR_SNVS); + + val = readl(SNVS_BASE_ADDR + SNVS_LPCR); + val |= BP_SNVS_LPCR_DP_EN | BP_SNVS_LPCR_TOP; + writel(val, SNVS_BASE_ADDR + SNVS_LPCR); +} diff --git a/arch/arm/mach-imx/mx7/psci.S b/arch/arm/mach-imx/mx7/psci.S index 59f98cd..3d15016 100644 --- a/arch/arm/mach-imx/mx7/psci.S +++ b/arch/arm/mach-imx/mx7/psci.S @@ -50,4 +50,11 @@ psci_system_reset: 2: wfi b 2b
+.globl psci_system_off +psci_system_off: + b imx_system_off + +3: wfi + b 3b + .popsection
On 1/4/2018 10:03 PM, Anson Huang wrote:
Add i.MX7 PSCI system power off support, linux kernel can use "poweroff" command to power off system via SNVS, PMIC power will be disabled.
Signed-off-by: Anson Huang Anson.Huang@nxp.com
arch/arm/mach-imx/mx7/psci-mx7.c | 18 ++++++++++++++++++ arch/arm/mach-imx/mx7/psci.S | 7 +++++++ 2 files changed, 25 insertions(+)
diff --git a/arch/arm/mach-imx/mx7/psci-mx7.c b/arch/arm/mach-imx/mx7/psci-mx7.c index 66f6db6..0e515f0 100644 --- a/arch/arm/mach-imx/mx7/psci-mx7.c +++ b/arch/arm/mach-imx/mx7/psci-mx7.c @@ -26,6 +26,12 @@ #define BP_SRC_A7RCR0_A7_CORE_RESET0 0 #define BP_SRC_A7RCR1_A7_CORE1_ENABLE 1
+#define SNVS_LPCR 0x38 +#define BP_SNVS_LPCR_DP_EN 0x20 +#define BP_SNVS_LPCR_TOP 0x40
+#define CCM_CCGR_SNVS 0x4250
static inline void imx_gpcv2_set_m_core_pgc(bool enable, u32 offset) { writel(enable, GPC_IPS_BASE_ADDR + offset); @@ -79,3 +85,15 @@ __secure void imx_system_reset(void) { writew(1 << 2, WDOG1_BASE_ADDR); }
+__secure void imx_system_off(void) +{
- u32 val;
- /* make sure SNVS clock is enabled */
- writel(0x3, CCM_BASE_ADDR + CCM_CCGR_SNVS);
- val = readl(SNVS_BASE_ADDR + SNVS_LPCR);
- val |= BP_SNVS_LPCR_DP_EN | BP_SNVS_LPCR_TOP;
- writel(val, SNVS_BASE_ADDR + SNVS_LPCR);
+} diff --git a/arch/arm/mach-imx/mx7/psci.S b/arch/arm/mach-imx/mx7/psci.S index 59f98cd..3d15016 100644 --- a/arch/arm/mach-imx/mx7/psci.S +++ b/arch/arm/mach-imx/mx7/psci.S @@ -50,4 +50,11 @@ psci_system_reset: 2: wfi b 2b
+.globl psci_system_off +psci_system_off:
- b imx_system_off
Should this be "bl" for this and the previous patch ?
+3: wfi
- b 3b
- .popsection
Best Regards! Anson Huang
-----Original Message----- From: Troy Kisky [mailto:troy.kisky@boundarydevices.com] Sent: 2018-01-06 2:49 AM To: Anson Huang anson.huang@nxp.com; sbabic@denx.de; Fabio Estevam fabio.estevam@nxp.com; albert.u.boot@aribaud.net; christian.gmeiner@gmail.com; Peng Fan peng.fan@nxp.com; u- boot@lists.denx.de Subject: Re: [U-Boot] [PATCH 3/3] imx: mx7: psci: add system power off support
On 1/4/2018 10:03 PM, Anson Huang wrote:
Add i.MX7 PSCI system power off support, linux kernel can use "poweroff" command to power off system via SNVS, PMIC power will be disabled.
Signed-off-by: Anson Huang Anson.Huang@nxp.com
arch/arm/mach-imx/mx7/psci-mx7.c | 18 ++++++++++++++++++ arch/arm/mach-imx/mx7/psci.S | 7 +++++++ 2 files changed, 25 insertions(+)
diff --git a/arch/arm/mach-imx/mx7/psci-mx7.c b/arch/arm/mach-imx/mx7/psci-mx7.c index 66f6db6..0e515f0 100644 --- a/arch/arm/mach-imx/mx7/psci-mx7.c +++ b/arch/arm/mach-imx/mx7/psci-mx7.c @@ -26,6 +26,12 @@ #define BP_SRC_A7RCR0_A7_CORE_RESET0 0 #define BP_SRC_A7RCR1_A7_CORE1_ENABLE 1
+#define SNVS_LPCR 0x38 +#define BP_SNVS_LPCR_DP_EN 0x20 +#define BP_SNVS_LPCR_TOP 0x40
+#define CCM_CCGR_SNVS 0x4250
static inline void imx_gpcv2_set_m_core_pgc(bool enable, u32 offset) { writel(enable, GPC_IPS_BASE_ADDR + offset); @@ -79,3 +85,15 @@ __secure void imx_system_reset(void) { writew(1 << 2, WDOG1_BASE_ADDR); }
+__secure void imx_system_off(void) +{
- u32 val;
- /* make sure SNVS clock is enabled */
- writel(0x3, CCM_BASE_ADDR + CCM_CCGR_SNVS);
- val = readl(SNVS_BASE_ADDR + SNVS_LPCR);
- val |= BP_SNVS_LPCR_DP_EN | BP_SNVS_LPCR_TOP;
- writel(val, SNVS_BASE_ADDR + SNVS_LPCR); }
diff --git a/arch/arm/mach-imx/mx7/psci.S b/arch/arm/mach-imx/mx7/psci.S index 59f98cd..3d15016 100644 --- a/arch/arm/mach-imx/mx7/psci.S +++ b/arch/arm/mach-imx/mx7/psci.S @@ -50,4 +50,11 @@ psci_system_reset: 2: wfi b 2b
+.globl psci_system_off +psci_system_off:
- b imx_system_off
Should this be "bl" for this and the previous patch ?
Ah, yes, thanks for your comment. I sent a V2 patch set, please help review.
Anson.
+3: wfi
- b 3b
- .popsection
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