Hi Bin

From: Bin Meng bmeng.cn@gmail.com Sent: Monday, June 14, 2021 11:48 AM To: Rick Jian-Zhi Chen(陳建志) rick@andestech.com; Leo Yu-Chi Liang(梁育齊) ycliang@andestech.com; U-Boot Mailing List u-boot@lists.denx.de Subject: Re: [RFT PATCH] riscv: andes_plic: Fix riscv_get_ipi() mask

On Wed, Jun 9, 2021 at 3:55 PM Bin Meng bmeng.cn@gmail.com wrote:

...

Current logic in riscv_get_ipi() for Andes PLICSW does not look good to me. The mask to test IPI pending bits for a hart should be left shifted by (8 * gd->arch.boot_hart), just the same as what is done in riscv_send_ipi().

Signed-off-by: Bin Meng bmeng.cn@gmail.com

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It looks there is no datasheet released from Andes that describes how PLICSW works, and its register fields. I can only get an understanding from current U-Boot and OpenSBI PLICSW driver.

This requires testing on Andes hardware, which I don't have access to.

arch/riscv/lib/andes_plic.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)

Ping?

Though there will be only one hart will jump to U-Boot proper currently, and this delay loop seem to be unnecessary. But it is still a good catch.

Thanks, Rick

Tested-by: Rick Chen rick@andestech.com Reviewed-by: Rick Chen rick@andestech.com