[PATCH v2 0/5] add DM based reset driver for SiFive SoC's
The FU540-C000 support in U-Boot is missing DM based reset driver, and is handling reset's to sub-system within the prci driver itself. The series here adds a generic DM reset driver for SiFive SoC's so as to leverage the U-Boot's reset framework and binds the reset driver with prci driver. The PRCI driver takes care of triggering the consumers reset signals appropriately.
Patch 1: Add necessary dt indexes for device reset register. Patch 2: Update macro's to use common dt indexes from binding header. Patch 3: Add reset producer and consumer entries within the device tree. Patch 4: Add reset dm driver and bind it within prci module. Patch 5: Add Kconfig, Makefile entries and enable the driver
This series is based on mainline U-Boot commit 922c6d5d0090 ("Merge tag 'mmc-2020-6-24' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmc")
History: ========================== V2: -Removed extra character in commit log of 2nd patch
V1: -Base version.
Sagar Shrikant Kadam (5): dt-bindings: prci: add indexes for reset signals available in prci fu540: prci: use common reset indexes defined in binding header fu540: dtsi: add reset producer and consumer entries sifive: reset: add DM based reset driver for SiFive SoC's configs: reset: fu540: enable dm reset framework for SiFive SoC
arch/riscv/dts/fu540-c000-u-boot.dtsi | 10 +++ arch/riscv/include/asm/arch-fu540/reset.h | 13 +++ configs/sifive_fu540_defconfig | 2 + drivers/clk/sifive/fu540-prci.c | 89 +++++++++++++------ drivers/reset/Kconfig | 9 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-sifive.c | 118 ++++++++++++++++++++++++++ include/dt-bindings/clock/sifive-fu540-prci.h | 8 ++ 8 files changed, 225 insertions(+), 25 deletions(-) create mode 100644 arch/riscv/include/asm/arch-fu540/reset.h create mode 100644 drivers/reset/reset-sifive.c
Add bit indexes for reset signals within the PRCI module on FU540-C000 SoC. The DDR and ethernet sub-system's have reset signals indicated by these reset indexes.
Signed-off-by: Sagar Shrikant Kadam sagar.kadam@sifive.com Reviewed-by: Pragnesh Patel Pragnesh.patel@sifive.com Reviewed-by: Bin Meng bin.meng@windriver.com --- include/dt-bindings/clock/sifive-fu540-prci.h | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h b/include/dt-bindings/clock/sifive-fu540-prci.h index 6a0b70a..1c03b09 100644 --- a/include/dt-bindings/clock/sifive-fu540-prci.h +++ b/include/dt-bindings/clock/sifive-fu540-prci.h @@ -15,4 +15,12 @@ #define PRCI_CLK_GEMGXLPLL 2 #define PRCI_CLK_TLCLK 3
+/* Reset bit indexes to be used by driver */ +#define PRCI_RST_DDR_CTRL_N 0 +#define PRCI_RST_DDR_AXI_N 1 +#define PRCI_RST_DDR_AHB_N 2 +#define PRCI_RST_DDR_PHY_N 3 +/* bit 4 is reserved bit */ +#define PRCI_RST_RSVD_N 4 +#define PRCI_RST_GEMGXL_N 5 #endif
On Thu, Jun 25, 2020 at 5:56 PM Sagar Shrikant Kadam sagar.kadam@sifive.com wrote:
Add bit indexes for reset signals within the PRCI module on FU540-C000 SoC. The DDR and ethernet sub-system's have reset signals indicated by these reset indexes.
Signed-off-by: Sagar Shrikant Kadam sagar.kadam@sifive.com Reviewed-by: Pragnesh Patel Pragnesh.patel@sifive.com Reviewed-by: Bin Meng bin.meng@windriver.com
include/dt-bindings/clock/sifive-fu540-prci.h | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h b/include/dt-bindings/clock/sifive-fu540-prci.h index 6a0b70a..1c03b09 100644 --- a/include/dt-bindings/clock/sifive-fu540-prci.h +++ b/include/dt-bindings/clock/sifive-fu540-prci.h @@ -15,4 +15,12 @@ #define PRCI_CLK_GEMGXLPLL 2 #define PRCI_CLK_TLCLK 3
+/* Reset bit indexes to be used by driver */ +#define PRCI_RST_DDR_CTRL_N 0 +#define PRCI_RST_DDR_AXI_N 1 +#define PRCI_RST_DDR_AHB_N 2 +#define PRCI_RST_DDR_PHY_N 3 +/* bit 4 is reserved bit */ +#define PRCI_RST_RSVD_N 4 +#define PRCI_RST_GEMGXL_N 5 #endif
Do these bindings are synced from Linux? If Yes better to sync with a particular commit or tag rather than patch.
Jagan.
Hi Jagan,
-----Original Message----- From: Jagan Teki jagan@amarulasolutions.com Sent: Thursday, June 25, 2020 11:13 PM To: Sagar Kadam sagar.kadam@sifive.com Cc: U-Boot-Denx u-boot@lists.denx.de; Rick Chen rick@andestech.com; Paul Walmsley ( Sifive) paul.walmsley@sifive.com; Palmer Dabbelt palmer@dabbelt.com; Anup Patel anup.patel@wdc.com; Atish Patra atish.patra@wdc.com; Lukasz Majewski lukma@denx.de; Pragnesh Patel pragnesh.patel@sifive.com; bin.meng@windriver.com; Simon Glass sjg@chromium.org; Trevor Woerner twoerner@gmail.com; Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com; Patrick Wildt patrick@blueri.se; Weijie Gao weijie.gao@mediatek.com; Fabio Estevam festevam@gmail.com Subject: Re: [PATCH v2 1/5] dt-bindings: prci: add indexes for reset signals available in prci
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On Thu, Jun 25, 2020 at 5:56 PM Sagar Shrikant Kadam sagar.kadam@sifive.com wrote:
Add bit indexes for reset signals within the PRCI module on FU540-C000 SoC. The DDR and ethernet sub-system's have reset signals indicated by these reset indexes.
Signed-off-by: Sagar Shrikant Kadam sagar.kadam@sifive.com Reviewed-by: Pragnesh Patel Pragnesh.patel@sifive.com Reviewed-by: Bin Meng bin.meng@windriver.com
include/dt-bindings/clock/sifive-fu540-prci.h | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h b/include/dt-
bindings/clock/sifive-fu540-prci.h
index 6a0b70a..1c03b09 100644 --- a/include/dt-bindings/clock/sifive-fu540-prci.h +++ b/include/dt-bindings/clock/sifive-fu540-prci.h @@ -15,4 +15,12 @@ #define PRCI_CLK_GEMGXLPLL 2 #define PRCI_CLK_TLCLK 3
+/* Reset bit indexes to be used by driver */ +#define PRCI_RST_DDR_CTRL_N 0 +#define PRCI_RST_DDR_AXI_N 1 +#define PRCI_RST_DDR_AHB_N 2 +#define PRCI_RST_DDR_PHY_N 3 +/* bit 4 is reserved bit */ +#define PRCI_RST_RSVD_N 4 +#define PRCI_RST_GEMGXL_N 5 #endif
Do these bindings are synced from Linux? If Yes better to sync with a particular commit or tag rather than patch.
No, these reset bindings are not synced from Linux.
Thanks & Regards, Sagar
Jagan.
On Fri, Jun 26, 2020 at 8:51 AM Sagar Kadam sagar.kadam@sifive.com wrote:
Hi Jagan,
-----Original Message----- From: Jagan Teki jagan@amarulasolutions.com Sent: Thursday, June 25, 2020 11:13 PM To: Sagar Kadam sagar.kadam@sifive.com Cc: U-Boot-Denx u-boot@lists.denx.de; Rick Chen rick@andestech.com; Paul Walmsley ( Sifive) paul.walmsley@sifive.com; Palmer Dabbelt palmer@dabbelt.com; Anup Patel anup.patel@wdc.com; Atish Patra atish.patra@wdc.com; Lukasz Majewski lukma@denx.de; Pragnesh Patel pragnesh.patel@sifive.com; bin.meng@windriver.com; Simon Glass sjg@chromium.org; Trevor Woerner twoerner@gmail.com; Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com; Patrick Wildt patrick@blueri.se; Weijie Gao weijie.gao@mediatek.com; Fabio Estevam festevam@gmail.com Subject: Re: [PATCH v2 1/5] dt-bindings: prci: add indexes for reset signals available in prci
[External Email] Do not click links or attachments unless you recognize the sender and know the content is safe
On Thu, Jun 25, 2020 at 5:56 PM Sagar Shrikant Kadam sagar.kadam@sifive.com wrote:
Add bit indexes for reset signals within the PRCI module on FU540-C000 SoC. The DDR and ethernet sub-system's have reset signals indicated by these reset indexes.
Signed-off-by: Sagar Shrikant Kadam sagar.kadam@sifive.com Reviewed-by: Pragnesh Patel Pragnesh.patel@sifive.com Reviewed-by: Bin Meng bin.meng@windriver.com
include/dt-bindings/clock/sifive-fu540-prci.h | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h b/include/dt-
bindings/clock/sifive-fu540-prci.h
index 6a0b70a..1c03b09 100644 --- a/include/dt-bindings/clock/sifive-fu540-prci.h +++ b/include/dt-bindings/clock/sifive-fu540-prci.h @@ -15,4 +15,12 @@ #define PRCI_CLK_GEMGXLPLL 2 #define PRCI_CLK_TLCLK 3
+/* Reset bit indexes to be used by driver */ +#define PRCI_RST_DDR_CTRL_N 0 +#define PRCI_RST_DDR_AXI_N 1 +#define PRCI_RST_DDR_AHB_N 2 +#define PRCI_RST_DDR_PHY_N 3 +/* bit 4 is reserved bit */ +#define PRCI_RST_RSVD_N 4 +#define PRCI_RST_GEMGXL_N 5 #endif
Do these bindings are synced from Linux? If Yes better to sync with a particular commit or tag rather than patch.
No, these reset bindings are not synced from Linux.
This is synced file from Linux, better to inline with Linux files always, if these bindings are not related to Linux then maintain it in a separate file or support it in Linux first if they do require for Linux.
Jagan.
Hello Jagan,
-----Original Message----- From: Jagan Teki jagan@amarulasolutions.com Sent: Monday, June 29, 2020 9:00 PM To: Sagar Kadam sagar.kadam@sifive.com Cc: U-Boot-Denx u-boot@lists.denx.de; Rick Chen rick@andestech.com; Paul Walmsley ( Sifive) paul.walmsley@sifive.com; Palmer Dabbelt palmer@dabbelt.com; Anup Patel anup.patel@wdc.com; Atish Patra atish.patra@wdc.com; Lukasz Majewski lukma@denx.de; Pragnesh Patel pragnesh.patel@sifive.com; bin.meng@windriver.com; Simon Glass sjg@chromium.org; Trevor Woerner twoerner@gmail.com; Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com; Patrick Wildt patrick@blueri.se; Weijie Gao weijie.gao@mediatek.com; Fabio Estevam festevam@gmail.com Subject: Re: [PATCH v2 1/5] dt-bindings: prci: add indexes for reset signals available in prci
[External Email] Do not click links or attachments unless you recognize the sender and know the content is safe
On Fri, Jun 26, 2020 at 8:51 AM Sagar Kadam sagar.kadam@sifive.com wrote:
Hi Jagan,
-----Original Message----- From: Jagan Teki jagan@amarulasolutions.com Sent: Thursday, June 25, 2020 11:13 PM To: Sagar Kadam sagar.kadam@sifive.com Cc: U-Boot-Denx u-boot@lists.denx.de; Rick Chen
Paul Walmsley ( Sifive) paul.walmsley@sifive.com; Palmer Dabbelt palmer@dabbelt.com; Anup Patel anup.patel@wdc.com; Atish
Patra
atish.patra@wdc.com; Lukasz Majewski lukma@denx.de; Pragnesh Patel pragnesh.patel@sifive.com; bin.meng@windriver.com; Simon
Glass
sjg@chromium.org; Trevor Woerner twoerner@gmail.com; Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com; Patrick Wildt patrick@blueri.se; Weijie Gao weijie.gao@mediatek.com; Fabio Estevam festevam@gmail.com Subject: Re: [PATCH v2 1/5] dt-bindings: prci: add indexes for reset
signals
available in prci
[External Email] Do not click links or attachments unless you recognize
the
sender and know the content is safe
On Thu, Jun 25, 2020 at 5:56 PM Sagar Shrikant Kadam sagar.kadam@sifive.com wrote:
Add bit indexes for reset signals within the PRCI module on FU540-C000 SoC. The DDR and ethernet sub-system's have reset signals indicated by these reset indexes.
Signed-off-by: Sagar Shrikant Kadam sagar.kadam@sifive.com Reviewed-by: Pragnesh Patel Pragnesh.patel@sifive.com Reviewed-by: Bin Meng bin.meng@windriver.com
include/dt-bindings/clock/sifive-fu540-prci.h | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h b/include/dt-
bindings/clock/sifive-fu540-prci.h
index 6a0b70a..1c03b09 100644 --- a/include/dt-bindings/clock/sifive-fu540-prci.h +++ b/include/dt-bindings/clock/sifive-fu540-prci.h @@ -15,4 +15,12 @@ #define PRCI_CLK_GEMGXLPLL 2 #define PRCI_CLK_TLCLK 3
+/* Reset bit indexes to be used by driver */ +#define PRCI_RST_DDR_CTRL_N 0 +#define PRCI_RST_DDR_AXI_N 1 +#define PRCI_RST_DDR_AHB_N 2 +#define PRCI_RST_DDR_PHY_N 3 +/* bit 4 is reserved bit */ +#define PRCI_RST_RSVD_N 4 +#define PRCI_RST_GEMGXL_N 5 #endif
Do these bindings are synced from Linux? If Yes better to sync with a particular commit or tag rather than patch.
No, these reset bindings are not synced from Linux.
This is synced file from Linux, better to inline with Linux files always, if these bindings are not related to Linux then maintain it in a separate file or support it in Linux first if they do require for Linux.
Ohh. Sorry I thought you were asking if reset-bindings are from Linux. Yes this file is synced from Linux but these reset-bindings are not related to Linux. So I can split it and place reset bindings into another file: "include/dt-bindings/reset/sifive-fu540-reset.h" and include it wherever required. Please let me know if this sounds okay.
Thanks & BR, Sagar Kadam
Jagan.
-----Original Message----- From: U-Boot u-boot-bounces@lists.denx.de On Behalf Of Sagar Kadam Sent: Monday, June 29, 2020 9:37 PM To: Jagan Teki jagan@amarulasolutions.com Cc: U-Boot-Denx u-boot@lists.denx.de; Rick Chen rick@andestech.com; Paul Walmsley ( Sifive) paul.walmsley@sifive.com; Palmer Dabbelt palmer@dabbelt.com; Anup Patel anup.patel@wdc.com; Atish Patra atish.patra@wdc.com; Lukasz Majewski lukma@denx.de; Pragnesh Patel pragnesh.patel@sifive.com; bin.meng@windriver.com; Simon Glass sjg@chromium.org; Trevor Woerner twoerner@gmail.com; Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com; Patrick Wildt patrick@blueri.se; Weijie Gao weijie.gao@mediatek.com; Fabio Estevam festevam@gmail.com Subject: RE: [PATCH v2 1/5] dt-bindings: prci: add indexes for reset signals available in prci
Hello Jagan,
-----Original Message----- From: Jagan Teki jagan@amarulasolutions.com Sent: Monday, June 29, 2020 9:00 PM To: Sagar Kadam sagar.kadam@sifive.com Cc: U-Boot-Denx u-boot@lists.denx.de; Rick Chen rick@andestech.com; Paul Walmsley ( Sifive) paul.walmsley@sifive.com; Palmer Dabbelt palmer@dabbelt.com;
Anup
Patel anup.patel@wdc.com; Atish Patra atish.patra@wdc.com; Lukasz Majewski lukma@denx.de; Pragnesh Patel
bin.meng@windriver.com; Simon Glass sjg@chromium.org; Trevor
Woerner
twoerner@gmail.com; Eugeniy Paltsev
Patrick Wildt patrick@blueri.se; Weijie Gao weijie.gao@mediatek.com; Fabio Estevam festevam@gmail.com Subject: Re: [PATCH v2 1/5] dt-bindings: prci: add indexes for reset signals available in prci
[External Email] Do not click links or attachments unless you recognize the sender and know the content is safe
On Fri, Jun 26, 2020 at 8:51 AM Sagar Kadam sagar.kadam@sifive.com wrote:
Hi Jagan,
-----Original Message----- From: Jagan Teki jagan@amarulasolutions.com Sent: Thursday, June 25, 2020 11:13 PM To: Sagar Kadam sagar.kadam@sifive.com Cc: U-Boot-Denx u-boot@lists.denx.de; Rick Chen
Paul Walmsley ( Sifive) paul.walmsley@sifive.com; Palmer Dabbelt palmer@dabbelt.com; Anup Patel anup.patel@wdc.com; Atish
Patra
atish.patra@wdc.com; Lukasz Majewski lukma@denx.de;
Pragnesh
Patel pragnesh.patel@sifive.com; bin.meng@windriver.com; Simon
Glass
sjg@chromium.org; Trevor Woerner twoerner@gmail.com;
Eugeniy
Paltsev Eugeniy.Paltsev@synopsys.com; Patrick Wildt patrick@blueri.se; Weijie Gao weijie.gao@mediatek.com; Fabio Estevam festevam@gmail.com Subject: Re: [PATCH v2 1/5] dt-bindings: prci: add indexes for reset
signals
available in prci
[External Email] Do not click links or attachments unless you recognize
the
sender and know the content is safe
On Thu, Jun 25, 2020 at 5:56 PM Sagar Shrikant Kadam sagar.kadam@sifive.com wrote:
Add bit indexes for reset signals within the PRCI module on FU540-C000 SoC. The DDR and ethernet sub-system's have reset signals indicated by these reset indexes.
Signed-off-by: Sagar Shrikant Kadam sagar.kadam@sifive.com Reviewed-by: Pragnesh Patel Pragnesh.patel@sifive.com Reviewed-by: Bin Meng bin.meng@windriver.com
include/dt-bindings/clock/sifive-fu540-prci.h | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h b/include/dt-
bindings/clock/sifive-fu540-prci.h
index 6a0b70a..1c03b09 100644 --- a/include/dt-bindings/clock/sifive-fu540-prci.h +++ b/include/dt-bindings/clock/sifive-fu540-prci.h @@ -15,4 +15,12 @@ #define PRCI_CLK_GEMGXLPLL 2 #define PRCI_CLK_TLCLK 3
+/* Reset bit indexes to be used by driver */ +#define PRCI_RST_DDR_CTRL_N 0 +#define PRCI_RST_DDR_AXI_N 1 +#define PRCI_RST_DDR_AHB_N 2 +#define PRCI_RST_DDR_PHY_N 3 +/* bit 4 is reserved bit */ +#define PRCI_RST_RSVD_N 4 +#define PRCI_RST_GEMGXL_N 5 #endif
Do these bindings are synced from Linux? If Yes better to sync with a particular commit or tag rather than patch.
No, these reset bindings are not synced from Linux.
This is synced file from Linux, better to inline with Linux files always, if these bindings are not related to Linux then maintain it in a separate file or support it in Linux first if they do require for Linux.
Ohh. Sorry I thought you were asking if reset-bindings are from Linux. Yes this file is synced from Linux but these reset-bindings are not related to Linux. So I can split it and place reset bindings into another file: "include/dt-bindings/reset/sifive-fu540-reset.h"
It will be "include/dt-bindings/reset/sifive-fu540-prci.h"
BR, Sagar
and include it wherever required. Please let me know if this sounds okay.
Thanks & BR, Sagar Kadam
Jagan.
On Fri, Jul 3, 2020 at 11:52 AM Sagar Kadam sagar.kadam@sifive.com wrote:
-----Original Message----- From: U-Boot u-boot-bounces@lists.denx.de On Behalf Of Sagar Kadam Sent: Monday, June 29, 2020 9:37 PM To: Jagan Teki jagan@amarulasolutions.com Cc: U-Boot-Denx u-boot@lists.denx.de; Rick Chen rick@andestech.com; Paul Walmsley ( Sifive) paul.walmsley@sifive.com; Palmer Dabbelt palmer@dabbelt.com; Anup Patel anup.patel@wdc.com; Atish Patra atish.patra@wdc.com; Lukasz Majewski lukma@denx.de; Pragnesh Patel pragnesh.patel@sifive.com; bin.meng@windriver.com; Simon Glass sjg@chromium.org; Trevor Woerner twoerner@gmail.com; Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com; Patrick Wildt patrick@blueri.se; Weijie Gao weijie.gao@mediatek.com; Fabio Estevam festevam@gmail.com Subject: RE: [PATCH v2 1/5] dt-bindings: prci: add indexes for reset signals available in prci
Hello Jagan,
-----Original Message----- From: Jagan Teki jagan@amarulasolutions.com Sent: Monday, June 29, 2020 9:00 PM To: Sagar Kadam sagar.kadam@sifive.com Cc: U-Boot-Denx u-boot@lists.denx.de; Rick Chen rick@andestech.com; Paul Walmsley ( Sifive) paul.walmsley@sifive.com; Palmer Dabbelt palmer@dabbelt.com;
Anup
Patel anup.patel@wdc.com; Atish Patra atish.patra@wdc.com; Lukasz Majewski lukma@denx.de; Pragnesh Patel
bin.meng@windriver.com; Simon Glass sjg@chromium.org; Trevor
Woerner
twoerner@gmail.com; Eugeniy Paltsev
Patrick Wildt patrick@blueri.se; Weijie Gao weijie.gao@mediatek.com; Fabio Estevam festevam@gmail.com Subject: Re: [PATCH v2 1/5] dt-bindings: prci: add indexes for reset signals available in prci
[External Email] Do not click links or attachments unless you recognize the sender and know the content is safe
On Fri, Jun 26, 2020 at 8:51 AM Sagar Kadam sagar.kadam@sifive.com wrote:
Hi Jagan,
-----Original Message----- From: Jagan Teki jagan@amarulasolutions.com Sent: Thursday, June 25, 2020 11:13 PM To: Sagar Kadam sagar.kadam@sifive.com Cc: U-Boot-Denx u-boot@lists.denx.de; Rick Chen
Paul Walmsley ( Sifive) paul.walmsley@sifive.com; Palmer Dabbelt palmer@dabbelt.com; Anup Patel anup.patel@wdc.com; Atish
Patra
atish.patra@wdc.com; Lukasz Majewski lukma@denx.de;
Pragnesh
Patel pragnesh.patel@sifive.com; bin.meng@windriver.com; Simon
Glass
sjg@chromium.org; Trevor Woerner twoerner@gmail.com;
Eugeniy
Paltsev Eugeniy.Paltsev@synopsys.com; Patrick Wildt patrick@blueri.se; Weijie Gao weijie.gao@mediatek.com; Fabio Estevam festevam@gmail.com Subject: Re: [PATCH v2 1/5] dt-bindings: prci: add indexes for reset
signals
available in prci
[External Email] Do not click links or attachments unless you recognize
the
sender and know the content is safe
On Thu, Jun 25, 2020 at 5:56 PM Sagar Shrikant Kadam sagar.kadam@sifive.com wrote:
Add bit indexes for reset signals within the PRCI module on FU540-C000 SoC. The DDR and ethernet sub-system's have reset signals indicated by these reset indexes.
Signed-off-by: Sagar Shrikant Kadam sagar.kadam@sifive.com Reviewed-by: Pragnesh Patel Pragnesh.patel@sifive.com Reviewed-by: Bin Meng bin.meng@windriver.com
include/dt-bindings/clock/sifive-fu540-prci.h | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h b/include/dt-
bindings/clock/sifive-fu540-prci.h
index 6a0b70a..1c03b09 100644 --- a/include/dt-bindings/clock/sifive-fu540-prci.h +++ b/include/dt-bindings/clock/sifive-fu540-prci.h @@ -15,4 +15,12 @@ #define PRCI_CLK_GEMGXLPLL 2 #define PRCI_CLK_TLCLK 3
+/* Reset bit indexes to be used by driver */ +#define PRCI_RST_DDR_CTRL_N 0 +#define PRCI_RST_DDR_AXI_N 1 +#define PRCI_RST_DDR_AHB_N 2 +#define PRCI_RST_DDR_PHY_N 3 +/* bit 4 is reserved bit */ +#define PRCI_RST_RSVD_N 4 +#define PRCI_RST_GEMGXL_N 5 #endif
Do these bindings are synced from Linux? If Yes better to sync with a particular commit or tag rather than patch.
No, these reset bindings are not synced from Linux.
This is synced file from Linux, better to inline with Linux files always, if these bindings are not related to Linux then maintain it in a separate file or support it in Linux first if they do require for Linux.
Ohh. Sorry I thought you were asking if reset-bindings are from Linux. Yes this file is synced from Linux but these reset-bindings are not related to Linux. So I can split it and place reset bindings into another file: "include/dt-bindings/reset/sifive-fu540-reset.h"
It will be "include/dt-bindings/reset/sifive-fu540-prci.h"
What if it would be the same directory structure and file name with -u-boot.h extension. This way we can identify these are u-boot related defines.
Jagan.
Hi Jagan,
-----Original Message----- From: Jagan Teki jagan@amarulasolutions.com Sent: Friday, July 3, 2020 12:04 PM To: Sagar Kadam sagar.kadam@sifive.com Cc: U-Boot-Denx u-boot@lists.denx.de; Rick Chen rick@andestech.com; Paul Walmsley ( Sifive) paul.walmsley@sifive.com; Palmer Dabbelt palmer@dabbelt.com; Anup Patel anup.patel@wdc.com; Atish Patra atish.patra@wdc.com; Lukasz Majewski lukma@denx.de; Pragnesh Patel pragnesh.patel@sifive.com; bin.meng@windriver.com; Simon Glass sjg@chromium.org; Trevor Woerner twoerner@gmail.com; Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com; Patrick Wildt patrick@blueri.se; Weijie Gao weijie.gao@mediatek.com; Fabio Estevam festevam@gmail.com Subject: Re: [PATCH v2 1/5] dt-bindings: prci: add indexes for reset signals available in prci
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On Fri, Jul 3, 2020 at 11:52 AM Sagar Kadam sagar.kadam@sifive.com wrote:
-----Original Message----- From: U-Boot u-boot-bounces@lists.denx.de On Behalf Of Sagar
Kadam
Sent: Monday, June 29, 2020 9:37 PM To: Jagan Teki jagan@amarulasolutions.com Cc: U-Boot-Denx u-boot@lists.denx.de; Rick Chen rick@andestech.com; Paul Walmsley ( Sifive) paul.walmsley@sifive.com; Palmer Dabbelt palmer@dabbelt.com; Anup Patel anup.patel@wdc.com; Atish Patra
Lukasz Majewski lukma@denx.de; Pragnesh Patel pragnesh.patel@sifive.com; bin.meng@windriver.com; Simon Glass sjg@chromium.org; Trevor Woerner twoerner@gmail.com; Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com; Patrick Wildt patrick@blueri.se; Weijie Gao weijie.gao@mediatek.com; Fabio Estevam festevam@gmail.com Subject: RE: [PATCH v2 1/5] dt-bindings: prci: add indexes for reset signals available in prci
Hello Jagan,
-----Original Message----- From: Jagan Teki jagan@amarulasolutions.com Sent: Monday, June 29, 2020 9:00 PM To: Sagar Kadam sagar.kadam@sifive.com Cc: U-Boot-Denx u-boot@lists.denx.de; Rick Chen rick@andestech.com; Paul Walmsley ( Sifive) paul.walmsley@sifive.com; Palmer Dabbelt palmer@dabbelt.com;
Anup
Patel anup.patel@wdc.com; Atish Patra atish.patra@wdc.com; Lukasz Majewski lukma@denx.de; Pragnesh Patel
bin.meng@windriver.com; Simon Glass sjg@chromium.org; Trevor
Woerner
twoerner@gmail.com; Eugeniy Paltsev
Patrick Wildt patrick@blueri.se; Weijie Gao weijie.gao@mediatek.com; Fabio Estevam festevam@gmail.com Subject: Re: [PATCH v2 1/5] dt-bindings: prci: add indexes for reset signals available in prci
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On Fri, Jun 26, 2020 at 8:51 AM Sagar Kadam sagar.kadam@sifive.com wrote:
Hi Jagan,
-----Original Message----- From: Jagan Teki jagan@amarulasolutions.com Sent: Thursday, June 25, 2020 11:13 PM To: Sagar Kadam sagar.kadam@sifive.com Cc: U-Boot-Denx u-boot@lists.denx.de; Rick Chen
Paul Walmsley ( Sifive) paul.walmsley@sifive.com; Palmer Dabbelt palmer@dabbelt.com; Anup Patel
Atish
Patra
atish.patra@wdc.com; Lukasz Majewski lukma@denx.de;
Pragnesh
Patel pragnesh.patel@sifive.com; bin.meng@windriver.com; Simon
Glass
sjg@chromium.org; Trevor Woerner twoerner@gmail.com;
Eugeniy
Paltsev Eugeniy.Paltsev@synopsys.com; Patrick Wildt patrick@blueri.se; Weijie Gao weijie.gao@mediatek.com; Fabio Estevam festevam@gmail.com Subject: Re: [PATCH v2 1/5] dt-bindings: prci: add indexes for reset
signals
available in prci
[External Email] Do not click links or attachments unless you recognize
the
sender and know the content is safe
On Thu, Jun 25, 2020 at 5:56 PM Sagar Shrikant Kadam sagar.kadam@sifive.com wrote: > > Add bit indexes for reset signals within the PRCI module on > FU540-C000 SoC. > The DDR and ethernet sub-system's have reset signals > indicated by these reset indexes. > > Signed-off-by: Sagar Shrikant Kadam sagar.kadam@sifive.com > Reviewed-by: Pragnesh Patel Pragnesh.patel@sifive.com > Reviewed-by: Bin Meng bin.meng@windriver.com > --- > include/dt-bindings/clock/sifive-fu540-prci.h | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h > b/include/dt- bindings/clock/sifive-fu540-prci.h > index 6a0b70a..1c03b09 100644 > --- a/include/dt-bindings/clock/sifive-fu540-prci.h > +++ b/include/dt-bindings/clock/sifive-fu540-prci.h > @@ -15,4 +15,12 @@ > #define PRCI_CLK_GEMGXLPLL 2 > #define PRCI_CLK_TLCLK 3 > > +/* Reset bit indexes to be used by driver */ > +#define PRCI_RST_DDR_CTRL_N 0 > +#define PRCI_RST_DDR_AXI_N 1 > +#define PRCI_RST_DDR_AHB_N 2 > +#define PRCI_RST_DDR_PHY_N 3 > +/* bit 4 is reserved bit */ > +#define PRCI_RST_RSVD_N 4 > +#define PRCI_RST_GEMGXL_N 5 > #endif
Do these bindings are synced from Linux? If Yes better to sync with a particular commit or tag rather than patch.
No, these reset bindings are not synced from Linux.
This is synced file from Linux, better to inline with Linux files always, if these bindings are not related to Linux then maintain it in a separate file or support it in Linux first if they do require for Linux.
Ohh. Sorry I thought you were asking if reset-bindings are from Linux. Yes this file is synced from Linux but these reset-bindings are not related to Linux. So I can split it and place reset bindings into another
file:
"include/dt-bindings/reset/sifive-fu540-reset.h"
It will be "include/dt-bindings/reset/sifive-fu540-prci.h"
What if it would be the same directory structure and file name with -u- boot.h extension. This way we can identify these are u-boot related defines.
Jagan.
That's a good suggestion. Having an -u-boot.h extension will make the point that it is needed only for u-boot. Please correct me if I am wrong here, but I do see few references of similar clock / reset module's ( eg: sun5i-ccu.h or tegra124-car.h etc.) sharing header names in 1. Clock bindings in include/dt-bindings/clock/ 2. reset bindings in include/dt-bindings/reset/ These headers provide respective clock and reset indexes. So I was thinking similarly for prci to have clock indexes in dt-bindings/clock and reset indexes in dt-bindings/reset.
Thanks & BR, Sagar
Hi Jagan,
A gentle reminder here.
-----Original Message----- From: U-Boot u-boot-bounces@lists.denx.de On Behalf Of Sagar Kadam Sent: Friday, July 3, 2020 12:25 PM To: Jagan Teki jagan@amarulasolutions.com Cc: U-Boot-Denx u-boot@lists.denx.de; Rick Chen rick@andestech.com; Paul Walmsley ( Sifive) paul.walmsley@sifive.com; Palmer Dabbelt palmer@dabbelt.com; Anup Patel anup.patel@wdc.com; Atish Patra atish.patra@wdc.com; Lukasz Majewski lukma@denx.de; Pragnesh Patel pragnesh.patel@sifive.com; bin.meng@windriver.com; Simon Glass sjg@chromium.org; Trevor Woerner twoerner@gmail.com; Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com; Patrick Wildt patrick@blueri.se; Weijie Gao weijie.gao@mediatek.com; Fabio Estevam festevam@gmail.com Subject: RE: [PATCH v2 1/5] dt-bindings: prci: add indexes for reset signals available in prci
Hi Jagan,
-----Original Message----- From: Jagan Teki jagan@amarulasolutions.com Sent: Friday, July 3, 2020 12:04 PM To: Sagar Kadam sagar.kadam@sifive.com Cc: U-Boot-Denx u-boot@lists.denx.de; Rick Chen
Paul Walmsley ( Sifive) paul.walmsley@sifive.com; Palmer Dabbelt palmer@dabbelt.com; Anup Patel anup.patel@wdc.com; Atish Patra atish.patra@wdc.com; Lukasz Majewski lukma@denx.de; Pragnesh Patel pragnesh.patel@sifive.com; bin.meng@windriver.com; Simon
Glass
sjg@chromium.org; Trevor Woerner twoerner@gmail.com; Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com; Patrick Wildt patrick@blueri.se; Weijie Gao weijie.gao@mediatek.com; Fabio Estevam festevam@gmail.com Subject: Re: [PATCH v2 1/5] dt-bindings: prci: add indexes for reset signals available in prci
[External Email] Do not click links or attachments unless you recognize the sender and know the content is safe
On Fri, Jul 3, 2020 at 11:52 AM Sagar Kadam sagar.kadam@sifive.com wrote:
-----Original Message----- From: U-Boot u-boot-bounces@lists.denx.de On Behalf Of Sagar
Kadam
Sent: Monday, June 29, 2020 9:37 PM To: Jagan Teki jagan@amarulasolutions.com Cc: U-Boot-Denx u-boot@lists.denx.de; Rick Chen rick@andestech.com; Paul Walmsley ( Sifive) paul.walmsley@sifive.com; Palmer Dabbelt palmer@dabbelt.com; Anup Patel anup.patel@wdc.com; Atish Patra
Lukasz Majewski lukma@denx.de; Pragnesh Patel pragnesh.patel@sifive.com; bin.meng@windriver.com; Simon Glass sjg@chromium.org; Trevor Woerner twoerner@gmail.com;
Eugeniy
Paltsev Eugeniy.Paltsev@synopsys.com; Patrick Wildt patrick@blueri.se; Weijie Gao weijie.gao@mediatek.com; Fabio Estevam festevam@gmail.com Subject: RE: [PATCH v2 1/5] dt-bindings: prci: add indexes for reset signals available in prci
Hello Jagan,
-----Original Message----- From: Jagan Teki jagan@amarulasolutions.com Sent: Monday, June 29, 2020 9:00 PM To: Sagar Kadam sagar.kadam@sifive.com Cc: U-Boot-Denx u-boot@lists.denx.de; Rick Chen rick@andestech.com; Paul Walmsley ( Sifive) paul.walmsley@sifive.com; Palmer Dabbelt
Anup
Patel anup.patel@wdc.com; Atish Patra atish.patra@wdc.com; Lukasz Majewski lukma@denx.de; Pragnesh Patel
bin.meng@windriver.com; Simon Glass sjg@chromium.org; Trevor
Woerner
twoerner@gmail.com; Eugeniy Paltsev
Patrick Wildt patrick@blueri.se; Weijie Gao weijie.gao@mediatek.com; Fabio Estevam festevam@gmail.com Subject: Re: [PATCH v2 1/5] dt-bindings: prci: add indexes for reset signals available in prci
[External Email] Do not click links or attachments unless you recognize the sender and know the content is safe
On Fri, Jun 26, 2020 at 8:51 AM Sagar Kadam sagar.kadam@sifive.com wrote:
Hi Jagan,
> -----Original Message----- > From: Jagan Teki jagan@amarulasolutions.com > Sent: Thursday, June 25, 2020 11:13 PM > To: Sagar Kadam sagar.kadam@sifive.com > Cc: U-Boot-Denx u-boot@lists.denx.de; Rick Chen
> Paul Walmsley ( Sifive) paul.walmsley@sifive.com; Palmer > Dabbelt palmer@dabbelt.com; Anup Patel
> Atish
Patra
> atish.patra@wdc.com; Lukasz Majewski lukma@denx.de;
Pragnesh
> Patel pragnesh.patel@sifive.com; bin.meng@windriver.com; > Simon
Glass
> sjg@chromium.org; Trevor Woerner twoerner@gmail.com;
Eugeniy
> Paltsev Eugeniy.Paltsev@synopsys.com; Patrick Wildt > patrick@blueri.se; Weijie Gao weijie.gao@mediatek.com; > Fabio Estevam festevam@gmail.com > Subject: Re: [PATCH v2 1/5] dt-bindings: prci: add indexes for > reset
signals
> available in prci > > [External Email] Do not click links or attachments unless you > recognize
the
> sender and know the content is safe > > On Thu, Jun 25, 2020 at 5:56 PM Sagar Shrikant Kadam > sagar.kadam@sifive.com wrote: > > > > Add bit indexes for reset signals within the PRCI module on > > FU540-C000 SoC. > > The DDR and ethernet sub-system's have reset signals > > indicated by these reset indexes. > > > > Signed-off-by: Sagar Shrikant Kadam sagar.kadam@sifive.com > > Reviewed-by: Pragnesh Patel Pragnesh.patel@sifive.com > > Reviewed-by: Bin Meng bin.meng@windriver.com > > --- > > include/dt-bindings/clock/sifive-fu540-prci.h | 8 ++++++++ > > 1 file changed, 8 insertions(+) > > > > diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h > > b/include/dt- > bindings/clock/sifive-fu540-prci.h > > index 6a0b70a..1c03b09 100644 > > --- a/include/dt-bindings/clock/sifive-fu540-prci.h > > +++ b/include/dt-bindings/clock/sifive-fu540-prci.h > > @@ -15,4 +15,12 @@ > > #define PRCI_CLK_GEMGXLPLL 2 > > #define PRCI_CLK_TLCLK 3 > > > > +/* Reset bit indexes to be used by driver */ > > +#define PRCI_RST_DDR_CTRL_N 0 > > +#define PRCI_RST_DDR_AXI_N 1 > > +#define PRCI_RST_DDR_AHB_N 2 > > +#define PRCI_RST_DDR_PHY_N 3 > > +/* bit 4 is reserved bit */ > > +#define PRCI_RST_RSVD_N 4 > > +#define PRCI_RST_GEMGXL_N 5 > > #endif > > Do these bindings are synced from Linux? If Yes better to sync > with a particular commit or tag rather than patch. >
No, these reset bindings are not synced from Linux.
This is synced file from Linux, better to inline with Linux files always, if these bindings are not related to Linux then maintain it in a separate file or support it in Linux first if they do require for Linux.
Ohh. Sorry I thought you were asking if reset-bindings are from Linux. Yes this file is synced from Linux but these reset-bindings are not related to Linux. So I can split it and place reset bindings into another
file:
"include/dt-bindings/reset/sifive-fu540-reset.h"
It will be "include/dt-bindings/reset/sifive-fu540-prci.h"
What if it would be the same directory structure and file name with -u- boot.h extension. This way we can identify these are u-boot related defines.
Jagan.
That's a good suggestion. Having an -u-boot.h extension will make the point that it is needed only for u-boot. Please correct me if I am wrong here, but I do see few references of similar clock / reset module's ( eg: sun5i-ccu.h or tegra124-car.h etc.) sharing header names in
- Clock bindings in include/dt-bindings/clock/
- reset bindings in include/dt-bindings/reset/
These headers provide respective clock and reset indexes. So I was thinking similarly for prci to have clock indexes in dt- bindings/clock and reset indexes in dt-bindings/reset.
Due to above understanding I am in a bit of dilemma, which approach can be more suitable.
Thanks & BR, Sagar
Thanks & BR, Sagar
Indexes of reset signals available in PRCI driver are also defined in include/dt-bindings/clock/sifive-fu540-prci.h. So use those instead of defining new ones again within the fu540-prci driver.
Signed-off-by: Sagar Shrikant Kadam sagar.kadam@sifive.com Reviewed-by: Pragnesh Patel Pragnesh.patel@sifive.com Reviewed-by: Bin Meng bin.meng@windriver.com --- drivers/clk/sifive/fu540-prci.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c index fe6e0d4..57d811e 100644 --- a/drivers/clk/sifive/fu540-prci.c +++ b/drivers/clk/sifive/fu540-prci.c @@ -131,21 +131,17 @@
/* DEVICESRESETREG */ #define PRCI_DEVICESRESETREG_OFFSET 0x28 -#define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT 0 + #define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_MASK \ - (0x1 << PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT) -#define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT 1 + (0x1 << PRCI_RST_DDR_CTRL_N) #define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_MASK \ - (0x1 << PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT) -#define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT 2 + (0x1 << PRCI_RST_DDR_AXI_N) #define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_MASK \ - (0x1 << PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT) -#define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT 3 + (0x1 << PRCI_RST_DDR_AHB_N) #define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_MASK \ - (0x1 << PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT) -#define PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT 5 + (0x1 << PRCI_RST_DDR_PHY_N) #define PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK \ - (0x1 << PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT) + (0x1 << PRCI_RST_GEMGXL_N)
/* CLKMUXSTATUSREG */ #define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c
The resets to DDR and ethernet sub-system are connected to PRCI device reset control register, these reset signals are active low and are held low at power-up. Add these reset producer and consumer details needed by the reset driver.
Signed-off-by: Sagar Shrikant Kadam sagar.kadam@sifive.com Reviewed-by: Pragnesh Patel Pragnesh.patel@sifive.com Reviewed-by: Bin Meng bin.meng@windriver.com --- arch/riscv/dts/fu540-c000-u-boot.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi index 9bba554..b37241e 100644 --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi @@ -59,6 +59,16 @@ reg = <0x0 0x2000000 0x0 0xc0000>; u-boot,dm-spl; }; + prci: clock-controller@10000000 { + #reset-cells = <1>; + resets = <&prci PRCI_RST_DDR_CTRL_N>, + <&prci PRCI_RST_DDR_AXI_N>, + <&prci PRCI_RST_DDR_AHB_N>, + <&prci PRCI_RST_DDR_PHY_N>, + <&prci PRCI_RST_GEMGXL_N>; + reset-names = "ddr_ctrl", "ddr_axi", "ddr_ahb", + "ddr_phy", "gemgxl_reset"; + }; dmc: dmc@100b0000 { compatible = "sifive,fu540-c000-ddr"; reg = <0x0 0x100b0000 0x0 0x0800
PRCI module within SiFive SoC's has register with which we can reset the sub-systems within the SoC. The resets to DDR and ethernet sub systems within FU540-C000 SoC are active low, and are hold low by default on power-up. Currently these are directly asserted within prci driver via register read/write. With the DM based reset driver support here, we bind the reset driver with clock (prci) driver and assert the reset signals of both sub-system's appropriately.
Signed-off-by: Sagar Shrikant Kadam sagar.kadam@sifive.com Reviewed-by: Pragnesh Patel Pragnesh.patel@sifive.com Reviewed-by: Bin Meng bin.meng@windriver.com Tested-by: Bin Meng bin.meng@windriver.com --- arch/riscv/include/asm/arch-fu540/reset.h | 13 ++++ drivers/clk/sifive/fu540-prci.c | 73 ++++++++++++++---- drivers/reset/reset-sifive.c | 118 ++++++++++++++++++++++++++++++ 3 files changed, 189 insertions(+), 15 deletions(-) create mode 100644 arch/riscv/include/asm/arch-fu540/reset.h create mode 100644 drivers/reset/reset-sifive.c
diff --git a/arch/riscv/include/asm/arch-fu540/reset.h b/arch/riscv/include/asm/arch-fu540/reset.h new file mode 100644 index 0000000..e42797a --- /dev/null +++ b/arch/riscv/include/asm/arch-fu540/reset.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2020 SiFive, Inc. + * + * Author: Sagar Kadam sagar.kadam@sifive.com + */ + +#ifndef __RESET_SIFIVE_H +#define __RESET_SIFIVE_H + +int sifive_reset_bind(struct udevice *dev, ulong count); + +#endif diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c index 57d811e..675b508 100644 --- a/drivers/clk/sifive/fu540-prci.c +++ b/drivers/clk/sifive/fu540-prci.c @@ -30,11 +30,15 @@
#include <common.h> #include <asm/io.h> +#include <asm/arch/reset.h> #include <clk-uclass.h> #include <clk.h> #include <div64.h> #include <dm.h> #include <errno.h> +#include <reset-uclass.h> +#include <dm/device.h> +#include <dm/uclass.h> #include <linux/delay.h> #include <linux/err.h>
@@ -131,6 +135,7 @@
/* DEVICESRESETREG */ #define PRCI_DEVICESRESETREG_OFFSET 0x28 +#define PRCI_DEVICERESETCNT 5
#define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_MASK \ (0x1 << PRCI_RST_DDR_CTRL_N) @@ -524,6 +529,41 @@ static const struct __prci_clock_ops sifive_fu540_prci_tlclksel_clk_ops = { .recalc_rate = sifive_fu540_prci_tlclksel_recalc_rate, };
+static int __prci_consumer_reset(const char *rst_name, bool trigger) +{ + struct udevice *dev; + struct reset_ctl rst_sig; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_RESET, + DM_GET_DRIVER(sifive_reset), + &dev); + if (ret) { + dev_err(dev, "Reset driver not found: %d\n", ret); + return ret; + } + + ret = reset_get_by_name(dev, rst_name, &rst_sig); + if (ret) { + dev_err(dev, "failed to get %s reset\n", rst_name); + return ret; + } + + if (reset_valid(&rst_sig)) { + if (trigger) + ret = reset_deassert(&rst_sig); + else + ret = reset_assert(&rst_sig); + if (ret) { + dev_err(dev, "failed to trigger reset id = %ld\n", + rst_sig.id); + return ret; + } + } + + return ret; +} + /** * __prci_ddr_release_reset() - Release DDR reset * @pd: struct __prci_data * for the PRCI containing the DDRCLK mux reg @@ -531,19 +571,20 @@ static const struct __prci_clock_ops sifive_fu540_prci_tlclksel_clk_ops = { */ static void __prci_ddr_release_reset(struct __prci_data *pd) { - u32 v; - - v = __prci_readl(pd, PRCI_DEVICESRESETREG_OFFSET); - v |= PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_MASK; - __prci_writel(v, PRCI_DEVICESRESETREG_OFFSET, pd); + /* Release DDR ctrl reset */ + __prci_consumer_reset("ddr_ctrl", true);
/* HACK to get the '1 full controller clock cycle'. */ asm volatile ("fence"); - v = __prci_readl(pd, PRCI_DEVICESRESETREG_OFFSET); - v |= (PRCI_DEVICESRESETREG_DDR_AXI_RST_N_MASK | - PRCI_DEVICESRESETREG_DDR_AHB_RST_N_MASK | - PRCI_DEVICESRESETREG_DDR_PHY_RST_N_MASK); - __prci_writel(v, PRCI_DEVICESRESETREG_OFFSET, pd); + + /* Release DDR AXI reset */ + __prci_consumer_reset("ddr_axi", true); + + /* Release DDR AHB reset */ + __prci_consumer_reset("ddr_ahb", true); + + /* Release DDR PHY reset */ + __prci_consumer_reset("ddr_phy", true);
/* HACK to get the '1 full controller clock cycle'. */ asm volatile ("fence"); @@ -563,12 +604,8 @@ static void __prci_ddr_release_reset(struct __prci_data *pd) */ static void __prci_ethernet_release_reset(struct __prci_data *pd) { - u32 v; - /* Release GEMGXL reset */ - v = __prci_readl(pd, PRCI_DEVICESRESETREG_OFFSET); - v |= PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK; - __prci_writel(v, PRCI_DEVICESRESETREG_OFFSET, pd); + __prci_consumer_reset("gemgxl_reset", true);
/* Procmon => core clock */ __prci_writel(PRCI_PROCMONCFG_CORE_CLOCK_MASK, PRCI_PROCMONCFG_OFFSET, @@ -753,6 +790,11 @@ static struct clk_ops sifive_fu540_prci_ops = { .disable = sifive_fu540_prci_disable, };
+static int sifive_fu540_clk_bind(struct udevice *dev) +{ + return sifive_reset_bind(dev, PRCI_DEVICERESETCNT); +} + static const struct udevice_id sifive_fu540_prci_ids[] = { { .compatible = "sifive,fu540-c000-prci" }, { } @@ -765,4 +807,5 @@ U_BOOT_DRIVER(sifive_fu540_prci) = { .probe = sifive_fu540_prci_probe, .ops = &sifive_fu540_prci_ops, .priv_auto_alloc_size = sizeof(struct __prci_data), + .bind = sifive_fu540_clk_bind, }; diff --git a/drivers/reset/reset-sifive.c b/drivers/reset/reset-sifive.c new file mode 100644 index 0000000..527757f --- /dev/null +++ b/drivers/reset/reset-sifive.c @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Sifive, Inc. + * Author: Sagar Kadam sagar.kadam@sifive.com + */ + +#include <common.h> +#include <dm.h> +#include <reset-uclass.h> +#include <asm/io.h> +#include <dm/device_compat.h> +#include <dm/lists.h> +#include <linux/bitops.h> + +#define PRCI_RESETREG_OFFSET 0x28 + +struct sifive_reset_priv { + void *base; + /* number of reset signals */ + int nr_reset; +}; + +static int sifive_rst_trigger(struct reset_ctl *rst, bool level) +{ + struct sifive_reset_priv *priv = dev_get_priv(rst->dev); + int id = rst->id; + int regval = readl(priv->base + PRCI_RESETREG_OFFSET); + + /* Derive bitposition from rst id */ + if (level) + /* Reset deassert */ + regval |= BIT(id); + else + /* Reset assert */ + regval &= ~BIT(id); + + writel(regval, priv->base + PRCI_RESETREG_OFFSET); + + return 0; +} + +static int sifive_reset_assert(struct reset_ctl *rst) +{ + return sifive_rst_trigger(rst, false); +} + +static int sifive_reset_deassert(struct reset_ctl *rst) +{ + return sifive_rst_trigger(rst, true); +} + +static int sifive_reset_request(struct reset_ctl *rst) +{ + struct sifive_reset_priv *priv = dev_get_priv(rst->dev); + + debug("%s(rst=%p) (dev=%p, id=%lu) (nr_reset=%d)\n", __func__, + rst, rst->dev, rst->id, priv->nr_reset); + + if (rst->id > priv->nr_reset) + return -EINVAL; + + return 0; +} + +static int sifive_reset_free(struct reset_ctl *rst) +{ + struct sifive_reset_priv *priv = dev_get_priv(rst->dev); + + debug("%s(rst=%p) (dev=%p, id=%lu) (nr_reset=%d)\n", __func__, + rst, rst->dev, rst->id, priv->nr_reset); + + return 0; +} + +static int sifive_reset_probe(struct udevice *dev) +{ + struct sifive_reset_priv *priv = dev_get_priv(dev); + + priv->base = dev_remap_addr(dev); + if (!priv->base) + return -ENOMEM; + + return 0; +} + +int sifive_reset_bind(struct udevice *dev, ulong count) +{ + struct udevice *rst_dev; + struct sifive_reset_priv *priv; + int ret; + + ret = device_bind_driver_to_node(dev, "sifive-reset", "reset", + dev_ofnode(dev), &rst_dev); + if (ret) { + dev_err(dev, "failed to bind sifive_reset driver (ret=%d)\n", ret); + return ret; + } + priv = malloc(sizeof(struct sifive_reset_priv)); + priv->nr_reset = count; + rst_dev->priv = priv; + + return 0; +} + +const struct reset_ops sifive_reset_ops = { + .request = sifive_reset_request, + .rfree = sifive_reset_free, + .rst_assert = sifive_reset_assert, + .rst_deassert = sifive_reset_deassert, +}; + +U_BOOT_DRIVER(sifive_reset) = { + .name = "sifive-reset", + .id = UCLASS_RESET, + .ops = &sifive_reset_ops, + .probe = sifive_reset_probe, + .priv_auto_alloc_size = sizeof(struct sifive_reset_priv), +};
Add necessary defconfig and Kconfig entries to enable SiFive SoC's reset driver so as to utilise U-Boot's reset framework.
Signed-off-by: Sagar Shrikant Kadam sagar.kadam@sifive.com Reviewed-by: Pragnesh Patel Pragnesh.patel@sifive.com Reviewed-by: Bin Meng bin.meng@windriver.com Tested-by: Bin Meng bin.meng@windriver.com --- configs/sifive_fu540_defconfig | 2 ++ drivers/reset/Kconfig | 9 +++++++++ drivers/reset/Makefile | 1 + 3 files changed, 12 insertions(+)
diff --git a/configs/sifive_fu540_defconfig b/configs/sifive_fu540_defconfig index 8d412f8..6d78943 100644 --- a/configs/sifive_fu540_defconfig +++ b/configs/sifive_fu540_defconfig @@ -21,3 +21,5 @@ CONFIG_DEFAULT_DEVICE_TREE="hifive-unleashed-a00" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_CLK=y CONFIG_DM_MTD=y +CONFIG_SPL_DM_RESET=y +CONFIG_DM_RESET=y diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 88d3be1..627f8e8 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -148,4 +148,13 @@ config RESET_IMX7 help Support for reset controller on i.MX7/8 SoCs.
+config RESET_SIFIVE + bool "Reset Driver for SiFive SoC's" + depends on DM_RESET && CLK_SIFIVE_FU540_PRCI && TARGET_SIFIVE_FU540 + default y + help + PRCI module within SiFive SoC's provides mechanism to reset + different hw blocks like DDR, gemgxl. With this driver we leverage + U-Boot's reset framework to reset these hardware blocks. + endmenu diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 0a044d5..e3c27c4 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -23,3 +23,4 @@ obj-$(CONFIG_RESET_MTMIPS) += reset-mtmips.o obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o obj-$(CONFIG_RESET_IMX7) += reset-imx7.o +obj-$(CONFIG_RESET_SIFIVE) += reset-sifive.o
participants (3)
-
Jagan Teki -
Sagar Kadam -
Sagar Shrikant Kadam