Signed-off-by: Albert ARIBAUD (3ADEV) albert.aribaud@3adev.fr ---

Changes in v2: None

arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 11 ++ arch/arm/include/asm/arch-lpc32xx/clk.h | 4 + arch/arm/include/asm/arch-lpc32xx/cpu.h | 2 + arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 + drivers/i2c/Makefile | 1 + drivers/i2c/lpc32xx_i2c.c | 249 ++++++++++++++++++++++++++ 6 files changed, 268 insertions(+) create mode 100644 drivers/i2c/lpc32xx_i2c.c

diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c index be4c93d..81b53ea 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c +++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c @@ -50,3 +50,14 @@ void lpc32xx_mlc_nand_init(void) /* Enable NAND interface */ writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, &clk->flashclk_ctrl); } + +void lpc32xx_i2c_init(unsigned int devnum) +{ + /* Enable I2C interface */ + uint32_t ctrl = readl(&clk->i2cclk_ctrl); + if (devnum == 1) + ctrl |= CLK_I2C1_ENABLE; + if (devnum == 2) + ctrl |= CLK_I2C2_ENABLE; + writel(ctrl, &clk->i2cclk_ctrl); +} diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h b/arch/arm/include/asm/arch-lpc32xx/clk.h index bc7d33d..781ac07 100644 --- a/arch/arm/include/asm/arch-lpc32xx/clk.h +++ b/arch/arm/include/asm/arch-lpc32xx/clk.h @@ -123,6 +123,10 @@ struct clk_pm_regs { #define CLK_MAC_SLAVE (1 << 1) #define CLK_MAC_REG (1 << 0)

+/* I2C Clock Control Register bits */ +#define CLK_I2C2_ENABLE (1 << 1) +#define CLK_I2C1_ENABLE (1 << 0) + /* Timer Clock Control1 Register bits */ #define CLK_TIMCLK_MOTOR (1 << 6) #define CLK_TIMCLK_TIMER3 (1 << 5) diff --git a/arch/arm/include/asm/arch-lpc32xx/cpu.h b/arch/arm/include/asm/arch-lpc32xx/cpu.h index 199b4a0..1067107 100644 --- a/arch/arm/include/asm/arch-lpc32xx/cpu.h +++ b/arch/arm/include/asm/arch-lpc32xx/cpu.h @@ -37,6 +37,8 @@ #define UART4_BASE 0x40088000 /* UART 4 registers base */ #define UART5_BASE 0x40090000 /* UART 5 registers base */ #define UART6_BASE 0x40098000 /* UART 6 registers base */ +#define I2C1_BASE 0x400A0000 /* I2C 1 registers base */ +#define I2C2_BASE 0x400A8000 /* I2C 2 registers base */

/* External SDRAM Memory Bank base addresses */ #define EMC_DYCS0_BASE 0x80000000 /* SDRAM DYCS0 base address */ diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h index 0c4e712..a4a05d1 100644 --- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h +++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h @@ -10,5 +10,6 @@ void lpc32xx_uart_init(unsigned int uart_id); void lpc32xx_mac_init(void); void lpc32xx_mlc_nand_init(void); +void lpc32xx_i2c_init(unsigned int devnum);

#endif /* _LPC32XX_SYS_PROTO_H */ diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 774bc94..26ea854 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o +obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o obj-$(CONFIG_SYS_I2C_MXS) += mxs_i2c.o diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c new file mode 100644 index 0000000..78d26e4 --- /dev/null +++ b/drivers/i2c/lpc32xx_i2c.c @@ -0,0 +1,249 @@ +/* + * LPC32xx I2C interface driver + * + * (C) Copyright 2014 DENX Software Engineering GmbH + * Written-by: Albert ARIBAUD - 3ADEV albert.aribaud@3adev.fr + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <i2c.h> +#include <asm/errno.h> +#include <asm/arch/clk.h> + +/* + * Provide default speed and slave if target did not + */ + +#if !defined(CONFIG_SYS_I2C_LPC32XX_SPEED) +#define CONFIG_SYS_I2C_LPC32XX_SPEED 350000 +#endif + +#if !defined(CONFIG_SYS_I2C_LPC32XX_SLAVE) +#define CONFIG_SYS_I2C_LPC32XX_SLAVE 0 +#endif + +/* i2c register set */ +struct lpc32xx_i2c_registers { + union { + u32 rx; + u32 tx; + }; + u32 stat; + u32 ctrl; + u32 clk_hi; + u32 clk_lo; + u32 adr; + u32 rxfl; + u32 txfl; + u32 rxb; + u32 txb; + u32 stx; + u32 stxfl; +}; + +/* TX register fields */ +#define LPC32XX_I2C_TX_START 0x00000100 +#define LPC32XX_I2C_TX_STOP 0x00000200 + +/* Control register values */ +#define LPC32XX_I2C_SOFT_RESET 0x00000100 + +/* Status register values */ +#define LPC32XX_I2C_STAT_TFF 0x00000400 +#define LPC32XX_I2C_STAT_RFE 0x00000200 +#define LPC32XX_I2C_STAT_DRMI 0x00000008 +#define LPC32XX_I2C_STAT_NAI 0x00000004 +#define LPC32XX_I2C_STAT_TDI 0x00000001 + +static struct lpc32xx_i2c_registers *lpc32xx_i2c[] = { + (struct lpc32xx_i2c_registers *)I2C1_BASE, + (struct lpc32xx_i2c_registers *)I2C2_BASE +}; + +/* Set I2C bus speed */ +static unsigned int lpc32xx_i2c_set_bus_speed(struct i2c_adapter *adap, + unsigned int speed) +{ + int half_period; + + if (speed == 0) + return -EINVAL; + + half_period = (105000000 / speed) / 2; + + if ((half_period > 255) || (half_period < 0)) + return -EINVAL; + + writel(half_period, &lpc32xx_i2c[adap->hwadapnr]->clk_hi); + writel(half_period, &lpc32xx_i2c[adap->hwadapnr]->clk_lo); + return 0; +} + +/* I2C init called by cmd_i2c when doing 'i2c reset'. */ +static void _i2c_init(struct i2c_adapter *adap, + int requested_speed, int slaveadd) +{ + struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr]; + + /* soft reset (auto-clears) */ + writel(LPC32XX_I2C_SOFT_RESET, &i2c->ctrl); + /* set HI and LO periods for about 350 kHz */ + lpc32xx_i2c_set_bus_speed(adap, requested_speed); +} + +/* I2C probe called by cmd_i2c when doing 'i2c probe'. */ +static int lpc32xx_i2c_probe(struct i2c_adapter *adap, u8 dev) +{ + struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr]; + int stat; + + /* Soft-reset the controller */ + writel(LPC32XX_I2C_SOFT_RESET, &i2c->ctrl); + while (readl(&i2c->ctrl) & LPC32XX_I2C_SOFT_RESET) + ; + /* Addre slave for write with start before and stop after */ + writel((dev<<1) | LPC32XX_I2C_TX_START | LPC32XX_I2C_TX_STOP, + &i2c->tx); + /* wait for end of transation */ + while (!((stat = readl(&i2c->stat)) & LPC32XX_I2C_STAT_TDI)) + ; + /* was there no acknowledge? */ + return (stat & LPC32XX_I2C_STAT_NAI) ? -1 : 0; +} + +/* + * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c + * Begin write, send address byte(s), begin read, receive data bytes, end. + */ +static int lpc32xx_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, + int alen, u8 *data, int length) +{ + struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr]; + int stat, wlen; + + /* Soft-reset the controller */ + writel(LPC32XX_I2C_SOFT_RESET, &i2c->ctrl); + while (readl(&i2c->ctrl) & LPC32XX_I2C_SOFT_RESET) + ; + /* do we need to write an address at all? */ + if (alen) { + /* Address slave in write mode */ + writel((dev<<1) | LPC32XX_I2C_TX_START, &i2c->tx); + /* write address bytes */ + while (alen--) { + /* compute address byte + stop for the last one */ + int a = (addr >> (8 * alen)) & 0xff; + if (!alen) + a |= LPC32XX_I2C_TX_STOP; + /* Send address byte */ + writel(a, &i2c->tx); + } + /* wait for end of transation */ + while (!((stat = readl(&i2c->stat)) & LPC32XX_I2C_STAT_TDI)) + ; + /* clear end-of-transaction flag */ + writel(1, &i2c->stat); + } + /* do we have to read data at all? */ + if (length) { + /* Address slave in read mode */ + writel(1 | (dev<<1) | LPC32XX_I2C_TX_START, &i2c->tx); + wlen = length; + /* get data */ + while (length | wlen) { + /* read status for TFF and RFE */ + stat = readl(&i2c->stat); + /* must we, can we write a trigger byte? */ + if ((wlen > 0) + & (!(stat & LPC32XX_I2C_STAT_TFF))) { + wlen--; + /* write trigger byte + stop if last */ + writel(wlen ? 0 : + LPC32XX_I2C_TX_STOP, &i2c->tx); + } + /* must we, can we read a data byte? */ + if ((length > 0) + & (!(stat & LPC32XX_I2C_STAT_RFE))) { + length--; + /* read byte */ + *(data++) = readl(&i2c->rx); + } + } + } + /* wait for end of transation */ + while (!((stat = readl(&i2c->stat)) & LPC32XX_I2C_STAT_TDI)) + ; + /* clear end-of-transaction flag */ + writel(1, &i2c->stat); + /* success */ + return 0; +} + +/* + * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c + * Begin write, send address byte(s), send data bytes, end. + */ +static int lpc32xx_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, + int alen, u8 *data, int length) +{ + struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr]; + int stat; + + /* Soft-reset the controller */ + writel(LPC32XX_I2C_SOFT_RESET, &i2c->ctrl); + while (readl(&i2c->ctrl) & LPC32XX_I2C_SOFT_RESET) + ; + /* do we need to write anything at all? */ + if (alen | length) + /* Address slave in write mode */ + writel((dev<<1) | LPC32XX_I2C_TX_START, &i2c->tx); + /* write address bytes */ + while (alen) { + /* wait for transmit fifo not full */ + stat = readl(&i2c->stat); + if (!(stat & LPC32XX_I2C_STAT_TFF)) { + alen--; + int a = (addr >> (8 * alen)) & 0xff; + if (!(alen | length)) + a |= LPC32XX_I2C_TX_STOP; + /* Send address byte */ + writel(a, &i2c->tx); + } + } + while (length) { + /* wait for transmit fifo not full */ + stat = readl(&i2c->stat); + if (!(stat & LPC32XX_I2C_STAT_TFF)) { + /* compute data byte, add stop if length==0 */ + length--; + int d = *(data++); + if (!length) + d |= LPC32XX_I2C_TX_STOP; + /* Send data byte */ + writel(d, &i2c->tx); + } + } + /* wait for end of transation */ + while (!((stat = readl(&i2c->stat)) & LPC32XX_I2C_STAT_TDI)) + ; + /* clear end-of-transaction flag */ + writel(1, &i2c->stat); + return 0; +} + +U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_0, _i2c_init, lpc32xx_i2c_probe, + lpc32xx_i2c_read, lpc32xx_i2c_write, + lpc32xx_i2c_set_bus_speed, + CONFIG_SYS_I2C_LPC32XX_SPEED, + CONFIG_SYS_I2C_LPC32XX_SLAVE, + 0) + +U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_1, _i2c_init, lpc32xx_i2c_probe, + lpc32xx_i2c_read, lpc32xx_i2c_write, + lpc32xx_i2c_set_bus_speed, + CONFIG_SYS_I2C_LPC32XX_SPEED, + CONFIG_SYS_I2C_LPC32XX_SLAVE, + 1)

Signed-off-by: Albert ARIBAUD (3ADEV) albert.aribaud@3adev.fr ---

Changes in v2: - added MUX setting for SSP0

arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 14 +++ arch/arm/include/asm/arch-lpc32xx/clk.h | 3 + arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 + drivers/spi/Makefile | 1 + drivers/spi/lpc32xx_ssp.c | 132 ++++++++++++++++++++++++++ 5 files changed, 151 insertions(+) create mode 100644 drivers/spi/lpc32xx_ssp.c

diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c index a407098..5a453e3 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c +++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c @@ -8,11 +8,13 @@ #include <asm/arch/cpu.h> #include <asm/arch/clk.h> #include <asm/arch/uart.h> +#include <asm/arch/mux.h> #include <asm/io.h> #include <dm.h>

static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE; +static struct mux_regs *mux = (struct mux_regs *)MUX_BASE;

void lpc32xx_uart_init(unsigned int uart_id) { @@ -66,3 +68,15 @@ void lpc32xx_i2c_init(unsigned int devnum) U_BOOT_DEVICE(lpc32xx_gpios) = { .name = "gpio_lpc32xx" }; + +/* Mux for SCK0, MISO0, MOSI0. We do not use SSEL0. */ + +#define P_MUX_SET_SSP0 0x1600 + +void lpc32xx_ssp_init(void) +{ + /* Enable SSP0 interface */ + writel(CLK_SSP0_ENABLE_CLOCK, &clk->ssp_ctrl); + /* Mux SSP0 pins */ + writel(P_MUX_SET_SSP0, &mux->p_mux_set); +} diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h b/arch/arm/include/asm/arch-lpc32xx/clk.h index 781ac07..2cb5703 100644 --- a/arch/arm/include/asm/arch-lpc32xx/clk.h +++ b/arch/arm/include/asm/arch-lpc32xx/clk.h @@ -155,6 +155,9 @@ struct clk_pm_regs { #define CLK_NAND_MLC (1 << 1) #define CLK_NAND_MLC_INT (1 << 5)

+/* SSP Clock Control Register bits */ +#define CLK_SSP0_ENABLE_CLOCK (1 << 0) + unsigned int get_sys_clk_rate(void); unsigned int get_hclk_pll_rate(void); unsigned int get_hclk_clk_div(void); diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h index a4a05d1..86d5ee9 100644 --- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h +++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h @@ -11,5 +11,6 @@ void lpc32xx_uart_init(unsigned int uart_id); void lpc32xx_mac_init(void); void lpc32xx_mlc_nand_init(void); void lpc32xx_i2c_init(unsigned int devnum); +void lpc32xx_ssp_init(void);

#endif /* _LPC32XX_SYS_PROTO_H */ diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index edbd520..ce6f1cc 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o obj-$(CONFIG_FTSSP010_SPI) += ftssp010_spi.o obj-$(CONFIG_ICH_SPI) += ich.o obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o +obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o obj-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o obj-$(CONFIG_MXC_SPI) += mxc_spi.o diff --git a/drivers/spi/lpc32xx_ssp.c b/drivers/spi/lpc32xx_ssp.c new file mode 100644 index 0000000..40270df --- /dev/null +++ b/drivers/spi/lpc32xx_ssp.c @@ -0,0 +1,132 @@ +/* + * LPC32xx SSP interface (SPI mode) + * + * (C) Copyright 2014 DENX Software Engineering GmbH + * Written-by: Albert ARIBAUD albert.aribaud@3adev.fr + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <linux/compat.h> +#include <asm/io.h> +#include <malloc.h> +#include <spi.h> +#include <asm/arch/clk.h> + +/* SSP chip registers */ +struct ssp_regs { + u32 cr0; + u32 cr1; + u32 data; + u32 sr; + u32 cpsr; + u32 imsc; + u32 ris; + u32 mis; + u32 icr; + u32 dmacr; +}; + +/* CR1 register defines */ +#define SSP_CR1_SSP_ENABLE 0x0002 + +/* SR register defines */ +#define SSP_SR_TNF 0x0002 +/* SSP status RX FIFO not empty bit */ +#define SSP_SR_RNE 0x0004 + +static struct ssp_regs *ssp0_regs = (struct ssp_regs *)SSP0_BASE; + +static struct spi_slave ssp0_slave = { + .bus = 0, + .cs = 0, + .op_mode_rx = 0, + .op_mode_tx = 0, + .wordlen = 8, + .max_write_size = 1, /* this is for SPI FLASHes -- don't care */ + .memory_map = NULL, /* for SPI FLASHes too */ + .option = 0, + .flags = 0 +}; + +/* spi_init is called during boot when CONFIG_CMD_SPI is defined */ +void spi_init(void) +{ + /* + * nothing to do: clocking was enabled in lpc32xx_ssp_enable() + * and configuration will be done in spi_setup_slave() + */ +} + +/* the following is called in sequence by do_spi_xfer() */ + +struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode) +{ + /* we only set up SSP0 for now, so ignore bus */ + + if (mode & SPI_3WIRE) { + error("3-wire mode not supported"); + return NULL; + } + + if (mode & SPI_SLAVE) { + error("slave mode not supported\n"); + return NULL; + } + + if (mode & SPI_PREAMBLE) { + error("preamble byte skipping not supported\n"); + return NULL; + } + + /* + * 8 bit frame, SPI fmt, 500kbps -> clock divider is 26. + * Set SCR to 0 and CPSDVSR to 26. + */ + + writel(0x7, &ssp0_regs->cr0); /* 8-bit chunks, SPI, 1 clk/bit */ + writel(26, &ssp0_regs->cpsr); /* SSP clock = HCLK/26 = 500kbps */ + writel(0, &ssp0_regs->imsc); /* do not raise any interrupts */ + writel(0, &ssp0_regs->icr); /* clear any pending interrupt */ + writel(0, &ssp0_regs->dmacr); /* do not do DMAs */ + writel(SSP_CR1_SSP_ENABLE, &ssp0_regs->cr1); /* enable SSP0 */ + return &ssp0_slave; +} + +int spi_claim_bus(struct spi_slave *slave) +{ + /* only one bus and slave so far, always available */ + return 0; +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + int bytelen = bitlen >> 3; + int idx_out = 0; + int idx_in = 0; + int start_time; + + start_time = get_timer(0); + while ((idx_out < bytelen) || (idx_in < bytelen)) { + int status = readl(&ssp0_regs->sr); + if ((idx_out < bytelen) && (status & SSP_SR_TNF)) + writel(((u8 *)dout)[idx_out++], &ssp0_regs->data); + if ((idx_in < bytelen) && (status & status & SSP_SR_RNE)) + ((u8 *)din)[idx_in++] = readl(&ssp0_regs->data); + if (get_timer(start_time) >= CONFIG_LPC32XX_SSP_TIMEOUT) + return -1; + } + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + /* do nothing */ +} + +void spi_free_slave(struct spi_slave *slave) +{ + /* do nothing */ +}

Signed-off-by: Albert ARIBAUD (3ADEV) albert.aribaud@3adev.fr ---

Changes in v2: - move boot image generation to mkimage framework

common/image.c | 1 + include/image.h | 1 + scripts/Makefile.spl | 9 +++ tools/Makefile | 1 + tools/lpc32xximage.c | 178 +++++++++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 190 insertions(+) create mode 100644 tools/lpc32xximage.c

diff --git a/common/image.c b/common/image.c index a911aa9..162b682 100644 --- a/common/image.c +++ b/common/image.c @@ -149,6 +149,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_MXSIMAGE, "mxsimage", "Freescale MXS Boot Image",}, { IH_TYPE_ATMELIMAGE, "atmelimage", "ATMEL ROM-Boot Image",}, { IH_TYPE_X86_SETUP, "x86_setup", "x86 setup.bin", }, + { IH_TYPE_LPC32XXIMAGE, "lpc32xximage", "LPC32XX Boot Image", }, { -1, "", "", }, };

diff --git a/include/image.h b/include/image.h index 0e6af00..3844be6 100644 --- a/include/image.h +++ b/include/image.h @@ -242,6 +242,7 @@ struct lmb; #define IH_TYPE_ATMELIMAGE 18 /* ATMEL ROM bootable Image */ #define IH_TYPE_SOCFPGAIMAGE 19 /* Altera SOCFPGA Preloader */ #define IH_TYPE_X86_SETUP 20 /* x86 setup.bin Image */ +#define IH_TYPE_LPC32XXIMAGE 21 /* x86 setup.bin Image */

/* * Compression Types diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index e4b9881..55d8b6f 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -147,6 +147,11 @@ endif boot.bin: $(obj)/u-boot-spl.bin $(call if_changed,mkimage)

+MKIMAGEFLAGS_lpc32xx-boot.bin = -T lpc32xximage -a $(CONFIG_SPL_TEXT_BASE) + +lpc32xx-boot.bin: $(obj)/u-boot-spl.bin + $(call if_changed,mkimage) + ALL-y += $(obj)/$(SPL_BIN).bin

ifdef CONFIG_SAMSUNG @@ -159,6 +164,10 @@ ALL-y += $(obj)/sunxi-spl.bin endif endif

+ifdef CONFIG_LPC32XX_SPL +ALL-y += lpc32xx-boot.bin +endif + ifeq ($(CONFIG_SYS_SOC),"at91") ALL-y += boot.bin endif diff --git a/tools/Makefile b/tools/Makefile index e4b23eb..c34c448 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -83,6 +83,7 @@ dumpimage-mkimage-objs := aisimage.o \ imximage.o \ kwbimage.o \ lib/md5.o \ + lpc32xximage.o \ mxsimage.o \ omapimage.o \ os_support.o \ diff --git a/tools/lpc32xximage.c b/tools/lpc32xximage.c new file mode 100644 index 0000000..6b3865f --- /dev/null +++ b/tools/lpc32xximage.c @@ -0,0 +1,178 @@ +/* + * Image manipulator for LPC32XX SoCs + * + * (C) Copyright 2015 DENX Software Engineering GmbH + * Written-by: Albert ARIBAUD albert.aribaud@3adev.fr + * + * Derived from omapimage.c: + * + * (C) Copyright 2010 + * Linaro LTD, www.linaro.org + * Author: John Rigby john.rigby@linaro.org + * Based on TI's signGP.c + * + * (C) Copyright 2009 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * (C) Copyright 2008 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar prafulla@marvell.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "imagetool.h" +#include <compiler.h> +#include <image.h> + +/* + * NAND page 0 boot header + */ + +struct nand_page_0_boot_header { + uint32_t data[129]; + uint32_t pad[383]; +}; + +/* + * Default ICC (interface configuration data [sic]) if none specified + * in board config + */ + +#ifndef LPC32XX_BOOT_ICR +#define LPC32XX_BOOT_ICR 0x00000096 +#endif + +/* + * Default boot NAND page size if none specified in board config + */ + +#ifndef LPC32XX_BOOT_NAND_PAGESIZE +#define LPC32XX_BOOT_NAND_PAGESIZE 2048 +#endif + +/* + * Default boot NAND pages per sector if none specified in board config + */ + +#ifndef LPC32XX_BOOT_NAND_PAGES_PER_SECTOR +#define LPC32XX_BOOT_NAND_PAGES_PER_SECTOR 64 +#endif + +/* + * Maximum size for boot code is 56K unless defined in board config + */ + +#ifndef LPC32XX_BOOT_CODESIZE +#define LPC32XX_BOOT_CODESIZE (56*1024) +#endif + +/* signature byte for a readable block */ + +#define LPC32XX_BOOT_BLOCK_OK 0xaa + +static struct nand_page_0_boot_header lpc32xximage_header; + +static int lpc32xximage_check_image_types(uint8_t type) +{ + if (type == IH_TYPE_LPC32XXIMAGE) + return EXIT_SUCCESS; + return EXIT_FAILURE; +} + +static int lpc32xximage_verify_header(unsigned char *ptr, int image_size, + struct image_tool_params *params) +{ + struct nand_page_0_boot_header *hdr = + (struct nand_page_0_boot_header *)ptr; + + /* turn image size from bytes to NAND pages, page 0 included */ + int image_size_in_pages = ((image_size - 1) + / LPC32XX_BOOT_NAND_PAGESIZE); + + if (hdr->data[0] != (0xff & LPC32XX_BOOT_ICR)) + return -1; + if (hdr->data[1] != (0xff & ~LPC32XX_BOOT_ICR)) + return -1; + if (hdr->data[2] != (0xff & LPC32XX_BOOT_ICR)) + return -1; + if (hdr->data[3] != (0xff & ~LPC32XX_BOOT_ICR)) + return -1; + if (hdr->data[4] != (0xff & image_size_in_pages)) + return -1; + if (hdr->data[5] != (0xff & ~image_size_in_pages)) + return -1; + if (hdr->data[6] != (0xff & image_size_in_pages)) + return -1; + if (hdr->data[7] != (0xff & ~image_size_in_pages)) + return -1; + if (hdr->data[8] != (0xff & image_size_in_pages)) + return -1; + if (hdr->data[9] != (0xff & ~image_size_in_pages)) + return -1; + if (hdr->data[10] != (0xff & image_size_in_pages)) + return -1; + if (hdr->data[11] != (0xff & ~image_size_in_pages)) + return -1; + if (hdr->data[12] != LPC32XX_BOOT_BLOCK_OK) + return -1; + if (hdr->data[128] != LPC32XX_BOOT_BLOCK_OK) + return -1; + return 0; +} + +static void print_hdr_byte(struct nand_page_0_boot_header *hdr, int ofs) +{ + printf("header[%d] = %02x\n", ofs, hdr->data[ofs]); +} + +static void lpc32xximage_print_header(const void *ptr) +{ + struct nand_page_0_boot_header *hdr = + (struct nand_page_0_boot_header *)ptr; + int ofs; + + for (ofs = 0; ofs <= 12; ofs++) + print_hdr_byte(hdr, ofs); + print_hdr_byte(hdr, 128); +} + +static void lpc32xximage_set_header(void *ptr, struct stat *sbuf, int ifd, + struct image_tool_params *params) +{ + struct nand_page_0_boot_header *hdr = + (struct nand_page_0_boot_header *)ptr; + + /* turn image size from bytes to NAND pages, page 0 included */ + int image_size_in_pages = ((sbuf->st_size + + LPC32XX_BOOT_NAND_PAGESIZE - 1) + / LPC32XX_BOOT_NAND_PAGESIZE); + + /* fill header -- default byte value is 0x00, not 0xFF */ + memset((void *)hdr, 0, sizeof(*hdr)); + hdr->data[0] = (hdr->data[2] = 0xff & LPC32XX_BOOT_ICR); + hdr->data[1] = (hdr->data[3] = 0xff & ~LPC32XX_BOOT_ICR); + hdr->data[4] = (hdr->data[6] = (hdr->data[8] + = (hdr->data[10] = 0xff & image_size_in_pages))); + hdr->data[5] = (hdr->data[7] = (hdr->data[9] + = (hdr->data[11] = 0xff & ~image_size_in_pages))); + hdr->data[12] = (hdr->data[128] = LPC32XX_BOOT_BLOCK_OK); +} + +/* + * lpc32xximage parameters + */ +U_BOOT_IMAGE_TYPE( + lpc32xximage, + "LPC32XX Boot Image", + sizeof(lpc32xximage_header), + (void *)&lpc32xximage_header, + NULL, + lpc32xximage_verify_header, + lpc32xximage_print_header, + lpc32xximage_set_header, + NULL, + lpc32xximage_check_image_types, + NULL, + NULL +);

Hi Albert,

please find some review comments below.

On 12.02.2015 18:37, Albert ARIBAUD (3ADEV) wrote:

Work_92105 from Work Microwave is an LPC3250- based board with the following features:

• 64MB SDR DRAM
• 1 GB SLC NAND, managed through MLC controller.
• Ethernet
• Ethernet + PHY SMSC8710
• I2C:
  • EEPROM (24M01-compatible)
  • RTC (DS1374-compatible)
  • Temperature sensor (DS620)
  • DACs (2 x MAX518)
• SPI (through SSP interface)
  • Port expander MAX6957
• LCD display (HD44780-compatible), controlled through the port expander and DACs

This board has SPL support, and uses the LPC32XX boot image format.

Signed-off-by: Albert ARIBAUD (3ADEV) albert.aribaud@3adev.fr

Changes in v2: None

arch/arm/Kconfig | 6 + arch/arm/cpu/arm926ejs/lpc32xx/Makefile | 2 + arch/arm/cpu/arm926ejs/lpc32xx/clk.c | 34 ++ arch/arm/cpu/arm926ejs/lpc32xx/cpu.c | 4 + arch/arm/cpu/arm926ejs/lpc32xx/dram.c | 80 +++++ arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S | 45 +++ arch/arm/include/asm/arch-lpc32xx/clk.h | 5 + arch/arm/include/asm/arch-lpc32xx/cpu.h | 1 + arch/arm/include/asm/arch-lpc32xx/mux.h | 18 ++ arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 4 +- board/work-microwave/work_92105/Kconfig | 15 + board/work-microwave/work_92105/MAINTAINERS | 6 + board/work-microwave/work_92105/Makefile | 8 + board/work-microwave/work_92105/README | 23 ++ board/work-microwave/work_92105/work_92105.c | 86 +++++ .../work-microwave/work_92105/work_92105_display.c | 349 +++++++++++++++++++++ .../work-microwave/work_92105/work_92105_display.h | 14 + configs/work_92105_defconfig | 5 + include/configs/work_92105.h | 259 +++++++++++++++ 19 files changed, 963 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/dram.c create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S create mode 100644 arch/arm/include/asm/arch-lpc32xx/mux.h create mode 100644 board/work-microwave/work_92105/Kconfig create mode 100644 board/work-microwave/work_92105/MAINTAINERS create mode 100644 board/work-microwave/work_92105/Makefile create mode 100644 board/work-microwave/work_92105/README create mode 100644 board/work-microwave/work_92105/work_92105.c create mode 100644 board/work-microwave/work_92105/work_92105_display.c create mode 100644 board/work-microwave/work_92105/work_92105_display.h create mode 100644 configs/work_92105_defconfig create mode 100644 include/configs/work_92105.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 47806f8..42983a3 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -247,6 +247,11 @@ config TARGET_DEVKIT3250 bool "Support devkit3250" select CPU_ARM926EJS

+config TARGET_WORK_92105

• bool "Support work_92105"
• select CPU_ARM926EJS
• select SUPPORT_SPL
• config TARGET_JADECPU bool "Support jadecpu" select CPU_ARM926EJS

@@ -999,6 +1004,7 @@ source "board/udoo/Kconfig" source "board/vpac270/Kconfig" source "board/wandboard/Kconfig" source "board/woodburn/Kconfig" +source "board/work-microwave/work_92105/Kconfig" source "board/xaeniax/Kconfig" source "board/zipitz2/Kconfig"

diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/Makefile b/arch/arm/cpu/arm926ejs/lpc32xx/Makefile index 314f004..4837377 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/Makefile +++ b/arch/arm/cpu/arm926ejs/lpc32xx/Makefile @@ -6,3 +6,5 @@ #

obj-y = cpu.o clk.o devices.o timer.o

+obj-$(CONFIG_SPL_BUILD) += dram.o lowlevel_init.o diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/clk.c b/arch/arm/cpu/arm926ejs/lpc32xx/clk.c index b7a44d5..1ef8a36 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/clk.c +++ b/arch/arm/cpu/arm926ejs/lpc32xx/clk.c @@ -98,6 +98,40 @@ unsigned int get_periph_clk_rate(void) return get_hclk_pll_rate() / get_periph_clk_div(); }

+unsigned int get_sdram_clk_rate(void) +{

• unsigned int src_clk;
• if (!(readl(&clk->pwr_ctrl) & CLK_PWR_NORMAL_RUN))

• return get_sys_clk_rate();
  

• src_clk = get_hclk_pll_rate();
• if (readl(&clk->sdramclk_ctrl) & CLK_SDRAM_DDR_SEL) {

• /* using DDR */
  

• switch (readl(&clk->hclkdiv_ctrl) & CLK_HCLK_DDRAM_MASK) {
  

• case CLK_HCLK_DDRAM_HALF:
  

• 	return src_clk/2;
  

• case CLK_HCLK_DDRAM_NOMINAL:
  

• 	return src_clk;
  

• default:
  

• 	return 0;
  

• }
  

• } else {

• /* using SDR */
  

• switch (readl(&clk->hclkdiv_ctrl) & CLK_HCLK_ARM_PLL_DIV_MASK) {
  

• case CLK_HCLK_ARM_PLL_DIV_4:
  

• 	return src_clk/4;
  

• case CLK_HCLK_ARM_PLL_DIV_2:
  

• 	return src_clk/2;
  

• case CLK_HCLK_ARM_PLL_DIV_1:
  

• 	return src_clk;
  

• default:
  

• 	return 0;
  

• }
  

• }

+}

• int get_serial_clock(void) { return get_periph_clk_rate();

diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c index eec4d9e..f4d7f02 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c +++ b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c @@ -9,6 +9,7 @@ #include <asm/arch/cpu.h> #include <asm/arch/clk.h> #include <asm/arch/wdt.h> +#include <asm/arch/sys_proto.h> #include <asm/io.h>

static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; @@ -33,6 +34,9 @@ void reset_cpu(ulong addr) #if defined(CONFIG_ARCH_CPU_INIT) int arch_cpu_init(void) { +#if defined(CONFIG_SPL_BUILD)

• ddr_init();

+#endif /* * It might be necessary to flush data cache, if U-boot is loaded * from kickstart bootloader, e.g. from S1L loader diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/dram.c b/arch/arm/cpu/arm926ejs/lpc32xx/dram.c new file mode 100644 index 0000000..606f49d --- /dev/null +++ b/arch/arm/cpu/arm926ejs/lpc32xx/dram.c @@ -0,0 +1,80 @@ +/*

• • LPC32xx dram init
• • (C) Copyright 2014 DENX Software Engineering GmbH
• • Written-by: Albert ARIBAUD albert.aribaud@3adev.fr
• • This is called by SPL to gain access to the SDR DRAM.
• • This code runs from SRAM.
• • Actual CONFIG_LPC32XX_SDRAM_* parameters must be provided
• • by the board configuration file.
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <netdev.h> +#include <asm/arch/cpu.h> +#include <asm/arch/clk.h> +#include <asm/arch/wdt.h> +#include <asm/arch/emc.h> +#include <asm/io.h>

+static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; +static struct emc_regs *emc = (struct emc_regs *)EMC_BASE;

+#if defined(CONFIG_SPL_BUILD)

Why don't you move this compiler switch to the Makefiles instead?

+void ddr_init(void) +{

• uint32_t ck;
• /* Enable EMC interface and choose little endian mode */
• emc->ctrl = 1;
• emc->config = 0;
• /* Select maximum EMC Dynamic Memory Refresh Time */
• emc->refresh = 0x7FF;
• /* Determine CLK */
• ck = get_sdram_clk_rate();
• /* Configure SDRAM */
• clk->sdramclk_ctrl = (CONFIG_LPC32XX_SDRAM_COMMAND_DELAY << 14);
• emc->config0 = CONFIG_LPC32XX_SDRAM_CONFIG0;
• emc->rascas0 = CONFIG_LPC32XX_SDRAM_RASCAS0;
• emc->read_config = CONFIG_LPC32XX_SDRAM_READ_CONFIG;
• /* Set timings */
• emc->t_rp = (ck / CONFIG_LPC32XX_SDRAM_T_RP) & 0x0000000F;
• emc->t_ras = (ck / CONFIG_LPC32XX_SDRAM_T_RAS) & 0x0000000F;
• emc->t_srex = (ck / CONFIG_LPC32XX_SDRAM_T_SREX) & 0x0000007F;
• emc->t_wr = (ck / CONFIG_LPC32XX_SDRAM_T_WR) & 0x0000000F;
• emc->t_rc = (ck / CONFIG_LPC32XX_SDRAM_T_RC) & 0x0000001F;
• emc->t_rfc = (ck / CONFIG_LPC32XX_SDRAM_T_RFC) & 0x0000001F;
• emc->t_xsr = (ck / CONFIG_LPC32XX_SDRAM_T_XSR) & 0x000000FF;
• emc->t_rrd = CONFIG_LPC32XX_SDRAM_T_RRD;
• emc->t_mrd = CONFIG_LPC32XX_SDRAM_T_MRD;
• emc->t_cdlr = CONFIG_LPC32XX_SDRAM_T_CDLR;
• /* Dynamic refresh */
• emc->refresh = (((ck / CONFIG_LPC32XX_SDRAM_REFRESH) >> 4) & 0x7FF);
• udelay(10);
• /* Force all clocks, enable inverted ck, issue NOP command */
• emc->control = 0x00000193;
• udelay(100);
• /* Keep all clocks enabled, issue a PRECHARGE ALL command */
• emc->control = 0x00000113;
• /* Fast dynamic refresh for at least a few SDRAM ck cycles */
• emc->refresh = (((128) >> 4) & 0x7FF);
• udelay(10);
• /* set correct dynamic refresh timing */
• emc->refresh = (((ck / CONFIG_LPC32XX_SDRAM_REFRESH) >> 4) & 0x7FF);
• udelay(10);
• /* set normal mode to CAS=3 */
• emc->control = 0x00000093;
• readl(EMC_DYCS0_BASE | CONFIG_LPC32XX_DRAM_MODE);
• /* set extended mode to all zeroes */
• emc->control = 0x00000093;
• readl(EMC_DYCS0_BASE | CONFIG_LPC32XX_DRAM_EMODE);
• /* stop forcing clocks, keep inverted clock, issue normal mode */
• emc->control = 0x00000010;

+} +#endif diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S b/arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S new file mode 100644 index 0000000..4b8053e --- /dev/null +++ b/arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S @@ -0,0 +1,45 @@ +/*

• • WORK Microwave work_92105 board low level init
• • (C) Copyright 2014 DENX Software Engineering GmbH
• • Written-by: Albert ARIBAUD albert.aribaud@3adev.fr
• • Low level init is called from SPL to set up the clocks.
• • On entry, the LPC3250 is in Direct Run mode with all clocks
• • running at 13 MHz; on exit, ARM clock is 208 MHz, HCLK is
• • 104 MHz and PCLK is 13 MHz.
• • This code must run from SRAM so that the clock changes do
• • not prevent it from executing.
• • SPDX-License-Identifier: GPL-2.0+
• */

+.globl lowlevel_init

+lowlevel_init:

• /* Set ARM, HCLK, PCLK dividers for normal mode */
• ldr r0, =0x0000003D
• ldr r1, =0x40004040
• str r0, [r1]
• /* Start HCLK PLL for 208 MHz */
• ldr r0, =0x0001401E
• ldr r1, =0x40004058
• str r0, [r1]
• /* wait for HCLK PLL to lock */

+1:

• ldr r0, [r1]
• ands r0, r0, #1
• beq 1b
• /* switch to normal mode */
• ldr r1, =0x40004044
• ldr r0, [r1]
• orr r0, #0x00000004
• str r0, [r1]
• /* Return to U-boot via saved link register */
• mov pc, lr

diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h b/arch/arm/include/asm/arch-lpc32xx/clk.h index 2cb5703..9449869 100644 --- a/arch/arm/include/asm/arch-lpc32xx/clk.h +++ b/arch/arm/include/asm/arch-lpc32xx/clk.h @@ -71,6 +71,7 @@ struct clk_pm_regs { };

/* HCLK Divider Control Register bits */ +#define CLK_HCLK_DDRAM_MASK (0x3 << 7) #define CLK_HCLK_DDRAM_HALF (0x2 << 7) #define CLK_HCLK_DDRAM_NOMINAL (0x1 << 7) #define CLK_HCLK_DDRAM_STOPPED (0x0 << 7) @@ -158,11 +159,15 @@ struct clk_pm_regs { /* SSP Clock Control Register bits */ #define CLK_SSP0_ENABLE_CLOCK (1 << 0)

+/* SDRAMCLK register bits */ +#define CLK_SDRAM_DDR_SEL (1 << 1)

• unsigned int get_sys_clk_rate(void); unsigned int get_hclk_pll_rate(void); unsigned int get_hclk_clk_div(void); unsigned int get_hclk_clk_rate(void); unsigned int get_periph_clk_div(void); unsigned int get_periph_clk_rate(void);

+unsigned int get_sdram_clk_rate(void);

#endif /* _LPC32XX_CLK_H */ diff --git a/arch/arm/include/asm/arch-lpc32xx/cpu.h b/arch/arm/include/asm/arch-lpc32xx/cpu.h index 1067107..0b5dca1 100644 --- a/arch/arm/include/asm/arch-lpc32xx/cpu.h +++ b/arch/arm/include/asm/arch-lpc32xx/cpu.h @@ -27,6 +27,7 @@ #define HS_UART7_BASE 0x4001C000 /* High speed UART 7 registers base */ #define RTC_BASE 0x40024000 /* RTC registers base */ #define GPIO_BASE 0x40028000 /* GPIO registers base */ +#define MUX_BASE 0x40028100 /* MUX registers base */ #define WDT_BASE 0x4003C000 /* Watchdog timer registers base */ #define TIMER0_BASE 0x40044000 /* Timer0 registers base */ #define TIMER1_BASE 0x4004C000 /* Timer1 registers base */ diff --git a/arch/arm/include/asm/arch-lpc32xx/mux.h b/arch/arm/include/asm/arch-lpc32xx/mux.h new file mode 100644 index 0000000..dc1b5bc --- /dev/null +++ b/arch/arm/include/asm/arch-lpc32xx/mux.h @@ -0,0 +1,18 @@ +/*

• • LPC32xx MUX interface
• • (C) Copyright 2015 DENX Software Engineering GmbH
• • Written-by: Albert ARIBAUD albert.aribaud@3adev.fr
• • SPDX-License-Identifier: GPL-2.0+
• */

+/**

• • MUX register map for LPC32xx
• */

+struct mux_regs {

• u32 p_mux_set;
• u32 p_mux_clr;
• u32 p_mux_state;

+}; diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h index 86d5ee9..edcc4bc 100644 --- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h +++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h @@ -12,5 +12,7 @@ void lpc32xx_mac_init(void); void lpc32xx_mlc_nand_init(void); void lpc32xx_i2c_init(unsigned int devnum); void lpc32xx_ssp_init(void);

+#if defined(CONFIG_SPL_BUILD) +void ddr_init(void); +#endif #endif /* _LPC32XX_SYS_PROTO_H */ diff --git a/board/work-microwave/work_92105/Kconfig b/board/work-microwave/work_92105/Kconfig new file mode 100644 index 0000000..74f004f --- /dev/null +++ b/board/work-microwave/work_92105/Kconfig @@ -0,0 +1,15 @@ +if TARGET_WORK_92105

+config SYS_BOARD

• default "work_92105"

+config SYS_VENDOR

• default "work-microwave"

+config SYS_SOC

• default "lpc32xx"

+config SYS_CONFIG_NAME

• default "work_92105"

+endif diff --git a/board/work-microwave/work_92105/MAINTAINERS b/board/work-microwave/work_92105/MAINTAINERS new file mode 100644 index 0000000..29a92c5 --- /dev/null +++ b/board/work-microwave/work_92105/MAINTAINERS @@ -0,0 +1,6 @@ +WORK_92105 BOARD +M: Albert ARIBAUD albert.aribaud@3adev.fr +S: Maintained +F: board/work-microwave/work_92105/ +F: include/configs/work_92105.h +F: configs/work_92105_defconfig diff --git a/board/work-microwave/work_92105/Makefile b/board/work-microwave/work_92105/Makefile new file mode 100644 index 0000000..853dea9 --- /dev/null +++ b/board/work-microwave/work_92105/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2014 DENX Software Engineering GmbH +# Written-by: Albert ARIBAUD albert.aribaud@3adev.fr +# +# SPDX-License-Identifier: GPL-2.0+ +#

+obj-y := work_92105.o work_92105_display.o diff --git a/board/work-microwave/work_92105/README b/board/work-microwave/work_92105/README new file mode 100644 index 0000000..091d731 --- /dev/null +++ b/board/work-microwave/work_92105/README @@ -0,0 +1,23 @@ +Work_92105 from Work Microwave is an LPC3250- based board with the +following features:

• • 64MB SDR DRAM
• • 1 GB SLC NAND, managed through MLC controller.
• • Ethernet
• • Ethernet + PHY SMSC8710
• • I2C:

•  - EEPROM (24M01-compatible)
  

•  - RTC (DS1374-compatible)
  

•  - Temperature sensor (DS620)
  

•  - DACs (2 x MAX518)
  

• • SPI (through SSP interface)

•  - Port expander MAX6957
  

• • LCD display (HD44780-compatible), controlled

•  through the port expander and DACs
  

+This board has SPL support, and uses the LPC32XX boot image format. +Once the U-Boot target "work_92105" is built, the following two files +can be flashed:

• spl/lpc32xx-spl.bin at offset 0x0
• u-boot.bin at offset 0x40000

Really u-boot.bin? Why don't you use u-boot.img with the header / CRC instead? This is commonly used by other SPL platforms.

And wouldn't it be nice to combine (concatenate) those two images into one image that can be flashed to the board? There are already some Makefile rules for doing this.

diff --git a/board/work-microwave/work_92105/work_92105.c b/board/work-microwave/work_92105/work_92105.c new file mode 100644 index 0000000..cad0d75 --- /dev/null +++ b/board/work-microwave/work_92105/work_92105.c @@ -0,0 +1,86 @@ +/*

• • WORK Microwave work_92105 board support
• • (C) Copyright 2014 DENX Software Engineering GmbH
• • Written-by: Albert ARIBAUD albert.aribaud@3adev.fr
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/cpu.h> +#include <asm/arch/emc.h> +#include <asm/gpio.h> +#include <spl.h> +#include "work_92105_display.h"

+DECLARE_GLOBAL_DATA_PTR;

+#if defined(CONFIG_SPL_BUILD)

I would perfer to move those SPL related function into a seperate file (e.g. spl.c) instead. And the Makefile can handle the conditional compilation then.

+void spl_board_init(void) +{

• /* initialize serial port for console */
• lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
• /* initialize console */
• preloader_console_init();
• /* init DDR and NAND to chainload U-Boot */
• ddr_init();
• lpc32xx_mlc_nand_init();

+}

+#else /* ! defined(CONFIG_SPL_BUILD) */

+int board_early_init_f(void) +{

• /* initialize serial port for console */
• lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART);
• /* enable I2C, SSP, MAC, NAND */
• lpc32xx_i2c_init(1); /* only I2C1 has devices, I2C2 has none */
• lpc32xx_ssp_init();
• lpc32xx_mac_init();
• lpc32xx_mlc_nand_init();
• /* Display must wait until after relocation and devices init */
• return 0;

+}

+#define GPO_19 115

+int board_early_init_r(void) +{

• /* Set NAND !WP to 1 through GPO_19 */
• gpio_request(GPO_19, "NAND_nWP");
• gpio_direction_output(GPO_19, 1);
• /* initialize display */
• work_92105_display_init();
• return 0;

+}

+#endif /* CONFIG_SPL_BUILD */

+int board_init(void) +{

• /* adress of boot parameters */
• gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
• return 0;

+}

+int dram_init(void) +{

• gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,

• 		    CONFIG_SYS_SDRAM_SIZE);
  

• return 0;

+}

+#if defined(CONFIG_SPL_BUILD) +u32 spl_boot_device(void) +{

• return BOOT_DEVICE_NAND;

+} +#endif diff --git a/board/work-microwave/work_92105/work_92105_display.c b/board/work-microwave/work_92105/work_92105_display.c new file mode 100644 index 0000000..c8b1013 --- /dev/null +++ b/board/work-microwave/work_92105/work_92105_display.c @@ -0,0 +1,349 @@ +/*

• • work_92105 display support
• • (C) Copyright 2014 DENX Software Engineering GmbH
• • Written-by: Albert ARIBAUD albert.aribaud@3adev.fr
• • The work_92105 display is a HD44780-compatible module
• • controlled through a MAX6957AAX SPI port expander, two
• • MAX518 I2C DACs and native LPC32xx GPO 15.
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/cpu.h> +#include <asm/arch/emc.h> +#include <asm/gpio.h> +#include <spi.h> +#include <i2c.h> +#include <version.h> +#include <vsprintf.h>

+/*

• • GPO 15 in port 3 is gpio 3*32+15 = 111
• */

+#define GPO_15 111

+/**

• • MAX6957AAX registers that we will be using
• */

+#define MAX6957_CONF 0x04

+#define MAX6957_CONF_08_11 0x0A +#define MAX6957_CONF_12_15 0x0B +#define MAX6957_CONF_16_19 0x0C

+/**

• • Individual gpio ports (one per gpio) to HD44780
• */

+#define MAX6957AAX_HD44780_RS 0x29 +#define MAX6957AAX_HD44780_R_W 0x2A +#define MAX6957AAX_HD44780_EN 0x2B +#define MAX6957AAX_HD44780_DATA 0x4C

+/**

• • Display controller instructions
• */

+/* Function set: eight bits, two lines, 8-dot font */ +#define HD44780_FUNCTION_SET 0x38

+/* Display ON / OFF: turn display on */ +#define HD44780_DISPLAY_ON_OFF_CONTROL 0x0C

+/* Entry mode: increment */ +#define HD44780_ENTRY_MODE_SET 0x06

+/* Clear */ +#define HD44780_CLEAR_DISPLAY 0x01

+/* Set DDRAM addr (to be ORed with exact address) */ +#define HD44780_SET_DDRAM_ADDR 0x80

+/* Set CGRAM addr (to be ORed with exact address) */ +#define HD44780_SET_CGRAM_ADDR 0x40

+/**

• • Default value for contrats
• */

+#define CONTRAST_DEFAULT 25

+/**

• • Define slave as a module-wide local to save passing it around,
• • plus we will need it after init for the "hd44780" command.
• */

+static struct spi_slave *slave;

+/*

• • Write a value into a MAX6957AAX register.
• */

+static void max6957aax_write(uint8_t reg, uint8_t value) +{

• uint8_t dout[2];
• dout[0] = reg;
• dout[1] = value;
• gpio_set_value(GPO_15, 0);
• /* do SPI read/write (passing din==dout is OK) */
• spi_xfer(slave, 16, dout, dout, SPI_XFER_BEGIN | SPI_XFER_END);
• gpio_set_value(GPO_15, 1);

+}

+/*

• • Read a value from a MAX6957AAX register.
• • According to the MAX6957AAX datasheet, we should release the chip
• • select halfway through the read sequence, when the actual register
• • value is read; but the WORK_92105 hardware prevents the MAX6957AAX
• • SPI OUT from reaching the LPC32XX SIP MISO if chip is not selected.
• • so let's release the CS an hold it again while reading the result.
• */

+static uint8_t max6957aax_read(uint8_t reg) +{

• uint8_t dout[2], din[2];
• /* send read command */
• dout[0] = reg | 0x80; /* set bit 7 to indicate read */
• dout[1] = 0;
• gpio_set_value(GPO_15, 0);
• /* do SPI read/write (passing din==dout is OK) */
• spi_xfer(slave, 16, dout, dout, SPI_XFER_BEGIN | SPI_XFER_END);
• /* latch read command */
• gpio_set_value(GPO_15, 1);
• /* read register -- din = noop on xmit, din[1] = reg on recv */
• din[0] = 0;
• din[1] = 0;
• gpio_set_value(GPO_15, 0);
• /* do SPI read/write (passing din==dout is OK) */
• spi_xfer(slave, 16, din, din, SPI_XFER_BEGIN | SPI_XFER_END);
• /* end of read. */
• gpio_set_value(GPO_15, 1);
• return din[1];

+}

+static void hd44780_instruction(unsigned long instruction) +{

• max6957aax_write(MAX6957AAX_HD44780_RS, 0);
• max6957aax_write(MAX6957AAX_HD44780_R_W, 0);
• max6957aax_write(MAX6957AAX_HD44780_EN, 1);
• max6957aax_write(MAX6957AAX_HD44780_DATA, instruction);
• max6957aax_write(MAX6957AAX_HD44780_EN, 0);
• /* HD44780 takes 37 us for most instructions, 1520 for clear */
• if (instruction == HD44780_CLEAR_DISPLAY)

• udelay(2000);
  

• else

• udelay(100);
  

+}

+static void hd44780_write_char(char c) +{

• max6957aax_write(MAX6957AAX_HD44780_RS, 1);
• max6957aax_write(MAX6957AAX_HD44780_R_W, 0);
• max6957aax_write(MAX6957AAX_HD44780_EN, 1);
• max6957aax_write(MAX6957AAX_HD44780_DATA, c);
• max6957aax_write(MAX6957AAX_HD44780_EN, 0);
• /* HD44780 takes 37 us to write to DDRAM or CGRAM */
• udelay(100);

+}

+static void hd44780_write_str(char *s) +{

• max6957aax_write(MAX6957AAX_HD44780_RS, 1);
• max6957aax_write(MAX6957AAX_HD44780_R_W, 0);
• while (*s) {

• max6957aax_write(MAX6957AAX_HD44780_EN, 1);
  

• max6957aax_write(MAX6957AAX_HD44780_DATA, *s);
  

• max6957aax_write(MAX6957AAX_HD44780_EN, 0);
  

• s++;
  

• /* HD44780 takes 37 us to write to DDRAM or CGRAM */
  

• udelay(100);
  

• }

+}

+/*

• • Existing user code might expect these custom characters to be
• • recognized and displayed on the LCD
• */

+static u8 char_gen_chars[] = {

• /* #8, empty rectangle */
• 0x1F, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x1F,
• /* #9, filled right arrow */
• 0x10, 0x18, 0x1C, 0x1E, 0x1C, 0x18, 0x10, 0x00,
• /* #10, filled left arrow */
• 0x01, 0x03, 0x07, 0x0F, 0x07, 0x03, 0x01, 0x00,
• /* #11, up and down arrow */
• 0x04, 0x0E, 0x1F, 0x00, 0x00, 0x1F, 0x0E, 0x04,
• /* #12, plus/minus */
• 0x04, 0x04, 0x1F, 0x04, 0x04, 0x00, 0x1F, 0x00,
• /* #13, fat exclamation mark */
• 0x06, 0x06, 0x06, 0x06, 0x00, 0x06, 0x06, 0x00,
• /* #14, empty square */
• 0x00, 0x1F, 0x11, 0x11, 0x11, 0x1F, 0x00, 0x00,
• /* #15, struck out square */
• 0x00, 0x1F, 0x19, 0x15, 0x13, 0x1F, 0x00, 0x00,

+};

+static void hd44780_init_char_gen(void) +{

• int i;
• hd44780_instruction(HD44780_SET_CGRAM_ADDR);
• for (i = 0; i < sizeof(char_gen_chars); i++)

• hd44780_write_char(char_gen_chars[i]);
  

• hd44780_instruction(HD44780_SET_DDRAM_ADDR);

+}

+void work_92105_display_init(void) +{

• int claim_err;
• char *display_contrast_str;
• uint8_t display_contrast = CONTRAST_DEFAULT;
• uint8_t enable_backlight = 0x96;
• slave = spi_setup_slave(0, 0, 500000, 0);
• if (!slave) {

• printf("Failed to set up SPI slave\n");
  

• return;
  

• }
• claim_err = spi_claim_bus(slave);
• if (claim_err)

• debug("Failed to claim SPI bus: %d\n", claim_err);
  

• /* enable backlight */
• i2c_write(0x2c, 0x01, 1, &enable_backlight, 1);
• /* set display contrast */
• display_contrast_str = getenv("fwopt_dispcontrast");
• if (display_contrast_str)

• display_contrast = simple_strtoul(display_contrast_str,
  

• 	NULL, 10);
  

• i2c_write(0x2c, 0x00, 1, &display_contrast, 1);
• /* request GPO_15 as an output initially set to 1 */
• gpio_request(GPO_15, "MAX6957_nCS");
• gpio_direction_output(GPO_15, 1);
• /* enable MAX6957 portexpander */
• max6957aax_write(MAX6957_CONF, 0x01);
• /* configure pin 8 as input, pins 9..19 as outputs */
• max6957aax_write(MAX6957_CONF_08_11, 0x56);
• max6957aax_write(MAX6957_CONF_12_15, 0x55);
• max6957aax_write(MAX6957_CONF_16_19, 0x55);
• /* initialize HD44780 */
• max6957aax_write(MAX6957AAX_HD44780_EN, 0);
• hd44780_instruction(HD44780_FUNCTION_SET);
• hd44780_instruction(HD44780_DISPLAY_ON_OFF_CONTROL);
• hd44780_instruction(HD44780_ENTRY_MODE_SET);
• /* write custom character glyphs */
• hd44780_init_char_gen();
• /* Show U-Boot version, date and time as a sign-of-life */
• hd44780_instruction(HD44780_CLEAR_DISPLAY);
• hd44780_instruction(HD44780_SET_DDRAM_ADDR | 0);
• hd44780_write_str(U_BOOT_VERSION);
• hd44780_instruction(HD44780_SET_DDRAM_ADDR | 64);
• hd44780_write_str(U_BOOT_DATE);
• hd44780_instruction(HD44780_SET_DDRAM_ADDR | 64 | 20);
• hd44780_write_str(U_BOOT_TIME);

+}

+#ifdef CONFIG_CMD_MAX6957

+static int do_max6957aax(cmd_tbl_t *cmdtp, int flag, int argc,

• 	 char *const argv[])
  

+{

• int reg, val;
• if (argc != 3)

• return CMD_RET_USAGE;
  

• switch (argv[1][0]) {
• case 'r':
• case 'R':

• reg = simple_strtoul(argv[2], NULL, 0);
  

• val = max6957aax_read(reg);
  

• printf("MAX6957 reg 0x%02x read 0x%02x\n", reg, val);
  

• return 0;
  

• default:

• reg = simple_strtoul(argv[1], NULL, 0);
  

• val = simple_strtoul(argv[2], NULL, 0);
  

• max6957aax_write(reg, val);
  

• printf("MAX6957 reg 0x%02x wrote 0x%02x\n", reg, val);
  

• return 0;
  

• }
• return 1;

+}

+#ifdef CONFIG_SYS_LONGHELP +static char max6957aax_help_text[] =

• "max6957aax - write or read display register:\n"

• "\tmax6957aax R|r reg - read display register;\n"
  

• "\tmax6957aax reg val - write display register.";
  

+#endif

+U_BOOT_CMD(

• max6957aax, 6, 1, do_max6957aax,
• "SPI MAX6957 display write/read",
• max6957aax_help_text

+); +#endif /* CONFIG_CMD_MAX6957 */

+#ifdef CONFIG_CMD_HD44760

+/*

• • We need the HUSH parser because we need string arguments, and
• • only HUSH can understand them.
• */

+#if !defined(CONFIG_SYS_HUSH_PARSER) +#error CONFIG_CMD_HD44760 requires CONFIG_SYS_HUSH_PARSER +#endif

+static int do_hd44780(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{

• char *cmd;
• if (argc != 3)

• return CMD_RET_USAGE;
  

• cmd = argv[1];
• if (strcasecmp(cmd, "cmd") == 0)

• hd44780_instruction(simple_strtol(argv[2], NULL, 0));
  

• else if (strcasecmp(cmd, "data") == 0)

• hd44780_write_char(simple_strtol(argv[2], NULL, 0));
  

• else if (strcasecmp(cmd, "str") == 0)

• hd44780_write_str(argv[2]);
  

• return 0;

+}

+#ifdef CONFIG_SYS_LONGHELP +static char hd44780_help_text[] =

• "hd44780 - control LCD driver:\n"

• "\thd44780 cmd <val> - send command <val> to driver;\n"
  

• "\thd44780 data <val> - send data <val> to driver;\n"
  

• "\thd44780 str \"<text>\" - send \"<text>\" to driver.";
  

+#endif

+U_BOOT_CMD(

• hd44780, 6, 1, do_hd44780,
• "HD44780 LCD driver control",
• hd44780_help_text

+); +#endif /* CONFIG_CMD_HD44780 */ diff --git a/board/work-microwave/work_92105/work_92105_display.h b/board/work-microwave/work_92105/work_92105_display.h new file mode 100644 index 0000000..dd6e768 --- /dev/null +++ b/board/work-microwave/work_92105/work_92105_display.h @@ -0,0 +1,14 @@ +/*

• • work_92105 display support interface
• • (C) Copyright 2014 DENX Software Engineering GmbH
• • Written-by: Albert ARIBAUD albert.aribaud@3adev.fr
• • The work_92105 display is a HD44780-compatible module
• • controlled through a MAX6957AAX SPI port expander, two
• • MAX518 I2C DACs and native LPC32xx GPO 15.
• • SPDX-License-Identifier: GPL-2.0+
• */

+void work_92105_display_init(void); diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig new file mode 100644 index 0000000..9be52a8 --- /dev/null +++ b/configs/work_92105_defconfig @@ -0,0 +1,5 @@ +CONFIG_DM=y +CONFIG_DM_GPIO=y +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_WORK_92105=y diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h new file mode 100644 index 0000000..fd242fb --- /dev/null +++ b/include/configs/work_92105.h @@ -0,0 +1,259 @@ +/*

• • WORK Microwave work_92105 board configuration file
• • (C) Copyright 2014 DENX Software Engineering GmbH
• • Written-by: Albert ARIBAUD albert.aribaud@3adev.fr
• • SPDX-License-Identifier: GPL-2.0+
• */

+#ifndef __CONFIG_WORK_92105_H__ +#define __CONFIG_WORK_92105_H__

+/* SoC and board defines */ +#include <linux/sizes.h> +#include <asm/arch/cpu.h>

+/*

• • Define work_92105 machine type by hand -- done only for compatibility
• • with original board code
• */

+#define MACH_TYPE_WORK_92105 736 +#define CONFIG_MACH_TYPE MACH_TYPE_WORK_92105

+#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF +#if !defined(CONFIG_SPL_BUILD) +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R

+/* generate LPC32XX-specific SPL image */ +#define CONFIG_LPC32XX_SPL

+/*

• • Memory configurations
• */

+#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_MALLOC_LEN SZ_1M +#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE +#define CONFIG_SYS_SDRAM_SIZE SZ_64M +#define CONFIG_SYS_TEXT_BASE 0x80100000 +#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K) +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M)

+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K)

+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \

• 			 - GENERATED_GBL_DATA_SIZE)
  

+/*

• • Serial Driver
• */

+#define CONFIG_SYS_LPC32XX_UART 5 /* UART5 - NS16550 */ +#define CONFIG_BAUDRATE 115200

+/*

• • Ethernet Driver
• */

+#define CONFIG_PHY_SMSC +#define CONFIG_LPC32XX_ETH +#define CONFIG_PHYLIB +#define CONFIG_PHY_ADDR 0 +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +/* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */

+/*

• • I2C driver
• */

+#define CONFIG_SYS_I2C_LPC32XX +#define CONFIG_SYS_I2C +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_SPEED 350000

+/*

• • I2C EEPROM
• */

+#define CONFIG_CMD_EEPROM +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x56 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2

+/*

• • I2C RTC
• */

+#define CONFIG_CMD_DATE +#define CONFIG_RTC_DS1374

+/*

• • I2C Temperature Sensor (DTT)
• */

+#define CONFIG_CMD_DTT +#define CONFIG_DTT_SENSORS { 0, 1 } +#define CONFIG_DTT_DS620

+/*

• • U-Boot General Configurations
• */

+#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_PBSIZE \

• (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)

+#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE

+#define CONFIG_SYS_HUSH_PARSER

+#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_VERSION_VARIABLE +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DOS_PARTITION

+#define CONFIG_CMD_DM

+/*

• • No NOR
• */

+#define CONFIG_SYS_NO_FLASH

+/*

• • NAND chip timings for FIXME: which one?
• */

+#define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333 +#define CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000 +#define CONFIG_LPC32XX_NAND_MLC_NAND_TA 18181818 +#define CONFIG_LPC32XX_NAND_MLC_RD_HIGH 31250000 +#define CONFIG_LPC32XX_NAND_MLC_RD_LOW 45454545 +#define CONFIG_LPC32XX_NAND_MLC_WR_HIGH 40000000 +#define CONFIG_LPC32XX_NAND_MLC_WR_LOW 83333333

+/*

• • NAND
• */

+/* driver configuration */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE MLC_NAND_BASE +#define CONFIG_NAND_LPC32XX_MLC

+#define CONFIG_CMD_NAND

+/*

• • GPIO
• */

+#define CONFIG_CMD_GPIO +#define CONFIG_LPC32XX_GPIO

+/*

• • SSP/SPI/DISPLAY
• */

+#define CONFIG_CMD_SPI +#define CONFIG_LPC32XX_SSP +#define CONFIG_LPC32XX_SSP_TIMEOUT 100000 +#define CONFIG_CMD_MAX6957 +#define CONFIG_CMD_HD44760 +/*

• • Environment
• */

+#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_SIZE 0x00020000 +#define CONFIG_ENV_OFFSET 0x00100000 +#define CONFIG_ENV_OFFSET_REDUND 0x00120000 +#define CONFIG_ENV_ADDR 0x80000100 +/* provide default ethernet address */ +#define CONFIG_ETHADDR 00:12:B4:00:AF:FE +#define CONFIG_OVERWRITE_ETHADDR_ONCE

We usually don't allow MAC addresses to be set in the board config files. Is this really needed?

Thanks, Stefan

On 12 February 2015 at 23:07, Albert ARIBAUD (3ADEV) albert.aribaud@3adev.fr wrote:

Signed-off-by: Albert ARIBAUD (3ADEV) albert.aribaud@3adev.fr

Changes in v2:

• added MUX setting for SSP0

arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 14 +++ arch/arm/include/asm/arch-lpc32xx/clk.h | 3 + arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 + drivers/spi/Makefile | 1 + drivers/spi/lpc32xx_ssp.c | 132 ++++++++++++++++++++++++++ 5 files changed, 151 insertions(+) create mode 100644 drivers/spi/lpc32xx_ssp.c

diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c index a407098..5a453e3 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c +++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c @@ -8,11 +8,13 @@ #include <asm/arch/cpu.h> #include <asm/arch/clk.h> #include <asm/arch/uart.h> +#include <asm/arch/mux.h> #include <asm/io.h> #include <dm.h>

static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE; +static struct mux_regs *mux = (struct mux_regs *)MUX_BASE;

void lpc32xx_uart_init(unsigned int uart_id) { @@ -66,3 +68,15 @@ void lpc32xx_i2c_init(unsigned int devnum) U_BOOT_DEVICE(lpc32xx_gpios) = { .name = "gpio_lpc32xx" };

+/* Mux for SCK0, MISO0, MOSI0. We do not use SSEL0. */

+#define P_MUX_SET_SSP0 0x1600

+void lpc32xx_ssp_init(void) +{

•   /* Enable SSP0 interface */
  

•   writel(CLK_SSP0_ENABLE_CLOCK, &clk->ssp_ctrl);
  

•   /* Mux SSP0 pins */
  

•   writel(P_MUX_SET_SSP0, &mux->p_mux_set);
  

+} diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h b/arch/arm/include/asm/arch-lpc32xx/clk.h index 781ac07..2cb5703 100644 --- a/arch/arm/include/asm/arch-lpc32xx/clk.h +++ b/arch/arm/include/asm/arch-lpc32xx/clk.h @@ -155,6 +155,9 @@ struct clk_pm_regs { #define CLK_NAND_MLC (1 << 1) #define CLK_NAND_MLC_INT (1 << 5)

+/* SSP Clock Control Register bits */ +#define CLK_SSP0_ENABLE_CLOCK (1 << 0)

unsigned int get_sys_clk_rate(void); unsigned int get_hclk_pll_rate(void); unsigned int get_hclk_clk_div(void); diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h index a4a05d1..86d5ee9 100644 --- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h +++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h @@ -11,5 +11,6 @@ void lpc32xx_uart_init(unsigned int uart_id); void lpc32xx_mac_init(void); void lpc32xx_mlc_nand_init(void); void lpc32xx_i2c_init(unsigned int devnum); +void lpc32xx_ssp_init(void);

#endif /* _LPC32XX_SYS_PROTO_H */ diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index edbd520..ce6f1cc 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o obj-$(CONFIG_FTSSP010_SPI) += ftssp010_spi.o obj-$(CONFIG_ICH_SPI) += ich.o obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o +obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o obj-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o obj-$(CONFIG_MXC_SPI) += mxc_spi.o diff --git a/drivers/spi/lpc32xx_ssp.c b/drivers/spi/lpc32xx_ssp.c new file mode 100644 index 0000000..40270df --- /dev/null +++ b/drivers/spi/lpc32xx_ssp.c @@ -0,0 +1,132 @@ +/*

• • LPC32xx SSP interface (SPI mode)
• • (C) Copyright 2014 DENX Software Engineering GmbH
• • Written-by: Albert ARIBAUD albert.aribaud@3adev.fr
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <linux/compat.h> +#include <asm/io.h> +#include <malloc.h> +#include <spi.h> +#include <asm/arch/clk.h>

+/* SSP chip registers */ +struct ssp_regs {

•   u32 cr0;
  

•   u32 cr1;
  

•   u32 data;
  

•   u32 sr;
  

•   u32 cpsr;
  

•   u32 imsc;
  

•   u32 ris;
  

•   u32 mis;
  

•   u32 icr;
  

•   u32 dmacr;
  

+};

+/* CR1 register defines */ +#define SSP_CR1_SSP_ENABLE 0x0002

+/* SR register defines */ +#define SSP_SR_TNF 0x0002 +/* SSP status RX FIFO not empty bit */ +#define SSP_SR_RNE 0x0004

+static struct ssp_regs *ssp0_regs = (struct ssp_regs *)SSP0_BASE;

Pls- use static inline instead of direct macro assignment.

+static struct spi_slave ssp0_slave = {

•   .bus = 0,
  

•   .cs = 0,
  

•   .op_mode_rx = 0,
  

•   .op_mode_tx = 0,
  

•   .wordlen = 8,
  

•   .max_write_size = 1, /* this is for SPI FLASHes -- don't care */
  

•   .memory_map = NULL, /* for SPI FLASHes too */
  

•   .option = 0,
  

•   .flags = 0
  

+};

This wouldn't require - spi_alloc_slave() is a generic func to do all the stuff. See comments below...

+/* spi_init is called during boot when CONFIG_CMD_SPI is defined */ +void spi_init(void) +{

•   /*
  

•    *  nothing to do: clocking was enabled in lpc32xx_ssp_enable()
  

•    * and configuration will be done in spi_setup_slave()
  

•   */
  

+}

+/* the following is called in sequence by do_spi_xfer() */

+struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode) +{

Define spi_cs_is_valid() that wikk ensure the controlling bus and cs options command prompt

use spi_alloc_slave() and members will be having reg_base and slave that's. See drivers/spi/zynq_spi.c for more info.

Suggested code: static struct ssp0_spi_slave { struct spi_slave slave; struct ssp_regs *base; };

static inline struct ssp0_regs *get_ssp0_spi_base(void) { return (struct ssp0_regs *) SSP0_BASE; }

in spi_setup_slave()

{ struct ssp0_spi_slave *ssp0;

/* valid bus and cs */

/* allocate */ ssp0 = spi_alloc_slave(struct ssp0_spi_slave, bus, cs);

ssp0->base = get_ssp0_spi_base();

}

•   /* we only set up SSP0 for now, so ignore bus */
  

•   if (mode & SPI_3WIRE) {
  

•           error("3-wire mode not supported");
  

•           return NULL;
  

•   }
  

•   if (mode & SPI_SLAVE) {
  

•           error("slave mode not supported\n");
  

•           return NULL;
  

•   }
  

•   if (mode & SPI_PREAMBLE) {
  

•           error("preamble byte skipping not supported\n");
  

•           return NULL;
  

•   }
  

•   /*
  

•    * 8 bit frame, SPI fmt, 500kbps -> clock divider is 26.
  

•    * Set SCR to 0 and CPSDVSR to 26.
  

•    */
  

•   writel(0x7, &ssp0_regs->cr0); /* 8-bit chunks, SPI, 1 clk/bit */
  

•   writel(26, &ssp0_regs->cpsr); /* SSP clock = HCLK/26 = 500kbps */
  

•   writel(0, &ssp0_regs->imsc); /* do not raise any interrupts */
  

•   writel(0, &ssp0_regs->icr); /* clear any pending interrupt */
  

•   writel(0, &ssp0_regs->dmacr); /* do not do DMAs */
  

•   writel(SSP_CR1_SSP_ENABLE, &ssp0_regs->cr1); /* enable SSP0 */
  

•   return &ssp0_slave;
  

+}

+int spi_claim_bus(struct spi_slave *slave) +{

•   /* only one bus and slave so far, always available */
  

•   return 0;
  

+}

+int spi_xfer(struct spi_slave *slave, unsigned int bitlen,

•   const void *dout, void *din, unsigned long flags)
  

+{

•   int bytelen = bitlen >> 3;
  

•   int idx_out = 0;
  

•   int idx_in = 0;
  

•   int start_time;
  

•   start_time = get_timer(0);
  

•   while ((idx_out < bytelen) || (idx_in < bytelen)) {
  

•           int status = readl(&ssp0_regs->sr);
  

•           if ((idx_out < bytelen) && (status & SSP_SR_TNF))
  

•                   writel(((u8 *)dout)[idx_out++], &ssp0_regs->data);
  

•           if ((idx_in < bytelen) && (status & status & SSP_SR_RNE))
  

•                   ((u8 *)din)[idx_in++] = readl(&ssp0_regs->data);
  

•           if (get_timer(start_time) >= CONFIG_LPC32XX_SSP_TIMEOUT)
  

•                   return -1;
  

•   }
  

•   return 0;
  

+}

+void spi_release_bus(struct spi_slave *slave) +{

•   /* do nothing */
  

+}

+void spi_free_slave(struct spi_slave *slave) +{

•   /* do nothing */
  

+}

2.1.0

thanks!

Hi Albert,

On 17 February 2015 at 15:21, Albert ARIBAUD albert.aribaud@3adev.fr wrote:

Bonjour Jagan,

Le Tue, 17 Feb 2015 15:03:16 +0530, Jagan Teki jagannadh.teki@gmail.com a écrit :

...

On 12 February 2015 at 23:07, Albert ARIBAUD (3ADEV) albert.aribaud@3adev.fr wrote:

...

Signed-off-by: Albert ARIBAUD (3ADEV) albert.aribaud@3adev.fr

Changes in v2:

• added MUX setting for SSP0

arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 14 +++ arch/arm/include/asm/arch-lpc32xx/clk.h | 3 + arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 + drivers/spi/Makefile | 1 + drivers/spi/lpc32xx_ssp.c | 132 ++++++++++++++++++++++++++ 5 files changed, 151 insertions(+) create mode 100644 drivers/spi/lpc32xx_ssp.c

diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c index a407098..5a453e3 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c +++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c @@ -8,11 +8,13 @@ #include <asm/arch/cpu.h> #include <asm/arch/clk.h> #include <asm/arch/uart.h> +#include <asm/arch/mux.h> #include <asm/io.h> #include <dm.h>

static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE; +static struct mux_regs *mux = (struct mux_regs *)MUX_BASE;

void lpc32xx_uart_init(unsigned int uart_id) { @@ -66,3 +68,15 @@ void lpc32xx_i2c_init(unsigned int devnum) U_BOOT_DEVICE(lpc32xx_gpios) = { .name = "gpio_lpc32xx" };

+/* Mux for SCK0, MISO0, MOSI0. We do not use SSEL0. */

+#define P_MUX_SET_SSP0 0x1600

+void lpc32xx_ssp_init(void) +{

•   /* Enable SSP0 interface */
  

•   writel(CLK_SSP0_ENABLE_CLOCK, &clk->ssp_ctrl);
  

•   /* Mux SSP0 pins */
  

•   writel(P_MUX_SET_SSP0, &mux->p_mux_set);
  

+} diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h b/arch/arm/include/asm/arch-lpc32xx/clk.h index 781ac07..2cb5703 100644 --- a/arch/arm/include/asm/arch-lpc32xx/clk.h +++ b/arch/arm/include/asm/arch-lpc32xx/clk.h @@ -155,6 +155,9 @@ struct clk_pm_regs { #define CLK_NAND_MLC (1 << 1) #define CLK_NAND_MLC_INT (1 << 5)

+/* SSP Clock Control Register bits */ +#define CLK_SSP0_ENABLE_CLOCK (1 << 0)

unsigned int get_sys_clk_rate(void); unsigned int get_hclk_pll_rate(void); unsigned int get_hclk_clk_div(void); diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h index a4a05d1..86d5ee9 100644 --- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h +++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h @@ -11,5 +11,6 @@ void lpc32xx_uart_init(unsigned int uart_id); void lpc32xx_mac_init(void); void lpc32xx_mlc_nand_init(void); void lpc32xx_i2c_init(unsigned int devnum); +void lpc32xx_ssp_init(void);

#endif /* _LPC32XX_SYS_PROTO_H */ diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index edbd520..ce6f1cc 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o obj-$(CONFIG_FTSSP010_SPI) += ftssp010_spi.o obj-$(CONFIG_ICH_SPI) += ich.o obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o +obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o obj-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o obj-$(CONFIG_MXC_SPI) += mxc_spi.o diff --git a/drivers/spi/lpc32xx_ssp.c b/drivers/spi/lpc32xx_ssp.c new file mode 100644 index 0000000..40270df --- /dev/null +++ b/drivers/spi/lpc32xx_ssp.c @@ -0,0 +1,132 @@ +/*

• • LPC32xx SSP interface (SPI mode)
• • (C) Copyright 2014 DENX Software Engineering GmbH
• • Written-by: Albert ARIBAUD albert.aribaud@3adev.fr
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <linux/compat.h> +#include <asm/io.h> +#include <malloc.h> +#include <spi.h> +#include <asm/arch/clk.h>

+/* SSP chip registers */ +struct ssp_regs {

•   u32 cr0;
  

•   u32 cr1;
  

•   u32 data;
  

•   u32 sr;
  

•   u32 cpsr;
  

•   u32 imsc;
  

•   u32 ris;
  

•   u32 mis;
  

•   u32 icr;
  

•   u32 dmacr;
  

+};

+/* CR1 register defines */ +#define SSP_CR1_SSP_ENABLE 0x0002

+/* SR register defines */ +#define SSP_SR_TNF 0x0002 +/* SSP status RX FIFO not empty bit */ +#define SSP_SR_RNE 0x0004

+static struct ssp_regs *ssp0_regs = (struct ssp_regs *)SSP0_BASE;

Pls- use static inline instead of direct macro assignment.

Hmm... What's the benefit of going through a static inline function when all that is performed is an assignment?

Sorry, it's my mistake i thought the driver handling more than one controller base. Your macro assignment is correct in that sense.

All I'm explained below is that changes in spi driver like how well it uses the generic spi calls and the format of the driver resembles same as others (reff. driver drivers/spi/zynq_spi.c)

All (most) of the drivers will follow the same.

If you still confused, may be I will look at it but pls- understand.

...

...

+static struct spi_slave ssp0_slave = {

•   .bus = 0,
  

•   .cs = 0,
  

•   .op_mode_rx = 0,
  

•   .op_mode_tx = 0,
  

•   .wordlen = 8,
  

•   .max_write_size = 1, /* this is for SPI FLASHes -- don't care */
  

•   .memory_map = NULL, /* for SPI FLASHes too */
  

•   .option = 0,
  

•   .flags = 0
  

+};

This wouldn't require - spi_alloc_slave() is a generic func to do all the stuff. See comments below...

...

+/* spi_init is called during boot when CONFIG_CMD_SPI is defined */ +void spi_init(void) +{

•   /*
  

•    *  nothing to do: clocking was enabled in lpc32xx_ssp_enable()
  

•    * and configuration will be done in spi_setup_slave()
  

•   */
  

+}

+/* the following is called in sequence by do_spi_xfer() */

+struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode) +{

Define spi_cs_is_valid() that wikk ensure the controlling bus and cs options command prompt

Not sure I understand what you mean here.

...

use spi_alloc_slave() and members will be having reg_base and slave that's. See drivers/spi/zynq_spi.c for more info.

Suggested code: static struct ssp0_spi_slave { struct spi_slave slave; struct ssp_regs *base; };

static inline struct ssp0_regs *get_ssp0_spi_base(void) { return (struct ssp0_regs *) SSP0_BASE; }

in spi_setup_slave()

{ struct ssp0_spi_slave *ssp0;

/* valid bus and cs */

/* allocate */
ssp0 = spi_alloc_slave(struct ssp0_spi_slave, bus, cs);

ssp0->base = get_ssp0_spi_base();

}

Ditto -- I don't see in what respect the code you suggest is supposed to improve things. Can you please develop?

...

...

•   /* we only set up SSP0 for now, so ignore bus */
  

•   if (mode & SPI_3WIRE) {
  

•           error("3-wire mode not supported");
  

•           return NULL;
  

•   }
  

•   if (mode & SPI_SLAVE) {
  

•           error("slave mode not supported\n");
  

•           return NULL;
  

•   }
  

•   if (mode & SPI_PREAMBLE) {
  

•           error("preamble byte skipping not supported\n");
  

•           return NULL;
  

•   }
  

•   /*
  

•    * 8 bit frame, SPI fmt, 500kbps -> clock divider is 26.
  

•    * Set SCR to 0 and CPSDVSR to 26.
  

•    */
  

•   writel(0x7, &ssp0_regs->cr0); /* 8-bit chunks, SPI, 1 clk/bit */
  

•   writel(26, &ssp0_regs->cpsr); /* SSP clock = HCLK/26 = 500kbps */
  

•   writel(0, &ssp0_regs->imsc); /* do not raise any interrupts */
  

•   writel(0, &ssp0_regs->icr); /* clear any pending interrupt */
  

•   writel(0, &ssp0_regs->dmacr); /* do not do DMAs */
  

•   writel(SSP_CR1_SSP_ENABLE, &ssp0_regs->cr1); /* enable SSP0 */
  

•   return &ssp0_slave;
  

+}

+int spi_claim_bus(struct spi_slave *slave) +{

•   /* only one bus and slave so far, always available */
  

•   return 0;
  

+}

+int spi_xfer(struct spi_slave *slave, unsigned int bitlen,

•   const void *dout, void *din, unsigned long flags)
  

+{

•   int bytelen = bitlen >> 3;
  

•   int idx_out = 0;
  

•   int idx_in = 0;
  

•   int start_time;
  

•   start_time = get_timer(0);
  

•   while ((idx_out < bytelen) || (idx_in < bytelen)) {
  

•           int status = readl(&ssp0_regs->sr);
  

•           if ((idx_out < bytelen) && (status & SSP_SR_TNF))
  

•                   writel(((u8 *)dout)[idx_out++], &ssp0_regs->data);
  

•           if ((idx_in < bytelen) && (status & status & SSP_SR_RNE))
  

•                   ((u8 *)din)[idx_in++] = readl(&ssp0_regs->data);
  

•           if (get_timer(start_time) >= CONFIG_LPC32XX_SSP_TIMEOUT)
  

•                   return -1;
  

•   }
  

•   return 0;
  

+}

+void spi_release_bus(struct spi_slave *slave) +{

•   /* do nothing */
  

+}

+void spi_free_slave(struct spi_slave *slave) +{

•   /* do nothing */
  

+}

2.1.0

thanks!

thanks!

Hi Simon,

Le Thu, 12 Feb 2015 22:06:51 -0700, Simon Glass sjg@chromium.org a écrit :

Hi Albert,

On 12 February 2015 at 10:37, Albert ARIBAUD (3ADEV) albert.aribaud@3adev.fr wrote:

...

This driver only supports Driver Model, not legacy model.

Signed-off-by: Albert ARIBAUD (3ADEV) albert.aribaud@3adev.fr

Changes in v2:

• move from legacy to Driver Model support

arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 5 + arch/arm/include/asm/arch-lpc32xx/gpio.h | 43 +++++ drivers/gpio/Makefile | 1 + drivers/gpio/lpc32xx_gpio.c | 268 +++++++++++++++++++++++++++++++ 4 files changed, 317 insertions(+) create mode 100644 arch/arm/include/asm/arch-lpc32xx/gpio.h create mode 100644 drivers/gpio/lpc32xx_gpio.c

diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c index 81b53ea..a407098 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c +++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c @@ -9,6 +9,7 @@ #include <asm/arch/clk.h> #include <asm/arch/uart.h> #include <asm/io.h> +#include <dm.h>

static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE; @@ -61,3 +62,7 @@ void lpc32xx_i2c_init(unsigned int devnum) ctrl |= CLK_I2C2_ENABLE; writel(ctrl, &clk->i2cclk_ctrl); }

+U_BOOT_DEVICE(lpc32xx_gpios) = {

•   .name = "gpio_lpc32xx"
  

+}; diff --git a/arch/arm/include/asm/arch-lpc32xx/gpio.h b/arch/arm/include/asm/arch-lpc32xx/gpio.h new file mode 100644 index 0000000..3bd94e3 --- /dev/null +++ b/arch/arm/include/asm/arch-lpc32xx/gpio.h @@ -0,0 +1,43 @@ +/*

• • LPC32xx GPIO interface
• • (C) Copyright 2014 DENX Software Engineering GmbH
• • Written-by: Albert ARIBAUD albert.aribaud@3adev.fr
• • SPDX-License-Identifier: GPL-2.0+
• */

+/**

• • GPIO Register map for LPC32xx
• */

+struct gpio_regs {

•   u32 p3_inp_state;
  

•   u32 p3_outp_set;
  

•   u32 p3_outp_clr;
  

•   u32 p3_outp_state;
  

•   /* Watch out! the following are shared between p2 and p3 */
  

•   u32 p2_p3_dir_set;
  

•   u32 p2_p3_dir_clr;
  

•   u32 p2_p3_dir_state;
  

•   /* Now back to 'one register for one port' */
  

•   u32 p2_inp_state;
  

•   u32 p2_outp_set;
  

•   u32 p2_outp_clr;
  

•   u32 reserved1[6];
  

•   u32 p0_inp_state;
  

•   u32 p0_outp_set;
  

•   u32 p0_outp_clr;
  

•   u32 p0_outp_state;
  

•   u32 p0_dir_set;
  

•   u32 p0_dir_clr;
  

•   u32 p0_dir_state;
  

•   u32 reserved2;
  

•   u32 p1_inp_state;
  

•   u32 p1_outp_set;
  

•   u32 p1_outp_clr;
  

•   u32 p1_outp_state;
  

•   u32 p1_dir_set;
  

•   u32 p1_dir_clr;
  

•   u32 p1_dir_state;
  

+}; diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index aa11f15..559894a 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -37,3 +37,4 @@ obj-$(CONFIG_ADI_GPIO2) += adi_gpio2.o obj-$(CONFIG_TCA642X) += tca642x.o oby-$(CONFIG_SX151X) += sx151x.o obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o +obj-$(CONFIG_LPC32XX_GPIO) += lpc32xx_gpio.o diff --git a/drivers/gpio/lpc32xx_gpio.c b/drivers/gpio/lpc32xx_gpio.c new file mode 100644 index 0000000..861975e --- /dev/null +++ b/drivers/gpio/lpc32xx_gpio.c @@ -0,0 +1,268 @@ +/*

• • LPC32xxGPIO driver
• • (C) Copyright 2014 DENX Software Engineering GmbH
• • Written-by: Albert ARIBAUD albert.aribaud@3adev.fr
• • SPDX-License-Identifier: GPL-2.0+
• */

+/**

• • We only support driver model
• */

+#ifndef CONFIG_DM_GPIO +#error Please enable Driver Model GPIO in your target configuration. +#endif

Minor note - if you base this on dm/master you can use Kconfig 'depends on DM' in this driver's Kconfig bit.

(pull request to mainline coming soon)

I will rebase then for v3.

...

+#include <asm/io.h> +#include <asm/arch-lpc32xx/cpu.h> +#include <asm/arch-lpc32xx/gpio.h> +#include <asm-generic/gpio.h> +#include <dm.h> +#include <malloc.h>

+/**

• • LPC32xx GPIOs work in banks but are non-homogeneous:
• • • each bank holds a different number of GPIOs
• • • some GPIOs are input/ouput, some input only, some output only;
• • • some GPIOs have different meanings as an input and as an output;
• • • some GPIOs are controlled on a given port and bit index, but
• • read on another one.

+*

• • In order to keep this code simple, GPIOS are considered here as
• • homogeneous and linear, from 0 to 127.

• • ** WARNING **
    

• • Client code is responsible for properly using valid GPIO numbers,
• • including cases where a single physical GPIO has differing numbers
• • for setting its direction, reading it and/or writing to it.
• */

+#define LPC32XX_GPIOS 128

+static struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;

Normally this would go in a

struct lpc32xx_priv

in the driver.

Will change this.

...

+/**

• • We have 4 GPIO ports of 32 bits each
• */

+#define MAX_GPIO 128

+#define GPIO_TO_PORT(gpio) ((gpio / 32) & 3) +#define GPIO_TO_RANK(gpio) (gpio % 32) +#define GPIO_TO_MASK(gpio) (1 << (gpio % 32))

+/**

• • Array of current GPIO functions. Allocated as unsigned chars to
• • limit memory consumption.
• */

+static signed char lpc32xx_function[LPC32XX_GPIOS];

...along with this.

Ditto.

...

+/**

• • Configure a GPIO number 'offset' as input
• */

+static int lpc32xx_gpio_direction_input(struct udevice *dev, unsigned offset) +{

•   int port, mask;
  

•   port = GPIO_TO_PORT(offset);
  

•   mask = GPIO_TO_MASK(offset);
  

•   switch (port) {
  

•   case 0:
  

•           writel(mask, &regs->p0_dir_clr);
  

•           break;
  

•   case 1:
  

•           writel(mask, &regs->p1_dir_clr);
  

•           break;
  

•   case 2:
  

•           /* ports 2 and 3 share a common direction */
  

•   case 3:
  

•           writel(mask, &regs->p2_p3_dir_clr);
  

•           break;
  

•   default:
  

•           return -1;
  

•   }
  

•   lpc32xx_function[offset] = GPIOF_INPUT;
  

Another way of doing this is to read the status from the hardware. This might allow you to support GPIOF_FUNCTION - i.e. the GPIO is currently used by a function.

Even under the simplified model I used for LPC32XX GPIOs, finding out the state of an individual gpio would be quite complicated and would incur much work for a feature which is actually only useful for the 'gpio' command -- a commodity but not a necessity as far a the actual board user is concerned.

...

•   return 0;
  

+}

+/**

• • Get the value of a GPIO
• */

+static int lpc32xx_gpio_get_value(struct udevice *dev, unsigned offset) +{

•   int port, rank, mask, value;
  

•   port = GPIO_TO_PORT(offset);
  

•   switch (port) {
  

•   case 0:
  

•           value = readl(&regs->p0_inp_state);
  

•           break;
  

•   case 1:
  

•           value = readl(&regs->p1_inp_state);
  

•           break;
  

•   case 2:
  

•           value = readl(&regs->p2_inp_state);
  

•           break;
  

•   case 3:
  

•           value = readl(&regs->p3_inp_state);
  

•           break;
  

•   default:
  

•           return -1;
  

•   }
  

•   rank = GPIO_TO_RANK(offset);
  

•   mask = GPIO_TO_MASK(offset);
  

•   return (value & mask) >> rank;
  

+}

+/**

• • Set a GPIO
• */

+static int gpio_set(unsigned gpio) +{

•   int port, mask;
  

•   port = GPIO_TO_PORT(gpio);
  

•   mask = GPIO_TO_MASK(gpio);
  

•   switch (port) {
  

•   case 0:
  

•           writel(mask, &regs->p0_outp_set);
  

•           break;
  

•   case 1:
  

•           writel(mask, &regs->p1_outp_set);
  

•           break;
  

•   case 2:
  

•           writel(mask, &regs->p2_outp_set);
  

•           break;
  

•   case 3:
  

•           writel(mask, &regs->p3_outp_set);
  

•           break;
  

•   default:
  

•           return -1;
  

•   }
  

•   return 0;
  

+}

+/**

• • Clear a GPIO
• */

+static int gpio_clr(unsigned gpio) +{

•   int port, mask;
  

•   port = GPIO_TO_PORT(gpio);
  

•   mask = GPIO_TO_MASK(gpio);
  

•   switch (port) {
  

•   case 0:
  

•           writel(mask, &regs->p0_outp_clr);
  

•           break;
  

•   case 1:
  

•           writel(mask, &regs->p1_outp_clr);
  

•           break;
  

•   case 2:
  

•           writel(mask, &regs->p2_outp_clr);
  

•           break;
  

•   case 3:
  

•           writel(mask, &regs->p3_outp_clr);
  

•           break;
  

•   default:
  

•           return -1;
  

•   }
  

•   return 0;
  

+}

+/**

• • Set the value of a GPIO
• */

+static int lpc32xx_gpio_set_value(struct udevice *dev, unsigned offset,

•                            int value)
  

+{

•   if (value)
  

•           return gpio_set(offset);
  

•   else
  

•           return gpio_clr(offset);
  

+}

+/**

• • Configure a GPIO number 'offset' as output with given initial value.
• */

+static int lpc32xx_gpio_direction_output(struct udevice *dev, unsigned offset,

•                                  int value)
  

+{

•   int port, mask;
  

•   port = GPIO_TO_PORT(offset);
  

•   mask = GPIO_TO_MASK(offset);
  

•   switch (port) {
  

•   case 0:
  

•           writel(mask, &regs->p0_dir_set);
  

•           break;
  

•   case 1:
  

•           writel(mask, &regs->p1_dir_set);
  

•           break;
  

•   case 2:
  

•           /* ports 2 and 3 share a common direction */
  

•   case 3:
  

•           writel(mask, &regs->p2_p3_dir_set);
  

•           break;
  

•   default:
  

•           return -1;
  

•   }
  

•   lpc32xx_function[offset] = GPIOF_OUTPUT;
  

•   return lpc32xx_gpio_set_value(dev, offset, value);
  

+}

+static int lpc32xx_gpio_get_function(struct udevice *dev, unsigned offset) +{

•   return lpc32xx_function[offset];
  

+}

+static const struct dm_gpio_ops gpio_lpc32xx_ops = {

•   .direction_input        = lpc32xx_gpio_direction_input,
  

•   .direction_output       = lpc32xx_gpio_direction_output,
  

•   .get_value              = lpc32xx_gpio_get_value,
  

•   .set_value              = lpc32xx_gpio_set_value,
  

•   .get_function           = lpc32xx_gpio_get_function,
  

+};

+static int lpc32xx_gpio_probe(struct udevice *dev) +{

•   struct gpio_dev_priv *uc_priv = dev->uclass_priv;
  

•   if (dev->of_offset == -1) {
  

•           /* Tell the uclass how many GPIOs we have */
  

•           uc_priv->gpio_count = LPC32XX_GPIOS;
  

•   }
  

•   /* all GPIO functions are unknown until requested */
  

•   memset(lpc32xx_function, GPIOF_UNKNOWN, LPC32XX_GPIOS);
  

•   return 0;
  

+}

+U_BOOT_DRIVER(gpio_lpc32xx) = {

•   .name   = "gpio_lpc32xx",
  

•   .id     = UCLASS_GPIO,
  

•   .ops    = &gpio_lpc32xx_ops,
  

•   .probe  = lpc32xx_gpio_probe,
  

•   .priv_auto_alloc_size = 0,
  

You can use sizeof(struct lpc32xx_priv) here and it will automatically allocate your structure when the device is probed.

Yep, that'll get in along with moving the base address and intenal gpio state array.

...

+};

2.1.0

Regards, Simon

Thanks for your review!

Cordialement, Albert ARIBAUD 3ADEV

Hello Albert,

Am 12.02.2015 18:37, schrieb Albert ARIBAUD (3ADEV):

Signed-off-by: Albert ARIBAUD (3ADEV) albert.aribaud@3adev.fr

Changes in v2: None

arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 11 ++ arch/arm/include/asm/arch-lpc32xx/clk.h | 4 + arch/arm/include/asm/arch-lpc32xx/cpu.h | 2 + arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 + drivers/i2c/Makefile | 1 + drivers/i2c/lpc32xx_i2c.c | 249 ++++++++++++++++++++++++++ 6 files changed, 268 insertions(+) create mode 100644 drivers/i2c/lpc32xx_i2c.c

Acked-by: Heiko Schocher hs@denx.de

Do you have a chance to use DM on this HW?

bye, Heiko

diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c index be4c93d..81b53ea 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c +++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c @@ -50,3 +50,14 @@ void lpc32xx_mlc_nand_init(void) /* Enable NAND interface */ writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, &clk->flashclk_ctrl); }

+void lpc32xx_i2c_init(unsigned int devnum) +{

• /* Enable I2C interface */
• uint32_t ctrl = readl(&clk->i2cclk_ctrl);
• if (devnum == 1)

• ctrl |= CLK_I2C1_ENABLE;
  

• if (devnum == 2)

• ctrl |= CLK_I2C2_ENABLE;
  

• writel(ctrl, &clk->i2cclk_ctrl);

+} diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h b/arch/arm/include/asm/arch-lpc32xx/clk.h index bc7d33d..781ac07 100644 --- a/arch/arm/include/asm/arch-lpc32xx/clk.h +++ b/arch/arm/include/asm/arch-lpc32xx/clk.h @@ -123,6 +123,10 @@ struct clk_pm_regs { #define CLK_MAC_SLAVE (1 << 1) #define CLK_MAC_REG (1 << 0)

+/* I2C Clock Control Register bits */ +#define CLK_I2C2_ENABLE (1 << 1) +#define CLK_I2C1_ENABLE (1 << 0)

• /* Timer Clock Control1 Register bits */ #define CLK_TIMCLK_MOTOR (1 << 6) #define CLK_TIMCLK_TIMER3 (1 << 5)

diff --git a/arch/arm/include/asm/arch-lpc32xx/cpu.h b/arch/arm/include/asm/arch-lpc32xx/cpu.h index 199b4a0..1067107 100644 --- a/arch/arm/include/asm/arch-lpc32xx/cpu.h +++ b/arch/arm/include/asm/arch-lpc32xx/cpu.h @@ -37,6 +37,8 @@ #define UART4_BASE 0x40088000 /* UART 4 registers base */ #define UART5_BASE 0x40090000 /* UART 5 registers base */ #define UART6_BASE 0x40098000 /* UART 6 registers base */ +#define I2C1_BASE 0x400A0000 /* I2C 1 registers base */ +#define I2C2_BASE 0x400A8000 /* I2C 2 registers base */

/* External SDRAM Memory Bank base addresses */ #define EMC_DYCS0_BASE 0x80000000 /* SDRAM DYCS0 base address */ diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h index 0c4e712..a4a05d1 100644 --- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h +++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h @@ -10,5 +10,6 @@ void lpc32xx_uart_init(unsigned int uart_id); void lpc32xx_mac_init(void); void lpc32xx_mlc_nand_init(void); +void lpc32xx_i2c_init(unsigned int devnum);

#endif /* _LPC32XX_SYS_PROTO_H */ diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 774bc94..26ea854 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o +obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o obj-$(CONFIG_SYS_I2C_MXS) += mxs_i2c.o diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c new file mode 100644 index 0000000..78d26e4 --- /dev/null +++ b/drivers/i2c/lpc32xx_i2c.c @@ -0,0 +1,249 @@ +/*

• • LPC32xx I2C interface driver
• • (C) Copyright 2014 DENX Software Engineering GmbH
• • Written-by: Albert ARIBAUD - 3ADEV albert.aribaud@3adev.fr
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <asm/io.h> +#include <i2c.h> +#include <asm/errno.h> +#include <asm/arch/clk.h>

+/*

• • Provide default speed and slave if target did not
• */

+#if !defined(CONFIG_SYS_I2C_LPC32XX_SPEED) +#define CONFIG_SYS_I2C_LPC32XX_SPEED 350000 +#endif

+#if !defined(CONFIG_SYS_I2C_LPC32XX_SLAVE) +#define CONFIG_SYS_I2C_LPC32XX_SLAVE 0 +#endif

+/* i2c register set */ +struct lpc32xx_i2c_registers {

• union {

• u32 rx;
  

• u32 tx;
  

• };
• u32 stat;
• u32 ctrl;
• u32 clk_hi;
• u32 clk_lo;
• u32 adr;
• u32 rxfl;
• u32 txfl;
• u32 rxb;
• u32 txb;
• u32 stx;
• u32 stxfl;

+};

+/* TX register fields */ +#define LPC32XX_I2C_TX_START 0x00000100 +#define LPC32XX_I2C_TX_STOP 0x00000200

+/* Control register values */ +#define LPC32XX_I2C_SOFT_RESET 0x00000100

+/* Status register values */ +#define LPC32XX_I2C_STAT_TFF 0x00000400 +#define LPC32XX_I2C_STAT_RFE 0x00000200 +#define LPC32XX_I2C_STAT_DRMI 0x00000008 +#define LPC32XX_I2C_STAT_NAI 0x00000004 +#define LPC32XX_I2C_STAT_TDI 0x00000001

+static struct lpc32xx_i2c_registers *lpc32xx_i2c[] = {

• (struct lpc32xx_i2c_registers *)I2C1_BASE,
• (struct lpc32xx_i2c_registers *)I2C2_BASE

+};

+/* Set I2C bus speed */ +static unsigned int lpc32xx_i2c_set_bus_speed(struct i2c_adapter *adap,

• 	unsigned int speed)
  

+{

• int half_period;
• if (speed == 0)

• return -EINVAL;
  

• half_period = (105000000 / speed) / 2;
• if ((half_period > 255) || (half_period < 0))

• return -EINVAL;
  

• writel(half_period, &lpc32xx_i2c[adap->hwadapnr]->clk_hi);
• writel(half_period, &lpc32xx_i2c[adap->hwadapnr]->clk_lo);
• return 0;

+}

+/* I2C init called by cmd_i2c when doing 'i2c reset'. */ +static void _i2c_init(struct i2c_adapter *adap,

• int requested_speed, int slaveadd)

+{

• struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];
• /* soft reset (auto-clears) */
• writel(LPC32XX_I2C_SOFT_RESET, &i2c->ctrl);
• /* set HI and LO periods for about 350 kHz */
• lpc32xx_i2c_set_bus_speed(adap, requested_speed);

+}

+/* I2C probe called by cmd_i2c when doing 'i2c probe'. */ +static int lpc32xx_i2c_probe(struct i2c_adapter *adap, u8 dev) +{

• struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];
• int stat;
• /* Soft-reset the controller */
• writel(LPC32XX_I2C_SOFT_RESET, &i2c->ctrl);
• while (readl(&i2c->ctrl) & LPC32XX_I2C_SOFT_RESET)

• ;
  

• /* Addre slave for write with start before and stop after */
• writel((dev<<1) | LPC32XX_I2C_TX_START | LPC32XX_I2C_TX_STOP,

•       &i2c->tx);
  

• /* wait for end of transation */
• while (!((stat = readl(&i2c->stat)) & LPC32XX_I2C_STAT_TDI))

• ;
  

• /* was there no acknowledge? */
• return (stat & LPC32XX_I2C_STAT_NAI) ? -1 : 0;

+}

+/*

• • I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
• • Begin write, send address byte(s), begin read, receive data bytes, end.
• */

+static int lpc32xx_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,

• 	 int alen, u8 *data, int length)
  

+{

• struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];
• int stat, wlen;
• /* Soft-reset the controller */
• writel(LPC32XX_I2C_SOFT_RESET, &i2c->ctrl);
• while (readl(&i2c->ctrl) & LPC32XX_I2C_SOFT_RESET)

• ;
  

• /* do we need to write an address at all? */
• if (alen) {

• /* Address slave in write mode */
  

• writel((dev<<1) | LPC32XX_I2C_TX_START, &i2c->tx);
  

• /* write address bytes */
  

• while (alen--) {
  

• 	/* compute address byte + stop for the last one */
  

• 	int a = (addr >> (8 * alen)) & 0xff;
  

• 	if (!alen)
  

• 		a |= LPC32XX_I2C_TX_STOP;
  

• 	/* Send address byte */
  

• 	writel(a, &i2c->tx);
  

• }
  

• /* wait for end of transation */
  

• while (!((stat = readl(&i2c->stat)) & LPC32XX_I2C_STAT_TDI))
  

• 	;
  

• /* clear end-of-transaction flag */
  

• writel(1, &i2c->stat);
  

• }
• /* do we have to read data at all? */
• if (length) {

• /* Address slave in read mode */
  

• writel(1 | (dev<<1) | LPC32XX_I2C_TX_START, &i2c->tx);
  

• wlen = length;
  

• /* get data */
  

• while (length | wlen) {
  

• 	/* read status for TFF and RFE */
  

• 	stat = readl(&i2c->stat);
  

• 	/* must we, can we write a trigger byte? */
  

• 	if ((wlen > 0)
  

• 	   & (!(stat & LPC32XX_I2C_STAT_TFF))) {
  

• 		wlen--;
  

• 		/* write trigger byte + stop if last */
  

• 		writel(wlen ? 0 :
  

• 		LPC32XX_I2C_TX_STOP, &i2c->tx);
  

• 	}
  

• 	/* must we, can we read a data byte? */
  

• 	if ((length > 0)
  

• 	   & (!(stat & LPC32XX_I2C_STAT_RFE))) {
  

• 		length--;
  

• 		/* read byte */
  

• 		*(data++) = readl(&i2c->rx);
  

• 	}
  

• }
  

• }
• /* wait for end of transation */
• while (!((stat = readl(&i2c->stat)) & LPC32XX_I2C_STAT_TDI))

• ;
  

• /* clear end-of-transaction flag */
• writel(1, &i2c->stat);
• /* success */
• return 0;

+}

+/*

• • I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
• • Begin write, send address byte(s), send data bytes, end.
• */

+static int lpc32xx_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,

• 	  int alen, u8 *data, int length)
  

+{

• struct lpc32xx_i2c_registers *i2c = lpc32xx_i2c[adap->hwadapnr];
• int stat;
• /* Soft-reset the controller */
• writel(LPC32XX_I2C_SOFT_RESET, &i2c->ctrl);
• while (readl(&i2c->ctrl) & LPC32XX_I2C_SOFT_RESET)

• ;
  

• /* do we need to write anything at all? */
• if (alen | length)

• /* Address slave in write mode */
  

• writel((dev<<1) | LPC32XX_I2C_TX_START, &i2c->tx);
  

• /* write address bytes */
• while (alen) {

• /* wait for transmit fifo not full */
  

• stat = readl(&i2c->stat);
  

• if (!(stat & LPC32XX_I2C_STAT_TFF)) {
  

• 	alen--;
  

• 	int a = (addr >> (8 * alen)) & 0xff;
  

• 	if (!(alen | length))
  

• 		a |= LPC32XX_I2C_TX_STOP;
  

• 	/* Send address byte */
  

• 	writel(a, &i2c->tx);
  

• }
  

• }
• while (length) {

• /* wait for transmit fifo not full */
  

• stat = readl(&i2c->stat);
  

• if (!(stat & LPC32XX_I2C_STAT_TFF)) {
  

• 	/* compute data byte, add stop if length==0 */
  

• 	length--;
  

• 	int d = *(data++);
  

• 	if (!length)
  

• 		d |= LPC32XX_I2C_TX_STOP;
  

• 	/* Send data byte */
  

• 	writel(d, &i2c->tx);
  

• }
  

• }
• /* wait for end of transation */
• while (!((stat = readl(&i2c->stat)) & LPC32XX_I2C_STAT_TDI))

• ;
  

• /* clear end-of-transaction flag */
• writel(1, &i2c->stat);
• return 0;

+}

+U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_0, _i2c_init, lpc32xx_i2c_probe,

• 	 lpc32xx_i2c_read, lpc32xx_i2c_write,
  

• 	 lpc32xx_i2c_set_bus_speed,
  

• 	 CONFIG_SYS_I2C_LPC32XX_SPEED,
  

• 	 CONFIG_SYS_I2C_LPC32XX_SLAVE,
  

• 	 0)
  

+U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_1, _i2c_init, lpc32xx_i2c_probe,

• 	 lpc32xx_i2c_read, lpc32xx_i2c_write,
  

• 	 lpc32xx_i2c_set_bus_speed,
  

• 	 CONFIG_SYS_I2C_LPC32XX_SPEED,
  

• 	 CONFIG_SYS_I2C_LPC32XX_SLAVE,
  

• 	 1)