[U-Boot] [PATCH v3 0/6] Support for the Turris Omnia router

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Marek Behun

6 Jun 2017 6 Jun '17

2:04 p.m.

This is the third version of patches for adding support for the Turris Omnia board, a router developed by the CZ.NIC.

The only modification from the second version is that the device tree added is unmodified, identical to the one in the Linux kernel. The additions are done in a separate, -u-boot.dtsi file.

The first patch modifies Marvell's DDR3 training code to be more general, so that board topology map can force 2t timing.

The second patch adds support for the hardware watchdog which can be found on Omnia. I have modified the driver to use the new driver model API.

The third patch adds the device tree for Turris Omnia taken from Linux kernel and also armada-385-turris-omnia-u-boot.dtsi file with some additions for U-Boot.

The fourth patch adds support for the I2C multiplexer found on Turris Omnia.

The fifth patch adds support for the ATSHA204A CryptoAuthentication chip, on which the Turris Omnia stores serial number and device MAC address.

The sixth patch adds the proper support for the board. I have modified config to use distro defaults as requested by Andreas Faerber and also removed unnecessary comments.

Marek Behun

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Marek Behun

6 Jun 6 Jun

2:04 p.m.

New subject: [U-Boot] [PATCH v3 1/6] driver/ddr: Add support for setting timing in hws_topology_map

From: Marek Behún marek.behun@nic.cz

The DDR3 training code for Marvell A38X currently computes 1t timing when given board topology map of the Turris Omnia, but Omnia needs 2t.

This patch adds support for enforcing the 2t timing in struct hws_topology_map, through a new enum hws_timing, which can assume following values: HWS_TIM_DEFAULT - default behaviour, compute whether to enable 2t from the number of CSs HWS_TIM_1T - enforce 1t HWS_TIM_2T - enforce 2t

This patch also sets all the board topology maps (db-88f6820-amc, db-88f6820-gp, controlcenterdc and clearfog) to have timing set to HWS_TIM_DEFAULT.

Signed-off-by: Marek Behun marek.behun@nic.cz

diff --git a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c index cade99c8d7..40fa599865 100644 --- a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c +++ b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c @@ -69,7 +69,8 @@ static struct hws_topology_map board_topology_map = { MEM_4G, /* mem_size */ DDR_FREQ_800, /* frequency */ 0, 0, /* cas_l cas_wl */ - HWS_TEMP_LOW} }, /* temperature */ + HWS_TEMP_LOW, /* temperature */ + HWS_TIM_DEFAULT} }, /* timing */ 5, /* Num Of Bus Per Interface*/ BUS_MASK_32BIT /* Busses mask */ }; diff --git a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c index e700781103..a1974cb4bd 100644 --- a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c +++ b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c @@ -90,7 +90,8 @@ static struct hws_topology_map board_topology_map = { MEM_4G, /* mem_size */ DDR_FREQ_800, /* frequency */ 0, 0, /* cas_l cas_wl */ - HWS_TEMP_LOW} }, /* temperature */ + HWS_TEMP_LOW, /* temperature */ + HWS_TIM_DEFAULT} }, /* timing */ 5, /* Num Of Bus Per Interface*/ BUS_MASK_32BIT /* Busses mask */ }; diff --git a/board/gdsys/a38x/controlcenterdc.c b/board/gdsys/a38x/controlcenterdc.c index f0efb53447..32168d3576 100644 --- a/board/gdsys/a38x/controlcenterdc.c +++ b/board/gdsys/a38x/controlcenterdc.c @@ -53,7 +53,8 @@ static struct hws_topology_map ddr_topology_map = { MEM_4G, /* mem_size */ DDR_FREQ_533, /* frequency */ 0, 0, /* cas_l cas_wl */ - HWS_TEMP_LOW} }, /* temperature */ + HWS_TEMP_LOW, /* temperature */ + HWS_TIM_DEFAULT} }, /* timing */ 5, /* Num Of Bus Per Interface*/ BUS_MASK_32BIT /* Busses mask */ }; diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c index 3a8257cac3..8906636f76 100644 --- a/board/solidrun/clearfog/clearfog.c +++ b/board/solidrun/clearfog/clearfog.c @@ -83,7 +83,8 @@ static struct hws_topology_map board_topology_map = { MEM_4G, /* mem_size */ DDR_FREQ_800, /* frequency */ 0, 0, /* cas_l cas_wl */ - HWS_TEMP_LOW} }, /* temperature */ + HWS_TEMP_LOW, /* temperature */ + HWS_TIM_DEFAULT} }, /* timing */ 5, /* Num Of Bus Per Interface*/ BUS_MASK_32BIT /* Busses mask */ }; diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c b/drivers/ddr/marvell/a38x/ddr3_training.c index 7e0749fde3..c79db6af5a 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training.c +++ b/drivers/ddr/marvell/a38x/ddr3_training.c @@ -571,6 +571,11 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_

if (mode2_t != 0xff) { t2t = mode2_t; + } else if (tm->interface_params[if_id]. + timing != HWS_TIM_DEFAULT) { + /* Board topology map is forcing timing */ + t2t = (tm->interface_params[if_id]. + timing == HWS_TIM_2T) ? 1 : 0; } else { /* calculate number of CS (per interface) */ CHECK_STATUS(calc_cs_num diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h b/drivers/ddr/marvell/a38x/ddr_topology_def.h index f8894e828a..229c3a127a 100644 --- a/drivers/ddr/marvell/a38x/ddr_topology_def.h +++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h @@ -37,6 +37,12 @@ enum hws_mem_size { MEM_SIZE_LAST };

+enum hws_timing { + HWS_TIM_DEFAULT, + HWS_TIM_1T, + HWS_TIM_2T +}; + struct bus_params { /* Chip Select (CS) bitmask (bits 0-CS0, bit 1- CS1 ...) */ u8 cs_bitmask; @@ -84,6 +90,9 @@ struct if_params {

/* operation temperature */ enum hws_temperature interface_temp; + + /* 2T vs 1T mode (by default computed from number of CSs) */ + enum hws_timing timing; };

struct hws_topology_map {

-- 2.13.0

Marek Behún

2:19 p.m.

New subject: [U-Boot] [PATCH v3 1/6] driver/ddr: Add support for setting timing in hws_topology_map

Damn, I forgot to add the change Stefan suggested in this commit. It will be included in next version of the patches.

On Tue, 6 Jun 2017 14:04:32 +0200 Marek Behun marek.behun@nic.cz wrote:

...

From: Marek Behún marek.behun@nic.cz

The DDR3 training code for Marvell A38X currently computes 1t timing when given board topology map of the Turris Omnia, but Omnia needs 2t.

This patch adds support for enforcing the 2t timing in struct hws_topology_map, through a new enum hws_timing, which can assume following values: HWS_TIM_DEFAULT - default behaviour, compute whether to enable 2t from the number of CSs HWS_TIM_1T - enforce 1t HWS_TIM_2T - enforce 2t

This patch also sets all the board topology maps (db-88f6820-amc, db-88f6820-gp, controlcenterdc and clearfog) to have timing set to HWS_TIM_DEFAULT.

Signed-off-by: Marek Behun marek.behun@nic.cz

diff --git a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c index cade99c8d7..40fa599865 100644 --- a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c +++ b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c @@ -69,7 +69,8 @@ static struct hws_topology_map board_topology_map = { MEM_4G, /* mem_size */ DDR_FREQ_800, /* frequency */ 0, 0, /* cas_l cas_wl */
   HWS_TEMP_LOW} },		/* temperature */
   HWS_TEMP_LOW,		/* temperature */
   HWS_TIM_DEFAULT} },		/* timing */
5, /* Num Of Bus Per
Interface*/ BUS_MASK_32BIT /* Busses mask */ }; diff --git a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c index e700781103..a1974cb4bd 100644 --- a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c +++ b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c @@ -90,7 +90,8 @@ static struct hws_topology_map board_topology_map = { MEM_4G, /* mem_size */ DDR_FREQ_800, /* frequency */ 0, 0, /* cas_l cas_wl */
   HWS_TEMP_LOW} },		/* temperature */
   HWS_TEMP_LOW,		/* temperature */
   HWS_TIM_DEFAULT} },		/* timing */
5, /* Num Of Bus Per
Interface*/ BUS_MASK_32BIT /* Busses mask */ }; diff --git a/board/gdsys/a38x/controlcenterdc.c b/board/gdsys/a38x/controlcenterdc.c index f0efb53447..32168d3576 100644 --- a/board/gdsys/a38x/controlcenterdc.c +++ b/board/gdsys/a38x/controlcenterdc.c @@ -53,7 +53,8 @@ static struct hws_topology_map ddr_topology_map = { MEM_4G, /* mem_size */ DDR_FREQ_533, /* frequency */ 0, 0, /* cas_l cas_wl */
   HWS_TEMP_LOW} },		/* temperature */
   HWS_TEMP_LOW,		/* temperature */
   HWS_TIM_DEFAULT} },		/* timing */
5, /* Num Of Bus Per
Interface*/ BUS_MASK_32BIT /* Busses mask */ }; diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c index 3a8257cac3..8906636f76 100644 --- a/board/solidrun/clearfog/clearfog.c +++ b/board/solidrun/clearfog/clearfog.c @@ -83,7 +83,8 @@ static struct hws_topology_map board_topology_map = { MEM_4G, /* mem_size */ DDR_FREQ_800, /* frequency */ 0, 0, /* cas_l cas_wl */
   HWS_TEMP_LOW} },		/* temperature */
   HWS_TEMP_LOW,		/* temperature */
   HWS_TIM_DEFAULT} },		/* timing */
5, /* Num Of Bus Per
Interface*/ BUS_MASK_32BIT /* Busses mask */ }; diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c b/drivers/ddr/marvell/a38x/ddr3_training.c index 7e0749fde3..c79db6af5a 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training.c +++ b/drivers/ddr/marvell/a38x/ddr3_training.c @@ -571,6 +571,11 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_ if (mode2_t != 0xff) { t2t = mode2_t;
	} else if (tm->interface_params[if_id].
		   timing != HWS_TIM_DEFAULT) {
		/* Board topology map is forcing
timing */
		t2t = (tm->interface_params[if_id].
		       timing == HWS_TIM_2T) ? 1 : 0;
} else {
	/* calculate number of CS (per
interface) */ CHECK_STATUS(calc_cs_num diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h b/drivers/ddr/marvell/a38x/ddr_topology_def.h index f8894e828a..229c3a127a 100644 --- a/drivers/ddr/marvell/a38x/ddr_topology_def.h +++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h @@ -37,6 +37,12 @@ enum hws_mem_size { MEM_SIZE_LAST };

+enum hws_timing {

HWS_TIM_DEFAULT,

HWS_TIM_1T,

HWS_TIM_2T

+};

struct bus_params { /* Chip Select (CS) bitmask (bits 0-CS0, bit 1- CS1 ...) */ u8 cs_bitmask; @@ -84,6 +90,9 @@ struct if_params {

/* operation temperature */ enum hws_temperature interface_temp;

/* 2T vs 1T mode (by default computed from number of CSs) */

enum hws_timing timing;

};

struct hws_topology_map {

Stefan Roese

2:27 p.m.

New subject: [U-Boot] [PATCH v3 1/6] driver/ddr: Add support for setting timing in hws_topology_map

Hi Marek,

On 06.06.2017 14:19, Marek Behún wrote:

...

Damn, I forgot to add the change Stefan suggested in this commit. It will be included in next version of the patches.

I was just writing a small comment. ;)

Thanks, Stefan

...

On Tue, 6 Jun 2017 14:04:32 +0200 Marek Behun marek.behun@nic.cz wrote:

...
From: Marek Behún marek.behun@nic.cz

The DDR3 training code for Marvell A38X currently computes 1t timing when given board topology map of the Turris Omnia, but Omnia needs 2t.

This patch adds support for enforcing the 2t timing in struct hws_topology_map, through a new enum hws_timing, which can assume following values: HWS_TIM_DEFAULT - default behaviour, compute whether to enable 2t from the number of CSs HWS_TIM_1T - enforce 1t HWS_TIM_2T - enforce 2t

This patch also sets all the board topology maps (db-88f6820-amc, db-88f6820-gp, controlcenterdc and clearfog) to have timing set to HWS_TIM_DEFAULT.

Signed-off-by: Marek Behun marek.behun@nic.cz

diff --git a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c index cade99c8d7..40fa599865 100644 --- a/board/Marvell/db-88f6820-amc/db-88f6820-amc.c +++ b/board/Marvell/db-88f6820-amc/db-88f6820-amc.c @@ -69,7 +69,8 @@ static struct hws_topology_map board_topology_map = { MEM_4G, /* mem_size */ DDR_FREQ_800, /* frequency */ 0, 0, /* cas_l cas_wl */
   HWS_TEMP_LOW} },		/* temperature */
   HWS_TEMP_LOW,		/* temperature */
   HWS_TIM_DEFAULT} },		/* timing */
5, /* Num Of Bus Per
Interface*/ BUS_MASK_32BIT /* Busses mask */ }; diff --git a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c index e700781103..a1974cb4bd 100644 --- a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c +++ b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c @@ -90,7 +90,8 @@ static struct hws_topology_map board_topology_map = { MEM_4G, /* mem_size */ DDR_FREQ_800, /* frequency */ 0, 0, /* cas_l cas_wl */
   HWS_TEMP_LOW} },		/* temperature */
   HWS_TEMP_LOW,		/* temperature */
   HWS_TIM_DEFAULT} },		/* timing */
5, /* Num Of Bus Per
Interface*/ BUS_MASK_32BIT /* Busses mask */ }; diff --git a/board/gdsys/a38x/controlcenterdc.c b/board/gdsys/a38x/controlcenterdc.c index f0efb53447..32168d3576 100644 --- a/board/gdsys/a38x/controlcenterdc.c +++ b/board/gdsys/a38x/controlcenterdc.c @@ -53,7 +53,8 @@ static struct hws_topology_map ddr_topology_map = { MEM_4G, /* mem_size */ DDR_FREQ_533, /* frequency */ 0, 0, /* cas_l cas_wl */
   HWS_TEMP_LOW} },		/* temperature */
   HWS_TEMP_LOW,		/* temperature */
   HWS_TIM_DEFAULT} },		/* timing */
5, /* Num Of Bus Per
Interface*/ BUS_MASK_32BIT /* Busses mask */ }; diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c index 3a8257cac3..8906636f76 100644 --- a/board/solidrun/clearfog/clearfog.c +++ b/board/solidrun/clearfog/clearfog.c @@ -83,7 +83,8 @@ static struct hws_topology_map board_topology_map = { MEM_4G, /* mem_size */ DDR_FREQ_800, /* frequency */ 0, 0, /* cas_l cas_wl */
   HWS_TEMP_LOW} },		/* temperature */
   HWS_TEMP_LOW,		/* temperature */
   HWS_TIM_DEFAULT} },		/* timing */
5, /* Num Of Bus Per
Interface*/ BUS_MASK_32BIT /* Busses mask */ }; diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c b/drivers/ddr/marvell/a38x/ddr3_training.c index 7e0749fde3..c79db6af5a 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training.c +++ b/drivers/ddr/marvell/a38x/ddr3_training.c @@ -571,6 +571,11 @@ int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_ if (mode2_t != 0xff) { t2t = mode2_t;
	} else if (tm->interface_params[if_id].
		   timing != HWS_TIM_DEFAULT) {
		/* Board topology map is forcing
timing */
		t2t = (tm->interface_params[if_id].
		       timing == HWS_TIM_2T) ? 1 : 0;
} else {
	/* calculate number of CS (per
interface) */ CHECK_STATUS(calc_cs_num diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h b/drivers/ddr/marvell/a38x/ddr_topology_def.h index f8894e828a..229c3a127a 100644 --- a/drivers/ddr/marvell/a38x/ddr_topology_def.h +++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h @@ -37,6 +37,12 @@ enum hws_mem_size { MEM_SIZE_LAST };

+enum hws_timing {

HWS_TIM_DEFAULT,

HWS_TIM_1T,

HWS_TIM_2T

+};

struct bus_params { /* Chip Select (CS) bitmask (bits 0-CS0, bit 1- CS1 ...) */ u8 cs_bitmask;

@@ -84,6 +90,9 @@ struct if_params {

/* operation temperature */ enum hws_temperature interface_temp;

/* 2T vs 1T mode (by default computed from number of CSs) */

enum hws_timing timing; };

struct hws_topology_map {

Viele Grüße, Stefan

-- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr@denx.de

Marek Behun

2:04 p.m.

New subject: [U-Boot] [PATCH v3 2/6] orion_wdt: Support for the Orion Watchdog

From: Marek Behún marek.behun@nic.cz

The Orion watchdog can be found on some Marvell Armada chips.

This driver is based on the code by Tomas Hlavacek in the CZ.NIC turris-omnia-uboot repository, which can be found at https://gitlab.labs.nic.cz/turris/turris-omnia-uboot, and that one is based on code by Sylver Bruneau. His code is already in mainline Linux kernel.

The code uses the new driver model API.

Signed-off-by: Tomas Hlavacek tomas.hlavacek@nic.cz Signed-off-by: Marek Behun marek.behun@nic.cz

create mode 100644 drivers/watchdog/orion_wdt.c

diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index b911233db3..d360a17d4d 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -62,4 +62,11 @@ config WDT_BCM6345 The watchdog timer is stopped when initialized. It performs full SoC reset.

+config WDT_ORION + bool "Orion watchdog timer support" + depends on WDT + help + Select this to enable Orion watchdog timer, which can be found on some + Marvell Armada chips. + endmenu diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 4b19e4ccf6..3230cbb2ad 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -20,3 +20,4 @@ obj-$(CONFIG_WDT_SANDBOX) += sandbox_wdt.o obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o obj-$(CONFIG_BCM2835_WDT) += bcm2835_wdt.o +obj-$(CONFIG_WDT_ORION) += orion_wdt.o diff --git a/drivers/watchdog/orion_wdt.c b/drivers/watchdog/orion_wdt.c new file mode 100644 index 0000000000..a0df02d103 --- /dev/null +++ b/drivers/watchdog/orion_wdt.c @@ -0,0 +1,177 @@ +/* + * drivers/watchdog/orion_wdt.c + * + * Watchdog driver for Orion/Kirkwood processors + * + * Authors: Tomas Hlavacek tmshlvck@gmail.com + * Sylver Bruneau sylver.bruneau@googlemail.com + * Marek Behun marek.behun@nic.cz + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <common.h> +#include <dm.h> +#include <wdt.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct orion_wdt_priv { + void __iomem *reg; + int wdt_counter_offset; + void __iomem *rstout; + void __iomem *rstout_mask; + u32 timeout; +}; + +#define RSTOUT_ENABLE_BIT BIT(8) +#define RSTOUT_MASK_BIT BIT(10) +#define WDT_ENABLE_BIT BIT(8) + +#define TIMER_CTRL 0x0000 +#define TIMER_A370_STATUS 0x04 + +#define WDT_AXP_FIXED_ENABLE_BIT BIT(10) +#define WDT_A370_EXPIRED BIT(31) + +static int orion_wdt_reset(struct udevice *dev) +{ + struct orion_wdt_priv *priv = dev_get_priv(dev); + + /* Reload watchdog duration */ + writel(priv->timeout, priv->reg + priv->wdt_counter_offset); + + return 0; +} + +static int orion_wdt_start(struct udevice *dev, u64 timeout, ulong flags) +{ + struct orion_wdt_priv *priv = dev_get_priv(dev); + u32 reg; + + priv->timeout = (u32) timeout; + + /* Enable the fixed watchdog clock input */ + reg = readl(priv->reg + TIMER_CTRL); + reg |= WDT_AXP_FIXED_ENABLE_BIT; + writel(reg, priv->reg + TIMER_CTRL); + + /* Set watchdog duration */ + writel(priv->timeout, priv->reg + priv->wdt_counter_offset); + + /* Clear the watchdog expiration bit */ + reg = readl(priv->reg + TIMER_A370_STATUS); + reg &= ~WDT_A370_EXPIRED; + writel(reg, priv->reg + TIMER_A370_STATUS); + + /* Enable watchdog timer */ + reg = readl(priv->reg + TIMER_CTRL); + reg |= WDT_ENABLE_BIT; + writel(reg, priv->reg + TIMER_CTRL); + + /* Enable reset on watchdog */ + reg = readl(priv->rstout); + reg |= RSTOUT_ENABLE_BIT; + writel(reg, priv->rstout); + + reg = readl(priv->rstout_mask); + reg &= ~RSTOUT_MASK_BIT; + writel(reg, priv->rstout_mask); + + return 0; +} + +static int orion_wdt_stop(struct udevice *dev) +{ + struct orion_wdt_priv *priv = dev_get_priv(dev); + u32 reg; + + /* Disable reset on watchdog */ + reg = readl(priv->rstout_mask); + reg |= RSTOUT_MASK_BIT; + writel(reg, priv->rstout_mask); + + reg = readl(priv->rstout); + reg &= ~RSTOUT_ENABLE_BIT; + writel(reg, priv->rstout); + + /* Disable watchdog timer */ + reg = readl(priv->reg + TIMER_CTRL); + reg &= ~WDT_ENABLE_BIT; + writel(reg, priv->reg + TIMER_CTRL); + + return 0; +} + +static inline bool save_reg_from_ofdata(struct udevice *dev, int index, + void __iomem **reg, int *offset) +{ + fdt_addr_t addr; + fdt_size_t off; + + addr = fdtdec_get_addr_size_auto_noparent( + gd->fdt_blob, dev_of_offset(dev), "reg", index, &off, true); + + if (addr == FDT_ADDR_T_NONE) + return false; + + *reg = (void __iomem *) addr; + if (offset) + *offset = off; + + return true; +} + +static int orion_wdt_ofdata_to_platdata(struct udevice *dev) +{ + struct orion_wdt_priv *priv = dev_get_priv(dev); + + if (!save_reg_from_ofdata(dev, 0, &priv->reg, + &priv->wdt_counter_offset)) + goto err; + + if (!save_reg_from_ofdata(dev, 1, &priv->rstout, NULL)) + goto err; + + if (!save_reg_from_ofdata(dev, 2, &priv->rstout_mask, NULL)) + goto err; + + return 0; +err: + debug("%s: Could not determine Orion wdt IO addresses\n", __func__); + return -ENXIO; +} + +static int orion_wdt_probe(struct udevice *dev) +{ + debug("%s: Probing wdt%u\n", __func__, dev->seq); + orion_wdt_stop(dev); + + return 0; +} + +static const struct wdt_ops orion_wdt_ops = { + .start = orion_wdt_start, + .reset = orion_wdt_reset, + .stop = orion_wdt_stop, +}; + +static const struct udevice_id orion_wdt_ids[] = { + { .compatible = "marvell,armada-380-wdt" }, + {} +}; + +U_BOOT_DRIVER(orion_wdt) = { + .name = "orion_wdt", + .id = UCLASS_WDT, + .of_match = orion_wdt_ids, + .probe = orion_wdt_probe, + .priv_auto_alloc_size = sizeof(struct orion_wdt_priv), + .ofdata_to_platdata = orion_wdt_ofdata_to_platdata, + .ops = &orion_wdt_ops, +};

-- 2.13.0

Marek Behun

2:04 p.m.

New subject: [U-Boot] [PATCH v3 3/6] arch/arm/dts: Add Turris Omnia device tree

From: Marek Behún marek.behun@nic.cz

This device tree is taken from mainline Linux kernel commit 7b7db5ab. Added is also a -u-boot.dtsi file with these additions:

- aliases for I2C devices are added, because u-boot i2cmux doesn't work otherwise - the ATSHA204A node is added in the i2c@5 node - "u-boot,dm-pre-reloc"s are added in needed nodes for SPL build to work correctly

Signed-off-by: Marek Behun marek.behun@nic.cz

create mode 100644 arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi create mode 100644 arch/arm/dts/armada-385-turris-omnia.dts

diff --git a/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi b/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi new file mode 100644 index 0000000000..44631e56d7 --- /dev/null +++ b/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2017 Marek Behun marek.behun@nic.cz + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/ { + aliases { + i2c0 = &i2c0; + i2c1 = &i2cmux; + }; +}; + +&i2c0 { + u-boot,dm-pre-reloc; + + i2cmux: i2cmux@70 { + u-boot,dm-pre-reloc; + + i2c@0 { + u-boot,dm-pre-reloc; + }; + + i2c@1 { + u-boot,dm-pre-reloc; + }; + + i2c@5 { + u-boot,dm-pre-reloc; + + /* ATSHA204A at address 0x64 */ + atsha204a@64 { + u-boot,dm-pre-reloc; + compatible = "atmel,atsha204a"; + reg = <0x64>; + }; + }; + }; +}; + +&spi0 { + u-boot,dm-pre-reloc; + + spi-nor@0 { + u-boot,dm-pre-reloc; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/armada-385-turris-omnia.dts b/arch/arm/dts/armada-385-turris-omnia.dts new file mode 100644 index 0000000000..28eede180e --- /dev/null +++ b/arch/arm/dts/armada-385-turris-omnia.dts @@ -0,0 +1,392 @@ +/* + * Device Tree file for the Turris Omnia + * + * Copyright (C) 2016 Uwe Kleine-König uwe@kleine-koenig.org + * Copyright (C) 2016 Tomas Hlavacek tmshlvkc@gmail.com + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Schematic available at https://www.turris.cz/doc/_media/rtrom01-schema.pdf + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include "armada-385.dtsi" + +/ { + model = "Turris Omnia"; + compatible = "cznic,turris-omnia", "marvell,armada385", "marvell,armada380"; + + chosen { + stdout-path = &uart0; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; /* 1024 MB */ + }; + + soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 + MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000 + MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000 + MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>; + + internal-regs { + + /* USB part of the PCIe2/USB 2.0 port */ + usb@58000 { + status = "okay"; + }; + + sata@a8000 { + status = "okay"; + }; + + sdhci@d8000 { + pinctrl-names = "default"; + pinctrl-0 = <&sdhci_pins>; + status = "okay"; + + bus-width = <8>; + no-1-8-v; + non-removable; + }; + + usb3@f0000 { + status = "okay"; + }; + + usb3@f8000 { + status = "okay"; + }; + }; + + pcie-controller { + status = "okay"; + + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; + + pcie@3,0 { + /* Port 2, Lane 0 */ + status = "okay"; + }; + }; + }; +}; + +/* Connected to 88E6176 switch, port 6 */ +&eth0 { + pinctrl-names = "default"; + pinctrl-0 = <&ge0_rgmii_pins>; + status = "okay"; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +/* Connected to 88E6176 switch, port 5 */ +&eth1 { + pinctrl-names = "default"; + pinctrl-0 = <&ge1_rgmii_pins>; + status = "okay"; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +/* WAN port */ +&eth2 { + status = "okay"; + phy-mode = "sgmii"; + phy = <&phy1>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + + i2cmux@70 { + compatible = "nxp,pca9547"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + status = "okay"; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + /* STM32F0 command interface at address 0x2a */ + /* leds device (in STM32F0) at address 0x2b */ + + eeprom@54 { + compatible = "at,24c64"; + reg = <0x54>; + + /* The EEPROM contains data for bootloader. + * Contents: + * struct omnia_eeprom { + * u32 magic; (=0x0341a034 in LE) + * u32 ramsize; (in GiB) + * char regdomain[4]; + * u32 crc32; + * }; + */ + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + /* routed to PCIe0/mSATA connector (CN7A) */ + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + /* routed to PCIe1/USB2 connector (CN61A) */ + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + /* routed to PCIe2 connector (CN62A) */ + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + + /* routed to SFP+ */ + }; + + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + + /* ATSHA204A at address 0x64 */ + }; + + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + + /* exposed on pin header */ + }; + + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + + pcawan: gpio@71 { + /* + * GPIO expander for SFP+ signals and + * and phy irq + */ + compatible = "nxp,pca9538"; + reg = <0x71>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcawan_pins>; + + interrupt-parent = <&gpio1>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + + gpio-controller; + #gpio-cells = <2>; + }; + }; + }; +}; + +&mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + status = "okay"; + + phy1: phy@1 { + status = "okay"; + compatible = "ethernet-phy-id0141.0DD1", "ethernet-phy-ieee802.3-c22"; + reg = <1>; + + /* irq is connected to &pcawan pin 7 */ + }; + + /* Switch MV88E6176 at address 0x10 */ + switch@10 { + compatible = "marvell,mv88e6085"; + #address-cells = <1>; + #size-cells = <0>; + dsa,member = <0 0>; + + reg = <0x10>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + ports@0 { + reg = <0>; + label = "lan0"; + }; + + ports@1 { + reg = <1>; + label = "lan1"; + }; + + ports@2 { + reg = <2>; + label = "lan2"; + }; + + ports@3 { + reg = <3>; + label = "lan3"; + }; + + ports@4 { + reg = <4>; + label = "lan4"; + }; + + ports@5 { + reg = <5>; + label = "cpu"; + ethernet = <&eth1>; + phy-mode = "rgmii-id"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + /* port 6 is connected to eth0 */ + }; + }; +}; + +&pinctrl { + pcawan_pins: pcawan-pins { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + + spi0cs0_pins: spi0cs0-pins { + marvell,pins = "mpp25"; + marvell,function = "spi0"; + }; + + spi0cs1_pins: spi0cs1-pins { + marvell,pins = "mpp26"; + marvell,function = "spi0"; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins &spi0cs0_pins>; + status = "okay"; + + spi-nor@0 { + compatible = "spansion,s25fl164k", "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <40000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x0 0x00100000>; + label = "U-Boot"; + }; + + partition@100000 { + reg = <0x00100000 0x00700000>; + label = "Rescue system"; + }; + }; + }; + + /* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */ +}; + +&uart0 { + /* Pin header CN10 */ + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&uart1 { + /* Pin header CN11 */ + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; +};

-- 2.13.0

Marek Behun

2:04 p.m.

New subject: [U-Boot] [PATCH v3 4/6] drivers/i2c/muxes/pca954x: Add pca9547 I2C mux support

From: Marek Behún marek.behun@nic.cz

This I2C mux is found, for example, on the Turris Omnia board.

Signed-off-by: Marek Behun marek.behun@nic.cz

diff --git a/drivers/i2c/muxes/pca954x.c b/drivers/i2c/muxes/pca954x.c index 1a6761858c..383f72f552 100644 --- a/drivers/i2c/muxes/pca954x.c +++ b/drivers/i2c/muxes/pca954x.c @@ -13,11 +13,40 @@

DECLARE_GLOBAL_DATA_PTR;

+enum pca_type { + PCA9544, + PCA9547, + PCA9548 +}; + +struct chip_desc { + u8 enable; + enum muxtype { + pca954x_ismux = 0, + pca954x_isswi, + } muxtype; +}; + struct pca954x_priv { u32 addr; /* I2C mux address */ u32 width; /* I2C mux width - number of busses */ };

+static const struct chip_desc chips[] = { + [PCA9544] = { + .enable = 0x4, + .muxtype = pca954x_ismux, + }, + [PCA9547] = { + .enable = 0x8, + .muxtype = pca954x_ismux, + }, + [PCA9548] = { + .enable = 0x8, + .muxtype = pca954x_isswi, + }, +}; + static int pca954x_deselect(struct udevice *mux, struct udevice *bus, uint channel) { @@ -31,7 +60,13 @@ static int pca954x_select(struct udevice *mux, struct udevice *bus, uint channel) { struct pca954x_priv *priv = dev_get_priv(mux); - uchar byte = 1 << channel; + const struct chip_desc *chip = &chips[dev_get_driver_data(mux)]; + uchar byte; + + if (chip->muxtype == pca954x_ismux) + byte = channel | chip->enable; + else + byte = 1 << channel;

return dm_i2c_write(mux, priv->addr, &byte, 1); } @@ -42,8 +77,9 @@ static const struct i2c_mux_ops pca954x_ops = { };

static const struct udevice_id pca954x_ids[] = { - { .compatible = "nxp,pca9548", .data = (ulong)8 }, - { .compatible = "nxp,pca9544", .data = (ulong)4 }, + { .compatible = "nxp,pca9544", .data = PCA9544 }, + { .compatible = "nxp,pca9547", .data = PCA9547 }, + { .compatible = "nxp,pca9548", .data = PCA9548 }, { } };

-- 2.13.0

Heiko Schocher

7 Jun 7 Jun

6:19 a.m.

New subject: [U-Boot] [PATCH v3 4/6] drivers/i2c/muxes/pca954x: Add pca9547 I2C mux support

Hello Marek,

Am 06.06.2017 um 14:04 schrieb Marek Behun:

...

From: Marek Behún marek.behun@nic.cz

This I2C mux is found, for example, on the Turris Omnia board.

Signed-off-by: Marek Behun marek.behun@nic.cz

Reviewed-by: Heiko Schocher hs@denx.de

bye, Heiko

...

diff --git a/drivers/i2c/muxes/pca954x.c b/drivers/i2c/muxes/pca954x.c index 1a6761858c..383f72f552 100644 --- a/drivers/i2c/muxes/pca954x.c +++ b/drivers/i2c/muxes/pca954x.c @@ -13,11 +13,40 @@

DECLARE_GLOBAL_DATA_PTR;

+enum pca_type {

PCA9544,

PCA9547,

PCA9548

+};

+struct chip_desc {
u8 enable;

enum muxtype {
pca954x_ismux = 0,
pca954x_isswi,
} muxtype;
+};

struct pca954x_priv { u32 addr; /* I2C mux address */ u32 width; /* I2C mux width - number of busses */ };

+static const struct chip_desc chips[] = {
[PCA9544] = {
.enable = 0x4,
.muxtype = pca954x_ismux,
},

[PCA9547] = {
.enable = 0x8,
.muxtype = pca954x_ismux,
},

[PCA9548] = {
.enable = 0x8,
.muxtype = pca954x_isswi,
},
+};

static int pca954x_deselect(struct udevice *mux, struct udevice *bus, uint channel) {

@@ -31,7 +60,13 @@ static int pca954x_select(struct udevice *mux, struct udevice *bus, uint channel) { struct pca954x_priv *priv = dev_get_priv(mux);

uchar byte = 1 << channel;
const struct chip_desc *chip = &chips[dev_get_driver_data(mux)];

uchar byte;

if (chip->muxtype == pca954x_ismux)
byte = channel | chip->enable;
else
byte = 1 << channel;
return dm_i2c_write(mux, priv->addr, &byte, 1); }
@@ -42,8 +77,9 @@ static const struct i2c_mux_ops pca954x_ops = { };

static const struct udevice_id pca954x_ids[] = {

{ .compatible = "nxp,pca9548", .data = (ulong)8 },

{ .compatible = "nxp,pca9544", .data = (ulong)4 },

{ .compatible = "nxp,pca9544", .data = PCA9544 },

{ .compatible = "nxp,pca9547", .data = PCA9547 },

{ .compatible = "nxp,pca9548", .data = PCA9548 }, { } };

-- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

Marek Behun

6 Jun 6 Jun

2:04 p.m.

New subject: [U-Boot] [PATCH v3 5/6] drivers/misc: Add basic support for ATSHA204A Crypto module

From: Marek Behún marek.behun@nic.cz

This module can be found on the Turris Omnia board connected via the I2C interface.

Among some cryptographic functions, the chip has a 512 bit One Time Programmable memory, 88 byte configuration memory and 512 byte general purpose memory.

The Turris Omnia stores serial number and device MAC address in the OTP memory.

This commit adds basic support for reading the EEPROM and also exposes the chips Random Number Generator.

The driver is based on code by Josh Datko, Cryptotronix, jbd@cryptotronix.com and also Tomas Hlavacek, CZ.NIC, tomas.hlavacek@nic.cz

Signed-off-by: Tomas Hlavacek tomas.hlavacek@nic.cz Signed-off-by: Marek Behun marek.behun@nic.cz

create mode 100644 drivers/misc/atsha204a-i2c.c create mode 100644 include/atsha204a-i2c.h

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index ecca159d14..8073cdc628 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -20,6 +20,14 @@ config ALTERA_SYSID Select this to enable a sysid for Altera devices. Please find details on the "Embedded Peripherals IP User Guide" of Altera.

+config ATSHA204A + bool "Support for Atmel ATSHA204A module" + depends on MISC + help + Enable support for I2C connected Atmel's ATSHA204A + CryptoAuthentication module found for example on the Turris Omnia + board. + config CMD_CROS_EC bool "Enable crosec command" depends on CROS_EC diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 4543cd647e..bb51f9fafe 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_MISC) += misc-uclass.o obj-$(CONFIG_ALI152X) += ali512x.o obj-$(CONFIG_ALTERA_SYSID) += altera_sysid.o +obj-$(CONFIG_ATSHA204A) += atsha204a-i2c.o obj-$(CONFIG_DS4510) += ds4510.o obj-$(CONFIG_CBMEM_CONSOLE) += cbmem_console.o ifndef CONFIG_SPL_BUILD diff --git a/drivers/misc/atsha204a-i2c.c b/drivers/misc/atsha204a-i2c.c new file mode 100644 index 0000000000..f9fff06072 --- /dev/null +++ b/drivers/misc/atsha204a-i2c.c @@ -0,0 +1,307 @@ +/* + * I2C Driver for Atmel ATSHA204 over I2C + * + * Copyright (C) 2014 Josh Datko, Cryptotronix, jbd@cryptotronix.com + * 2016 Tomas Hlavacek, CZ.NIC, tmshlvck@gmail.com + * 2017 Marek Behun, CZ.NIC, marek.behun@nic.cz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <common.h> +#include <dm.h> +#include <i2c.h> +#include <errno.h> +#include <atsha204a-i2c.h> + +#define ATSHA204A_TWLO 60 +#define ATSHA204A_TRANSACTION_TIMEOUT 100000 +#define ATSHA204A_TRANSACTION_RETRY 5 +#define ATSHA204A_EXECTIME 5000 + +DECLARE_GLOBAL_DATA_PTR; + +static u16 atsha204a_crc16(const u8 *buf, u8 len) +{ + u8 i; + u16 crc16 = 0; + u8 shift; + + for (i = 0; i < len; i++) { + for (shift = 0x01; shift > 0x00; shift <<= 1) { + u8 data_bit = (buf[i] & shift) ? 1 : 0; + u8 crc_bit = crc16 >> 15; + + crc16 <<= 1; + + if ((data_bit ^ crc_bit) != 0) + crc16 ^= 0x8005; + } + } + + return cpu_to_le16(crc16); +} + +static int atsha204a_send(struct udevice *dev, const u8 *buf, u8 len) +{ + fdt_addr_t *priv = dev_get_priv(dev); + struct i2c_msg msg; + + msg.addr = *priv; + msg.flags = I2C_M_STOP; + msg.len = len; + msg.buf = (u8 *) buf; + + return dm_i2c_xfer(dev, &msg, 1); +} + +static int atsha204a_recv(struct udevice *dev, u8 *buf, u8 len) +{ + fdt_addr_t *priv = dev_get_priv(dev); + struct i2c_msg msg; + + msg.addr = *priv; + msg.flags = I2C_M_RD | I2C_M_STOP; + msg.len = len; + msg.buf = (u8 *) buf; + + return dm_i2c_xfer(dev, &msg, 1); +} + +static int atsha204a_recv_resp(struct udevice *dev, + struct atsha204a_resp *resp) +{ + int res; + u16 resp_crc, computed_crc; + u8 *p = (u8 *) resp; + + res = atsha204a_recv(dev, p, 4); + if (res) + return res; + + if (resp->length > 4) { + if (resp->length > sizeof(*resp)) + return -EMSGSIZE; + + res = atsha204a_recv(dev, p + 4, resp->length - 4); + if (res) + return res; + } + + resp_crc = (u16) p[resp->length - 2] + | (((u16) p[resp->length - 1]) << 8); + computed_crc = atsha204a_crc16(p, resp->length - 2); + + if (resp_crc != computed_crc) { + debug("Invalid checksum in ATSHA204A response\n"); + return -EBADMSG; + } + + return 0; +} + +int atsha204a_wakeup(struct udevice *dev) +{ + u8 req[4]; + struct atsha204a_resp resp; + int try, res; + + debug("Waking up ATSHA204A\n"); + + for (try = 1; try <= 10; ++try) { + debug("Try %i... ", try); + + memset(req, 0, 4); + res = atsha204a_send(dev, req, 4); + if (res) { + debug("failed on I2C send, trying again\n"); + continue; + } + + udelay(ATSHA204A_TWLO); + + res = atsha204a_recv_resp(dev, &resp); + if (res) { + debug("failed on receiving response, ending\n"); + return res; + } + + if (resp.code != ATSHA204A_STATUS_AFTER_WAKE) { + debug ("failed (responce code = %02x), ending\n", + resp.code); + return -EBADMSG; + } + + debug("success\n"); + break; + } + + return 0; +} + +int atsha204a_idle(struct udevice *dev) +{ + int res; + u8 req = ATSHA204A_FUNC_IDLE; + + res = atsha204a_send(dev, &req, 1); + if (res) + debug("Failed putting ATSHA204A idle\n"); + return res; +} + +int atsha204a_sleep(struct udevice *dev) +{ + int res; + u8 req = ATSHA204A_FUNC_IDLE; + + res = atsha204a_send(dev, &req, 1); + if (res) + debug("Failed putting ATSHA204A to sleep\n"); + return res; +} + +static int atsha204a_transaction(struct udevice *dev, struct atsha204a_req *req, + struct atsha204a_resp *resp) +{ + int res, timeout = ATSHA204A_TRANSACTION_TIMEOUT; + + res = atsha204a_send(dev, (u8 *) req, req->length + 1); + if (res) { + debug("ATSHA204A transaction send failed\n"); + return -EBUSY; + } + + do { + res = atsha204a_recv_resp(dev, resp); + if (!res || res == -EMSGSIZE || res == -EBADMSG) + break; + + debug("ATSHA204A transaction polling for response " + "(timeout = %d)\n", timeout); + + udelay(ATSHA204A_EXECTIME); + timeout -= ATSHA204A_EXECTIME; + } while (timeout > 0); + + if (timeout <= 0) { + debug("ATSHA204A transaction timed out\n"); + return -ETIMEDOUT; + } + + return res; +} + +static void atsha204a_req_crc32(struct atsha204a_req *req) +{ + u8 *p = (u8 *) req; + u16 computed_crc; + u16 *crc_ptr = (u16 *) &p[req->length - 1]; + + /* The buffer to crc16 starts at byte 1, not 0 */ + computed_crc = atsha204a_crc16(p + 1, req->length - 2); + + *crc_ptr = cpu_to_le16(computed_crc); +} + +int atsha204a_read(struct udevice *dev, enum atsha204a_zone zone, bool read32, + u16 addr, u8 *buffer) +{ + int res, retry = ATSHA204A_TRANSACTION_RETRY; + struct atsha204a_req req; + struct atsha204a_resp resp; + + req.function = ATSHA204A_FUNC_COMMAND; + req.length = 7; + req.command = ATSHA204A_CMD_READ; + + req.param1 = (u8) zone; + if (read32) + req.param1 |= 0x80; + + req.param2 = cpu_to_le16(addr); + + atsha204a_req_crc32(&req); + + do { + res = atsha204a_transaction(dev, &req, &resp); + if (!res) + break; + + debug("ATSHA204A read retry (%d)\n", retry); + retry--; + atsha204a_wakeup(dev); + } while (retry >= 0); + + if (res) { + debug("ATSHA204A read failed\n"); + return res; + } + + if (resp.length != (read32 ? 32 : 4) + 3) { + debug("ATSHA204A read bad response length (%d)\n", + resp.length); + return -EBADMSG; + } + + memcpy(buffer, ((u8 *) &resp) + 1, read32 ? 32 : 4); + + return 0; +} + +int atsha204a_get_random(struct udevice *dev, u8 *buffer, size_t max) +{ + int res; + struct atsha204a_req req; + struct atsha204a_resp resp; + + req.function = ATSHA204A_FUNC_COMMAND; + req.length = 7; + req.command = ATSHA204A_CMD_RANDOM; + + req.param1 = 1; + req.param2 = 0; + + /* We do not have to compute the checksum dynamically */ + req.data[0] = 0x27; + req.data[1] = 0x47; + + res = atsha204a_transaction(dev, &req, &resp); + if (res) { + debug("ATSHA204A random transaction failed\n"); + return res; + } + + memcpy(buffer, ((u8 *) &resp) + 1, max >= 32 ? 32 : max); + return 0; +} + +static int atsha204a_ofdata_to_platdata(struct udevice *dev) +{ + fdt_addr_t *priv = dev_get_priv(dev); + fdt_addr_t addr; + + addr = fdtdec_get_addr(gd->fdt_blob, dev_of_offset(dev), "reg"); + if (addr == FDT_ADDR_T_NONE) { + debug("Can't get ATSHA204A I2C base address\n"); + return -ENXIO; + } + + *priv = addr; + return 0; +} + +static const struct udevice_id atsha204a_ids[] = { + { .compatible = "atmel,atsha204a" }, + { } +}; + +U_BOOT_DRIVER(atsha204) = { + .name = "atsha204", + .id = UCLASS_MISC, + .of_match = atsha204a_ids, + .ofdata_to_platdata = atsha204a_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(fdt_addr_t), +}; diff --git a/include/atsha204a-i2c.h b/include/atsha204a-i2c.h new file mode 100644 index 0000000000..344fd8ace7 --- /dev/null +++ b/include/atsha204a-i2c.h @@ -0,0 +1,69 @@ +/* + * I2C Driver for Atmel ATSHA204 over I2C + * + * Copyright (C) 2014 Josh Datko, Cryptotronix, jbd@cryptotronix.com + * 2016 Tomas Hlavacek, CZ.NIC, tmshlvck@gmail.com + * 2017 Marek Behun, CZ.NIC, marek.behun@nic.cz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef _ATSHA204_I2C_H_ +#define _ATSHA204_I2C_H_ + +enum atsha204a_zone +{ + ATSHA204A_ZONE_CONFIG = 0, + ATSHA204A_ZONE_OTP = 1, + ATSHA204A_ZONE_DATA = 2, +}; + +enum atsha204a_status +{ + ATSHA204A_STATUS_SUCCESS = 0x00, + ATSHA204A_STATUS_MISCOMPARE = 0x01, + ATSHA204A_STATUS_PARSE_ERROR = 0x03, + ATSHA204A_STATUS_EXEC_ERROR = 0x0F, + ATSHA204A_STATUS_AFTER_WAKE = 0x11, + ATSHA204A_STATUS_CRC_ERROR = 0xFF, +}; + +enum atsha204a_func +{ + ATSHA204A_FUNC_RESET = 0x00, + ATSHA204A_FUNC_SLEEP = 0x01, + ATSHA204A_FUNC_IDLE = 0x02, + ATSHA204A_FUNC_COMMAND = 0x03, +}; + +enum atsha204a_cmd +{ + ATSHA204A_CMD_READ = 0x02, + ATSHA204A_CMD_RANDOM = 0x1B, +}; + +struct atsha204a_resp +{ + u8 length; + u8 code; + u8 data[82]; +} __attribute__ ((packed)); + +struct atsha204a_req +{ + u8 function; + u8 length; + u8 command; + u8 param1; + u16 param2; + u8 data[78]; +} __attribute__ ((packed)); + +int atsha204a_wakeup(struct udevice *); +int atsha204a_idle(struct udevice *); +int atsha204a_sleep(struct udevice *); +int atsha204a_read(struct udevice *, enum atsha204a_zone, bool, u16, u8 *); +int atsha204a_get_random(struct udevice *, u8 *, size_t); + +#endif /* _ATSHA204_I2C_H_ */

-- 2.13.0

Marek Behun

2:04 p.m.

New subject: [U-Boot] [PATCH v3 6/6] marvell: armada385: Add the Turris Omnia board

From: Marek Behún marek.behun@nic.cz

The Turris Omnia is a open-source router created by CZ.NIC.

The code is based on the Marvell/db-88f6820-gp by Stefan Roese with modifications from Tomas Hlavacek in the CZ.NIC turris-omnia-uboot repository, which can be found at https://gitlab.labs.nic.cz/turris/turris-omnia-uboot

By default, the Turris Omnia uses btrfs as the main and only filesystem, and also loads kernel and device tree from this filesystem. Since U-Boot does not yet support btrfs, you should not flash your Turris Omnia board with this unless you know what you are doing.

Signed-off-by: Tomas Hlavacek tomas.hlavacek@nic.cz Signed-off-by: Marek Behun marek.behun@nic.cz

create mode 100644 board/CZ.NIC/turris_omnia/Makefile create mode 100644 board/CZ.NIC/turris_omnia/kwbimage.cfg create mode 100644 board/CZ.NIC/turris_omnia/turris_omnia.c create mode 100644 configs/turris_omnia_defconfig create mode 100644 include/configs/turris_omnia.h

diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 6ae54ef46a..6b16f57464 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -90,6 +90,10 @@ config TARGET_DB_88F6820_AMC bool "Support DB-88F6820-AMC" select 88F6820

+config TARGET_TURRIS_OMNIA + bool "Support Turris Omnia" + select 88F6820 + config TARGET_MVEBU_ARMADA_8K bool "Support Armada 7k/8k platforms" select ARMADA_8K @@ -124,6 +128,7 @@ config SYS_BOARD default "db-88f6720" if TARGET_DB_88F6720 default "db-88f6820-gp" if TARGET_DB_88F6820_GP default "db-88f6820-amc" if TARGET_DB_88F6820_AMC + default "turris_omnia" if TARGET_TURRIS_OMNIA default "mvebu_armada-8k" if TARGET_MVEBU_ARMADA_8K default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP default "ds414" if TARGET_DS414 @@ -141,6 +146,7 @@ config SYS_CONFIG_NAME default "ds414" if TARGET_DS414 default "maxbcm" if TARGET_MAXBCM default "theadorable" if TARGET_THEADORABLE + default "turris_omnia" if TARGET_TURRIS_OMNIA

config SYS_VENDOR default "Marvell" if TARGET_DB_MV784MP_GP @@ -151,10 +157,26 @@ config SYS_VENDOR default "Marvell" if TARGET_MVEBU_ARMADA_8K default "solidrun" if TARGET_CLEARFOG default "Synology" if TARGET_DS414 + default "CZ.NIC" if TARGET_TURRIS_OMNIA

config SYS_SOC default "mvebu"

+if TARGET_TURRIS_OMNIA + +choice + prompt "Turris Omnia boot method" + +config TURRIS_OMNIA_SPL_BOOT_DEVICE_SPI + bool "SPI NOR flash" + +config TURRIS_OMNIA_SPL_BOOT_DEVICE_MMC + bool "SDIO/MMC card" + +endchoice + +endif + config MVEBU_EFUSE bool "Enable eFuse support" default n diff --git a/board/CZ.NIC/turris_omnia/Makefile b/board/CZ.NIC/turris_omnia/Makefile new file mode 100644 index 0000000000..f2ae50654f --- /dev/null +++ b/board/CZ.NIC/turris_omnia/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2017 Marek Behun marek.behun@nic.cz +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := turris_omnia.o diff --git a/board/CZ.NIC/turris_omnia/kwbimage.cfg b/board/CZ.NIC/turris_omnia/kwbimage.cfg new file mode 100644 index 0000000000..cc05792556 --- /dev/null +++ b/board/CZ.NIC/turris_omnia/kwbimage.cfg @@ -0,0 +1,12 @@ +# +# Copyright (C) 2014 Stefan Roese sr@denx.de +# + +# Armada XP uses version 1 image format +VERSION 1 + +# Boot Media configurations +BOOT_FROM spi + +# Binary Header (bin_hdr) with DDR3 training code +BINARY spl/u-boot-spl.bin 0000005b 00000068 diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c new file mode 100644 index 0000000000..3492e4f398 --- /dev/null +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -0,0 +1,504 @@ +/* + * Copyright (C) 2017 Marek Behun marek.behun@nic.cz + * Copyright (C) 2016 Tomas Hlavacek tomas.hlavacek@nic.cz + * + * Derived from the code for + * Marvell/db-88f6820-gp by Stefan Roese sr@denx.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> +#include <dm/uclass.h> +#include <fdt_support.h> + +#ifdef CONFIG_ATSHA204A +# include <atsha204a-i2c.h> +#endif + +#ifdef CONFIG_WDT_ORION +# include <wdt.h> +#endif + +#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h" +#include <../serdes/a38x/high_speed_env_spec.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define OMNIA_I2C_EEPROM_DM_NAME "i2c@0" +#define OMNIA_I2C_EEPROM 0x54 +#define OMNIA_I2C_EEPROM_CONFIG_ADDR 0x0 +#define OMNIA_I2C_EEPROM_ADDRLEN 2 +#define OMNIA_I2C_EEPROM_MAGIC 0x0341a034 + +#define OMNIA_I2C_MCU_DM_NAME "i2c@1" +#define OMNIA_I2C_MCU_ADDR_STATUS 0x1 +#define OMNIA_I2C_MCU_SATA 0x20 +#define OMNIA_I2C_MCU_CARDDET 0x10 +#define OMNIA_I2C_MCU 0x2a +#define OMNIA_I2C_MCU_WDT_ADDR 0x0b + +#define OMNIA_ATSHA204_OTP_VERSION 0 +#define OMNIA_ATSHA204_OTP_SERIAL 1 +#define OMNIA_ATSHA204_OTP_MAC0 3 +#define OMNIA_ATSHA204_OTP_MAC1 4 + +#define MVTWSI_ARMADA_DEBUG_REG 0x8c + +/* + * Those values and defines are taken from the Marvell U-Boot version + * "u-boot-2013.01-2014_T3.0" + */ +#define OMNIA_GPP_OUT_ENA_LOW \ + (~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \ + BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) | \ + BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31))) +#define OMNIA_GPP_OUT_ENA_MID \ + (~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \ + BIT(16) | BIT(17) | BIT(18))) + +#define OMNIA_GPP_OUT_VAL_LOW 0x0 +#define OMNIA_GPP_OUT_VAL_MID 0x0 +#define OMNIA_GPP_POL_LOW 0x0 +#define OMNIA_GPP_POL_MID 0x0 + +static struct serdes_map board_serdes_map_pex[] = { + {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, + {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, + {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, + {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, + {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, + {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0} +}; + +static struct serdes_map board_serdes_map_sata[] = { + {SATA0, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0}, + {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, + {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, + {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, + {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, + {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0} +}; + +static bool omnia_detect_sata(void) +{ + struct udevice *bus, *dev; + int ret; + u16 mode; + + puts("SERDES0 card detect: "); + + if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_MCU_DM_NAME, &bus)) { + puts("Cannot find MCU bus!\n"); + return false; + } + + ret = i2c_get_chip(bus, OMNIA_I2C_MCU, 1, &dev); + if (ret) { + puts("Cannot get MCU chip!\n"); + return false; + } + + ret = dm_i2c_read(dev, OMNIA_I2C_MCU_ADDR_STATUS, (uchar *) &mode, 2); + if (ret) { + puts("I2C read failed! Default PEX\n"); + return false; + } + + if (!(mode & OMNIA_I2C_MCU_CARDDET)) { + puts("NONE\n"); + return false; + } + + if (mode & OMNIA_I2C_MCU_SATA) { + puts("SATA\n"); + return true; + } else { + puts("PEX\n"); + return false; + } +} + +int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count) +{ + if (omnia_detect_sata()) { + *serdes_map_array = board_serdes_map_sata; + *count = ARRAY_SIZE(board_serdes_map_sata); + } else { + *serdes_map_array = board_serdes_map_pex; + *count = ARRAY_SIZE(board_serdes_map_pex); + } + + return 0; +} + +struct omnia_eeprom { + u32 magic; + u32 ramsize; + char region[4]; + u32 crc; +}; + +static int omnia_read_eeprom(struct omnia_eeprom *oep) +{ + struct udevice *bus, *dev; + int ret, crc, retry = 3; + + if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_EEPROM_DM_NAME, &bus)) { + puts("Cannot find EEPROM bus\n"); + return false; + } + + ret = i2c_get_chip(bus, OMNIA_I2C_EEPROM, OMNIA_I2C_EEPROM_ADDRLEN, &dev); + if (ret) { + puts("Cannot get EEPROM chip\n"); + return false; + } + + for (; retry > 0; --retry) { + ret = dm_i2c_read(dev, OMNIA_I2C_EEPROM_CONFIG_ADDR, (uchar *) oep, sizeof(struct omnia_eeprom)); + if (ret) + continue; + + if (oep->magic != OMNIA_I2C_EEPROM_MAGIC) { + puts("I2C EEPROM missing magic number!\n"); + continue; + } + + crc = crc32(0, (unsigned char *) oep, + sizeof(struct omnia_eeprom) - 4); + if (crc == oep->crc) { + break; + } else { + printf("CRC of EEPROM memory config failed! " + "calc=0x%04x saved=0x%04x\n", crc, oep->crc); + } + } + + if (!retry) { + puts("I2C EEPROM read failed!\n"); + return -1; + } + + return 0; +} + +/* + * Define the DDR layout / topology here in the board file. This will + * be used by the DDR3 init code in the SPL U-Boot version to configure + * the DDR3 controller. + */ +static struct hws_topology_map board_topology_map_1g = { + 0x1, /* active interfaces */ + /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */ + { { { {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0} }, + SPEED_BIN_DDR_1600K, /* speed_bin */ + BUS_WIDTH_16, /* memory_width */ + MEM_4G, /* mem_size */ + DDR_FREQ_800, /* frequency */ + 0, 0, /* cas_l cas_wl */ + HWS_TEMP_NORMAL, /* temperature */ + HWS_TIM_2T} }, /* timing (force 2t) */ + 5, /* Num Of Bus Per Interface*/ + BUS_MASK_32BIT /* Busses mask */ +}; + +static struct hws_topology_map board_topology_map_2g = { + 0x1, /* active interfaces */ + /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */ + { { { {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0}, + {0x1, 0, 0, 0} }, + SPEED_BIN_DDR_1600K, /* speed_bin */ + BUS_WIDTH_16, /* memory_width */ + MEM_8G, /* mem_size */ + DDR_FREQ_800, /* frequency */ + 0, 0, /* cas_l cas_wl */ + HWS_TEMP_NORMAL, /* temperature */ + HWS_TIM_2T} }, /* timing (force 2t) */ + 5, /* Num Of Bus Per Interface*/ + BUS_MASK_32BIT /* Busses mask */ +}; + +struct hws_topology_map *ddr3_get_topology_map(void) +{ + static int mem = 0; + struct omnia_eeprom oep; + + /* Get the board config from EEPROM */ + if (mem == 0) { + if(omnia_read_eeprom(&oep)) + goto out; + + printf("Memory config in EEPROM: 0x%02x\n", oep.ramsize); + + if (oep.ramsize == 0x2) + mem = 2; + else + mem = 1; + } + + /* Hardcoded fallback */ +out: if (mem == 0) { + puts("WARNING: Memory config from EEPROM read failed.\n"); + puts("Falling back to default 1GiB map.\n"); + mem = 1; + } + + /* Return the board topology as defined in the board code */ + if (mem == 1) + return &board_topology_map_1g; + if (mem == 2) + return &board_topology_map_2g; + + return &board_topology_map_1g; +} + +#ifndef CONFIG_SPL_BUILD +static int set_regdomain(void) +{ + struct omnia_eeprom oep; + char rd[3] = {' ', ' ', 0}; + + if(!(omnia_read_eeprom(&oep))) + memcpy(rd, &oep.region, 2); + else + puts("EEPROM regdomain read failed.\n"); + + printf("Regdomain set to %s\n", rd); + return setenv("regdomain", rd); +} +#endif + +int board_early_init_f(void) +{ + u32 i2c_debug_reg; + + /* Configure MPP */ + writel(0x11111111, MVEBU_MPP_BASE + 0x00); + writel(0x11111111, MVEBU_MPP_BASE + 0x04); + writel(0x11244011, MVEBU_MPP_BASE + 0x08); + writel(0x22222111, MVEBU_MPP_BASE + 0x0c); + writel(0x22200002, MVEBU_MPP_BASE + 0x10); + writel(0x30042022, MVEBU_MPP_BASE + 0x14); + writel(0x55550555, MVEBU_MPP_BASE + 0x18); + writel(0x00005550, MVEBU_MPP_BASE + 0x1c); + + /* Set GPP Out value */ + writel(OMNIA_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); + writel(OMNIA_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); + + /* Set GPP Polarity */ + writel(OMNIA_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c); + writel(OMNIA_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c); + + /* Set GPP Out Enable */ + writel(OMNIA_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); + writel(OMNIA_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); + + /* Disable I2C debug mode blocking 0x64 I2C address */ + i2c_debug_reg = readl(MVEBU_TWSI_BASE + MVTWSI_ARMADA_DEBUG_REG); + i2c_debug_reg &= ~(1<<18); + writel(i2c_debug_reg, MVEBU_TWSI_BASE + MVTWSI_ARMADA_DEBUG_REG); + + return 0; +} + +#ifndef CONFIG_SPL_BUILD +static int disable_mcu_watchdog(void) +{ + struct udevice *bus, *dev; + int ret, retry = 3; + uchar buf[1] = {0x0}; + + if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_MCU_DM_NAME, &bus)) { + puts("Cannot find MCU bus! Can not disable MCU WDT.\n"); + return false; + } + + ret = i2c_get_chip(bus, OMNIA_I2C_MCU, 1, &dev); + if (ret) { + puts("Cannot get MCU chip! Can not disable MCU WDT.\n"); + return false; + } + + for (; retry > 0; --retry) + if (!dm_i2c_write(dev, OMNIA_I2C_MCU_WDT_ADDR, (uchar *) buf, 1)) + break; + + if (retry <= 0) { + puts("I2C MCU watchdog failed to disable!\n"); + return -2; + } + + return 0; +} +#endif + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + +#ifndef CONFIG_SPL_BUILD +# ifdef CONFIG_WDT_ORION + struct udevice *dev; + + if (uclass_get_device(UCLASS_WDT, 0, &dev)) { + puts("Cannot find Armada 385 watchdog!\n"); + } else { + puts("Enabling Armada 385 watchdog.\n"); + wdt_start(dev, (u32) 25000000 * 120, 0); + } +# endif + + puts("Disabling MCU startup watchdog.\n"); + disable_mcu_watchdog(); + + set_regdomain(); +#endif + + return 0; +} + +int board_late_init(void) +{ +#ifndef CONFIG_SPL_BUILD + set_regdomain(); +#endif + + return 0; +} + +#ifdef CONFIG_ATSHA204A +static struct udevice *get_atsha204a_dev(void) +{ + static struct udevice *dev = NULL; + + if (dev != NULL) + return dev; + + if (uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", &dev)) { + puts("Cannot find ATSHA204A on I2C bus!\n"); + dev = NULL; + } + + return dev; +} +#endif + +int checkboard(void) +{ + u32 version_num, serial_num; + int err = 1; + +#ifdef CONFIG_ATSHA204A + struct udevice *dev = get_atsha204a_dev(); + + if (dev) { + err = atsha204a_wakeup(dev); + if (err) + goto out; + + err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, + OMNIA_ATSHA204_OTP_VERSION, + (u8 *) &version_num); + if (err) + goto out; + + err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, + OMNIA_ATSHA204_OTP_SERIAL, + (u8 *) &serial_num); + if (err) + goto out; + + atsha204a_sleep(dev); + } + +out: +#endif + + if (err) + printf("Board: Turris Omnia (ver N/A). SN: N/A\n"); + else + printf("Board: Turris Omnia SNL %08X%08X\n", + be32_to_cpu(version_num), be32_to_cpu(serial_num)); + + return 0; +} + +static void increment_mac(u8 *mac) +{ + int i; + + for (i = 5; i >= 3; i--) { + mac[i] += 1; + if (mac[i]) + break; + } +} + +int misc_init_r(void) +{ +#ifdef CONFIG_ATSHA204A + int err; + struct udevice *dev = get_atsha204a_dev(); + u8 mac0[4], mac1[4], mac[6]; + + if (!dev) + goto out; + + err = atsha204a_wakeup(dev); + if (err) + goto out; + + err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, + OMNIA_ATSHA204_OTP_MAC0, mac0); + if (err) + goto out; + + err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, + OMNIA_ATSHA204_OTP_MAC1, mac1); + if (err) + goto out; + + atsha204a_sleep(dev); + + mac[0] = mac0[1]; + mac[1] = mac0[2]; + mac[2] = mac0[3]; + mac[3] = mac1[1]; + mac[4] = mac1[2]; + mac[5] = mac1[3]; + + if (is_valid_ethaddr(mac)) + eth_setenv_enetaddr("ethaddr", mac); + + increment_mac(mac); + + if (is_valid_ethaddr(mac)) + eth_setenv_enetaddr("eth1addr", mac); + + increment_mac(mac); + + if (is_valid_ethaddr(mac)) + eth_setenv_enetaddr("eth2addr", mac); + +out: +#endif + + return 0; +} + diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig new file mode 100644 index 0000000000..512b9da74d --- /dev/null +++ b/configs/turris_omnia_defconfig @@ -0,0 +1,62 @@ +CONFIG_ARM=y +CONFIG_ARCH_MVEBU=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_TURRIS_OMNIA=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_BOOT_DEVICE_SPI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_DEFAULT_DEVICE_TREE="armada-385-turris-omnia" +CONFIG_BOOTDELAY=3 +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_SPL=y +CONFIG_SPL_I2C_SUPPORT=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GO=y +CONFIG_CMD_RUN=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_LOADB=y +CONFIG_CMD_LOADS=y +CONFIG_CMD_MEMORY=y +CONFIG_CMD_ECHO=y +CONFIG_CMD_SETEXPR=y +# CONFIG_PARTITION_UUIDS is not set +# CONFIG_SPL_PARTITION_UUIDS is not set +CONFIG_DOS_PARTITION=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_MISC=y +CONFIG_ATSHA204A=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_NS16550=y +CONFIG_DEBUG_UART_BASE=0xd0012000 +CONFIG_DEBUG_UART_CLOCK=250000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_MV=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI=y +CONFIG_USB_EHCI_MARVELL=y +CONFIG_USB_STORAGE=y +CONFIG_WDT=y +CONFIG_WDT_ORION=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_CMDLINE=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="=> " +# CONFIG_DISPLAY_BOARDINFO is not set diff --git a/include/configs/turris_omnia.h b/include/configs/turris_omnia.h new file mode 100644 index 0000000000..a9d3deba60 --- /dev/null +++ b/include/configs/turris_omnia.h @@ -0,0 +1,174 @@ +/* + * Copyright (C) 2017 Marek Behun marek.behun@nic.cz + * Copyright (C) 2016 Tomas Hlavacek tomas.hlavacek@nic.cz + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_TURRIS_OMNIA_H +#define _CONFIG_TURRIS_OMNIA_H + +/* + * High Level Configuration Options (easy to change) + */ + +#define CONFIG_MISC_INIT_R +#define CONFIG_DISPLAY_BOARDINFO_LATE + +/* + * TEXT_BASE needs to be below 16MiB, since this area is scrubbed + * for DDR ECC byte filling in the SPL before loading the main + * U-Boot into it. + */ +#define CONFIG_SYS_TEXT_BASE 0x00800000 +#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ + +/* + * Commands configuration + */ +#define CONFIG_CMD_PCI + +/* I2C support */ +#define CONFIG_DM_I2C +#define CONFIG_I2C_MUX +#define CONFIG_I2C_MUX_PCA954x +#define CONFIG_SPL_I2C_MUX +#define CONFIG_SYS_I2C_MVTWSI + +/* SPI NOR flash default params, used by sf commands */ +#define CONFIG_SF_DEFAULT_SPEED 1000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 +#define CONFIG_SPI_FLASH_SPANSION + +/* + * SDIO/MMC Card Configuration + */ +#define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE + +/* + * SATA/SCSI/AHCI configuration + */ +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + +/* Partition support */ + +/* Additional FS support/configuration */ +#define CONFIG_SUPPORT_VFAT + +/* USB/EHCI configuration */ +#define CONFIG_EHCI_IS_TDI + +/* Environment in SPI NOR flash */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET (3*(1 << 18)) /* 768KiB in */ +#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ +#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ + +#define CONFIG_PHY_MARVELL /* there is a marvell phy */ +#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ + +/* PCIe support */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_PCI_MVEBU +#define CONFIG_PCI_SCAN_SHOW +#endif + +#define CONFIG_SYS_ALT_MEMTEST + +/* Keep device tree and initrd in lower memory so the kernel can access them */ +#define RELOCATION_LIMITS_ENV_SETTINGS \ + "fdt_high=0x10000000\0" \ + "initrd_high=0x10000000\0" + +/* Defines for SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_SIZE (140 << 10) +#define CONFIG_SPL_TEXT_BASE 0x40000030 +#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030) + +#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) +#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MALLOC_SIMPLE +#endif + +#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) +#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT + +#ifdef CONFIG_TURRIS_OMNIA_SPL_BOOT_DEVICE_SPI +/* SPL related SPI defines */ +# define CONFIG_SPL_SPI_LOAD +# define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000 +# define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS +#endif + +#ifdef CONFIG_TURRIS_OMNIA_SPL_BOOT_DEVICE_MMC +/* SPL related MMC defines */ +# define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10) +# define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS +# ifdef CONFIG_SPL_BUILD +# define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ +# endif +#endif + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* Include the common distro boot environment */ +#ifndef CONFIG_SPL_BUILD +#include <config_distro_defaults.h> + +#ifdef CONFIG_MMC +#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) +#else +#define BOOT_TARGET_DEVICES_MMC(func) +#endif + +#ifdef CONFIG_USB_STORAGE +#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) +#else +#define BOOT_TARGET_DEVICES_USB(func) +#endif + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_USB(func) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#define KERNEL_ADDR_R __stringify(0x1000000) +#define FDT_ADDR_R __stringify(0x2000000) +#define RAMDISK_ADDR_R __stringify(0x2200000) +#define SCRIPT_ADDR_R __stringify(0x1800000) +#define PXEFILE_ADDR_R __stringify(0x1900000) + +#define LOAD_ADDRESS_ENV_SETTINGS \ + "kernel_addr_r=" KERNEL_ADDR_R "\0" \ + "fdt_addr_r=" FDT_ADDR_R "\0" \ + "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \ + "scriptaddr=" SCRIPT_ADDR_R "\0" \ + "pxefile_addr_r=" PXEFILE_ADDR_R "\0" + +#include <config_distro_bootcmd.h> + +#define CONFIG_EXTRA_ENV_SETTINGS \ + RELOCATION_LIMITS_ENV_SETTINGS \ + LOAD_ADDRESS_ENV_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + "console=ttyS0,115200\0" \ + BOOTENV + +#endif /* CONFIG_SPL_BUILD */ + +#endif /* _CONFIG_TURRIS_OMNIA_H */

-- 2.13.0

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Heiko Schocher
Marek Behun
Marek Behún
Stefan Roese