[U-Boot] [PATCH v2 0/7] FPGA cleanup + zynq support
Fpga code is pretty old and none has tried to clean it up. My attempt is related to new code I want to push to mainline which is add support for checking bitstream and if bitstream is valid for the selected device. For this I need to do cleanup code and move code from cmd_fpga.c to fpga.c in driver folder.
Zynq driver: Depends on previous zynq patches sent some days ago.
Tested by: set fload tftp ${addr} fpga.bin;fpga info 0;fpga load 0 ${addr} ${filesize} set floadb tftp ${addr} download.bit;fpga info 0;fpga loadb 0 ${addr} ${filesize} set addr 10000000 run fload run floadb set addr 10000001 run fload run floadb set addr 10000002 run fload run floadb set addr 10000003 run fload run floadb
Thanks for your comments, Michal
Changes in v2: - Fix compilation warnings - Fix grammer in the commit message - Fix bugs reported by Tom Rini - Fix checkpatch warnings (fpga) - Fix comments (fpga) - Do not use CamelCase for XilinxZynq (fpga) - Move to fpga series and extend this driver - New patch in this series
Michal Simek (7): fpga: Clean coding style fpga: Fix debug message compilation error cmd: fpga: Clean coding style cmd: fpga: Move fpga_loadbitstream to fpga.c cmd: fpga: Do not include net.h fpga: zynq: Add support for loading bitstream fpga: Check device name against bitstream name
arch/arm/cpu/armv7/zynq/slcr.c | 35 +++ arch/arm/include/asm/arch-zynq/hardware.h | 10 +- arch/arm/include/asm/arch-zynq/sys_proto.h | 3 + board/xilinx/zynq/board.c | 37 +++ common/cmd_fpga.c | 254 +++++++-------------- drivers/fpga/Makefile | 1 + drivers/fpga/fpga.c | 330 +++++++++++++++++---------- drivers/fpga/xilinx.c | 39 ++++ drivers/fpga/zynqpl.c | 355 +++++++++++++++++++++++++++++ include/configs/zynq.h | 6 + include/fpga.h | 1 + include/xilinx.h | 5 + include/zynqpl.h | 59 +++++ 13 files changed, 840 insertions(+), 295 deletions(-) create mode 100644 drivers/fpga/zynqpl.c create mode 100644 include/zynqpl.h
-- 1.8.2.1
No functional changes.
Signed-off-by: Michal Simek michal.simek@xilinx.com --- Changes in v2: - Fix compilation warnings
drivers/fpga/fpga.c | 216 ++++++++++++++++++++++++---------------------------- 1 file changed, 98 insertions(+), 118 deletions(-)
diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c index 26d2443..ddebd49 100644 --- a/drivers/fpga/fpga.c +++ b/drivers/fpga/fpga.c @@ -22,122 +22,99 @@ * */
-/* - * Generic FPGA support - */ +/* Generic FPGA support */ #include <common.h> /* core U-Boot definitions */ #include <xilinx.h> /* xilinx specific definitions */ #include <altera.h> /* altera specific definitions */ #include <lattice.h>
-#if 0 -#define FPGA_DEBUG /* define FPGA_DEBUG to get debug messages */ -#endif - /* Local definitions */ #ifndef CONFIG_MAX_FPGA_DEVICES #define CONFIG_MAX_FPGA_DEVICES 5 #endif
-/* Enable/Disable debug console messages */ -#ifdef FPGA_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - /* Local static data */ static int next_desc = FPGA_INVALID_DEVICE; static fpga_desc desc_table[CONFIG_MAX_FPGA_DEVICES];
-/* Local static functions */ -static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_get_desc( int devnum ); -static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_validate(int devnum, const void *buf, - size_t bsize, char *fn ); -static int fpga_dev_info( int devnum ); - - -/* ------------------------------------------------------------------------- */ - -/* fpga_no_sup +/* + * fpga_no_sup * 'no support' message function */ -static void fpga_no_sup( char *fn, char *msg ) +static void fpga_no_sup(char *fn, char *msg) { - if ( fn && msg ) { - printf( "%s: No support for %s.\n", fn, msg); - } else if ( msg ) { - printf( "No support for %s.\n", msg); - } else { - printf( "No FPGA suport!\n"); - } + if (fn && msg) + printf("%s: No support for %s.\n", fn, msg); + else if (msg) + printf("No support for %s.\n", msg); + else + printf("No FPGA suport!\n"); }
/* fpga_get_desc * map a device number to a descriptor */ -static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_get_desc( int devnum ) +static const fpga_desc *const fpga_get_desc(int devnum) { - fpga_desc *desc = (fpga_desc * )NULL; + fpga_desc *desc = (fpga_desc *)NULL;
- if (( devnum >= 0 ) && (devnum < next_desc )) { + if ((devnum >= 0) && (devnum < next_desc)) { desc = &desc_table[devnum]; - PRINTF( "%s: found fpga descriptor #%d @ 0x%p\n", - __FUNCTION__, devnum, desc ); + debug("%s: found fpga descriptor #%d @ 0x%p\n", + __func__, devnum, desc); }
return desc; }
- -/* fpga_validate +/* + * fpga_validate * generic parameter checking code */ -static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_validate(int devnum, const void *buf, - size_t bsize, char *fn ) +static const fpga_desc *const fpga_validate(int devnum, const void *buf, + size_t bsize, char *fn) { - fpga_desc * desc = fpga_get_desc( devnum ); + const fpga_desc *desc = fpga_get_desc(devnum);
- if ( !desc ) { - printf( "%s: Invalid device number %d\n", fn, devnum ); - } + if (!desc) + printf("%s: Invalid device number %d\n", fn, devnum);
- if ( !buf ) { - printf( "%s: Null buffer.\n", fn ); + if (!buf) { + printf("%s: Null buffer.\n", fn); return (fpga_desc * const)NULL; } return desc; }
- -/* fpga_dev_info +/* + * fpga_dev_info * generic multiplexing code */ -static int fpga_dev_info( int devnum ) +static int fpga_dev_info(int devnum) { - int ret_val = FPGA_FAIL; /* assume failure */ - const fpga_desc * const desc = fpga_get_desc( devnum ); + int ret_val = FPGA_FAIL; /* assume failure */ + const fpga_desc * const desc = fpga_get_desc(devnum);
- if ( desc ) { - PRINTF( "%s: Device Descriptor @ 0x%p\n", - __FUNCTION__, desc->devdesc ); + if (desc) { + debug("%s: Device Descriptor @ 0x%p\n", + __func__, desc->devdesc);
- switch ( desc->devtype ) { + switch (desc->devtype) { case fpga_xilinx: #if defined(CONFIG_FPGA_XILINX) - printf( "Xilinx Device\nDescriptor @ 0x%p\n", desc ); - ret_val = xilinx_info( desc->devdesc ); + printf("Xilinx Device\nDescriptor @ 0x%p\n", desc); + ret_val = xilinx_info(desc->devdesc); #else - fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" ); + fpga_no_sup((char *)__func__, "Xilinx devices"); #endif break; case fpga_altera: #if defined(CONFIG_FPGA_ALTERA) - printf( "Altera Device\nDescriptor @ 0x%p\n", desc ); - ret_val = altera_info( desc->devdesc ); + printf("Altera Device\nDescriptor @ 0x%p\n", desc); + ret_val = altera_info(desc->devdesc); #else - fpga_no_sup( (char *)__FUNCTION__, "Altera devices" ); + fpga_no_sup((char *)__func__, "Altera devices"); #endif break; case fpga_lattice: @@ -145,171 +122,174 @@ static int fpga_dev_info( int devnum ) printf("Lattice Device\nDescriptor @ 0x%p\n", desc); ret_val = lattice_info(desc->devdesc); #else - fpga_no_sup( (char *)__FUNCTION__, "Lattice devices" ); + fpga_no_sup((char *)__func__, "Lattice devices"); #endif break; default: - printf( "%s: Invalid or unsupported device type %d\n", - __FUNCTION__, desc->devtype ); + printf("%s: Invalid or unsupported device type %d\n", + __func__, desc->devtype); } } else { - printf( "%s: Invalid device number %d\n", - __FUNCTION__, devnum ); + printf("%s: Invalid device number %d\n", __func__, devnum); }
return ret_val; }
- -/* ------------------------------------------------------------------------- */ -/* fgpa_init is usually called from misc_init_r() and MUST be called +/* + * fgpa_init is usually called from misc_init_r() and MUST be called * before any of the other fpga functions are used. */ void fpga_init(void) { next_desc = 0; - memset( desc_table, 0, sizeof(desc_table)); + memset(desc_table, 0, sizeof(desc_table));
- PRINTF( "%s: CONFIG_FPGA = 0x%x\n", __FUNCTION__, CONFIG_FPGA ); + debug("%s: CONFIG_FPGA = 0x%x\n", __func__, CONFIG_FPGA); }
-/* fpga_count +/* + * fpga_count * Basic interface function to get the current number of devices available. */ -int fpga_count( void ) +int fpga_count(void) { return next_desc; }
-/* fpga_add +/* + * fpga_add * Add the device descriptor to the device table. */ -int fpga_add( fpga_type devtype, void *desc ) +int fpga_add(fpga_type devtype, void *desc) { int devnum = FPGA_INVALID_DEVICE;
- if ( next_desc < 0 ) { - printf( "%s: FPGA support not initialized!\n", __FUNCTION__ ); - } else if (( devtype > fpga_min_type ) && ( devtype < fpga_undefined )) { - if ( desc ) { - if ( next_desc < CONFIG_MAX_FPGA_DEVICES ) { + if (next_desc < 0) { + printf("%s: FPGA support not initialized!\n", __func__); + } else if ((devtype > fpga_min_type) && (devtype < fpga_undefined)) { + if (desc) { + if (next_desc < CONFIG_MAX_FPGA_DEVICES) { devnum = next_desc; desc_table[next_desc].devtype = devtype; desc_table[next_desc++].devdesc = desc; } else { - printf( "%s: Exceeded Max FPGA device count\n", __FUNCTION__ ); + printf("%s: Exceeded Max FPGA device count\n", + __func__); } } else { - printf( "%s: NULL device descriptor\n", __FUNCTION__ ); + printf("%s: NULL device descriptor\n", __func__); } } else { - printf( "%s: Unsupported FPGA type %d\n", __FUNCTION__, devtype ); + printf("%s: Unsupported FPGA type %d\n", __func__, devtype); }
return devnum; }
/* - * Generic multiplexing code + * Generic multiplexing code */ int fpga_load(int devnum, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume failure */ - fpga_desc * desc = fpga_validate( devnum, buf, bsize, (char *)__FUNCTION__ ); + const fpga_desc *desc = fpga_validate(devnum, buf, bsize, + (char *)__func__);
- if ( desc ) { - switch ( desc->devtype ) { + if (desc) { + switch (desc->devtype) { case fpga_xilinx: #if defined(CONFIG_FPGA_XILINX) - ret_val = xilinx_load( desc->devdesc, buf, bsize ); + ret_val = xilinx_load(desc->devdesc, buf, bsize); #else - fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" ); + fpga_no_sup((char *)__func__, "Xilinx devices"); #endif break; case fpga_altera: #if defined(CONFIG_FPGA_ALTERA) - ret_val = altera_load( desc->devdesc, buf, bsize ); + ret_val = altera_load(desc->devdesc, buf, bsize); #else - fpga_no_sup( (char *)__FUNCTION__, "Altera devices" ); + fpga_no_sup((char *)__func__, "Altera devices"); #endif break; case fpga_lattice: #if defined(CONFIG_FPGA_LATTICE) ret_val = lattice_load(desc->devdesc, buf, bsize); #else - fpga_no_sup( (char *)__FUNCTION__, "Lattice devices" ); + fpga_no_sup((char *)__func__, "Lattice devices"); #endif break; default: - printf( "%s: Invalid or unsupported device type %d\n", - __FUNCTION__, desc->devtype ); + printf("%s: Invalid or unsupported device type %d\n", + __func__, desc->devtype); } }
return ret_val; }
-/* fpga_dump +/* + * fpga_dump * generic multiplexing code */ int fpga_dump(int devnum, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume failure */ - fpga_desc * desc = fpga_validate( devnum, buf, bsize, (char *)__FUNCTION__ ); + const fpga_desc *desc = fpga_validate(devnum, buf, bsize, + (char *)__func__);
- if ( desc ) { - switch ( desc->devtype ) { + if (desc) { + switch (desc->devtype) { case fpga_xilinx: #if defined(CONFIG_FPGA_XILINX) - ret_val = xilinx_dump( desc->devdesc, buf, bsize ); + ret_val = xilinx_dump(desc->devdesc, buf, bsize); #else - fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" ); + fpga_no_sup((char *)__func__, "Xilinx devices"); #endif break; case fpga_altera: #if defined(CONFIG_FPGA_ALTERA) - ret_val = altera_dump( desc->devdesc, buf, bsize ); + ret_val = altera_dump(desc->devdesc, buf, bsize); #else - fpga_no_sup( (char *)__FUNCTION__, "Altera devices" ); + fpga_no_sup((char *)__func__, "Altera devices"); #endif break; case fpga_lattice: #if defined(CONFIG_FPGA_LATTICE) ret_val = lattice_dump(desc->devdesc, buf, bsize); #else - fpga_no_sup( (char *)__FUNCTION__, "Lattice devices" ); + fpga_no_sup((char *)__func__, "Lattice devices"); #endif break; default: - printf( "%s: Invalid or unsupported device type %d\n", - __FUNCTION__, desc->devtype ); + printf("%s: Invalid or unsupported device type %d\n", + __func__, desc->devtype); } }
return ret_val; }
- -/* fpga_info +/* + * fpga_info * front end to fpga_dev_info. If devnum is invalid, report on all * available devices. */ -int fpga_info( int devnum ) +int fpga_info(int devnum) { - if ( devnum == FPGA_INVALID_DEVICE ) { - if ( next_desc > 0 ) { + if (devnum == FPGA_INVALID_DEVICE) { + if (next_desc > 0) { int dev;
- for ( dev = 0; dev < next_desc; dev++ ) { - fpga_dev_info( dev ); - } + for (dev = 0; dev < next_desc; dev++) + fpga_dev_info(dev); + return FPGA_SUCCESS; } else { - printf( "%s: No FPGA devices available.\n", __FUNCTION__ ); + printf("%s: No FPGA devices available.\n", __func__); return FPGA_FAIL; } } - else return fpga_dev_info( devnum ); -}
-/* ------------------------------------------------------------------------- */ + return fpga_dev_info(devnum); +} -- 1.8.2.1
CONFIG_FPGA in past was a bitfield where bits were use for vendor identification.
This fix should be the part of this commit: "Improve configuration of FPGA subsystem" (sha1: 0133502e39ff89b67c26cb4015e0e7e8d9571184)
Signed-off-by: Michal Simek michal.simek@xilinx.com --- Changes in v2: - Fix grammer in the commit message
drivers/fpga/fpga.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c index ddebd49..43bdf4f 100644 --- a/drivers/fpga/fpga.c +++ b/drivers/fpga/fpga.c @@ -145,7 +145,7 @@ void fpga_init(void) next_desc = 0; memset(desc_table, 0, sizeof(desc_table));
- debug("%s: CONFIG_FPGA = 0x%x\n", __func__, CONFIG_FPGA); + debug("%s\n", __func__); }
/* -- 1.8.2.1
No functional changes.
Signed-off-by: Michal Simek michal.simek@xilinx.com --- Changes in v2: None
I had to shorten some debug messages and divide them to two parts to pass checkpatch. --- common/cmd_fpga.c | 213 +++++++++++++++++++++++++++--------------------------- 1 file changed, 107 insertions(+), 106 deletions(-)
diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c index 1834246..f3579bb 100644 --- a/common/cmd_fpga.c +++ b/common/cmd_fpga.c @@ -34,7 +34,7 @@ #include <malloc.h>
/* Local functions */ -static int fpga_get_op (char *opstr); +static int fpga_get_op(char *opstr);
/* Local defines */ #define FPGA_NONE -1 @@ -45,7 +45,7 @@ static int fpga_get_op (char *opstr); #define FPGA_LOADMK 4
/* Convert bitstream data and load into the fpga */ -int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size) +int fpga_loadbitstream(unsigned long dev, char *fpgadata, size_t size) { #if defined(CONFIG_FPGA_XILINX) unsigned int length; @@ -58,38 +58,36 @@ int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size) dataptr = (unsigned char *)fpgadata;
/* skip the first bytes of the bitsteam, their meaning is unknown */ - length = (*dataptr << 8) + *(dataptr+1); - dataptr+=2; - dataptr+=length; + length = (*dataptr << 8) + *(dataptr + 1); + dataptr += 2; + dataptr += length;
/* get design name (identifier, length, string) */ - length = (*dataptr << 8) + *(dataptr+1); - dataptr+=2; + length = (*dataptr << 8) + *(dataptr + 1); + dataptr += 2; if (*dataptr++ != 0x61) { - debug("%s: Design name identifier not recognized " - "in bitstream\n", - __func__); + debug("%s: Design name id not recognized in bitstream\n", + __func__); return FPGA_FAIL; }
- length = (*dataptr << 8) + *(dataptr+1); - dataptr+=2; - for(i=0;i<length;i++) + length = (*dataptr << 8) + *(dataptr + 1); + dataptr += 2; + for (i = 0; i < length; i++) buffer[i] = *dataptr++;
printf(" design filename = "%s"\n", buffer);
/* get part number (identifier, length, string) */ if (*dataptr++ != 0x62) { - printf("%s: Part number identifier not recognized " - "in bitstream\n", - __func__); + printf("%s: Part number id not recognized in bitstream\n", + __func__); return FPGA_FAIL; }
- length = (*dataptr << 8) + *(dataptr+1); - dataptr+=2; - for(i=0;i<length;i++) + length = (*dataptr << 8) + *(dataptr + 1); + dataptr += 2; + for (i = 0; i < length; i++) buffer[i] = *dataptr++; printf(" part number = "%s"\n", buffer);
@@ -101,35 +99,35 @@ int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size) }
length = (*dataptr << 8) + *(dataptr+1); - dataptr+=2; - for(i=0;i<length;i++) + dataptr += 2; + for (i = 0; i < length; i++) buffer[i] = *dataptr++; printf(" date = "%s"\n", buffer);
/* get time (identifier, length, string) */ if (*dataptr++ != 0x64) { printf("%s: Time identifier not recognized in bitstream\n", - __func__); + __func__); return FPGA_FAIL; }
length = (*dataptr << 8) + *(dataptr+1); - dataptr+=2; - for(i=0;i<length;i++) + dataptr += 2; + for (i = 0; i < length; i++) buffer[i] = *dataptr++; printf(" time = "%s"\n", buffer);
/* get fpga data length (identifier, length) */ if (*dataptr++ != 0x65) { - printf("%s: Data length identifier not recognized in bitstream\n", - __func__); + printf("%s: Data length id not recognized in bitstream\n", + __func__); return FPGA_FAIL; } - swapsize = ((unsigned int) *dataptr <<24) + - ((unsigned int) *(dataptr+1) <<16) + - ((unsigned int) *(dataptr+2) <<8 ) + - ((unsigned int) *(dataptr+3) ) ; - dataptr+=4; + swapsize = ((unsigned int) *dataptr << 24) + + ((unsigned int) *(dataptr + 1) << 16) + + ((unsigned int) *(dataptr + 2) << 8) + + ((unsigned int) *(dataptr + 3)); + dataptr += 4; printf(" bytes in bitstream = %d\n", swapsize);
rc = fpga_load(dev, dataptr, swapsize); @@ -148,81 +146,81 @@ int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size) * If there is no data addr field, the fpgadata environment variable is used. * The info command requires no data address field. */ -int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) +int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { int op, dev = FPGA_INVALID_DEVICE; size_t data_size = 0; void *fpga_data = NULL; - char *devstr = getenv ("fpga"); - char *datastr = getenv ("fpgadata"); + char *devstr = getenv("fpga"); + char *datastr = getenv("fpgadata"); int rc = FPGA_FAIL; int wrong_parms = 0; -#if defined (CONFIG_FIT) +#if defined(CONFIG_FIT) const char *fit_uname = NULL; ulong fit_addr; #endif
if (devstr) - dev = (int) simple_strtoul (devstr, NULL, 16); + dev = (int) simple_strtoul(devstr, NULL, 16); if (datastr) - fpga_data = (void *) simple_strtoul (datastr, NULL, 16); + fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
switch (argc) { case 5: /* fpga <op> <dev> <data> <datasize> */ - data_size = simple_strtoul (argv[4], NULL, 16); + data_size = simple_strtoul(argv[4], NULL, 16);
case 4: /* fpga <op> <dev> <data> */ #if defined(CONFIG_FIT) - if (fit_parse_subimage (argv[3], (ulong)fpga_data, - &fit_addr, &fit_uname)) { + if (fit_parse_subimage(argv[3], (ulong)fpga_data, + &fit_addr, &fit_uname)) { fpga_data = (void *)fit_addr; - debug("* fpga: subimage '%s' from FIT image " - "at 0x%08lx\n", - fit_uname, fit_addr); + debug("* fpga: subimage '%s' from FIT image ", + fit_uname); + debug("at 0x%08lx\n", fit_addr); } else #endif { - fpga_data = (void *) simple_strtoul (argv[3], NULL, 16); + fpga_data = (void *)simple_strtoul(argv[3], NULL, 16); debug("* fpga: cmdline image address = 0x%08lx\n", - (ulong)fpga_data); + (ulong)fpga_data); } - debug("%s: fpga_data = 0x%x\n", __func__, (uint) fpga_data); + debug("%s: fpga_data = 0x%x\n", __func__, (uint)fpga_data);
case 3: /* fpga <op> <dev | data addr> */ - dev = (int) simple_strtoul (argv[2], NULL, 16); + dev = (int)simple_strtoul(argv[2], NULL, 16); debug("%s: device = %d\n", __func__, dev); /* FIXME - this is a really weak test */ - if ((argc == 3) && (dev > fpga_count ())) { /* must be buffer ptr */ + if ((argc == 3) && (dev > fpga_count())) { + /* must be buffer ptr */ debug("%s: Assuming buffer pointer in arg 3\n", - __func__); + __func__);
#if defined(CONFIG_FIT) - if (fit_parse_subimage (argv[2], (ulong)fpga_data, - &fit_addr, &fit_uname)) { + if (fit_parse_subimage(argv[2], (ulong)fpga_data, + &fit_addr, &fit_uname)) { fpga_data = (void *)fit_addr; - debug("* fpga: subimage '%s' from FIT image " - "at 0x%08lx\n", - fit_uname, fit_addr); + debug("* fpga: subimage '%s' from FIT image ", + fit_uname); + debug("at 0x%08lx\n", fit_addr); } else #endif { - fpga_data = (void *) dev; - debug("* fpga: cmdline image address = " - "0x%08lx\n", (ulong)fpga_data); + fpga_data = (void *)dev; + debug("* fpga: cmdline image addr = 0x%08lx\n", + (ulong)fpga_data); }
debug("%s: fpga_data = 0x%x\n", - __func__, (uint) fpga_data); + __func__, (uint)fpga_data); dev = FPGA_INVALID_DEVICE; /* reset device num */ }
case 2: /* fpga <op> */ - op = (int) fpga_get_op (argv[1]); + op = (int)fpga_get_op(argv[1]); break;
default: - debug("%s: Too many or too few args (%d)\n", - __func__, argc); + debug("%s: Too many or too few args (%d)\n", __func__, argc); op = FPGA_NONE; /* force usage display */ break; } @@ -258,11 +256,11 @@ int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) return CMD_RET_USAGE;
case FPGA_INFO: - rc = fpga_info (dev); + rc = fpga_info(dev); break;
case FPGA_LOAD: - rc = fpga_load (dev, fpga_data, data_size); + rc = fpga_load(dev, fpga_data, data_size); break;
case FPGA_LOADB: @@ -270,15 +268,16 @@ int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) break;
case FPGA_LOADMK: - switch (genimg_get_format (fpga_data)) { + switch (genimg_get_format(fpga_data)) { case IMAGE_FORMAT_LEGACY: { - image_header_t *hdr = (image_header_t *)fpga_data; - ulong data; + image_header_t *hdr = + (image_header_t *)fpga_data; + ulong data;
- data = (ulong)image_get_data (hdr); - data_size = image_get_data_size (hdr); - rc = fpga_load (dev, (void *)data, data_size); + data = (ulong)image_get_data(hdr); + data_size = image_get_data_size(hdr); + rc = fpga_load(dev, (void *)data, data_size); } break; #if defined(CONFIG_FIT) @@ -289,95 +288,97 @@ int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) const void *fit_data;
if (fit_uname == NULL) { - puts ("No FIT subimage unit name\n"); + puts("No FIT subimage unit name\n"); return 1; }
- if (!fit_check_format (fit_hdr)) { - puts ("Bad FIT image format\n"); + if (!fit_check_format(fit_hdr)) { + puts("Bad FIT image format\n"); return 1; }
/* get fpga component image node offset */ - noffset = fit_image_get_node (fit_hdr, fit_uname); + noffset = fit_image_get_node(fit_hdr, + fit_uname); if (noffset < 0) { - printf ("Can't find '%s' FIT subimage\n", fit_uname); + printf("Can't find '%s' FIT subimage\n", + fit_uname); return 1; }
/* verify integrity */ - if (!fit_image_check_hashes (fit_hdr, noffset)) { - puts ("Bad Data Hash\n"); + if (!fit_image_check_hashes(fit_hdr, noffset)) { + puts("Bad Data Hash\n"); return 1; }
/* get fpga subimage data address and length */ - if (fit_image_get_data (fit_hdr, noffset, &fit_data, &data_size)) { - puts ("Could not find fpga subimage data\n"); + if (fit_image_get_data(fit_hdr, noffset, + &fit_data, &data_size)) { + puts("Fpga subimage data not found\n"); return 1; }
- rc = fpga_load (dev, fit_data, data_size); + rc = fpga_load(dev, fit_data, data_size); } break; #endif default: - puts ("** Unknown image type\n"); + puts("** Unknown image type\n"); rc = FPGA_FAIL; break; } break;
case FPGA_DUMP: - rc = fpga_dump (dev, fpga_data, data_size); + rc = fpga_dump(dev, fpga_data, data_size); break;
default: - printf ("Unknown operation\n"); + printf("Unknown operation\n"); return CMD_RET_USAGE; } - return (rc); + return rc; }
/* * Map op to supported operations. We don't use a table since we * would just have to relocate it from flash anyway. */ -static int fpga_get_op (char *opstr) +static int fpga_get_op(char *opstr) { int op = FPGA_NONE;
- if (!strcmp ("info", opstr)) { + if (!strcmp("info", opstr)) op = FPGA_INFO; - } else if (!strcmp ("loadb", opstr)) { + else if (!strcmp("loadb", opstr)) op = FPGA_LOADB; - } else if (!strcmp ("load", opstr)) { + else if (!strcmp("load", opstr)) op = FPGA_LOAD; - } else if (!strcmp ("loadmk", opstr)) { + else if (!strcmp("loadmk", opstr)) op = FPGA_LOADMK; - } else if (!strcmp ("dump", opstr)) { + else if (!strcmp("dump", opstr)) op = FPGA_DUMP; - }
- if (op == FPGA_NONE) { - printf ("Unknown fpga operation "%s"\n", opstr); - } + if (op == FPGA_NONE) + printf("Unknown fpga operation "%s"\n", opstr); + return op; }
-U_BOOT_CMD (fpga, 6, 1, do_fpga, - "loadable FPGA image support", - "[operation type] [device number] [image address] [image size]\n" - "fpga operations:\n" - " dump\t[dev]\t\t\tLoad device to memory buffer\n" - " info\t[dev]\t\t\tlist known device information\n" - " load\t[dev] [address] [size]\tLoad device from memory buffer\n" - " loadb\t[dev] [address] [size]\t" - "Load device from bitstream buffer (Xilinx only)\n" - " loadmk [dev] [address]\tLoad device generated with mkimage" +U_BOOT_CMD(fpga, 6, 1, do_fpga, + "loadable FPGA image support", + "[operation type] [device number] [image address] [image size]\n" + "fpga operations:\n" + " dump\t[dev]\t\t\tLoad device to memory buffer\n" + " info\t[dev]\t\t\tlist known device information\n" + " load\t[dev] [address] [size]\tLoad device from memory buffer\n" + " loadb\t[dev] [address] [size]\t" + "Load device from bitstream buffer (Xilinx only)\n" + " loadmk [dev] [address]\tLoad device generated with mkimage" #if defined(CONFIG_FIT) - "\n" - "\tFor loadmk operating on FIT format uImage address must include\n" - "\tsubimage unit name in the form of addr:<subimg_uname>" + "\n" + "\tFor loadmk operating on FIT format uImage address must include\n" + "\tsubimage unit name in the form of addr:<subimg_uname>" #endif ); -- 1.8.2.1
In bitstream decoding you can directly check device which you want to load and in fpga.c are fpga_validate and fpga_dev_info functions which should be used for it.
Signed-off-by: Michal Simek michal.simek@xilinx.com --- Changes in v2: None
common/cmd_fpga.c | 94 ----------------------------------------------------- drivers/fpga/fpga.c | 94 +++++++++++++++++++++++++++++++++++++++++++++++++++++ include/fpga.h | 1 + 3 files changed, 95 insertions(+), 94 deletions(-)
diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c index f3579bb..aa14ceb 100644 --- a/common/cmd_fpga.c +++ b/common/cmd_fpga.c @@ -44,100 +44,6 @@ static int fpga_get_op(char *opstr); #define FPGA_DUMP 3 #define FPGA_LOADMK 4
-/* Convert bitstream data and load into the fpga */ -int fpga_loadbitstream(unsigned long dev, char *fpgadata, size_t size) -{ -#if defined(CONFIG_FPGA_XILINX) - unsigned int length; - unsigned int swapsize; - char buffer[80]; - unsigned char *dataptr; - unsigned int i; - int rc; - - dataptr = (unsigned char *)fpgadata; - - /* skip the first bytes of the bitsteam, their meaning is unknown */ - length = (*dataptr << 8) + *(dataptr + 1); - dataptr += 2; - dataptr += length; - - /* get design name (identifier, length, string) */ - length = (*dataptr << 8) + *(dataptr + 1); - dataptr += 2; - if (*dataptr++ != 0x61) { - debug("%s: Design name id not recognized in bitstream\n", - __func__); - return FPGA_FAIL; - } - - length = (*dataptr << 8) + *(dataptr + 1); - dataptr += 2; - for (i = 0; i < length; i++) - buffer[i] = *dataptr++; - - printf(" design filename = "%s"\n", buffer); - - /* get part number (identifier, length, string) */ - if (*dataptr++ != 0x62) { - printf("%s: Part number id not recognized in bitstream\n", - __func__); - return FPGA_FAIL; - } - - length = (*dataptr << 8) + *(dataptr + 1); - dataptr += 2; - for (i = 0; i < length; i++) - buffer[i] = *dataptr++; - printf(" part number = "%s"\n", buffer); - - /* get date (identifier, length, string) */ - if (*dataptr++ != 0x63) { - printf("%s: Date identifier not recognized in bitstream\n", - __func__); - return FPGA_FAIL; - } - - length = (*dataptr << 8) + *(dataptr+1); - dataptr += 2; - for (i = 0; i < length; i++) - buffer[i] = *dataptr++; - printf(" date = "%s"\n", buffer); - - /* get time (identifier, length, string) */ - if (*dataptr++ != 0x64) { - printf("%s: Time identifier not recognized in bitstream\n", - __func__); - return FPGA_FAIL; - } - - length = (*dataptr << 8) + *(dataptr+1); - dataptr += 2; - for (i = 0; i < length; i++) - buffer[i] = *dataptr++; - printf(" time = "%s"\n", buffer); - - /* get fpga data length (identifier, length) */ - if (*dataptr++ != 0x65) { - printf("%s: Data length id not recognized in bitstream\n", - __func__); - return FPGA_FAIL; - } - swapsize = ((unsigned int) *dataptr << 24) + - ((unsigned int) *(dataptr + 1) << 16) + - ((unsigned int) *(dataptr + 2) << 8) + - ((unsigned int) *(dataptr + 3)); - dataptr += 4; - printf(" bytes in bitstream = %d\n", swapsize); - - rc = fpga_load(dev, dataptr, swapsize); - return rc; -#else - printf("Bitstream support only for Xilinx devices\n"); - return FPGA_FAIL; -#endif -} - /* ------------------------------------------------------------------------- */ /* command form: * fpga <op> <device number> <data addr> <datasize> diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c index 43bdf4f..b74c84f 100644 --- a/drivers/fpga/fpga.c +++ b/drivers/fpga/fpga.c @@ -187,6 +187,100 @@ int fpga_add(fpga_type devtype, void *desc) return devnum; }
+/* Convert bitstream data and load into the fpga */ +int fpga_loadbitstream(unsigned long dev, char *fpgadata, size_t size) +{ +#if defined(CONFIG_FPGA_XILINX) + unsigned int length; + unsigned int swapsize; + char buffer[80]; + unsigned char *dataptr; + unsigned int i; + int rc; + + dataptr = (unsigned char *)fpgadata; + + /* skip the first bytes of the bitsteam, their meaning is unknown */ + length = (*dataptr << 8) + *(dataptr + 1); + dataptr += 2; + dataptr += length; + + /* get design name (identifier, length, string) */ + length = (*dataptr << 8) + *(dataptr + 1); + dataptr += 2; + if (*dataptr++ != 0x61) { + debug("%s: Design name id not recognized in bitstream\n", + __func__); + return FPGA_FAIL; + } + + length = (*dataptr << 8) + *(dataptr + 1); + dataptr += 2; + for (i = 0; i < length; i++) + buffer[i] = *dataptr++; + + printf(" design filename = "%s"\n", buffer); + + /* get part number (identifier, length, string) */ + if (*dataptr++ != 0x62) { + printf("%s: Part number id not recognized in bitstream\n", + __func__); + return FPGA_FAIL; + } + + length = (*dataptr << 8) + *(dataptr + 1); + dataptr += 2; + for (i = 0; i < length; i++) + buffer[i] = *dataptr++; + printf(" part number = "%s"\n", buffer); + + /* get date (identifier, length, string) */ + if (*dataptr++ != 0x63) { + printf("%s: Date identifier not recognized in bitstream\n", + __func__); + return FPGA_FAIL; + } + + length = (*dataptr << 8) + *(dataptr+1); + dataptr += 2; + for (i = 0; i < length; i++) + buffer[i] = *dataptr++; + printf(" date = "%s"\n", buffer); + + /* get time (identifier, length, string) */ + if (*dataptr++ != 0x64) { + printf("%s: Time identifier not recognized in bitstream\n", + __func__); + return FPGA_FAIL; + } + + length = (*dataptr << 8) + *(dataptr+1); + dataptr += 2; + for (i = 0; i < length; i++) + buffer[i] = *dataptr++; + printf(" time = "%s"\n", buffer); + + /* get fpga data length (identifier, length) */ + if (*dataptr++ != 0x65) { + printf("%s: Data length id not recognized in bitstream\n", + __func__); + return FPGA_FAIL; + } + swapsize = ((unsigned int) *dataptr << 24) + + ((unsigned int) *(dataptr + 1) << 16) + + ((unsigned int) *(dataptr + 2) << 8) + + ((unsigned int) *(dataptr + 3)); + dataptr += 4; + printf(" bytes in bitstream = %d\n", swapsize); + + rc = fpga_load(dev, dataptr, swapsize); + return rc; +#else + printf("Bitstream support only for Xilinx devices\n"); + return FPGA_FAIL; +#endif +} + /* * Generic multiplexing code */ diff --git a/include/fpga.h b/include/fpga.h index 30a4e6a..0d01e04 100644 --- a/include/fpga.h +++ b/include/fpga.h @@ -68,6 +68,7 @@ extern void fpga_init(void); extern int fpga_add(fpga_type devtype, void *desc); extern int fpga_count(void); extern int fpga_load(int devnum, const void *buf, size_t bsize); +extern int fpga_loadbitstream(unsigned long dev, char *fpgadata, size_t size); extern int fpga_dump(int devnum, const void *buf, size_t bsize); extern int fpga_info(int devnum);
-- 1.8.2.1
On Wed, May 01, 2013 at 10:59:20AM +0200, Michal Simek wrote:
In bitstream decoding you can directly check device which you want to load and in fpga.c are fpga_validate and fpga_dev_info functions which should be used for it.
Signed-off-by: Michal Simek michal.simek@xilinx.com
[snip]
+++ b/drivers/fpga/fpga.c
[snip]
+#else
- printf("Bitstream support only for Xilinx devices\n");
- return FPGA_FAIL;
+#endif
How about we re-work this as a __weak fpga_loadbitstream in drivers/fpga/fpga.c that just says "Bitstream support not implemented for this FPGA device", return FPGA_FAIL, and move the xilinx one into drivers/fpga/xilinx.c ?
On 05/01/2013 05:03 PM, Tom Rini wrote:
On Wed, May 01, 2013 at 10:59:20AM +0200, Michal Simek wrote:
In bitstream decoding you can directly check device which you want to load and in fpga.c are fpga_validate and fpga_dev_info functions which should be used for it.
Signed-off-by: Michal Simek michal.simek@xilinx.com
[snip]
+++ b/drivers/fpga/fpga.c
[snip]
+#else
- printf("Bitstream support only for Xilinx devices\n");
- return FPGA_FAIL;
+#endif
How about we re-work this as a __weak fpga_loadbitstream in drivers/fpga/fpga.c that just says "Bitstream support not implemented for this FPGA device", return FPGA_FAIL, and move the xilinx one into drivers/fpga/xilinx.c ?
yep. Make sense to do it because at least from this code altera or lattice don't support bitstream loading. It will be more problematic if there is a board on the market with different fpgas.
I even not sure if other fpga vendors have bitstream with any header which should be used by this command.
Thanks, Michal
There is no reason to include net.h header in fpga code.
Signed-off-by: Michal Simek michal.simek@xilinx.com --- Changes in v2: None
common/cmd_fpga.c | 3 --- 1 file changed, 3 deletions(-)
diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c index aa14ceb..5e1d037 100644 --- a/common/cmd_fpga.c +++ b/common/cmd_fpga.c @@ -27,9 +27,6 @@ */ #include <common.h> #include <command.h> -#if defined(CONFIG_CMD_NET) -#include <net.h> -#endif #include <fpga.h> #include <malloc.h>
-- 1.8.2.1
Devcfg device requires to load bitstream in binary format. But u-boot also has an option for loading bitstream in bit format. Let's handle both cases by zynqpl driver. Also add suport for loading partial bitstreams.
The first driver version was done by: Joe Hershberger joe.hershberger@ni.com
Signed-off-by: Michal Simek michal.simek@xilinx.com --- Changes in v2: - Fix bugs reported by Tom Rini - Fix checkpatch warnings (fpga) - Fix comments (fpga) - Do not use CamelCase for XilinxZynq (fpga) - Move to fpga series and extend this driver
This patch was the part of zynq series but I have decided to extend it with partial bitstream support, loadb support and create separate patchset just for fpga patches. The origin patch was reviewed by Tom Rini.
--- arch/arm/cpu/armv7/zynq/slcr.c | 35 +++ arch/arm/include/asm/arch-zynq/hardware.h | 10 +- arch/arm/include/asm/arch-zynq/sys_proto.h | 3 + board/xilinx/zynq/board.c | 37 +++ drivers/fpga/Makefile | 1 + drivers/fpga/xilinx.c | 37 +++ drivers/fpga/zynqpl.c | 355 +++++++++++++++++++++++++++++ include/configs/zynq.h | 6 + include/xilinx.h | 4 + include/zynqpl.h | 59 +++++ 10 files changed, 545 insertions(+), 2 deletions(-) create mode 100644 drivers/fpga/zynqpl.c create mode 100644 include/zynqpl.h
diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c index 5a8674a..52048c6 100644 --- a/arch/arm/cpu/armv7/zynq/slcr.c +++ b/arch/arm/cpu/armv7/zynq/slcr.c @@ -28,6 +28,9 @@ #define SLCR_LOCK_MAGIC 0x767B #define SLCR_UNLOCK_MAGIC 0xDF0D
+#define SLCR_IDCODE_MASK 0x1F000 +#define SLCR_IDCODE_SHIFT 12 + static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
void zynq_slcr_lock(void) @@ -87,3 +90,35 @@ void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk) out: zynq_slcr_lock(); } + +void zynq_slcr_devcfg_disable(void) +{ + zynq_slcr_unlock(); + + /* Disable AXI interface */ + writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl); + + /* Set Level Shifters DT618760 */ + writel(0xA, &slcr_base->lvl_shftr_en); + + zynq_slcr_lock(); +} + +void zynq_slcr_devcfg_enable(void) +{ + zynq_slcr_unlock(); + + /* Set Level Shifters DT618760 */ + writel(0xF, &slcr_base->lvl_shftr_en); + + /* Disable AXI interface */ + writel(0x0, &slcr_base->fpga_rst_ctrl); + + zynq_slcr_lock(); +} + +u32 zynq_slcr_get_idcode(void) +{ + return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >> + SLCR_IDCODE_SHIFT; +} diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h index 6af892a..8b8a91a 100644 --- a/arch/arm/include/asm/arch-zynq/hardware.h +++ b/arch/arm/include/asm/arch-zynq/hardware.h @@ -53,11 +53,17 @@ struct slcr_regs { u32 boot_mode; /* 0x25c */ u32 reserved4[116]; u32 trust_zone; /* 0x430 */ /* FIXME */ - u32 reserved5[115]; + u32 reserved5_1[63]; + u32 pss_idcode; /* 0x530 */ + u32 reserved5_2[51]; u32 ddr_urgent; /* 0x600 */ u32 reserved6[6]; u32 ddr_urgent_sel; /* 0x61c */ - u32 reserved7[188]; + u32 reserved7[56]; + u32 mio_pin[54]; /* 0x700 - 0x7D4 */ + u32 reserved8[74]; + u32 lvl_shftr_en; /* 0x900 */ + u32 reserved9[3]; u32 ocm_cfg; /* 0x910 */ };
diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h index af9e7f8..2317121 100644 --- a/arch/arm/include/asm/arch-zynq/sys_proto.h +++ b/arch/arm/include/asm/arch-zynq/sys_proto.h @@ -27,6 +27,9 @@ extern void zynq_slcr_lock(void); extern void zynq_slcr_unlock(void); extern void zynq_slcr_cpu_reset(void); extern void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk); +extern void zynq_slcr_devcfg_disable(void); +extern void zynq_slcr_devcfg_enable(void); +extern u32 zynq_slcr_get_idcode(void);
/* Driver extern functions */ extern int zynq_sdhci_init(u32 regbase); diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 1589d21..b02c364 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -22,15 +22,52 @@
#include <common.h> #include <netdev.h> +#include <zynqpl.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_FPGA +Xilinx_desc fpga; + +/* It can be done differently */ +Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); +Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); +Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); +Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); +#endif + int board_init(void) { +#ifdef CONFIG_FPGA + u32 idcode; + + idcode = zynq_slcr_get_idcode(); + + switch (idcode) { + case XILINX_ZYNQ_7010: + fpga = fpga010; + break; + case XILINX_ZYNQ_7020: + fpga = fpga020; + break; + case XILINX_ZYNQ_7030: + fpga = fpga030; + break; + case XILINX_ZYNQ_7045: + fpga = fpga045; + break; + } +#endif + icache_enable();
+#ifdef CONFIG_FPGA + fpga_init(); + fpga_add(fpga_xilinx, &fpga); +#endif + return 0; }
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index b48f623..0b51dcd 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -30,6 +30,7 @@ COBJS-y += fpga.o COBJS-$(CONFIG_FPGA_SPARTAN2) += spartan2.o COBJS-$(CONFIG_FPGA_SPARTAN3) += spartan3.o COBJS-$(CONFIG_FPGA_VIRTEX2) += virtex2.o +COBJS-$(CONFIG_FPGA_ZYNQPL) += zynqpl.o COBJS-$(CONFIG_FPGA_XILINX) += xilinx.o COBJS-$(CONFIG_FPGA_LATTICE) += ivm_core.o lattice.o ifdef CONFIG_FPGA_ALTERA diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index 32787b2..fe324ab 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -1,4 +1,6 @@ /* + * (C) Copyright 2012-2013, Xilinx, Michal Simek + * * (C) Copyright 2002 * Rich Ireland, Enterasys Networks, rireland@enterasys.com. * Keith Outwater, keith_outwater@mvis.com @@ -31,6 +33,7 @@ #include <virtex2.h> #include <spartan2.h> #include <spartan3.h> +#include <zynqpl.h>
#if 0 #define FPGA_DEBUG @@ -86,6 +89,16 @@ int xilinx_load(Xilinx_desc *desc, const void *buf, size_t bsize) __FUNCTION__); #endif break; + case xilinx_zynq: +#if defined(CONFIG_FPGA_ZYNQPL) + PRINTF("%s: Launching the Zynq PL Loader...\n", + __func__); + ret_val = zynq_load(desc, buf, bsize); +#else + printf("%s: No support for Zynq devices.\n", + __func__); +#endif + break;
default: printf ("%s: Unsupported family type, %d\n", @@ -133,6 +146,16 @@ int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize) __FUNCTION__); #endif break; + case xilinx_zynq: +#if defined(CONFIG_FPGA_ZYNQPL) + PRINTF("%s: Launching the Zynq PL Reader...\n", + __func__); + ret_val = zynq_dump(desc, buf, bsize); +#else + printf("%s: No support for Zynq devices.\n", + __func__); +#endif + break;
default: printf ("%s: Unsupported family type, %d\n", @@ -158,6 +181,9 @@ int xilinx_info (Xilinx_desc * desc) case Xilinx_Virtex2: printf ("Virtex-II\n"); break; + case xilinx_zynq: + printf("Zynq PL\n"); + break; /* Add new family types here */ default: printf ("Unknown family type, %d\n", desc->family); @@ -183,6 +209,9 @@ int xilinx_info (Xilinx_desc * desc) case master_selectmap: printf ("Master SelectMap Mode\n"); break; + case devcfg: + printf("Device configuration interface (Zynq)\n"); + break; /* Add new interface types here */ default: printf ("Unsupported interface type, %d\n", desc->iface); @@ -222,6 +251,14 @@ int xilinx_info (Xilinx_desc * desc) __FUNCTION__); #endif break; + case xilinx_zynq: +#if defined(CONFIG_FPGA_ZYNQPL) + zynq_info(desc); +#else + /* just in case */ + printf("%s: No support for Zynq devices.\n", + __func__); +#endif /* Add new family types here */ default: /* we don't need a message here - we give one up above */ diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c new file mode 100644 index 0000000..8feccde --- /dev/null +++ b/drivers/fpga/zynqpl.c @@ -0,0 +1,355 @@ +/* + * (C) Copyright 2012-2013, Xilinx, Michal Simek + * + * (C) Copyright 2012 + * Joe Hershberger joe.hershberger@ni.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <zynqpl.h> +#include <asm/arch/hardware.h> +#include <asm/arch/sys_proto.h> + +#define DEVCFG_CTRL_PCFG_PROG_B 0x40000000 +#define DEVCFG_ISR_FATAL_ERROR_MASK 0x00740040 +#define DEVCFG_ISR_ERROR_FLAGS_MASK 0x00340840 +#define DEVCFG_ISR_RX_FIFO_OV 0x00040000 +#define DEVCFG_ISR_DMA_DONE 0x00002000 +#define DEVCFG_ISR_PCFG_DONE 0x00000004 +#define DEVCFG_STATUS_DMA_CMD_Q_F 0x80000000 +#define DEVCFG_STATUS_DMA_CMD_Q_E 0x40000000 +#define DEVCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 +#define DEVCFG_STATUS_PCFG_INIT 0x00000010 +#define DEVCFG_MCTRL_RFIFO_FLUSH 0x00000002 +#define DEVCFG_MCTRL_WFIFO_FLUSH 0x00000001 + +#ifndef CONFIG_SYS_FPGA_WAIT +#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ +#endif + +#ifndef CONFIG_SYS_FPGA_PROG_TIME +#define CONFIG_SYS_FPGA_PROG_TIME CONFIG_SYS_HZ /* 1 s */ +#endif + +int zynq_info(Xilinx_desc *desc) +{ + return FPGA_SUCCESS; +} + +#define DUMMY_WORD 0xffffffff + +/* Xilinx binary format header */ +static const u32 bin_format[] = { + DUMMY_WORD, /* Dummy words */ + DUMMY_WORD, + DUMMY_WORD, + DUMMY_WORD, + DUMMY_WORD, + DUMMY_WORD, + DUMMY_WORD, + DUMMY_WORD, + 0x000000bb, /* Sync word */ + 0x11220044, /* Sync word */ + DUMMY_WORD, + DUMMY_WORD, + 0xaa995566, /* Sync word */ +}; + +#define SWAP_NO 1 +#define SWAP_DONE 2 + +/* + * Load the whole word from unaligned buffer + * Keep in your mind that it is byte loading on little-endian system + */ +static u32 load_word(const void *buf, u32 swap) +{ + u32 word = 0; + u8 *bitc = (u8 *)buf; + int p; + + if (swap == SWAP_NO) { + for (p = 0; p < 4; p++) { + word <<= 8; + word |= bitc[p]; + } + } else { + for (p = 3; p >= 0; p--) { + word <<= 8; + word |= bitc[p]; + } + } + + return word; +} + +static u32 check_header(const void *buf) +{ + u32 i, pattern; + int swap = SWAP_NO; + u32 *test = (u32 *)buf; + + debug("%s: Let's check bitstream header\n", __func__); + + /* Checking that passing bin is not a bitstream */ + for (i = 0; i < ARRAY_SIZE(bin_format); i++) { + pattern = load_word(&test[i], swap); + + /* + * Bitstreams in binary format are swapped + * compare to regular bistream. + * Do not swap dummy word but if swap is done assume + * that parsing buffer is binary format + */ + if ((__swab32(pattern) != DUMMY_WORD) && + (__swab32(pattern) == bin_format[i])) { + pattern = __swab32(pattern); + swap = SWAP_DONE; + debug("%s: data swapped - let's swap\n", __func__); + } + + debug("%s: %d/%x: pattern %x/%x bin_format\n", __func__, i, + (u32)&test[i], pattern, bin_format[i]); + if (pattern != bin_format[i]) { + debug("%s: Bitstream is not recognized\n", __func__); + return 0; + } + } + debug("%s: Found bitstream header at %x %s swapinng\n", __func__, + (u32)buf, swap == SWAP_NO ? "without" : "with"); + + return swap; +} + +static void *check_data(u8 *buf, size_t bsize, u32 *swap) +{ + u32 word, p = 0; /* possition */ + + /* Because buf doesn't need to be aligned let's read it by chars */ + for (p = 0; p < bsize; p++) { + word = load_word(&buf[p], SWAP_NO); + debug("%s: word %x %x/%x\n", __func__, word, p, (u32)&buf[p]); + + /* Find the first bitstream dummy word */ + if (word == DUMMY_WORD) { + debug("%s: Found dummy word at position %x/%x\n", + __func__, p, (u32)&buf[p]); + *swap = check_header(&buf[p]); + if (*swap) { + /* FIXME add full bitstream checking here */ + return &buf[p]; + } + } + /* Loop can be huge - support CTRL + C */ + if (ctrlc()) + return 0; + } + return 0; +} + + +int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) +{ + unsigned long ts; /* Timestamp */ + u32 partialbit = 0; + u32 i, control, isr_status, status, swap, diff; + u32 *buf_start; + + /* Detect if we are going working with partial or full bitstream */ + if (bsize != desc->size) { + printf("%s: Working with partial bitstream\n", __func__); + partialbit = 1; + } + + buf_start = check_data((u8 *)buf, bsize, &swap); + if (!buf_start) + return FPGA_FAIL; + + /* Check if data is postpone from start */ + diff = (u32)buf_start - (u32)buf; + if (diff) { + printf("%s: Bitstream is not validated yet (diff %x)\n", + __func__, diff); + return FPGA_FAIL; + } + + if ((u32)buf_start & 0x3) { + u32 *new_buf = (u32 *)((u32)buf & ~0x3); + + printf("%s: Align buffer at %x to %x(swap %d)\n", __func__, + (u32)buf_start, (u32)new_buf, swap); + + for (i = 0; i < (bsize/4); i++) + new_buf[i] = load_word(&buf_start[i], swap); + + swap = SWAP_DONE; + buf = new_buf; + } else if (swap != SWAP_DONE) { + /* For bitstream which are aligned */ + u32 *new_buf = (u32 *)buf; + + printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__, + swap); + + for (i = 0; i < (bsize/4); i++) + new_buf[i] = load_word(&buf_start[i], swap); + + swap = SWAP_DONE; + } + + if (!partialbit) { + zynq_slcr_devcfg_disable(); + + /* Setting PCFG_PROG_B signal to high */ + control = readl(&devcfg_base->ctrl); + writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl); + /* Setting PCFG_PROG_B signal to low */ + writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl); + + /* Polling the PCAP_INIT status for Reset */ + ts = get_timer(0); + while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) { + if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { + printf("%s: Timeout wait for INIT to clear\n", + __func__); + return FPGA_FAIL; + } + } + + /* Setting PCFG_PROG_B signal to high */ + writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl); + + /* Polling the PCAP_INIT status for Set */ + ts = get_timer(0); + while (!(readl(&devcfg_base->status) & + DEVCFG_STATUS_PCFG_INIT)) { + if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { + printf("%s: Timeout wait for INIT to set\n", + __func__); + return FPGA_FAIL; + } + } + } + + isr_status = readl(&devcfg_base->int_sts); + + /* Clear it all, so if Boot ROM comes back, it can proceed */ + writel(0xFFFFFFFF, &devcfg_base->int_sts); + + if (isr_status & DEVCFG_ISR_FATAL_ERROR_MASK) { + debug("%s: Fatal errors in PCAP 0x%X\n", __func__, isr_status); + + /* If RX FIFO overflow, need to flush RX FIFO first */ + if (isr_status & DEVCFG_ISR_RX_FIFO_OV) { + writel(DEVCFG_MCTRL_RFIFO_FLUSH, &devcfg_base->mctrl); + writel(0xFFFFFFFF, &devcfg_base->int_sts); + } + return FPGA_FAIL; + } + + status = readl(&devcfg_base->status); + + debug("%s: Status = 0x%08X\n", __func__, status); + + if (status & DEVCFG_STATUS_DMA_CMD_Q_F) { + debug("%s: Error: device busy\n", __func__); + return FPGA_FAIL; + } + + debug("%s: Device ready\n", __func__); + + if (!(status & DEVCFG_STATUS_DMA_CMD_Q_E)) { + if (!(readl(&devcfg_base->int_sts) & DEVCFG_ISR_DMA_DONE)) { + /* Error state, transfer cannot occur */ + debug("%s: ISR indicates error\n", __func__); + return FPGA_FAIL; + } else { + /* Clear out the status */ + writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts); + } + } + + if (status & DEVCFG_STATUS_DMA_DONE_CNT_MASK) { + /* Clear the count of completed DMA transfers */ + writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, &devcfg_base->status); + } + + debug("%s: Source = 0x%08X\n", __func__, (u32)buf); + debug("%s: Size = %zu\n", __func__, bsize); + + /* Set up the transfer */ + writel((u32)buf | 1, &devcfg_base->dma_src_addr); + writel(0xFFFFFFFF, &devcfg_base->dma_dst_addr); + writel(bsize >> 2, &devcfg_base->dma_src_len); + writel(0, &devcfg_base->dma_dst_len); + + isr_status = readl(&devcfg_base->int_sts); + + /* Polling the PCAP_INIT status for Set */ + ts = get_timer(0); + while (!(isr_status & DEVCFG_ISR_DMA_DONE)) { + if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) { + debug("%s: Error: isr = 0x%08X\n", __func__, + isr_status); + debug("%s: Write count = 0x%08X\n", __func__, + readl(&devcfg_base->write_count)); + debug("%s: Read count = 0x%08X\n", __func__, + readl(&devcfg_base->read_count)); + + return FPGA_FAIL; + } + if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) { + printf("%s: Timeout wait for DMA to complete\n", + __func__); + return FPGA_FAIL; + } + isr_status = readl(&devcfg_base->int_sts); + } + + debug("%s: DMA transfer is done\n", __func__); + + /* Check FPGA configuration completion */ + ts = get_timer(0); + while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) { + if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { + printf("%s: Timeout wait for FPGA to config\n", + __func__); + return FPGA_FAIL; + } + isr_status = readl(&devcfg_base->int_sts); + } + + debug("%s: FPGA config done\n", __func__); + + /* Clear out the DMA status */ + writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts); + + if (!partialbit) + zynq_slcr_devcfg_enable(); + + return FPGA_SUCCESS; +} + +int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +{ + return FPGA_FAIL; +} diff --git a/include/configs/zynq.h b/include/configs/zynq.h index f1f182e..38f04f6 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -88,6 +88,12 @@ # define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */ #endif
+/* Enable the PL to be downloaded */ +#define CONFIG_FPGA +#define CONFIG_FPGA_XILINX +#define CONFIG_FPGA_ZYNQPL +#define CONFIG_CMD_FPGA + #define CONFIG_BOOTP_SERVERIP #define CONFIG_BOOTP_BOOTPATH #define CONFIG_BOOTP_GATEWAY diff --git a/include/xilinx.h b/include/xilinx.h index 5f25b7a..592cbea 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -33,10 +33,12 @@ #define CONFIG_SYS_VIRTEX_E CONFIG_SYS_FPGA_DEV( 0x2 ) #define CONFIG_SYS_VIRTEX2 CONFIG_SYS_FPGA_DEV( 0x4 ) #define CONFIG_SYS_SPARTAN3 CONFIG_SYS_FPGA_DEV( 0x8 ) +#define CONFIG_SYS_ZYNQ CONFIG_SYS_FPGA_DEV(0x10) #define CONFIG_SYS_XILINX_SPARTAN2 (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_SPARTAN2) #define CONFIG_SYS_XILINX_VIRTEX_E (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_VIRTEX_E) #define CONFIG_SYS_XILINX_VIRTEX2 (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_VIRTEX2) #define CONFIG_SYS_XILINX_SPARTAN3 (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_SPARTAN3) +#define CONFIG_SYS_XILINX_ZYNQ (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_ZYNQ) /* XXX - Add new models here */
@@ -59,6 +61,7 @@ typedef enum { /* typedef Xilinx_iface */ jtag_mode, /* jtag/tap serial (not used ) */ master_selectmap, /* master SelectMap (virtex2) */ slave_selectmap, /* slave SelectMap (virtex2) */ + devcfg, /* devcfg interface (zynq) */ max_xilinx_iface_type /* insert all new types before this */ } Xilinx_iface; /* end, typedef Xilinx_iface */
@@ -68,6 +71,7 @@ typedef enum { /* typedef Xilinx_Family */ Xilinx_VirtexE, /* Virtex-E Family */ Xilinx_Virtex2, /* Virtex2 Family */ Xilinx_Spartan3, /* Spartan-III Family */ + xilinx_zynq, /* Zynq Family */ max_xilinx_type /* insert all new types before this */ } Xilinx_Family; /* end, typedef Xilinx_Family */
diff --git a/include/zynqpl.h b/include/zynqpl.h new file mode 100644 index 0000000..bc9b948 --- /dev/null +++ b/include/zynqpl.h @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2012-2013, Xilinx, Michal Simek + * + * (C) Copyright 2012 + * Joe Hershberger joe.hershberger@ni.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ZYNQPL_H_ +#define _ZYNQPL_H_ + +#include <xilinx.h> + +extern int zynq_load(Xilinx_desc *desc, const void *image, size_t size); +extern int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +extern int zynq_info(Xilinx_desc *desc); + +#define XILINX_ZYNQ_7010 0x2 +#define XILINX_ZYNQ_7020 0x7 +#define XILINX_ZYNQ_7030 0xc +#define XILINX_ZYNQ_7045 0x11 + +/* Device Image Sizes */ +#define XILINX_XC7Z010_SIZE 16669920/8 +#define XILINX_XC7Z020_SIZE 32364512/8 +#define XILINX_XC7Z030_SIZE 47839328/8 +#define XILINX_XC7Z045_SIZE 106571232/8 + +/* Descriptor Macros */ +#define XILINX_XC7Z010_DESC(cookie) \ +{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie } + +#define XILINX_XC7Z020_DESC(cookie) \ +{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie } + +#define XILINX_XC7Z030_DESC(cookie) \ +{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie } + +#define XILINX_XC7Z045_DESC(cookie) \ +{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie } + +#endif /* _ZYNQPL_H_ */ -- 1.8.2.1
Ensure that wrong bitstream won't be loaded to current device.
Signed-off-by: Michal Simek michal.simek@xilinx.com
--- Changes in v2: - New patch in this series
drivers/fpga/fpga.c | 20 ++++++++++++++++++++ drivers/fpga/xilinx.c | 2 ++ include/xilinx.h | 1 + include/zynqpl.h | 8 ++++---- 4 files changed, 27 insertions(+), 4 deletions(-)
diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c index b74c84f..5ba8cf0 100644 --- a/drivers/fpga/fpga.c +++ b/drivers/fpga/fpga.c @@ -197,8 +197,14 @@ int fpga_loadbitstream(unsigned long dev, char *fpgadata, size_t size) unsigned char *dataptr; unsigned int i; int rc; + const fpga_desc *desc; + Xilinx_desc *xdesc;
dataptr = (unsigned char *)fpgadata; + /* Find out fpga_description */ + desc = fpga_validate(dev, dataptr, 0, (char *)__func__); + /* Assign xilinx device description */ + xdesc = desc->devdesc;
/* skip the first bytes of the bitsteam, their meaning is unknown */ length = (*dataptr << 8) + *(dataptr + 1); @@ -232,6 +238,20 @@ int fpga_loadbitstream(unsigned long dev, char *fpgadata, size_t size) dataptr += 2; for (i = 0; i < length; i++) buffer[i] = *dataptr++; + + if (xdesc->name) { + i = strncmp(buffer, xdesc->name, strlen(xdesc->name)); + if (i) { + printf("%s: Wrong bitstream ID for this device\n", + __func__); + printf("%s: Bitstream ID %s, current device ID %d/%s\n", + __func__, dev, xdesc->name, buffer); + return FPGA_FAIL; + } + } else { + printf("%s: Please fill correct device ID to Xilinx_desc\n", + __func__); + } printf(" part number = "%s"\n", buffer);
/* get date (identifier, length, string) */ diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index fe324ab..bd740c2 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -220,6 +220,8 @@ int xilinx_info (Xilinx_desc * desc) printf ("Device Size: \t%d bytes\n" "Cookie: \t0x%x (%d)\n", desc->size, desc->cookie, desc->cookie); + if (desc->name) + printf("Device name: \t%s\n", desc->name);
if (desc->iface_fns) { printf ("Device Function Table @ 0x%p\n", desc->iface_fns); diff --git a/include/xilinx.h b/include/xilinx.h index 592cbea..bcfe76d 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -81,6 +81,7 @@ typedef struct { /* typedef Xilinx_desc */ size_t size; /* bytes of data part can accept */ void *iface_fns; /* interface function table */ int cookie; /* implementation specific cookie */ + char *name; /* device name in bitstream */ } Xilinx_desc; /* end, typedef Xilinx_desc */
/* Generic Xilinx Functions diff --git a/include/zynqpl.h b/include/zynqpl.h index bc9b948..0247ef6 100644 --- a/include/zynqpl.h +++ b/include/zynqpl.h @@ -45,15 +45,15 @@ extern int zynq_info(Xilinx_desc *desc);
/* Descriptor Macros */ #define XILINX_XC7Z010_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie } +{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, "7z010" }
#define XILINX_XC7Z020_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie } +{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, "7z020" }
#define XILINX_XC7Z030_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie } +{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, "7z030" }
#define XILINX_XC7Z045_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie } +{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, "7z045" }
#endif /* _ZYNQPL_H_ */ -- 1.8.2.1
On Wed, May 01, 2013 at 10:59:16AM +0200, Michal Simek wrote:
Fpga code is pretty old and none has tried to clean it up. My attempt is related to new code I want to push to mainline which is add support for checking bitstream and if bitstream is valid for the selected device. For this I need to do cleanup code and move code from cmd_fpga.c to fpga.c in driver folder.
Aside from my comments to 4/7, everything else looks good and a step forward.
Looking at 7/7 however, it seems like: - None of CONFIG_SYS_XILINX_IF_* are used - CONFIG_SYS_... model definitions... aren't used, now that CONFIG_FPGA isn't a bitfield anymore, and are only used by configs that still act like it is.
So we could just clean up and remove those parts of the header, yes?
On 05/01/2013 05:14 PM, Tom Rini wrote:
On Wed, May 01, 2013 at 10:59:16AM +0200, Michal Simek wrote:
Fpga code is pretty old and none has tried to clean it up. My attempt is related to new code I want to push to mainline which is add support for checking bitstream and if bitstream is valid for the selected device. For this I need to do cleanup code and move code from cmd_fpga.c to fpga.c in driver folder.
Aside from my comments to 4/7, everything else looks good and a step forward.
ok
Looking at 7/7 however, it seems like:
- None of CONFIG_SYS_XILINX_IF_* are used
- CONFIG_SYS_... model definitions... aren't used, now that CONFIG_FPGA isn't a bitfield anymore, and are only used by configs that still act like it is.
So we could just clean up and remove those parts of the header, yes?
yep, you are right. I will create one more patch which remove these values. (It should be done in 2008).
Thanks, Michal
participants (3)
-
Michal Simek -
Michal Simek -
Tom Rini