[U-Boot] [PATCH 0/6] pcie-layerscape: Enable PCI-LUT initialization for NXP-Chasis-2
This patch series enables PCI-LUT table initialization for NXP Chassis-2 (for example ls1043, ls1046 and LS1012) devices. As part of this, stream-ids allocation is added which is similar to Chassis-3 (ls2080a)
Also this series have a minor cleanup, as stream-id definition file is given generic name for chassis-3 devices. This allows new SOCs, ls2088, ls1088 etc to use same allocation mechanism.
Bharat Bhushan (6): fsl-lsch3: rename ls2080a_stream_id.h to stream_id_lsch3.h fsl-lsch3: Rewording to support other Chassis-3 Socs pcie-layerscape: Define stream-ids for Layerscape Chassis-2 fsl-lsch2: Use Chassis-2 streamid definition for ls1046a fsl-lsch2: Use Chassis-2 streamid definition for ls1012a pcie-layerscape: Initialize pci-lut for NXP chasis-2 socs
.../asm/arch-fsl-layerscape/stream_id_lsch2.h | 60 ++++++++++++++++++++++ .../{ls2080a_stream_id.h => stream_id_lsch3.h} | 12 ++--- drivers/pci/pcie_layerscape_fixup.c | 4 +- include/configs/ls1012a_common.h | 1 + include/configs/ls1043a_common.h | 1 + include/configs/ls1046a_common.h | 1 + include/configs/ls2080a_common.h | 2 +- 7 files changed, 72 insertions(+), 9 deletions(-) create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h rename arch/arm/include/asm/arch-fsl-layerscape/{ls2080a_stream_id.h => stream_id_lsch3.h} (86%)
The stream ID allocation for Chasis3.0 devices, LS1088, LS2088 and LS2080, can be shared.
This patch renames this accordingly.
Signed-off-by: Bharat Bhushan Bharat.Bhushan@nxp.com --- .../asm/arch-fsl-layerscape/{ls2080a_stream_id.h => stream_id_lsch3.h} | 0 include/configs/ls2080a_common.h | 2 +- 2 files changed, 1 insertion(+), 1 deletion(-) rename arch/arm/include/asm/arch-fsl-layerscape/{ls2080a_stream_id.h => stream_id_lsch3.h} (100%)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h similarity index 100% rename from arch/arm/include/asm/arch-fsl-layerscape/ls2080a_stream_id.h rename to arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 4bfd0ac..ee432ae 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -13,7 +13,7 @@ #define CONFIG_GICV3 #define CONFIG_FSL_TZPC_BP147
-#include <asm/arch/ls2080a_stream_id.h> +#include <asm/arch/stream_id_lsch3.h> #include <asm/arch/config.h>
/* Link Definitions */
LS2080a, LS1088a and LS2088a SOCs are based on Chassis-3 and shared same stream-id partitioning. This patch rewords the definition to support all these SOCs.
Signed-off-by: Bharat Bhushan Bharat.Bhushan@nxp.com --- arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index ee28323..6e97909 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -8,11 +8,11 @@ #define __FSL_STREAM_ID_H
/* - * Stream IDs on ls2080a devices are not hardwired and are - * programmed by sw. There are a limited number of stream IDs - * available, and the partitioning of them is scenario dependent. - * This header defines the partitioning between legacy, PCI, - * and DPAA2 devices. + * Stream IDs on NXP Chassis-3 (for example ls2080a, ls1088a, ls2088a) + * devices are not hardwired and are programmed by sw. There are a limited + * number of stream IDs available, and the partitioning of them is scenario + * dependent. This header defines the partitioning between legacy, + * PCI, and DPAA2 devices. * * This partitioning can be customized in this file depending * on the specific hardware config: @@ -36,7 +36,7 @@ * -the MC is responsible for allocating and setting up 'isolation context * IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices. * - * On ls2080a SoCs stream IDs are programmed in AMQ registers (32-bits) for + * On Chasis-3 SoCs stream IDs are programmed in AMQ registers (32-bits) for * each of the different bus masters. The relationship between * the AMQ registers and stream IDs is defined in the table below: * AMQ bit streamID bit
Layerscape Chassis-2 have PCIe device, some platform devices and DPAA1 devices which will use stream-ids for iommu level isolation as they lies behind SMMU.
This patch defines the stream-ids for Chassis-2 devices. stream-ids for DPAA1 are reserved for future use.
Signed-off-by: Bharat Bhushan Bharat.Bhushan@nxp.com --- .../asm/arch-fsl-layerscape/stream_id_lsch2.h | 60 ++++++++++++++++++++++ include/configs/ls1043a_common.h | 1 + 2 files changed, 61 insertions(+) create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h new file mode 100644 index 0000000..d41dd2e --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h @@ -0,0 +1,60 @@ +/* + * Copyright 2017 NXP Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ +#ifndef __FSL_STREAM_ID_H +#define __FSL_STREAM_ID_H + +/* + * Stream IDs on Chassis-2 (for example ls1043a, ls1046a, ls1012) devices + * are not hardwired and are programmed by sw. There are a limited number + * of stream IDs available, and the partitioning of them is scenario + * dependent. This header defines the partitioning between legacy, PCI, + * and DPAA1 devices. + * + * This partitioning can be customized in this file depending + * on the specific hardware config: + * + * -non-PCI legacy, platform devices (USB, SDHC, SATA, DMA, QE etc) + * -all legacy devices get a unique stream ID assigned and programmed in + * their AMQR registers by u-boot + * + * -PCIe + * -there is a range of stream IDs set aside for PCI in this + * file. U-boot will scan the PCI bus and for each device discovered: + * -allocate a streamID + * -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID' + * -set a msi-map entry in the PEXn controller node in the + * device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt + * for more info on the msi-map definition) + * + * -DPAA1 + * - Stream ids for DPAA1 use are reserved for future usecase. + * + */ + + +#define FSL_INVALID_STREAM_ID 0 + +/* legacy devices */ +#define FSL_USB1_STREAM_ID 1 +#define FSL_USB2_STREAM_ID 2 +#define FSL_USB3_STREAM_ID 3 +#define FSL_SDHC_STREAM_ID 4 +#define FSL_SATA_STREAM_ID 5 +#define FSL_QE_STREAM_ID 6 +#define FSL_QDMA_STREAM_ID 7 +#define FSL_EDMA_STREAM_ID 8 +#define FSL_ETR_STREAM_ID 9 + +/* PCI - programmed in PEXn_LUT */ +#define FSL_PEX_STREAM_ID_START 11 +#define FSL_PEX_STREAM_ID_END 26 + +/* DPAA1 - Stream-ID that can be programmed in DPAA1 h/w */ +#define FSL_DPAA1_STREAM_ID_START 27 +#define FSL_DPAA1_STREAM_ID_END 63 + +#endif diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index c4b05e0..5f84497 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -13,6 +13,7 @@ #define CONFIG_MP #define CONFIG_GICV2
+#include <asm/arch/stream_id_lsch2.h> #include <asm/arch/config.h>
/* Link Definitions */
On 2/24/2017 10:02 AM, Bharat Bhushan wrote:
Layerscape Chassis-2 have PCIe device, some platform devices and DPAA1 devices which will use stream-ids for iommu level isolation as they lies behind SMMU.
This patch defines the stream-ids for Chassis-2 devices. stream-ids for DPAA1 are reserved for future use.
Signed-off-by: Bharat Bhushan Bharat.Bhushan@nxp.com
.../asm/arch-fsl-layerscape/stream_id_lsch2.h | 60 ++++++++++++++++++++++ include/configs/ls1043a_common.h | 1 + 2 files changed, 61 insertions(+) create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h new file mode 100644 index 0000000..d41dd2e --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h @@ -0,0 +1,60 @@ +/*
- Copyright 2017 NXP Semiconductor, Inc.
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __FSL_STREAM_ID_H +#define __FSL_STREAM_ID_H
+/*
- Stream IDs on Chassis-2 (for example ls1043a, ls1046a, ls1012) devices
- are not hardwired and are programmed by sw. There are a limited number
- of stream IDs available, and the partitioning of them is scenario
- dependent. This header defines the partitioning between legacy, PCI,
- and DPAA1 devices.
- This partitioning can be customized in this file depending
- on the specific hardware config:
- -non-PCI legacy, platform devices (USB, SDHC, SATA, DMA, QE etc)
-all legacy devices get a unique stream ID assigned and programmed in
their AMQR registers by u-boot
- -PCIe
-there is a range of stream IDs set aside for PCI in this
file. U-boot will scan the PCI bus and for each device discovered:
-allocate a streamID
-set a PEXn LUT table entry mapping 'requester ID' to 'stream ID'
-set a msi-map entry in the PEXn controller node in the
device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt
for more info on the msi-map definition)
Only msi-map? Don't we need an iommu-map as well?
- -DPAA1
- Stream ids for DPAA1 use are reserved for future usecase.
- */
+#define FSL_INVALID_STREAM_ID 0
+/* legacy devices */ +#define FSL_USB1_STREAM_ID 1 +#define FSL_USB2_STREAM_ID 2 +#define FSL_USB3_STREAM_ID 3 +#define FSL_SDHC_STREAM_ID 4 +#define FSL_SATA_STREAM_ID 5 +#define FSL_QE_STREAM_ID 6 +#define FSL_QDMA_STREAM_ID 7 +#define FSL_EDMA_STREAM_ID 8 +#define FSL_ETR_STREAM_ID 9
+/* PCI - programmed in PEXn_LUT */ +#define FSL_PEX_STREAM_ID_START 11 +#define FSL_PEX_STREAM_ID_END 26
+/* DPAA1 - Stream-ID that can be programmed in DPAA1 h/w */ +#define FSL_DPAA1_STREAM_ID_START 27 +#define FSL_DPAA1_STREAM_ID_END 63
+#endif diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index c4b05e0..5f84497 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -13,6 +13,7 @@ #define CONFIG_MP #define CONFIG_GICV2
+#include <asm/arch/stream_id_lsch2.h> #include <asm/arch/config.h>
/* Link Definitions */
Diana
As ls1046a is Chassis-2 type SOC and shares same streamid definition, this patch adds using streamids for ls1046
Signed-off-by: Bharat Bhushan Bharat.Bhushan@nxp.com --- include/configs/ls1046a_common.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index be65e4f..b4b198b 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -13,6 +13,7 @@ #define CONFIG_GICV2
#include <asm/arch/config.h> +#include <asm/arch/stream_id_lsch2.h>
/* Link Definitions */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
As ls1012a is Chassis-2 type SOC and shares same streamid definition, this patch adds using streamids for ls1012a
Signed-off-by: Bharat Bhushan Bharat.Bhushan@nxp.com --- include/configs/ls1012a_common.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index e556c92..5765181 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -11,6 +11,7 @@ #define CONFIG_GICV2
#include <asm/arch/config.h> +#include <asm/arch/stream_id_lsch2.h>
#define CONFIG_SUPPORT_RAW_INITRD
From: Bharat Bhushan bharat.bhushan@nxp.com
Layerscape Chasis-2 also uses same PCIe controller as used in Chasis-3 and have similar PCI-Lut.
We need to initialize the pcie-lut for Chasis-2 also as in Chasis-3.
Signed-off-by: Bharat Bhushan bharat.bhushan@nxp.com --- drivers/pci/pcie_layerscape_fixup.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c index 19ede2f..8f8f6b6 100644 --- a/drivers/pci/pcie_layerscape_fixup.c +++ b/drivers/pci/pcie_layerscape_fixup.c @@ -15,7 +15,7 @@ #include <fdt_support.h> #include "pcie_layerscape.h"
-#ifdef CONFIG_FSL_LSCH3 +#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2) /* * Return next available LUT index. */ @@ -175,7 +175,7 @@ void ft_pci_setup(void *blob, bd_t *bd) list_for_each_entry(pcie, &ls_pcie_list, list) ft_pcie_ls_setup(blob, pcie);
-#ifdef CONFIG_FSL_LSCH3 +#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2) fdt_fixup_pcie(blob); #endif }
participants (2)
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Bharat Bhushan -
Diana Madalina Craciun