[U-Boot] [PATCH] armv8: ls2080ardb: Update default sysclk to 100MHz
As per board documentation, default sysclk is 100MHz So, update the default value in ls0280ardb board file to return 100MHz
Signed-off-by: Priyanka Jain priyanka.jain@nxp.com --- board/freescale/ls2080ardb/ls2080ardb.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index 1de5058..1bd555b 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -117,7 +117,7 @@ unsigned long get_board_sys_clk(void) return 166666666; } #endif - return 66666666; + return 100000000; }
int select_i2c_ch_pca9547(u8 ch)
On 04/22/2017 02:42 AM, Priyanka Jain wrote:
As per board documentation, default sysclk is 100MHz So, update the default value in ls0280ardb board file to return 100MHz
This doesn't explain why you are changing the clock now. You only need this value returned if CPLD is not accessible. You should explain it in your commit message.
York
-----Original Message----- From: York Sun [mailto:york.sun@nxp.com] Sent: Monday, April 24, 2017 9:24 PM To: Priyanka Jain priyanka.jain@nxp.com; u-boot@lists.denx.de Subject: Re: [PATCH] armv8: ls2080ardb: Update default sysclk to 100MHz
On 04/22/2017 02:42 AM, Priyanka Jain wrote:
As per board documentation, default sysclk is 100MHz So, update the default value in ls0280ardb board file to return 100MHz
This doesn't explain why you are changing the clock now. You only need this value returned if CPLD is not accessible. You should explain it in your commit message.
York
The code change is required only with "Updae QIXIS code" patch. So, I have merge this code change with that patch.
Priyanka
participants (2)
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Priyanka Jain -
York Sun