[U-Boot] [PATCH v8 19/23] rockchip: rk3036: Add core Soc start-up code
From: huang lin hl@rock-chips.com
rk3036 only 4K size SRAM for SPL, so only support timer, uart, sdram driver in SPL stage, when finish initial sdram, back to bootrom.And in rk3036 sdmmc and debug uart use same iomux, so if you want to boot from sdmmc, you must disable debug uart.
Signed-off-by: Lin Huang hl@rock-chips.com Acked-by: Simon Glass sjg@chromium.org Fixed build error for chromebook_jerry, firefly-rk3288: Signed-off-by: Simon Glass sjg@chromium.org
---
Changes in v8: - Fix build error for chromebook_jerry, firefly-rk3288
arch/arm/mach-rockchip/Kconfig | 10 ++- arch/arm/mach-rockchip/Makefile | 4 +- arch/arm/mach-rockchip/board.c | 1 + arch/arm/mach-rockchip/rk3036-board-spl.c | 55 +++++++++++++ arch/arm/mach-rockchip/rk3036/Kconfig | 3 + arch/arm/mach-rockchip/rk3036/Makefile | 1 + arch/arm/mach-rockchip/rk3036/save_boot_param.S | 32 ++++++++ include/configs/rk3036_common.h | 103 ++++++++++++++++++++++++ 8 files changed, 207 insertions(+), 2 deletions(-) create mode 100644 arch/arm/mach-rockchip/rk3036-board-spl.c create mode 100644 arch/arm/mach-rockchip/rk3036/Kconfig create mode 100644 arch/arm/mach-rockchip/rk3036/save_boot_param.S create mode 100644 include/configs/rk3036_common.h
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index da665ef..6b608db 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -9,6 +9,14 @@ config ROCKCHIP_RK3288 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UART,s, SPI, I2C and PWMs.
+config ROCKCHIP_RK3036 + bool "Support Rockchip RK3036" + help + The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7 + including NEON and GPU, Mali-400 graphics, several DDR3 options + and video codec support. Peripherals include Gigabit Ethernet, + USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. + config SYS_MALLOC_F default y
@@ -34,5 +42,5 @@ config ROCKCHIP_SERIAL default y
source "arch/arm/mach-rockchip/rk3288/Kconfig" - +source "arch/arm/mach-rockchip/rk3036/Kconfig" endif diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index a29675d..b703c3c 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -6,10 +6,12 @@
ifdef CONFIG_SPL_BUILD obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o +obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o else -obj-y += board.o +obj-$(CONFIG_ROCKCHIP_RK3288) += board.o endif obj-y += rk_timer.o obj-y += rk_early_print.o obj-$(CONFIG_$(SPL_)ROCKCHIP_COMMON) += common.o obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/ +obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/ diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c index 688bc0f..f026abf 100644 --- a/arch/arm/mach-rockchip/board.c +++ b/arch/arm/mach-rockchip/board.c @@ -7,6 +7,7 @@ #include <common.h> #include <dm.h> #include <ram.h> +#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/mach-rockchip/rk3036-board-spl.c b/arch/arm/mach-rockchip/rk3036-board-spl.c new file mode 100644 index 0000000..3a1491c --- /dev/null +++ b/arch/arm/mach-rockchip/rk3036-board-spl.c @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/grf_rk3036.h> +#include <asm/arch/hardware.h> +#include <asm/arch/sdram_rk3036.h> +#include <asm/arch/timer.h> +#include <asm/arch/uart.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define GRF_BASE 0x20008000 +static struct rk3036_grf * const grf = (void *)GRF_BASE; + +#define DEBUG_UART_BASE 0x20068000 + +extern void back_to_bootrom(void); + +void board_init_f(ulong dummy) +{ +#ifdef EARLY_DEBUG + /* + * NOTE: sd card and debug uart use same iomux in rk3036, + * so if you enable uart, + * you can not boot from sdcard + */ + rk_clrsetreg(&grf->gpio1c_iomux, + GPIO1C3_MASK << GPIO1C3_SHIFT | + GPIO1C2_MASK << GPIO1C2_SHIFT, + GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT | + GPIO1C2_UART2_SIN << GPIO1C2_SHIFT); + rk_uart_init((void *)DEBUG_UART_BASE); +#endif + rockchip_timer_init(); + sdram_init(); + + /* return to maskrom */ + back_to_bootrom(); +} + +/* Place Holders */ +void board_init_r(gd_t *id, ulong dest_addr) +{ + /* + * Function attribute is no-return + * This Function never executes + */ + while (1) + ; +} diff --git a/arch/arm/mach-rockchip/rk3036/Kconfig b/arch/arm/mach-rockchip/rk3036/Kconfig new file mode 100644 index 0000000..d76d5e1 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3036/Kconfig @@ -0,0 +1,3 @@ +if ROCKCHIP_RK3036 + +endif diff --git a/arch/arm/mach-rockchip/rk3036/Makefile b/arch/arm/mach-rockchip/rk3036/Makefile index 6095777..97d299d 100644 --- a/arch/arm/mach-rockchip/rk3036/Makefile +++ b/arch/arm/mach-rockchip/rk3036/Makefile @@ -10,3 +10,4 @@ obj-y += syscon_rk3036.o endif
obj-y += sdram_rk3036.o +obj-y += save_boot_param.o diff --git a/arch/arm/mach-rockchip/rk3036/save_boot_param.S b/arch/arm/mach-rockchip/rk3036/save_boot_param.S new file mode 100644 index 0000000..778ec83 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3036/save_boot_param.S @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/linkage.h> + +.globl SAVE_SP_ADDR +SAVE_SP_ADDR: + .word 0 + +/* + * void save_boot_params + * + * Save sp, lr, r1~r12 + */ +ENTRY(save_boot_params) + push {r1-r12, lr} + ldr r0, =SAVE_SP_ADDR + str sp, [r0] + b save_boot_params_ret @ back to my caller +ENDPROC(save_boot_params) + + +.globl back_to_bootrom +ENTRY(back_to_bootrom) + ldr r0, =SAVE_SP_ADDR + ldr sp, [r0] + mov r0, #0 + pop {r1-r12, pc} +ENDPROC(back_to_bootrom) diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h new file mode 100644 index 0000000..525fabc --- /dev/null +++ b/include/configs/rk3036_common.h @@ -0,0 +1,103 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIG_RK3036_COMMON_H +#define __CONFIG_RK3036_COMMON_H + +#include <asm/arch/hardware.h> + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_MALLOC_LEN (32 << 20) +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_THUMB_BUILD +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) +#define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */ +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_MEM32 + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MALLOC_SIMPLE +#endif + +#define CONFIG_SYS_TEXT_BASE 0x60000000 +#define CONFIG_SYS_INIT_SP_ADDR 0x60100000 +#define CONFIG_SYS_LOAD_ADDR 0x60800800 +#define CONFIG_SPL_STACK 0x10081fff +#define CONFIG_SPL_TEXT_BASE 0x10081004 + +#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (4 << 10) +#define CONFIG_ROCKCHIP_CHIP_TAG "RK30" + +#define CONFIG_ROCKCHIP_COMMON + +/* MMC/SD IP block */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_MMC +#define CONFIG_SDHCI +#define CONFIG_DWMMC +#define CONFIG_BOUNCE_BUFFER + +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_FAT_WRITE +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_PARTITION_UUIDS +#define CONFIG_CMD_PART + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_TIME + +#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CONFIG_NR_DRAM_BANKS 1 +#define SDRAM_BANK_SIZE (512UL << 20UL) + +#define CONFIG_SPI_FLASH +#define CONFIG_SPI +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_SPI_FLASH_GIGADEVICE +#define CONFIG_SF_DEFAULT_SPEED 20000000 + +#define CONFIG_CMD_I2C + +#ifndef CONFIG_SPL_BUILD +#include <config_distro_defaults.h> + +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x60000000\0" \ + "pxefile_addr_r=0x60100000\0" \ + "fdt_addr_r=0x61f00000\0" \ + "kernel_addr_r=0x62000000\0" \ + "ramdisk_addr_r=0x64000000\0" + +/* First try to boot from SD (index 0), then eMMC (index 1 */ +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) + +#include <config_distro_bootcmd.h> + +/* Linux fails to load the fdt if it's loaded above 512M on a evb-rk3036 board, + * so limit the fdt reallocation to that */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0x7fffffff\0" \ + ENV_MEM_LAYOUT_SETTINGS \ + BOOTENV +#endif + +#endif
From: huang lin hl@rock-chips.com
This add some basic files required to allow the board to dispaly serial message and can run command(mmc info etc)
Signed-off-by: Lin Huang hl@rock-chips.com Acked-by: Simon Glass sjg@chromium.org Moved board Kconfig fragment from previous patch into this one to fix build error: Signed-off-by: Simon Glass sjg@chromium.org
---
Changes in v8: - moved board Kconfig fragment from previous patch into this one
arch/arm/dts/Makefile | 3 +- arch/arm/dts/rk3036-sdk.dts | 46 ++++++++++++++++++++++++++++++ arch/arm/mach-rockchip/rk3036/Kconfig | 14 +++++++++ board/evb_rk3036/evb_rk3036/Kconfig | 15 ++++++++++ board/evb_rk3036/evb_rk3036/MAINTAINERS | 0 board/evb_rk3036/evb_rk3036/Makefile | 7 +++++ board/evb_rk3036/evb_rk3036/evb_rk3036.c | 49 ++++++++++++++++++++++++++++++++ configs/evb-rk3036_defconfig | 26 +++++++++++++++++ include/configs/evb_rk3036.h | 12 ++++++++ 9 files changed, 171 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3036-sdk.dts create mode 100644 board/evb_rk3036/evb_rk3036/Kconfig create mode 100644 board/evb_rk3036/evb_rk3036/MAINTAINERS create mode 100644 board/evb_rk3036/evb_rk3036/Makefile create mode 100644 board/evb_rk3036/evb_rk3036/evb_rk3036.c create mode 100644 configs/evb-rk3036_defconfig create mode 100644 include/configs/evb_rk3036.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9542fff..b383500 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -21,7 +21,8 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ exynos5422-odroidxu3.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-firefly.dtb \ - rk3288-jerry.dtb + rk3288-jerry.dtb \ + rk3036-sdk.dtb dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ tegra20-paz00.dtb \ diff --git a/arch/arm/dts/rk3036-sdk.dts b/arch/arm/dts/rk3036-sdk.dts new file mode 100644 index 0000000..a83badb --- /dev/null +++ b/arch/arm/dts/rk3036-sdk.dts @@ -0,0 +1,46 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "rk3036.dtsi" + +/ { + model = "SDK-RK3036"; + compatible = "sdk,sdk-rk3036", "rockchip,rk3036"; + + chosen { + stdout-path = &uart2; + }; + + usb_control { + compatible = "rockchip,rk3036-usb-control"; + host_drv_gpio = <&gpio2 23 GPIO_ACTIVE_LOW>; + otg_drv_gpio = <&gpio0 26 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c1 { + status = "okay"; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + }; +}; + +&usb_host { + status = "okay"; +}; + +&usb_otg { + status = "okay"; + + dr_mode = "host"; +}; diff --git a/arch/arm/mach-rockchip/rk3036/Kconfig b/arch/arm/mach-rockchip/rk3036/Kconfig index d76d5e1..0fbc58e 100644 --- a/arch/arm/mach-rockchip/rk3036/Kconfig +++ b/arch/arm/mach-rockchip/rk3036/Kconfig @@ -1,3 +1,17 @@ if ROCKCHIP_RK3036
+config TARGET_EVB_RK3036 + bool "EVB_RK3036" + +config SYS_SOC + default "rockchip" + +config SYS_MALLOC_F_LEN + default 0x400 + +config ROCKCHIP_COMMON + bool "Support rk common fuction" + +source "board/evb_rk3036/evb_rk3036/Kconfig" + endif diff --git a/board/evb_rk3036/evb_rk3036/Kconfig b/board/evb_rk3036/evb_rk3036/Kconfig new file mode 100644 index 0000000..ae2a9eb --- /dev/null +++ b/board/evb_rk3036/evb_rk3036/Kconfig @@ -0,0 +1,15 @@ +if TARGET_EVB_RK3036 + +config SYS_BOARD + default "evb_rk3036" + +config SYS_VENDOR + default "evb_rk3036" + +config SYS_CONFIG_NAME + default "evb_rk3036" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/evb_rk3036/evb_rk3036/MAINTAINERS b/board/evb_rk3036/evb_rk3036/MAINTAINERS new file mode 100644 index 0000000..e69de29 diff --git a/board/evb_rk3036/evb_rk3036/Makefile b/board/evb_rk3036/evb_rk3036/Makefile new file mode 100644 index 0000000..0403836 --- /dev/null +++ b/board/evb_rk3036/evb_rk3036/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2015 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += evb_rk3036.o diff --git a/board/evb_rk3036/evb_rk3036/evb_rk3036.c b/board/evb_rk3036/evb_rk3036/evb_rk3036.c new file mode 100644 index 0000000..f5758b1 --- /dev/null +++ b/board/evb_rk3036/evb_rk3036/evb_rk3036.c @@ -0,0 +1,49 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <asm/arch/uart.h> +#include <asm/arch/sdram_rk3036.h> + +DECLARE_GLOBAL_DATA_PTR; + +void get_ddr_config(struct rk3036_ddr_config *config) +{ + /* K4B4G1646Q config */ + config->ddr_type = 3; + config->rank = 2; + config->cs0_row = 15; + config->cs1_row = 15; + + /* 8bank */ + config->bank = 3; + config->col = 10; + + /* 16bit bw */ + config->bw = 1; +} + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = sdram_size(); + + return 0; +} + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig new file mode 100644 index 0000000..2e915ff --- /dev/null +++ b/configs/evb-rk3036_defconfig @@ -0,0 +1,26 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_ROCKCHIP_RK3036=y +CONFIG_TARGET_EVB_RK3036=y +CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk" +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_ADDR=0x80000 +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CLK=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_RESET=y +CONFIG_LED=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_ROCKCHIP_DWMMC=y +CONFIG_ROCKCHIP_3036_PINCTRL=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_RAM=y +CONFIG_DM_MMC=y +CONFIG_USE_PRIVATE_LIBGCC=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_ERRNO_STR=y diff --git a/include/configs/evb_rk3036.h b/include/configs/evb_rk3036.h new file mode 100644 index 0000000..aa07889 --- /dev/null +++ b/include/configs/evb_rk3036.h @@ -0,0 +1,12 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/rk3036_common.h> + +#endif
On 18 November 2015 at 21:50, Simon Glass sjg@chromium.org wrote:
From: huang lin hl@rock-chips.com
This add some basic files required to allow the board to dispaly serial message and can run command(mmc info etc)
Signed-off-by: Lin Huang hl@rock-chips.com Acked-by: Simon Glass sjg@chromium.org Moved board Kconfig fragment from previous patch into this one to fix build error: Signed-off-by: Simon Glass sjg@chromium.org
Changes in v8:
- moved board Kconfig fragment from previous patch into this one
arch/arm/dts/Makefile | 3 +- arch/arm/dts/rk3036-sdk.dts | 46 ++++++++++++++++++++++++++++++ arch/arm/mach-rockchip/rk3036/Kconfig | 14 +++++++++ board/evb_rk3036/evb_rk3036/Kconfig | 15 ++++++++++ board/evb_rk3036/evb_rk3036/MAINTAINERS | 0 board/evb_rk3036/evb_rk3036/Makefile | 7 +++++ board/evb_rk3036/evb_rk3036/evb_rk3036.c | 49 ++++++++++++++++++++++++++++++++ configs/evb-rk3036_defconfig | 26 +++++++++++++++++ include/configs/evb_rk3036.h | 12 ++++++++ 9 files changed, 171 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3036-sdk.dts create mode 100644 board/evb_rk3036/evb_rk3036/Kconfig create mode 100644 board/evb_rk3036/evb_rk3036/MAINTAINERS create mode 100644 board/evb_rk3036/evb_rk3036/Makefile create mode 100644 board/evb_rk3036/evb_rk3036/evb_rk3036.c create mode 100644 configs/evb-rk3036_defconfig create mode 100644 include/configs/evb_rk3036.h
Applied to u-boot-rockchip, thanks!
From: Jeffy Chen jeffy.chen@rock-chips.com
Our chips may have different max spl size and spl header, so we need to add configs for that.
Signed-off-by: Jeffy Chen jeffy.chen@rock-chips.com Acked-by: Simon Glass sjg@chromium.org Dropped CONFIG_ROCKCHIP_MAX_SPL_SIZE from rk3288_common.h, Added $(if...) to tools/Makefile to fix widespread build breakage Signed-off-by: Simon Glass sjg@chromium.org
---
Changes in v8: - Drop CONFIG_ROCKCHIP_MAX_SPL_SIZE from rk3288_common.h, - Add $(if...) to tools/Makefile to fix widespread build breakage
arch/arm/mach-rockchip/Kconfig | 15 +++++++++++++++ arch/arm/mach-rockchip/rk3036/Kconfig | 6 ++++++ arch/arm/mach-rockchip/rk3288/Kconfig | 6 ++++++ tools/Makefile | 8 +++++++- tools/rkcommon.c | 2 +- tools/rkcommon.h | 1 - tools/rkimage.c | 2 +- tools/rksd.c | 4 ++-- tools/rkspi.c | 4 ++-- 9 files changed, 40 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 6b608db..4848018 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -17,6 +17,21 @@ config ROCKCHIP_RK3036 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
+config ROCKCHIP_SPL_HDR + string "Header of rockchip's spl loader" + help + Rockchip's bootrom requires the spl loader to start with a 4-bytes + header. The content of this header depends on the chip type. + +config ROCKCHIP_MAX_SPL_SIZE + hex "Max size of rockchip's spl loader" + help + Different chip may have different sram size. And if we want to jump + back to the bootrom after spl, we may need to reserve some sram space + for the bootrom. + The max spl loader size should be sram size minus reserved + size(if needed) + config SYS_MALLOC_F default y
diff --git a/arch/arm/mach-rockchip/rk3036/Kconfig b/arch/arm/mach-rockchip/rk3036/Kconfig index 0fbc58e..95fb2b9 100644 --- a/arch/arm/mach-rockchip/rk3036/Kconfig +++ b/arch/arm/mach-rockchip/rk3036/Kconfig @@ -9,6 +9,12 @@ config SYS_SOC config SYS_MALLOC_F_LEN default 0x400
+config ROCKCHIP_SPL_HDR + default "RK30" + +config ROCKCHIP_MAX_SPL_SIZE + default 0x1000 + config ROCKCHIP_COMMON bool "Support rk common fuction"
diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index d0a7276..3de3878 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -16,6 +16,12 @@ config TARGET_CHROMEBOOK_JERRY WiFi. It includes a Chrome OS EC (Cortex-M3) to provide access to the keyboard and battery functions.
+config ROCKCHIP_SPL_HDR + default "RK32" + +config ROCKCHIP_MAX_SPL_SIZE + default 0x8000 + config SYS_SOC default "rockchip"
diff --git a/tools/Makefile b/tools/Makefile index 9082bda..117b07e 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -64,7 +64,7 @@ RSA_OBJS-$(CONFIG_FIT_SIGNATURE) := $(addprefix lib/rsa/, \ rsa-sign.o rsa-verify.o rsa-checksum.o \ rsa-mod-exp.o)
-ROCKCHIP_OBS = lib/rc4.o rkcommon.o rkimage.o rksd.o +ROCKCHIP_OBS = $(if $(CONFIG_ARCH_ROCKCHIP),lib/rc4.o rkcommon.o rkimage.o rksd.o,)
# common objs for dumpimage and mkimage dumpimage-mkimage-objs := aisimage.o \ @@ -108,6 +108,12 @@ fit_check_sign-objs := $(dumpimage-mkimage-objs) fit_check_sign.o
# TODO(sjg@chromium.org): Is this correct on Mac OS?
+ifneq ($(CONFIG_ARCH_ROCKCHIP),) +HOST_EXTRACFLAGS += \ + -DCONFIG_ROCKCHIP_MAX_SPL_SIZE=$(CONFIG_ROCKCHIP_MAX_SPL_SIZE) \ + -DCONFIG_ROCKCHIP_SPL_HDR=""$(CONFIG_ROCKCHIP_SPL_HDR)"" +endif + ifneq ($(CONFIG_MX23)$(CONFIG_MX28),) # Add CONFIG_MXS into host CFLAGS, so we can check whether or not register # the mxsimage support within tools/mxsimage.c . diff --git a/tools/rkcommon.c b/tools/rkcommon.c index 4389622..18778aa 100644 --- a/tools/rkcommon.c +++ b/tools/rkcommon.c @@ -50,7 +50,7 @@ int rkcommon_set_header(void *buf, uint file_size) { struct header0_info *hdr;
- if (file_size > RK_MAX_CODE1_SIZE) + if (file_size > CONFIG_ROCKCHIP_MAX_SPL_SIZE) return -ENOSPC;
memset(buf, '\0', RK_CODE1_OFFSET * RK_BLK_SIZE); diff --git a/tools/rkcommon.h b/tools/rkcommon.h index 57fd726..39b1d52 100644 --- a/tools/rkcommon.h +++ b/tools/rkcommon.h @@ -11,7 +11,6 @@ enum { RK_BLK_SIZE = 512, RK_CODE1_OFFSET = 4, - RK_MAX_CODE1_SIZE = 32 << 10, };
/** diff --git a/tools/rkimage.c b/tools/rkimage.c index 7b292f4..73634e3 100644 --- a/tools/rkimage.c +++ b/tools/rkimage.c @@ -30,7 +30,7 @@ static void rkimage_print_header(const void *buf) static void rkimage_set_header(void *buf, struct stat *sbuf, int ifd, struct image_tool_params *params) { - memcpy(buf, "RK32", 4); + memcpy(buf, CONFIG_ROCKCHIP_SPL_HDR, 4); }
static int rkimage_extract_subimage(void *buf, struct image_tool_params *params) diff --git a/tools/rksd.c b/tools/rksd.c index a8dbe98..30b149d 100644 --- a/tools/rksd.c +++ b/tools/rksd.c @@ -50,7 +50,7 @@ static void rksd_set_header(void *buf, struct stat *sbuf, int ifd, size); }
- memcpy(buf + RKSD_SPL_HDR_START, "RK32", 4); + memcpy(buf + RKSD_SPL_HDR_START, CONFIG_ROCKCHIP_SPL_HDR, 4); }
static int rksd_extract_subimage(void *buf, struct image_tool_params *params) @@ -72,7 +72,7 @@ static int rksd_vrec_header(struct image_tool_params *params, { int pad_size;
- pad_size = RKSD_SPL_HDR_START + RK_MAX_CODE1_SIZE; + pad_size = RKSD_SPL_HDR_START + CONFIG_ROCKCHIP_MAX_SPL_SIZE; debug("pad_size %x\n", pad_size);
return pad_size - params->file_size; diff --git a/tools/rkspi.c b/tools/rkspi.c index a3c4c73..13cc593 100644 --- a/tools/rkspi.c +++ b/tools/rkspi.c @@ -53,7 +53,7 @@ static void rkspi_set_header(void *buf, struct stat *sbuf, int ifd, size); }
- memcpy(buf + RKSPI_SPL_HDR_START, "RK32", 4); + memcpy(buf + RKSPI_SPL_HDR_START, CONFIG_ROCKCHIP_SPL_HDR, 4);
/* * Spread the image out so we only use the first 2KB of each 4KB @@ -89,7 +89,7 @@ static int rkspi_vrec_header(struct image_tool_params *params, { int pad_size;
- pad_size = (RK_MAX_CODE1_SIZE + 0x7ff) / 0x800 * 0x800; + pad_size = (CONFIG_ROCKCHIP_MAX_SPL_SIZE + 0x7ff) / 0x800 * 0x800; params->orig_file_size = pad_size;
/* We will double the image size due to the SPI format */
On 18 November 2015 at 21:50, Simon Glass sjg@chromium.org wrote:
From: Jeffy Chen jeffy.chen@rock-chips.com
Our chips may have different max spl size and spl header, so we need to add configs for that.
Signed-off-by: Jeffy Chen jeffy.chen@rock-chips.com Acked-by: Simon Glass sjg@chromium.org Dropped CONFIG_ROCKCHIP_MAX_SPL_SIZE from rk3288_common.h, Added $(if...) to tools/Makefile to fix widespread build breakage Signed-off-by: Simon Glass sjg@chromium.org
Changes in v8:
- Drop CONFIG_ROCKCHIP_MAX_SPL_SIZE from rk3288_common.h,
- Add $(if...) to tools/Makefile to fix widespread build breakage
arch/arm/mach-rockchip/Kconfig | 15 +++++++++++++++ arch/arm/mach-rockchip/rk3036/Kconfig | 6 ++++++ arch/arm/mach-rockchip/rk3288/Kconfig | 6 ++++++ tools/Makefile | 8 +++++++- tools/rkcommon.c | 2 +- tools/rkcommon.h | 1 - tools/rkimage.c | 2 +- tools/rksd.c | 4 ++-- tools/rkspi.c | 4 ++-- 9 files changed, 40 insertions(+), 8 deletions(-)
Applied to u-boot-rockchip, thanks!
This will need to be done a different way - I only just realised this. I'll reply on the cover letter.
- Simon
On 18 November 2015 at 21:50, Simon Glass sjg@chromium.org wrote:
From: huang lin hl@rock-chips.com
rk3036 only 4K size SRAM for SPL, so only support timer, uart, sdram driver in SPL stage, when finish initial sdram, back to bootrom.And in rk3036 sdmmc and debug uart use same iomux, so if you want to boot from sdmmc, you must disable debug uart.
Signed-off-by: Lin Huang hl@rock-chips.com Acked-by: Simon Glass sjg@chromium.org Fixed build error for chromebook_jerry, firefly-rk3288: Signed-off-by: Simon Glass sjg@chromium.org
Changes in v8:
- Fix build error for chromebook_jerry, firefly-rk3288
arch/arm/mach-rockchip/Kconfig | 10 ++- arch/arm/mach-rockchip/Makefile | 4 +- arch/arm/mach-rockchip/board.c | 1 + arch/arm/mach-rockchip/rk3036-board-spl.c | 55 +++++++++++++ arch/arm/mach-rockchip/rk3036/Kconfig | 3 + arch/arm/mach-rockchip/rk3036/Makefile | 1 + arch/arm/mach-rockchip/rk3036/save_boot_param.S | 32 ++++++++ include/configs/rk3036_common.h | 103 ++++++++++++++++++++++++ 8 files changed, 207 insertions(+), 2 deletions(-) create mode 100644 arch/arm/mach-rockchip/rk3036-board-spl.c create mode 100644 arch/arm/mach-rockchip/rk3036/Kconfig create mode 100644 arch/arm/mach-rockchip/rk3036/save_boot_param.S create mode 100644 include/configs/rk3036_common.h
Applied to u-boot-rockchip, thanks!
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Simon Glass