[U-Boot] [PATCH 1/3] mx35: Remove duplicate GPIO3_BASE_ADDR

newer
[U-Boot] [PATCH 1/7] mx35: Move...

older
[U-Boot] [PATCH] arm: trats: Turn...

Benoît Thébaudeau

14 Aug 2012 14 Aug '12

11:03 p.m.

Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de --- .../arch/arm/include/asm/arch-mx35/imx-regs.h | 1 - 1 file changed, 1 deletion(-)

diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/imx-regs.h u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/imx-regs.h index 3146006..5cb7656 100644 --- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/imx-regs.h +++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/imx-regs.h @@ -72,7 +72,6 @@ #define MMC_SDHC2_BASE_ADDR 0x53FB8000 #define MMC_SDHC3_BASE_ADDR 0x53FBC000 #define IPU_CTRL_BASE_ADDR 0x53FC0000 -#define GPIO3_BASE_ADDR 0x53FA4000 #define GPIO1_BASE_ADDR 0x53FCC000 #define GPIO2_BASE_ADDR 0x53FD0000 #define SDMA_BASE_ADDR 0x53FD4000

Show replies by date

Benoît Thébaudeau

14 Aug 14 Aug

11:03 p.m.

New subject: [U-Boot] [PATCH 2/3] mx35: Define MAX and AIPS registers

Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de --- .../arch/arm/cpu/arm1136/mx35/asm-offsets.c | 33 ++++++++++++- .../arch/arm/include/asm/arch-mx35/imx-regs.h | 52 ++++++++++++++++++++ 2 files changed, 84 insertions(+), 1 deletion(-)

diff --git u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/asm-offsets.c u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/asm-offsets.c index d2678e2..26e14da 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/asm-offsets.c +++ u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/asm-offsets.c @@ -22,7 +22,6 @@

int main(void) { - /* Round up to make sure size gives nice stack alignment */ DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr)); DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0)); @@ -38,6 +37,38 @@ int main(void) DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0)); DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1)); DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2)); + DEFINE(CLKCTL_CGR3, offsetof(struct ccm_regs, cgr3)); + + /* Multi-Layer AHB Crossbar Switch */ + DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0)); + DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0)); + DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1)); + DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1)); + DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2)); + DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2)); + DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3)); + DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3)); + DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4)); + DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4)); + DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0)); + DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1)); + DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2)); + DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3)); + DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4)); + DEFINE(MAX_MGPCR5, offsetof(struct max_regs, mgpcr5)); + + /* AHB <-> IP-Bus Interface */ + DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7)); + DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15)); + DEFINE(AIPS_PACR_0_7, offsetof(struct aips_regs, pacr_0_7)); + DEFINE(AIPS_PACR_8_15, offsetof(struct aips_regs, pacr_8_15)); + DEFINE(AIPS_PACR_16_23, offsetof(struct aips_regs, pacr_16_23)); + DEFINE(AIPS_PACR_24_31, offsetof(struct aips_regs, pacr_24_31)); + DEFINE(AIPS_OPACR_0_7, offsetof(struct aips_regs, opacr_0_7)); + DEFINE(AIPS_OPACR_8_15, offsetof(struct aips_regs, opacr_8_15)); + DEFINE(AIPS_OPACR_16_23, offsetof(struct aips_regs, opacr_16_23)); + DEFINE(AIPS_OPACR_24_31, offsetof(struct aips_regs, opacr_24_31)); + DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39));

return 0; } diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/imx-regs.h u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/imx-regs.h index 5cb7656..f69f690 100644 --- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/imx-regs.h +++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/imx-regs.h @@ -338,6 +338,58 @@ struct esdc_regs { #define ESDC_MISC_DDR_EN (1 << 8) #define ESDC_MISC_DDR2_EN (1 << 9)

+/* Multi-Layer AHB Crossbar Switch (MAX) registers */ +struct max_regs { + u32 mpr0; + u32 pad00[3]; + u32 sgpcr0; + u32 pad01[59]; + u32 mpr1; + u32 pad02[3]; + u32 sgpcr1; + u32 pad03[59]; + u32 mpr2; + u32 pad04[3]; + u32 sgpcr2; + u32 pad05[59]; + u32 mpr3; + u32 pad06[3]; + u32 sgpcr3; + u32 pad07[59]; + u32 mpr4; + u32 pad08[3]; + u32 sgpcr4; + u32 pad09[251]; + u32 mgpcr0; + u32 pad10[63]; + u32 mgpcr1; + u32 pad11[63]; + u32 mgpcr2; + u32 pad12[63]; + u32 mgpcr3; + u32 pad13[63]; + u32 mgpcr4; + u32 pad14[63]; + u32 mgpcr5; +}; + +/* AHB <-> IP-Bus Interface (AIPS) */ +struct aips_regs { + u32 mpr_0_7; + u32 mpr_8_15; + u32 pad0[6]; + u32 pacr_0_7; + u32 pacr_8_15; + u32 pacr_16_23; + u32 pacr_24_31; + u32 pad1[4]; + u32 opacr_0_7; + u32 opacr_8_15; + u32 opacr_16_23; + u32 opacr_24_31; + u32 opacr_32_39; +}; + /* * NFMS bit in RCSR register for pagesize of nandflash */

Stefano Babic

30 Sep 30 Sep

2:56 p.m.

New subject: [U-Boot] [PATCH 2/3] mx35: Define MAX and AIPS registers

On 14/08/2012 23:03, Benoît Thébaudeau wrote:

...

Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de

.../arch/arm/cpu/arm1136/mx35/asm-offsets.c | 33 ++++++++++++-

Applied to u-boot-imx, next branch, thanks.

Best regards, Stefano Babic

-- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de =====================================================================

Benoît Thébaudeau

14 Aug 14 Aug

11:04 p.m.

New subject: [U-Boot] [PATCH 3/3] mx35: Clean up lowlevel_init

Clean up mx35 lowlevel_init: - Indent with tabs. - Fix comments. - Use defined values instead of literal constants. - Use defined macros instead of duplicating code.

Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de --- .../arm/include/asm/arch-mx35/lowlevel_macro.S | 153 ++++++++------------ .../board/CarMediaLab/flea3/lowlevel_init.S | 19 +-- .../board/freescale/mx35pdk/lowlevel_init.S | 119 +-------------- .../board/freescale/mx35pdk/mx35pdk.h | 14 +- 4 files changed, 78 insertions(+), 227 deletions(-)

diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/lowlevel_macro.S u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/lowlevel_macro.S index 05aa951..9d7c133 100644 --- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/lowlevel_macro.S +++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/lowlevel_macro.S @@ -19,122 +19,93 @@ * MA 02111-1307 USA */

+#include <asm/arch/imx-regs.h> +#include <generated/asm-offsets.h> +#include <asm/macro.h> + /* * AIPS setup - Only setup MPROTx registers. * The PACR default values are good. */ .macro init_aips - /* - * Set all MPROTx to be non-bufferable, trusted for R/W, - * not forced to user-mode. - */ - ldr r0, =AIPS1_BASE_ADDR - ldr r1, =AIPS_MPR_CONFIG - str r1, [r0, #0x00] - str r1, [r0, #0x04] - ldr r0, =AIPS2_BASE_ADDR - str r1, [r0, #0x00] - str r1, [r0, #0x04] + ldr r0, =AIPS1_BASE_ADDR + ldr r1, =AIPS_MPR_CONFIG + str r1, [r0, #AIPS_MPR_0_7] + str r1, [r0, #AIPS_MPR_8_15] + ldr r2, =AIPS2_BASE_ADDR + str r1, [r2, #AIPS_MPR_0_7] + str r1, [r2, #AIPS_MPR_8_15]

- /* - * Clear the on and off peripheral modules Supervisor Protect bit - * for SDMA to access them. Did not change the AIPS control registers - * (offset 0x20) access type - */ - ldr r0, =AIPS1_BASE_ADDR - ldr r1, =AIPS_OPACR_CONFIG - str r1, [r0, #0x40] - str r1, [r0, #0x44] - str r1, [r0, #0x48] - str r1, [r0, #0x4C] - str r1, [r0, #0x50] - ldr r0, =AIPS2_BASE_ADDR - str r1, [r0, #0x40] - str r1, [r0, #0x44] - str r1, [r0, #0x48] - str r1, [r0, #0x4C] - str r1, [r0, #0x50] + /* Did not change the AIPS control registers access type. */ + ldr r1, =AIPS_OPACR_CONFIG + str r1, [r0, #AIPS_OPACR_0_7] + str r1, [r0, #AIPS_OPACR_8_15] + str r1, [r0, #AIPS_OPACR_16_23] + str r1, [r0, #AIPS_OPACR_24_31] + str r1, [r0, #AIPS_OPACR_32_39] + str r1, [r2, #AIPS_OPACR_0_7] + str r1, [r2, #AIPS_OPACR_8_15] + str r1, [r2, #AIPS_OPACR_16_23] + str r1, [r2, #AIPS_OPACR_24_31] + str r1, [r2, #AIPS_OPACR_32_39] .endm

/* MAX (Multi-Layer AHB Crossbar Switch) setup */ .macro init_max - ldr r0, =MAX_BASE_ADDR - /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ - ldr r1, =MAX_MPR_CONFIG - str r1, [r0, #0x000] /* for S0 */ - str r1, [r0, #0x100] /* for S1 */ - str r1, [r0, #0x200] /* for S2 */ - str r1, [r0, #0x300] /* for S3 */ - str r1, [r0, #0x400] /* for S4 */ - /* SGPCR - always park on last master */ - ldr r1, =MAX_SGPCR_CONFIG - str r1, [r0, #0x010] /* for S0 */ - str r1, [r0, #0x110] /* for S1 */ - str r1, [r0, #0x210] /* for S2 */ - str r1, [r0, #0x310] /* for S3 */ - str r1, [r0, #0x410] /* for S4 */ - /* MGPCR - restore default values */ - ldr r1, =MAX_MGPCR_CONFIG - str r1, [r0, #0x800] /* for M0 */ - str r1, [r0, #0x900] /* for M1 */ - str r1, [r0, #0xA00] /* for M2 */ - str r1, [r0, #0xB00] /* for M3 */ - str r1, [r0, #0xC00] /* for M4 */ - str r1, [r0, #0xD00] /* for M5 */ + ldr r0, =MAX_BASE_ADDR + ldr r1, =MAX_MPR_CONFIG + str r1, [r0, #MAX_MPR0] /* for S0 */ + str r1, [r0, #MAX_MPR1] /* for S1 */ + str r1, [r0, #MAX_MPR2] /* for S2 */ + str r1, [r0, #MAX_MPR3] /* for S3 */ + str r1, [r0, #MAX_MPR4] /* for S4 */ + ldr r1, =MAX_SGPCR_CONFIG + str r1, [r0, #MAX_SGPCR0] /* for S0 */ + str r1, [r0, #MAX_SGPCR1] /* for S1 */ + str r1, [r0, #MAX_SGPCR2] /* for S2 */ + str r1, [r0, #MAX_SGPCR3] /* for S3 */ + str r1, [r0, #MAX_SGPCR4] /* for S4 */ + ldr r1, =MAX_MGPCR_CONFIG + str r1, [r0, #MAX_MGPCR0] /* for M0 */ + str r1, [r0, #MAX_MGPCR1] /* for M1 */ + str r1, [r0, #MAX_MGPCR2] /* for M2 */ + str r1, [r0, #MAX_MGPCR3] /* for M3 */ + str r1, [r0, #MAX_MGPCR4] /* for M4 */ + str r1, [r0, #MAX_MGPCR5] /* for M5 */ .endm

/* M3IF setup */ .macro init_m3if - /* Configure M3IF registers */ - ldr r1, =M3IF_BASE_ADDR - /* - * M3IF Control Register (M3IFCTL) - * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 - * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000 - * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000 - * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 - * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 - * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 - * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 - * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 - * ------------ - * 0x00000040 - */ - ldr r0, =M3IF_CONFIG - str r0, [r1] /* M3IF control reg */ + /* M3IF Control Register (M3IFCTL) */ + write32 M3IF_BASE_ADDR, M3IFCTL_CONFIG .endm

.macro core_init - mrc 15, 0, r1, c1, c0, 0 + mrc p15, 0, r1, c1, c0, 0

- mrc 15, 0, r0, c1, c0, 1 - orr r0, r0, #7 - mcr 15, 0, r0, c1, c0, 1 - orr r1, r1, #(1<<11) + /* Set branch prediction enable */ + mrc p15, 0, r0, c1, c0, 1 + orr r0, r0, #7 + mcr p15, 0, r0, c1, c0, 1 + orr r1, r1, #1 << 11

/* Set unaligned access enable */ - orr r1, r1, #(1<<22) + orr r1, r1, #1 << 22

/* Set low int latency enable */ - orr r1, r1, #(1<<21) + orr r1, r1, #1 << 21

- mcr 15, 0, r1, c1, c0, 0 + mcr p15, 0, r1, c1, c0, 0

- mov r0, #0 + mov r0, #0

- /* Set branch prediction enable */ - mcr 15, 0, r0, c15, c2, 4 + mcr p15, 0, r0, c15, c2, 4

- mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */ - mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */ - mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */ + mcr p15, 0, r0, c7, c7, 0 /* Invalidate I cache and D cache */ + mcr p15, 0, r0, c8, c7, 0 /* Invalidate TLBs */ + mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffer */

- /* - * initializes very early AIPS - * Then it also initializes Multi-Layer AHB Crossbar Switch, - * M3IF - * Also setup the Peripheral Port Remap register inside the core - */ - ldr r0, =0x40000015 /* start from AIPS 2GB region */ - mcr p15, 0, r0, c15, c2, 4 + /* Setup the Peripheral Port Memory Remap Register */ + ldr r0, =0x40000015 /* Start from AIPS 2-GB region */ + mcr p15, 0, r0, c15, c2, 4 .endm diff --git u-boot-4d3c95f.orig/board/CarMediaLab/flea3/lowlevel_init.S u-boot-4d3c95f/board/CarMediaLab/flea3/lowlevel_init.S index 2f42fc9..e7e5cd7 100644 --- u-boot-4d3c95f.orig/board/CarMediaLab/flea3/lowlevel_init.S +++ u-boot-4d3c95f/board/CarMediaLab/flea3/lowlevel_init.S @@ -22,9 +22,6 @@ */

#include <config.h> -#include <asm-offsets.h> -#include <asm/arch/imx-regs.h> -#include <generated/asm-offsets.h>

/* * Configuration for the flea3 board. @@ -46,19 +43,17 @@ /* * M3IF Control Register (M3IFCTL) * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 - * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000 - * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000 - * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 - * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 - * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 + * MRRP[1] = L2CC1 not on priority list (0 << 1) = 0x00000000 + * MRRP[2] = MBX not on priority list (0 << 2) = 0x00000000 + * MRRP[3] = MAX1 not on priority list (0 << 3) = 0x00000000 + * MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000 + * MRRP[5] = MPEG4 not on priority list (0 << 5) = 0x00000000 * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 - * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 + * MRRP[7] = IPU2 not on priority list (0 << 7) = 0x00000000 * ------------ * 0x00000040 */ -#define M3IF_CONFIG 0x00000040 - -#define CCM_PDR0_CONFIG 0x00801000 +#define M3IFCTL_CONFIG 0x00000040

/* * includes MX35 utility macros diff --git u-boot-4d3c95f.orig/board/freescale/mx35pdk/lowlevel_init.S u-boot-4d3c95f/board/freescale/mx35pdk/lowlevel_init.S index 698c4cf..75bb958 100644 --- u-boot-4d3c95f.orig/board/freescale/mx35pdk/lowlevel_init.S +++ u-boot-4d3c95f/board/freescale/mx35pdk/lowlevel_init.S @@ -23,6 +23,7 @@ #include <asm/arch/imx-regs.h> #include <generated/asm-offsets.h> #include "mx35pdk.h" +#include <asm/arch/lowlevel_macro.S>

/* * return soc version @@ -40,91 +41,6 @@ addne \ret, \ret, #0x10 .endm

-/* - * AIPS setup - Only setup MPROTx registers. - * The PACR default values are good. - */ -.macro init_aips - /* - * Set all MPROTx to be non-bufferable, trusted for R/W, - * not forced to user-mode. - */ - ldr r0, =AIPS1_BASE_ADDR - ldr r1, =AIPS_MPR_CONFIG - str r1, [r0, #0x00] - str r1, [r0, #0x04] - ldr r0, =AIPS2_BASE_ADDR - str r1, [r0, #0x00] - str r1, [r0, #0x04] - - /* - * Clear the on and off peripheral modules Supervisor Protect bit - * for SDMA to access them. Did not change the AIPS control registers - * (offset 0x20) access type - */ - ldr r0, =AIPS1_BASE_ADDR - ldr r1, =AIPS_OPACR_CONFIG - str r1, [r0, #0x40] - str r1, [r0, #0x44] - str r1, [r0, #0x48] - str r1, [r0, #0x4C] - str r1, [r0, #0x50] - ldr r0, =AIPS2_BASE_ADDR - str r1, [r0, #0x40] - str r1, [r0, #0x44] - str r1, [r0, #0x48] - str r1, [r0, #0x4C] - str r1, [r0, #0x50] -.endm - -/* MAX (Multi-Layer AHB Crossbar Switch) setup */ -.macro init_max - ldr r0, =MAX_BASE_ADDR - /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ - ldr r1, =MAX_MPR_CONFIG - str r1, [r0, #0x000] /* for S0 */ - str r1, [r0, #0x100] /* for S1 */ - str r1, [r0, #0x200] /* for S2 */ - str r1, [r0, #0x300] /* for S3 */ - str r1, [r0, #0x400] /* for S4 */ - /* SGPCR - always park on last master */ - ldr r1, =MAX_SGPCR_CONFIG - str r1, [r0, #0x010] /* for S0 */ - str r1, [r0, #0x110] /* for S1 */ - str r1, [r0, #0x210] /* for S2 */ - str r1, [r0, #0x310] /* for S3 */ - str r1, [r0, #0x410] /* for S4 */ - /* MGPCR - restore default values */ - ldr r1, =MAX_MGPCR_CONFIG - str r1, [r0, #0x800] /* for M0 */ - str r1, [r0, #0x900] /* for M1 */ - str r1, [r0, #0xA00] /* for M2 */ - str r1, [r0, #0xB00] /* for M3 */ - str r1, [r0, #0xC00] /* for M4 */ - str r1, [r0, #0xD00] /* for M5 */ -.endm - -/* M3IF setup */ -.macro init_m3if - /* Configure M3IF registers */ - ldr r1, =M3IF_BASE_ADDR - /* - * M3IF Control Register (M3IFCTL) - * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 - * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000 - * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000 - * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 - * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 - * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 - * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 - * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 - * ------------ - * 0x00000040 - */ - ldr r0, =M3IF_CONFIG - str r0, [r1] /* M3IF control reg */ -.endm - /* CPLD on CS5 setup */ .macro init_debug_board ldr r0, =DBG_BASE_ADDR @@ -210,38 +126,7 @@ lowlevel_init: mov r10, lr

- mrc 15, 0, r1, c1, c0, 0 - - mrc 15, 0, r0, c1, c0, 1 - orr r0, r0, #7 - mcr 15, 0, r0, c1, c0, 1 - orr r1, r1, #(1<<11) - - /* Set unaligned access enable */ - orr r1, r1, #(1<<22) - - /* Set low int latency enable */ - orr r1, r1, #(1<<21) - - mcr 15, 0, r1, c1, c0, 0 - - mov r0, #0 - - /* Set branch prediction enable */ - mcr 15, 0, r0, c15, c2, 4 - - mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */ - mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */ - mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */ - - /* - * initializes very early AIPS - * Then it also initializes Multi-Layer AHB Crossbar Switch, - * M3IF - * Also setup the Peripheral Port Remap register inside the core - */ - ldr r0, =0x40000015 /* start from AIPS 2GB region */ - mcr p15, 0, r0, c15, c2, 4 + core_init

init_aips

diff --git u-boot-4d3c95f.orig/board/freescale/mx35pdk/mx35pdk.h u-boot-4d3c95f/board/freescale/mx35pdk/mx35pdk.h index 6aeb218..9e44f1f 100644 --- u-boot-4d3c95f.orig/board/freescale/mx35pdk/mx35pdk.h +++ u-boot-4d3c95f/board/freescale/mx35pdk/mx35pdk.h @@ -39,17 +39,17 @@ /* * M3IF Control Register (M3IFCTL) * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 - * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000 - * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000 - * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 - * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 - * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 + * MRRP[1] = L2CC1 not on priority list (0 << 1) = 0x00000000 + * MRRP[2] = MBX not on priority list (0 << 2) = 0x00000000 + * MRRP[3] = MAX1 not on priority list (0 << 3) = 0x00000000 + * MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000 + * MRRP[5] = MPEG4 not on priority list (0 << 5) = 0x00000000 * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 - * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 + * MRRP[7] = IPU2 not on priority list (0 << 7) = 0x00000000 * ------------ * 0x00000040 */ -#define M3IF_CONFIG 0x00000040 +#define M3IFCTL_CONFIG 0x00000040

#define DBG_BASE_ADDR WEIM_CTRL_CS5 #define DBG_CSCR_U_CONFIG 0x0000D843

Benoît Thébaudeau

20 Aug 20 Aug

2:09 p.m.

New subject: [U-Boot] [PATCH 3/3] mx35: Clean up lowlevel_init

Hi Stefano,

...

Clean up mx35 lowlevel_init:

Indent with tabs.

Fix comments.

Use defined values instead of literal constants.

Use defined macros instead of duplicating code.

Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de

.../arm/include/asm/arch-mx35/lowlevel_macro.S | 153 ++++++++------------ .../board/CarMediaLab/flea3/lowlevel_init.S | 19 +-- .../board/freescale/mx35pdk/lowlevel_init.S | 119 +-------------- .../board/freescale/mx35pdk/mx35pdk.h | 14 +- 4 files changed, 78 insertions(+), 227 deletions(-)

diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/lowlevel_macro.S u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/lowlevel_macro.S index 05aa951..9d7c133 100644

u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/lowlevel_macro.S +++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/lowlevel_macro.S @@ -19,122 +19,93 @@

MA 02111-1307 USA

*/

+#include <asm/arch/imx-regs.h> +#include <generated/asm-offsets.h> +#include <asm/macro.h>

/*

AIPS setup - Only setup MPROTx registers.

The PACR default values are good.

*/ .macro init_aips
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
* not forced to user-mode.
*/
ldr r0, =AIPS1_BASE_ADDR

ldr r1, =AIPS_MPR_CONFIG

str r1, [r0, #0x00]

str r1, [r0, #0x04]

ldr r0, =AIPS2_BASE_ADDR

str r1, [r0, #0x00]

str r1, [r0, #0x04]
ldr r0, =AIPS1_BASE_ADDR

ldr r1, =AIPS_MPR_CONFIG

str r1, [r0, #AIPS_MPR_0_7]

str r1, [r0, #AIPS_MPR_8_15]

ldr r2, =AIPS2_BASE_ADDR

str r1, [r2, #AIPS_MPR_0_7]

str r1, [r2, #AIPS_MPR_8_15]
/*
* Clear the on and off peripheral modules Supervisor Protect bit
* for SDMA to access them. Did not change the AIPS control
registers
* (offset 0x20) access type
*/
ldr r0, =AIPS1_BASE_ADDR

ldr r1, =AIPS_OPACR_CONFIG

str r1, [r0, #0x40]

str r1, [r0, #0x44]

str r1, [r0, #0x48]

str r1, [r0, #0x4C]

str r1, [r0, #0x50]

ldr r0, =AIPS2_BASE_ADDR

str r1, [r0, #0x40]

str r1, [r0, #0x44]

str r1, [r0, #0x48]

str r1, [r0, #0x4C]

str r1, [r0, #0x50]
/* Did not change the AIPS control registers access type. */

ldr r1, =AIPS_OPACR_CONFIG

str r1, [r0, #AIPS_OPACR_0_7]

str r1, [r0, #AIPS_OPACR_8_15]

str r1, [r0, #AIPS_OPACR_16_23]

str r1, [r0, #AIPS_OPACR_24_31]

str r1, [r0, #AIPS_OPACR_32_39]

str r1, [r2, #AIPS_OPACR_0_7]

str r1, [r2, #AIPS_OPACR_8_15]

str r1, [r2, #AIPS_OPACR_16_23]

str r1, [r2, #AIPS_OPACR_24_31]

str r1, [r2, #AIPS_OPACR_32_39]

.endm

/* MAX (Multi-Layer AHB Crossbar Switch) setup */ .macro init_max

ldr r0, =MAX_BASE_ADDR

/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */

ldr r1, =MAX_MPR_CONFIG

str r1, [r0, #0x000] /* for S0 */

str r1, [r0, #0x100] /* for S1 */

str r1, [r0, #0x200] /* for S2 */

str r1, [r0, #0x300] /* for S3 */

str r1, [r0, #0x400] /* for S4 */

/* SGPCR - always park on last master */

ldr r1, =MAX_SGPCR_CONFIG

str r1, [r0, #0x010] /* for S0 */

str r1, [r0, #0x110] /* for S1 */

str r1, [r0, #0x210] /* for S2 */

str r1, [r0, #0x310] /* for S3 */

str r1, [r0, #0x410] /* for S4 */

/* MGPCR - restore default values */

ldr r1, =MAX_MGPCR_CONFIG

str r1, [r0, #0x800] /* for M0 */

str r1, [r0, #0x900] /* for M1 */

str r1, [r0, #0xA00] /* for M2 */

str r1, [r0, #0xB00] /* for M3 */

str r1, [r0, #0xC00] /* for M4 */

str r1, [r0, #0xD00] /* for M5 */

ldr r0, =MAX_BASE_ADDR

ldr r1, =MAX_MPR_CONFIG

str r1, [r0, #MAX_MPR0] /* for S0 */

str r1, [r0, #MAX_MPR1] /* for S1 */

str r1, [r0, #MAX_MPR2] /* for S2 */

str r1, [r0, #MAX_MPR3] /* for S3 */

str r1, [r0, #MAX_MPR4] /* for S4 */

ldr r1, =MAX_SGPCR_CONFIG

str r1, [r0, #MAX_SGPCR0] /* for S0 */

str r1, [r0, #MAX_SGPCR1] /* for S1 */

str r1, [r0, #MAX_SGPCR2] /* for S2 */

str r1, [r0, #MAX_SGPCR3] /* for S3 */

str r1, [r0, #MAX_SGPCR4] /* for S4 */

ldr r1, =MAX_MGPCR_CONFIG

str r1, [r0, #MAX_MGPCR0] /* for M0 */

str r1, [r0, #MAX_MGPCR1] /* for M1 */

str r1, [r0, #MAX_MGPCR2] /* for M2 */

str r1, [r0, #MAX_MGPCR3] /* for M3 */

str r1, [r0, #MAX_MGPCR4] /* for M4 */

str r1, [r0, #MAX_MGPCR5] /* for M5 */

.endm

/* M3IF setup */ .macro init_m3if
/* Configure M3IF registers */

ldr r1, =M3IF_BASE_ADDR

/*

M3IF Control Register (M3IFCTL)

MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000

MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000

MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000

MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000

MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000

MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000

MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040

MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
				------------
				  0x00000040
*/

ldr r0, =M3IF_CONFIG

str r0, [r1] /* M3IF control reg */
/* M3IF Control Register (M3IFCTL) */

write32 M3IF_BASE_ADDR, M3IFCTL_CONFIG

.endm

.macro core_init

mrc 15, 0, r1, c1, c0, 0

mrc p15, 0, r1, c1, c0, 0

mrc 15, 0, r0, c1, c0, 1

orr r0, r0, #7

mcr 15, 0, r0, c1, c0, 1

orr r1, r1, #(1<<11)

/* Set branch prediction enable */

mrc p15, 0, r0, c1, c0, 1

orr r0, r0, #7

mcr p15, 0, r0, c1, c0, 1

orr r1, r1, #1 << 11

/* Set unaligned access enable */

orr r1, r1, #(1<<22)

orr r1, r1, #1 << 22

/* Set low int latency enable */

orr r1, r1, #(1<<21)

orr r1, r1, #1 << 21

mcr 15, 0, r1, c1, c0, 0

mcr p15, 0, r1, c1, c0, 0

mov r0, #0

mov r0, #0

/* Set branch prediction enable */

mcr 15, 0, r0, c15, c2, 4

mcr p15, 0, r0, c15, c2, 4

mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache

*/

mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */

mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */

mcr p15, 0, r0, c7, c7, 0 /* Invalidate I cache and D cache */

mcr p15, 0, r0, c8, c7, 0 /* Invalidate TLBs */

mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffer */
/*
* initializes very early AIPS
* Then it also initializes Multi-Layer AHB Crossbar Switch,
* M3IF
* Also setup the Peripheral Port Remap register inside the core
*/
ldr r0, =0x40000015 /* start from AIPS 2GB region */

mcr p15, 0, r0, c15, c2, 4
/* Setup the Peripheral Port Memory Remap Register */

ldr r0, =0x40000015 /* Start from AIPS 2-GB region */

mcr p15, 0, r0, c15, c2, 4

.endm diff --git u-boot-4d3c95f.orig/board/CarMediaLab/flea3/lowlevel_init.S u-boot-4d3c95f/board/CarMediaLab/flea3/lowlevel_init.S index 2f42fc9..e7e5cd7 100644 --- u-boot-4d3c95f.orig/board/CarMediaLab/flea3/lowlevel_init.S +++ u-boot-4d3c95f/board/CarMediaLab/flea3/lowlevel_init.S @@ -22,9 +22,6 @@ */

#include <config.h> -#include <asm-offsets.h> -#include <asm/arch/imx-regs.h> -#include <generated/asm-offsets.h>

/*

Configuration for the flea3 board.

@@ -46,19 +43,17 @@ /*

M3IF Control Register (M3IFCTL)

MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000

MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000

MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000

MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000

MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000

MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000

MRRP[1] = L2CC1 not on priority list (0 << 1) = 0x00000000

MRRP[2] = MBX not on priority list (0 << 2) = 0x00000000

MRRP[3] = MAX1 not on priority list (0 << 3) = 0x00000000

MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000

MRRP[5] = MPEG4 not on priority list (0 << 5) = 0x00000000

MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040

MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
MRRP[7] = IPU2 not on priority list (0 << 7) = 0x00000000
                                          ------------
                                            0x00000040
*/
-#define M3IF_CONFIG 0x00000040

-#define CCM_PDR0_CONFIG 0x00801000 +#define M3IFCTL_CONFIG 0x00000040

/*

includes MX35 utility macros

diff --git u-boot-4d3c95f.orig/board/freescale/mx35pdk/lowlevel_init.S u-boot-4d3c95f/board/freescale/mx35pdk/lowlevel_init.S index 698c4cf..75bb958 100644 --- u-boot-4d3c95f.orig/board/freescale/mx35pdk/lowlevel_init.S +++ u-boot-4d3c95f/board/freescale/mx35pdk/lowlevel_init.S @@ -23,6 +23,7 @@ #include <asm/arch/imx-regs.h> #include <generated/asm-offsets.h> #include "mx35pdk.h" +#include <asm/arch/lowlevel_macro.S>

/*

return soc version

@@ -40,91 +41,6 @@ addne \ret, \ret, #0x10 .endm

-/*

AIPS setup - Only setup MPROTx registers.

The PACR default values are good.

*/

-.macro init_aips
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
* not forced to user-mode.
*/
ldr r0, =AIPS1_BASE_ADDR

ldr r1, =AIPS_MPR_CONFIG

str r1, [r0, #0x00]

str r1, [r0, #0x04]

ldr r0, =AIPS2_BASE_ADDR

str r1, [r0, #0x00]

str r1, [r0, #0x04]

/*
* Clear the on and off peripheral modules Supervisor Protect bit
* for SDMA to access them. Did not change the AIPS control
registers
* (offset 0x20) access type
*/
ldr r0, =AIPS1_BASE_ADDR

ldr r1, =AIPS_OPACR_CONFIG

str r1, [r0, #0x40]

str r1, [r0, #0x44]

str r1, [r0, #0x48]

str r1, [r0, #0x4C]

str r1, [r0, #0x50]

ldr r0, =AIPS2_BASE_ADDR

str r1, [r0, #0x40]

str r1, [r0, #0x44]

str r1, [r0, #0x48]

str r1, [r0, #0x4C]

str r1, [r0, #0x50]
-.endm

-/* MAX (Multi-Layer AHB Crossbar Switch) setup */ -.macro init_max

ldr r0, =MAX_BASE_ADDR

/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */

ldr r1, =MAX_MPR_CONFIG

str r1, [r0, #0x000] /* for S0 */

str r1, [r0, #0x100] /* for S1 */

str r1, [r0, #0x200] /* for S2 */

str r1, [r0, #0x300] /* for S3 */

str r1, [r0, #0x400] /* for S4 */

/* SGPCR - always park on last master */

ldr r1, =MAX_SGPCR_CONFIG

str r1, [r0, #0x010] /* for S0 */

str r1, [r0, #0x110] /* for S1 */

str r1, [r0, #0x210] /* for S2 */

str r1, [r0, #0x310] /* for S3 */

str r1, [r0, #0x410] /* for S4 */

/* MGPCR - restore default values */

ldr r1, =MAX_MGPCR_CONFIG

str r1, [r0, #0x800] /* for M0 */

str r1, [r0, #0x900] /* for M1 */

str r1, [r0, #0xA00] /* for M2 */

str r1, [r0, #0xB00] /* for M3 */

str r1, [r0, #0xC00] /* for M4 */

str r1, [r0, #0xD00] /* for M5 */

-.endm

-/* M3IF setup */ -.macro init_m3if
/* Configure M3IF registers */

ldr r1, =M3IF_BASE_ADDR

/*

M3IF Control Register (M3IFCTL)

MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000

MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000

MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000

MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000

MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000

MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000

MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040

MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
				------------
				  0x00000040
*/

ldr r0, =M3IF_CONFIG

str r0, [r1] /* M3IF control reg */
-.endm

/* CPLD on CS5 setup */ .macro init_debug_board ldr r0, =DBG_BASE_ADDR @@ -210,38 +126,7 @@ lowlevel_init: mov r10, lr

mrc 15, 0, r1, c1, c0, 0

mrc 15, 0, r0, c1, c0, 1

orr r0, r0, #7

mcr 15, 0, r0, c1, c0, 1

orr r1, r1, #(1<<11)

/* Set unaligned access enable */

orr r1, r1, #(1<<22)

/* Set low int latency enable */

orr r1, r1, #(1<<21)

mcr 15, 0, r1, c1, c0, 0

mov r0, #0

/* Set branch prediction enable */

mcr 15, 0, r0, c15, c2, 4

mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache

*/
mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */

mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */

/*
* initializes very early AIPS
* Then it also initializes Multi-Layer AHB Crossbar Switch,
* M3IF
* Also setup the Peripheral Port Remap register inside the core
*/
ldr r0, =0x40000015 /* start from AIPS 2GB region */

mcr p15, 0, r0, c15, c2, 4
core_init

init_aips

diff --git u-boot-4d3c95f.orig/board/freescale/mx35pdk/mx35pdk.h u-boot-4d3c95f/board/freescale/mx35pdk/mx35pdk.h index 6aeb218..9e44f1f 100644 --- u-boot-4d3c95f.orig/board/freescale/mx35pdk/mx35pdk.h +++ u-boot-4d3c95f/board/freescale/mx35pdk/mx35pdk.h @@ -39,17 +39,17 @@ /*

M3IF Control Register (M3IFCTL)

MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000

MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000

MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000

MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000

MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000

MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000

MRRP[1] = L2CC1 not on priority list (0 << 1) = 0x00000000

MRRP[2] = MBX not on priority list (0 << 2) = 0x00000000

MRRP[3] = MAX1 not on priority list (0 << 3) = 0x00000000

MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000

MRRP[5] = MPEG4 not on priority list (0 << 5) = 0x00000000

MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040

MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
MRRP[7] = IPU2 not on priority list (0 << 7) = 0x00000000
                                          ------------
                                            0x00000040
*/
-#define M3IF_CONFIG 0x00000040 +#define M3IFCTL_CONFIG 0x00000040

#define DBG_BASE_ADDR WEIM_CTRL_CS5 #define DBG_CSCR_U_CONFIG 0x0000D843

Note that I will send a v2 for this patch replacing the configs with macro parameters having default values.

Do you think that it's worth keeping the configs in mx35pdk.h after that (just in case, so that they can be easily changed without modifying board/freescale/mx35pdk/lowlevel_init.S)? IMHO, it's better to remove them if they have the default values of macro parameters.

Best regards, Benoît

stefano babic

9:42 p.m.

New subject: [U-Boot] [PATCH 3/3] mx35: Clean up lowlevel_init

Am 20/08/2012 14:09, schrieb Benoît Thébaudeau:

...

Hi Stefano,

...
Clean up mx35 lowlevel_init:

Indent with tabs.

Fix comments.

Use defined values instead of literal constants.

Use defined macros instead of duplicating code.

Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de

.../arm/include/asm/arch-mx35/lowlevel_macro.S | 153 ++++++++------------ .../board/CarMediaLab/flea3/lowlevel_init.S | 19 +-- .../board/freescale/mx35pdk/lowlevel_init.S | 119 +-------------- .../board/freescale/mx35pdk/mx35pdk.h | 14 +- 4 files changed, 78 insertions(+), 227 deletions(-)

diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/lowlevel_macro.S u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/lowlevel_macro.S index 05aa951..9d7c133 100644

u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/lowlevel_macro.S +++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/lowlevel_macro.S @@ -19,122 +19,93 @@

MA 02111-1307 USA

*/

+#include <asm/arch/imx-regs.h> +#include <generated/asm-offsets.h> +#include <asm/macro.h>

/*

AIPS setup - Only setup MPROTx registers.

The PACR default values are good.

*/ .macro init_aips
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
* not forced to user-mode.
*/
ldr r0, =AIPS1_BASE_ADDR

ldr r1, =AIPS_MPR_CONFIG

str r1, [r0, #0x00]

str r1, [r0, #0x04]

ldr r0, =AIPS2_BASE_ADDR

str r1, [r0, #0x00]

str r1, [r0, #0x04]
ldr r0, =AIPS1_BASE_ADDR

ldr r1, =AIPS_MPR_CONFIG

str r1, [r0, #AIPS_MPR_0_7]

str r1, [r0, #AIPS_MPR_8_15]

ldr r2, =AIPS2_BASE_ADDR

str r1, [r2, #AIPS_MPR_0_7]

str r1, [r2, #AIPS_MPR_8_15]
/*
* Clear the on and off peripheral modules Supervisor Protect bit
* for SDMA to access them. Did not change the AIPS control
registers
* (offset 0x20) access type
*/
ldr r0, =AIPS1_BASE_ADDR

ldr r1, =AIPS_OPACR_CONFIG

str r1, [r0, #0x40]

str r1, [r0, #0x44]

str r1, [r0, #0x48]

str r1, [r0, #0x4C]

str r1, [r0, #0x50]

ldr r0, =AIPS2_BASE_ADDR

str r1, [r0, #0x40]

str r1, [r0, #0x44]

str r1, [r0, #0x48]

str r1, [r0, #0x4C]

str r1, [r0, #0x50]
/* Did not change the AIPS control registers access type. */

ldr r1, =AIPS_OPACR_CONFIG

str r1, [r0, #AIPS_OPACR_0_7]

str r1, [r0, #AIPS_OPACR_8_15]

str r1, [r0, #AIPS_OPACR_16_23]

str r1, [r0, #AIPS_OPACR_24_31]

str r1, [r0, #AIPS_OPACR_32_39]

str r1, [r2, #AIPS_OPACR_0_7]

str r1, [r2, #AIPS_OPACR_8_15]

str r1, [r2, #AIPS_OPACR_16_23]

str r1, [r2, #AIPS_OPACR_24_31]

str r1, [r2, #AIPS_OPACR_32_39]

.endm

/* MAX (Multi-Layer AHB Crossbar Switch) setup */ .macro init_max

ldr r0, =MAX_BASE_ADDR

/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */

ldr r1, =MAX_MPR_CONFIG

str r1, [r0, #0x000] /* for S0 */

str r1, [r0, #0x100] /* for S1 */

str r1, [r0, #0x200] /* for S2 */

str r1, [r0, #0x300] /* for S3 */

str r1, [r0, #0x400] /* for S4 */

/* SGPCR - always park on last master */

ldr r1, =MAX_SGPCR_CONFIG

str r1, [r0, #0x010] /* for S0 */

str r1, [r0, #0x110] /* for S1 */

str r1, [r0, #0x210] /* for S2 */

str r1, [r0, #0x310] /* for S3 */

str r1, [r0, #0x410] /* for S4 */

/* MGPCR - restore default values */

ldr r1, =MAX_MGPCR_CONFIG

str r1, [r0, #0x800] /* for M0 */

str r1, [r0, #0x900] /* for M1 */

str r1, [r0, #0xA00] /* for M2 */

str r1, [r0, #0xB00] /* for M3 */

str r1, [r0, #0xC00] /* for M4 */

str r1, [r0, #0xD00] /* for M5 */

ldr r0, =MAX_BASE_ADDR

ldr r1, =MAX_MPR_CONFIG

str r1, [r0, #MAX_MPR0] /* for S0 */

str r1, [r0, #MAX_MPR1] /* for S1 */

str r1, [r0, #MAX_MPR2] /* for S2 */

str r1, [r0, #MAX_MPR3] /* for S3 */

str r1, [r0, #MAX_MPR4] /* for S4 */

ldr r1, =MAX_SGPCR_CONFIG

str r1, [r0, #MAX_SGPCR0] /* for S0 */

str r1, [r0, #MAX_SGPCR1] /* for S1 */

str r1, [r0, #MAX_SGPCR2] /* for S2 */

str r1, [r0, #MAX_SGPCR3] /* for S3 */

str r1, [r0, #MAX_SGPCR4] /* for S4 */

ldr r1, =MAX_MGPCR_CONFIG

str r1, [r0, #MAX_MGPCR0] /* for M0 */

str r1, [r0, #MAX_MGPCR1] /* for M1 */

str r1, [r0, #MAX_MGPCR2] /* for M2 */

str r1, [r0, #MAX_MGPCR3] /* for M3 */

str r1, [r0, #MAX_MGPCR4] /* for M4 */

str r1, [r0, #MAX_MGPCR5] /* for M5 */

.endm

/* M3IF setup */ .macro init_m3if
/* Configure M3IF registers */

ldr r1, =M3IF_BASE_ADDR

/*

M3IF Control Register (M3IFCTL)

MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000

MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000

MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000

MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000

MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000

MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000

MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040

MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
				------------
				  0x00000040
*/

ldr r0, =M3IF_CONFIG

str r0, [r1] /* M3IF control reg */
/* M3IF Control Register (M3IFCTL) */

write32 M3IF_BASE_ADDR, M3IFCTL_CONFIG

.endm

.macro core_init

mrc 15, 0, r1, c1, c0, 0

mrc p15, 0, r1, c1, c0, 0

mrc 15, 0, r0, c1, c0, 1

orr r0, r0, #7

mcr 15, 0, r0, c1, c0, 1

orr r1, r1, #(1<<11)

/* Set branch prediction enable */

mrc p15, 0, r0, c1, c0, 1

orr r0, r0, #7

mcr p15, 0, r0, c1, c0, 1

orr r1, r1, #1 << 11

/* Set unaligned access enable */

orr r1, r1, #(1<<22)

orr r1, r1, #1 << 22

/* Set low int latency enable */

orr r1, r1, #(1<<21)

orr r1, r1, #1 << 21

mcr 15, 0, r1, c1, c0, 0

mcr p15, 0, r1, c1, c0, 0

mov r0, #0

mov r0, #0

/* Set branch prediction enable */

mcr 15, 0, r0, c15, c2, 4

mcr p15, 0, r0, c15, c2, 4

mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache

*/

mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */

mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */

mcr p15, 0, r0, c7, c7, 0 /* Invalidate I cache and D cache */

mcr p15, 0, r0, c8, c7, 0 /* Invalidate TLBs */

mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffer */
/*
* initializes very early AIPS
* Then it also initializes Multi-Layer AHB Crossbar Switch,
* M3IF
* Also setup the Peripheral Port Remap register inside the core
*/
ldr r0, =0x40000015 /* start from AIPS 2GB region */

mcr p15, 0, r0, c15, c2, 4
/* Setup the Peripheral Port Memory Remap Register */

ldr r0, =0x40000015 /* Start from AIPS 2-GB region */

mcr p15, 0, r0, c15, c2, 4

.endm diff --git u-boot-4d3c95f.orig/board/CarMediaLab/flea3/lowlevel_init.S u-boot-4d3c95f/board/CarMediaLab/flea3/lowlevel_init.S index 2f42fc9..e7e5cd7 100644 --- u-boot-4d3c95f.orig/board/CarMediaLab/flea3/lowlevel_init.S +++ u-boot-4d3c95f/board/CarMediaLab/flea3/lowlevel_init.S @@ -22,9 +22,6 @@ */

#include <config.h> -#include <asm-offsets.h> -#include <asm/arch/imx-regs.h> -#include <generated/asm-offsets.h>

/*

Configuration for the flea3 board.

@@ -46,19 +43,17 @@ /*

M3IF Control Register (M3IFCTL)

MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000

MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000

MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000

MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000

MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000

MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000

MRRP[1] = L2CC1 not on priority list (0 << 1) = 0x00000000

MRRP[2] = MBX not on priority list (0 << 2) = 0x00000000

MRRP[3] = MAX1 not on priority list (0 << 3) = 0x00000000

MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000

MRRP[5] = MPEG4 not on priority list (0 << 5) = 0x00000000

MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040

MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
MRRP[7] = IPU2 not on priority list (0 << 7) = 0x00000000
                                          ------------
                                            0x00000040
*/
-#define M3IF_CONFIG 0x00000040

-#define CCM_PDR0_CONFIG 0x00801000 +#define M3IFCTL_CONFIG 0x00000040

/*

includes MX35 utility macros

diff --git u-boot-4d3c95f.orig/board/freescale/mx35pdk/lowlevel_init.S u-boot-4d3c95f/board/freescale/mx35pdk/lowlevel_init.S index 698c4cf..75bb958 100644 --- u-boot-4d3c95f.orig/board/freescale/mx35pdk/lowlevel_init.S +++ u-boot-4d3c95f/board/freescale/mx35pdk/lowlevel_init.S @@ -23,6 +23,7 @@ #include <asm/arch/imx-regs.h> #include <generated/asm-offsets.h> #include "mx35pdk.h" +#include <asm/arch/lowlevel_macro.S>

/*

return soc version

@@ -40,91 +41,6 @@ addne \ret, \ret, #0x10 .endm

-/*

AIPS setup - Only setup MPROTx registers.

The PACR default values are good.

*/

-.macro init_aips
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
* not forced to user-mode.
*/
ldr r0, =AIPS1_BASE_ADDR

ldr r1, =AIPS_MPR_CONFIG

str r1, [r0, #0x00]

str r1, [r0, #0x04]

ldr r0, =AIPS2_BASE_ADDR

str r1, [r0, #0x00]

str r1, [r0, #0x04]

/*
* Clear the on and off peripheral modules Supervisor Protect bit
* for SDMA to access them. Did not change the AIPS control
registers
* (offset 0x20) access type
*/
ldr r0, =AIPS1_BASE_ADDR

ldr r1, =AIPS_OPACR_CONFIG

str r1, [r0, #0x40]

str r1, [r0, #0x44]

str r1, [r0, #0x48]

str r1, [r0, #0x4C]

str r1, [r0, #0x50]

ldr r0, =AIPS2_BASE_ADDR

str r1, [r0, #0x40]

str r1, [r0, #0x44]

str r1, [r0, #0x48]

str r1, [r0, #0x4C]

str r1, [r0, #0x50]
-.endm

-/* MAX (Multi-Layer AHB Crossbar Switch) setup */ -.macro init_max

ldr r0, =MAX_BASE_ADDR

/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */

ldr r1, =MAX_MPR_CONFIG

str r1, [r0, #0x000] /* for S0 */

str r1, [r0, #0x100] /* for S1 */

str r1, [r0, #0x200] /* for S2 */

str r1, [r0, #0x300] /* for S3 */

str r1, [r0, #0x400] /* for S4 */

/* SGPCR - always park on last master */

ldr r1, =MAX_SGPCR_CONFIG

str r1, [r0, #0x010] /* for S0 */

str r1, [r0, #0x110] /* for S1 */

str r1, [r0, #0x210] /* for S2 */

str r1, [r0, #0x310] /* for S3 */

str r1, [r0, #0x410] /* for S4 */

/* MGPCR - restore default values */

ldr r1, =MAX_MGPCR_CONFIG

str r1, [r0, #0x800] /* for M0 */

str r1, [r0, #0x900] /* for M1 */

str r1, [r0, #0xA00] /* for M2 */

str r1, [r0, #0xB00] /* for M3 */

str r1, [r0, #0xC00] /* for M4 */

str r1, [r0, #0xD00] /* for M5 */

-.endm

-/* M3IF setup */ -.macro init_m3if
/* Configure M3IF registers */

ldr r1, =M3IF_BASE_ADDR

/*

M3IF Control Register (M3IFCTL)

MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000

MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000

MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000

MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000

MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000

MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000

MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040

MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
				------------
				  0x00000040
*/

ldr r0, =M3IF_CONFIG

str r0, [r1] /* M3IF control reg */
-.endm

/* CPLD on CS5 setup */ .macro init_debug_board ldr r0, =DBG_BASE_ADDR @@ -210,38 +126,7 @@ lowlevel_init: mov r10, lr

mrc 15, 0, r1, c1, c0, 0

mrc 15, 0, r0, c1, c0, 1

orr r0, r0, #7

mcr 15, 0, r0, c1, c0, 1

orr r1, r1, #(1<<11)

/* Set unaligned access enable */

orr r1, r1, #(1<<22)

/* Set low int latency enable */

orr r1, r1, #(1<<21)

mcr 15, 0, r1, c1, c0, 0

mov r0, #0

/* Set branch prediction enable */

mcr 15, 0, r0, c15, c2, 4

mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache

*/
mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */

mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */

/*
* initializes very early AIPS
* Then it also initializes Multi-Layer AHB Crossbar Switch,
* M3IF
* Also setup the Peripheral Port Remap register inside the core
*/
ldr r0, =0x40000015 /* start from AIPS 2GB region */

mcr p15, 0, r0, c15, c2, 4
core_init

init_aips

diff --git u-boot-4d3c95f.orig/board/freescale/mx35pdk/mx35pdk.h u-boot-4d3c95f/board/freescale/mx35pdk/mx35pdk.h index 6aeb218..9e44f1f 100644 --- u-boot-4d3c95f.orig/board/freescale/mx35pdk/mx35pdk.h +++ u-boot-4d3c95f/board/freescale/mx35pdk/mx35pdk.h @@ -39,17 +39,17 @@ /*

M3IF Control Register (M3IFCTL)

MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000

MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000

MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000

MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000

MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000

MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000

MRRP[1] = L2CC1 not on priority list (0 << 1) = 0x00000000

MRRP[2] = MBX not on priority list (0 << 2) = 0x00000000

MRRP[3] = MAX1 not on priority list (0 << 3) = 0x00000000

MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000

MRRP[5] = MPEG4 not on priority list (0 << 5) = 0x00000000

MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040

MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
MRRP[7] = IPU2 not on priority list (0 << 7) = 0x00000000
                                          ------------
                                            0x00000040
*/
-#define M3IF_CONFIG 0x00000040 +#define M3IFCTL_CONFIG 0x00000040

#define DBG_BASE_ADDR WEIM_CTRL_CS5 #define DBG_CSCR_U_CONFIG 0x0000D843
Note that I will send a v2 for this patch replacing the configs with macro parameters having default values.

Do you think that it's worth keeping the configs in mx35pdk.h after that (just in case, so that they can be easily changed without modifying board/freescale/mx35pdk/lowlevel_init.S)?

...

IMHO, it's better to remove them if they have the default values of macro parameters.

Yes. Note that the mx35pdk was the first board with mx35, and the lowlevel_init.S comes mainly from the Freescale's delivery.

With the flea3 I have made some clean-up, making the lowLevel_init.S essential. Same changes were not reported back to the mx35pdk. I am going also to put in a common place the functions to setup the DDR controller ( board_setup_sdram_bank() in the flea3 directory). This should allow to factorize some other code, reducing the lowlevel_init.S.

Best regards, Stefano

-- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office@denx.de =====================================================================

Benoît Thébaudeau

9:54 p.m.

New subject: [U-Boot] [PATCH v2 3/3] mx35: Clean up lowlevel_init

Clean up mx35 lowlevel_init: - Indent with tabs. - Fix comments. - Use defined values instead of literal constants. - Use defined macros instead of duplicating code. - Use macro parameters with default values instead of #define'd configs.

Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de --- Changes for v2: - Use macro arguments with default values instead of #define's.

.../arm/include/asm/arch-mx35/lowlevel_macro.S | 191 ++++++++++---------- .../board/CarMediaLab/flea3/lowlevel_init.S | 41 ----- .../board/freescale/mx35pdk/lowlevel_init.S | 119 +----------- .../board/freescale/mx35pdk/mx35pdk.h | 25 --- 4 files changed, 97 insertions(+), 279 deletions(-)

diff --git u-boot-imx-84ab1cb.orig/arch/arm/include/asm/arch-mx35/lowlevel_macro.S u-boot-imx-84ab1cb/arch/arm/include/asm/arch-mx35/lowlevel_macro.S index 05aa951..bc6dbea 100644 --- u-boot-imx-84ab1cb.orig/arch/arm/include/asm/arch-mx35/lowlevel_macro.S +++ u-boot-imx-84ab1cb/arch/arm/include/asm/arch-mx35/lowlevel_macro.S @@ -19,122 +19,121 @@ * MA 02111-1307 USA */

+#include <asm/arch/imx-regs.h> +#include <generated/asm-offsets.h> +#include <asm/macro.h> + /* * AIPS setup - Only setup MPROTx registers. * The PACR default values are good. + * + * Default argument values: + * - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to + * user-mode. + * - OPACR: Clear the on and off peripheral modules Supervisor Protect bit for + * SDMA to access them. */ -.macro init_aips - /* - * Set all MPROTx to be non-bufferable, trusted for R/W, - * not forced to user-mode. - */ - ldr r0, =AIPS1_BASE_ADDR - ldr r1, =AIPS_MPR_CONFIG - str r1, [r0, #0x00] - str r1, [r0, #0x04] - ldr r0, =AIPS2_BASE_ADDR - str r1, [r0, #0x00] - str r1, [r0, #0x04] +.macro init_aips mpr=0x77777777, opacr=0x00000000 + ldr r0, =AIPS1_BASE_ADDR + ldr r1, =\mpr + str r1, [r0, #AIPS_MPR_0_7] + str r1, [r0, #AIPS_MPR_8_15] + ldr r2, =AIPS2_BASE_ADDR + str r1, [r2, #AIPS_MPR_0_7] + str r1, [r2, #AIPS_MPR_8_15]

- /* - * Clear the on and off peripheral modules Supervisor Protect bit - * for SDMA to access them. Did not change the AIPS control registers - * (offset 0x20) access type - */ - ldr r0, =AIPS1_BASE_ADDR - ldr r1, =AIPS_OPACR_CONFIG - str r1, [r0, #0x40] - str r1, [r0, #0x44] - str r1, [r0, #0x48] - str r1, [r0, #0x4C] - str r1, [r0, #0x50] - ldr r0, =AIPS2_BASE_ADDR - str r1, [r0, #0x40] - str r1, [r0, #0x44] - str r1, [r0, #0x48] - str r1, [r0, #0x4C] - str r1, [r0, #0x50] + /* Did not change the AIPS control registers access type. */ + ldr r1, =\opacr + str r1, [r0, #AIPS_OPACR_0_7] + str r1, [r0, #AIPS_OPACR_8_15] + str r1, [r0, #AIPS_OPACR_16_23] + str r1, [r0, #AIPS_OPACR_24_31] + str r1, [r0, #AIPS_OPACR_32_39] + str r1, [r2, #AIPS_OPACR_0_7] + str r1, [r2, #AIPS_OPACR_8_15] + str r1, [r2, #AIPS_OPACR_16_23] + str r1, [r2, #AIPS_OPACR_24_31] + str r1, [r2, #AIPS_OPACR_32_39] .endm

-/* MAX (Multi-Layer AHB Crossbar Switch) setup */ -.macro init_max - ldr r0, =MAX_BASE_ADDR - /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ - ldr r1, =MAX_MPR_CONFIG - str r1, [r0, #0x000] /* for S0 */ - str r1, [r0, #0x100] /* for S1 */ - str r1, [r0, #0x200] /* for S2 */ - str r1, [r0, #0x300] /* for S3 */ - str r1, [r0, #0x400] /* for S4 */ - /* SGPCR - always park on last master */ - ldr r1, =MAX_SGPCR_CONFIG - str r1, [r0, #0x010] /* for S0 */ - str r1, [r0, #0x110] /* for S1 */ - str r1, [r0, #0x210] /* for S2 */ - str r1, [r0, #0x310] /* for S3 */ - str r1, [r0, #0x410] /* for S4 */ - /* MGPCR - restore default values */ - ldr r1, =MAX_MGPCR_CONFIG - str r1, [r0, #0x800] /* for M0 */ - str r1, [r0, #0x900] /* for M1 */ - str r1, [r0, #0xA00] /* for M2 */ - str r1, [r0, #0xB00] /* for M3 */ - str r1, [r0, #0xC00] /* for M4 */ - str r1, [r0, #0xD00] /* for M5 */ +/* + * MAX (Multi-Layer AHB Crossbar Switch) setup + * + * Default argument values: + * - MPR: priority is M4 > M2 > M3 > M5 > M0 > M1 + * - SGPCR: always park on last master + * - MGPCR: restore default values + */ +.macro init_max mpr=0x00302154, sgpcr=0x00000010, mgpcr=0x00000000 + ldr r0, =MAX_BASE_ADDR + ldr r1, =\mpr + str r1, [r0, #MAX_MPR0] /* for S0 */ + str r1, [r0, #MAX_MPR1] /* for S1 */ + str r1, [r0, #MAX_MPR2] /* for S2 */ + str r1, [r0, #MAX_MPR3] /* for S3 */ + str r1, [r0, #MAX_MPR4] /* for S4 */ + ldr r1, =\sgpcr + str r1, [r0, #MAX_SGPCR0] /* for S0 */ + str r1, [r0, #MAX_SGPCR1] /* for S1 */ + str r1, [r0, #MAX_SGPCR2] /* for S2 */ + str r1, [r0, #MAX_SGPCR3] /* for S3 */ + str r1, [r0, #MAX_SGPCR4] /* for S4 */ + ldr r1, =\mgpcr + str r1, [r0, #MAX_MGPCR0] /* for M0 */ + str r1, [r0, #MAX_MGPCR1] /* for M1 */ + str r1, [r0, #MAX_MGPCR2] /* for M2 */ + str r1, [r0, #MAX_MGPCR3] /* for M3 */ + str r1, [r0, #MAX_MGPCR4] /* for M4 */ + str r1, [r0, #MAX_MGPCR5] /* for M5 */ .endm

-/* M3IF setup */ -.macro init_m3if - /* Configure M3IF registers */ - ldr r1, =M3IF_BASE_ADDR - /* - * M3IF Control Register (M3IFCTL) - * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 - * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000 - * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000 - * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 - * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 - * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 - * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 - * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 - * ------------ - * 0x00000040 - */ - ldr r0, =M3IF_CONFIG - str r0, [r1] /* M3IF control reg */ +/* + * M3IF setup + * + * Default argument values: + * - CTL: + * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 + * MRRP[1] = L2CC1 not on priority list (0 << 1) = 0x00000000 + * MRRP[2] = MBX not on priority list (0 << 2) = 0x00000000 + * MRRP[3] = MAX1 not on priority list (0 << 3) = 0x00000000 + * MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000 + * MRRP[5] = MPEG4 not on priority list (0 << 5) = 0x00000000 + * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 + * MRRP[7] = IPU2 not on priority list (0 << 7) = 0x00000000 + * ------------ + * 0x00000040 + */ +.macro init_m3if ctl=0x00000040 + /* M3IF Control Register (M3IFCTL) */ + write32 M3IF_BASE_ADDR, \ctl .endm

.macro core_init - mrc 15, 0, r1, c1, c0, 0 + mrc p15, 0, r1, c1, c0, 0

/* Set unaligned access enable */ - orr r1, r1, #(1<<22) + orr r1, r1, #1 << 22

/* Set low int latency enable */ - orr r1, r1, #(1<<21) + orr r1, r1, #1 << 21

- mcr 15, 0, r1, c1, c0, 0 + mcr p15, 0, r1, c1, c0, 0

- mov r0, #0 + mov r0, #0

- /* Set branch prediction enable */ - mcr 15, 0, r0, c15, c2, 4 + mcr p15, 0, r0, c15, c2, 4

- /* - * initializes very early AIPS - * Then it also initializes Multi-Layer AHB Crossbar Switch, - * M3IF - * Also setup the Peripheral Port Remap register inside the core - */ - ldr r0, =0x40000015 /* start from AIPS 2GB region */ - mcr p15, 0, r0, c15, c2, 4 + /* Setup the Peripheral Port Memory Remap Register */ + ldr r0, =0x40000015 /* Start from AIPS 2-GB region */ + mcr p15, 0, r0, c15, c2, 4 .endm diff --git u-boot-imx-84ab1cb.orig/board/CarMediaLab/flea3/lowlevel_init.S u-boot-imx-84ab1cb/board/CarMediaLab/flea3/lowlevel_init.S index 2f42fc9..57fb1b1 100644 --- u-boot-imx-84ab1cb.orig/board/CarMediaLab/flea3/lowlevel_init.S +++ u-boot-imx-84ab1cb/board/CarMediaLab/flea3/lowlevel_init.S @@ -22,47 +22,6 @@ */

#include <config.h> -#include <asm-offsets.h> -#include <asm/arch/imx-regs.h> -#include <generated/asm-offsets.h> - -/* - * Configuration for the flea3 board. - * These defines are used by the included macros and must - * be defined first - */ -#define AIPS_MPR_CONFIG 0x77777777 -#define AIPS_OPACR_CONFIG 0x00000000 - -/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ -#define MAX_MPR_CONFIG 0x00302154 - -/* SGPCR - always park on last master */ -#define MAX_SGPCR_CONFIG 0x00000010 - -/* MGPCR - restore default values */ -#define MAX_MGPCR_CONFIG 0x00000000 - -/* - * M3IF Control Register (M3IFCTL) - * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 - * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000 - * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000 - * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 - * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 - * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 - * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 - * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 - * ------------ - * 0x00000040 - */ -#define M3IF_CONFIG 0x00000040 - -#define CCM_PDR0_CONFIG 0x00801000 - -/* - * includes MX35 utility macros - */ #include <asm/arch/lowlevel_macro.S>

.globl lowlevel_init diff --git u-boot-imx-84ab1cb.orig/board/freescale/mx35pdk/lowlevel_init.S u-boot-imx-84ab1cb/board/freescale/mx35pdk/lowlevel_init.S index 698c4cf..75bb958 100644 --- u-boot-imx-84ab1cb.orig/board/freescale/mx35pdk/lowlevel_init.S +++ u-boot-imx-84ab1cb/board/freescale/mx35pdk/lowlevel_init.S @@ -23,6 +23,7 @@ #include <asm/arch/imx-regs.h> #include <generated/asm-offsets.h> #include "mx35pdk.h" +#include <asm/arch/lowlevel_macro.S>

/* * return soc version @@ -40,91 +41,6 @@ addne \ret, \ret, #0x10 .endm

init_aips

diff --git u-boot-imx-84ab1cb.orig/board/freescale/mx35pdk/mx35pdk.h u-boot-imx-84ab1cb/board/freescale/mx35pdk/mx35pdk.h index 6aeb218..f15aa4f 100644 --- u-boot-imx-84ab1cb.orig/board/freescale/mx35pdk/mx35pdk.h +++ u-boot-imx-84ab1cb/board/freescale/mx35pdk/mx35pdk.h @@ -26,31 +26,6 @@ #ifndef __BOARD_MX35_3STACK_H #define __BOARD_MX35_3STACK_H

-#define AIPS_MPR_CONFIG 0x77777777 -#define AIPS_OPACR_CONFIG 0x00000000 - -/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ -#define MAX_MPR_CONFIG 0x00302154 -/* SGPCR - always park on last master */ -#define MAX_SGPCR_CONFIG 0x00000010 -/* MGPCR - restore default values */ -#define MAX_MGPCR_CONFIG 0x00000000 - -/* - * M3IF Control Register (M3IFCTL) - * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 - * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000 - * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000 - * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 - * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 - * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 - * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 - * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 - * ------------ - * 0x00000040 - */ -#define M3IF_CONFIG 0x00000040 - #define DBG_BASE_ADDR WEIM_CTRL_CS5 #define DBG_CSCR_U_CONFIG 0x0000D843 #define DBG_CSCR_L_CONFIG 0x22252521

Stefano Babic

10 Oct 10 Oct

1:26 p.m.

New subject: [U-Boot] [PATCH v2 3/3] mx35: Clean up lowlevel_init

On 20/08/2012 21:54, Benoît Thébaudeau wrote:

...

Clean up mx35 lowlevel_init:

Indent with tabs.

Fix comments.

Use defined values instead of literal constants.

Use defined macros instead of duplicating code.

Use macro parameters with default values instead of #define'd configs.

Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de

Applied to u-boot-imx, next branch, thanks.

Best regards, Stefano Babic

Fabio Estevam

20 Aug 20 Aug

10:25 p.m.

New subject: [U-Boot] [PATCH 3/3] mx35: Clean up lowlevel_init

Hi Stefano,

On Mon, Aug 20, 2012 at 4:42 PM, stefano babic sbabic@denx.de wrote:

...

With the flea3 I have made some clean-up, making the lowLevel_init.S essential. Same changes were not reported back to the mx35pdk. I am going also to put in a common place the functions to setup the DDR controller ( board_setup_sdram_bank() in the flea3 directory). This should allow to factorize some other code, reducing the lowlevel_init.S.

Maybe even better would be to convert the init from lowlevel_init.S into C code, like was done on mx31.

It is much easier to debug/maintain C code then assemby.

Regards,

Fabio Estevam

Stefano Babic

21 Aug 21 Aug

8:05 a.m.

New subject: [U-Boot] [PATCH 3/3] mx35: Clean up lowlevel_init

On 20/08/2012 22:25, Fabio Estevam wrote:

...

Hi Stefano,

On Mon, Aug 20, 2012 at 4:42 PM, stefano babic sbabic@denx.de wrote:

...
With the flea3 I have made some clean-up, making the lowLevel_init.S essential. Same changes were not reported back to the mx35pdk. I am going also to put in a common place the functions to setup the DDR controller ( board_setup_sdram_bank() in the flea3 directory). This should allow to factorize some other code, reducing the lowlevel_init.S.

Maybe even better would be to convert the init from lowlevel_init.S into C code, like was done on mx31.

It is much easier to debug/maintain C code then assemby.

Yes, agree.

Regards, Stefano

Benoît Thébaudeau

2:58 p.m.

New subject: [U-Boot] [PATCH 3/3] mx35: Clean up lowlevel_init

Hi Stefano, Fabio,

...

On 20/08/2012 22:25, Fabio Estevam wrote:

...
Hi Stefano,

On Mon, Aug 20, 2012 at 4:42 PM, stefano babic sbabic@denx.de wrote:

...
With the flea3 I have made some clean-up, making the lowLevel_init.S essential. Same changes were not reported back to the mx35pdk. I am going also to put in a common place the functions to setup the DDR controller ( board_setup_sdram_bank() in the flea3 directory). This should allow to factorize some other code, reducing the lowlevel_init.S.

Maybe even better would be to convert the init from lowlevel_init.S into C code, like was done on mx31.

It is much easier to debug/maintain C code then assemby.

Yes, agree.

Regards, Stefano

Yes, but we must also not forget the size constraints for SPLs.

Best regards, Benoît

Stefano Babic

17 Aug 17 Aug

9:57 p.m.

On 14/08/2012 23:03, Benoît Thébaudeau wrote:

...

Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de

.../arch/arm/include/asm/arch-mx35/imx-regs.h | 1 - 1 file changed, 1 deletion(-)

diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/imx-regs.h u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/imx-regs.h index 3146006..5cb7656 100644 --- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/imx-regs.h +++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/imx-regs.h @@ -72,7 +72,6 @@ #define MMC_SDHC2_BASE_ADDR 0x53FB8000 #define MMC_SDHC3_BASE_ADDR 0x53FBC000 #define IPU_CTRL_BASE_ADDR 0x53FC0000 -#define GPIO3_BASE_ADDR 0x53FA4000 #define GPIO1_BASE_ADDR 0x53FCC000 #define GPIO2_BASE_ADDR 0x53FD0000 #define SDMA_BASE_ADDR 0x53FD4000

Acked-by: Stefano Babic sbabic@denx.de

Best regards, Stefano Babic

Stefano Babic

20 Aug 20 Aug

9:57 a.m.

On 14/08/2012 23:03, Benoît Thébaudeau wrote:

...

Signed-off-by: Benoît Thébaudeau benoit.thebaudeau@advansee.com Cc: Stefano Babic sbabic@denx.de

.../arch/arm/include/asm/arch-mx35/imx-regs.h | 1 - 1 file changed, 1 deletion(-)

diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/imx-regs.h u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/imx-regs.h index 3146006..5cb7656 100644 --- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/imx-regs.h +++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/imx-regs.h @@ -72,7 +72,6 @@ #define MMC_SDHC2_BASE_ADDR 0x53FB8000 #define MMC_SDHC3_BASE_ADDR 0x53FBC000 #define IPU_CTRL_BASE_ADDR 0x53FC0000 -#define GPIO3_BASE_ADDR 0x53FA4000 #define GPIO1_BASE_ADDR 0x53FCC000 #define GPIO2_BASE_ADDR 0x53FD0000 #define SDMA_BASE_ADDR 0x53FD4000

Applied to u-boot-imx, thanks.

Best regards, Stefano Babic

4596

Age (days ago)

4653

Last active (days ago)

List overview

Download

12 comments

4 participants

tags (0)

participants (4)

Benoît Thébaudeau
Fabio Estevam
Stefano Babic
stefano babic