[U-Boot] [PATCH 00/34] imx: ventana: Ventana clean-up and updates
This collection of patches comprises a set of various updates that has been sitting in my queue for a while.
There are a couple of patches pending that this series depends on: - fdt: add new fdt_fixup_display function to configure display - arm: mx6: ddr: add pd_fast_exit flag to system information
Pushpal Sidhu (3): imx: ventana: add DT fixup for GW522x to change PCIE_RST# GPIO imx: ventana: Add new memory configuration imx: ventana: Update missing memory/calib handling
Tim Harvey (31): imx: ventana: disable 4k tftp/nfs packets imx: ventana: add i210 support imx: ventana: assign default ethprime dynamically imx: ventana: remove unused GPIO configuration imx: ventana: add usb_pcisel hwconfig support imx: ventana: enable precharge power-down fast-exit mode imx: ventana: add support for 4Gb density mem devices with IMX6DL imx: ventana: set LTC3676 PMIC to appropriate values per datasheet imx: ventana: config: add USB Mass Storage (ums) support imx: ventana: config: Support ramdisk imx: ventana: config: enable edid support imx: ventana: config: enable EXT4 filesystem read/write support imx: ventana: fix various sparse warnings imx: ventana: disable IMX6 watchdogs on GW51xx RevA and RevB imx: ventana: Add support for GW551x imx: ventana: add usb_pgood_delay 2sec default imx: ventana: add wdis config for GW5520 imx: ventana: only pinmux FEC enet signals for boards using it imx: ventana: update boot scripts to support ubifs boot vol imx: ventana: remove GSC hwmon voltage rail min/max test imx: ventana: add mem_mb dynamic env var imx: ventana: gsc: add new hwmon rails imx: ventana: added DT fixup for GW551x-A video input imx: ventana: updated 16bit DDR calibration imx: ventana: remove 128x16 calibration (share with 128x32) imx: ventana: add DT fixup for GW54xx compatibility with older kernels imx: ventana: add support for DLC-700JMGT4 and DLC-800FIGT3 LCD displays imx: ventana: added device-tree display configuration for LVDS displays imx: ventana: add 'gsc wd' command for enabling and disabling GSC watchdog imx: ventana: use hdmiinfmt env var to override HDMI capture format imx: ventana: set HDMI video in to yuv422bt656 for GW551x-A
board/gateworks/gw_ventana/eeprom.c | 10 +- board/gateworks/gw_ventana/gsc.c | 130 +++++++--- board/gateworks/gw_ventana/gsc.h | 10 +- board/gateworks/gw_ventana/gw_ventana.c | 367 +++++++++++++++++++++++----- board/gateworks/gw_ventana/gw_ventana_spl.c | 129 +++++++++- board/gateworks/gw_ventana/ventana_eeprom.h | 1 + include/configs/gw_ventana.h | 68 ++++-- 7 files changed, 578 insertions(+), 137 deletions(-)
I've encountered issues when using 4k packets through certain switches. For now disable this and go back to using MTU size packets.
Signed-off-by: Tim Harvey tharvey@gateworks.com --- include/configs/gw_ventana.h | 5 ----- 1 file changed, 5 deletions(-)
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 620f950..e60173f 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -115,11 +115,6 @@ #define CONFIG_CMD_UBIFS #define CONFIG_DOS_PARTITION
-/* Network config - Allow larger/faster download for TFTP/NFS */ -#define CONFIG_IP_DEFRAG -#define CONFIG_TFTP_BLOCKSIZE 4096 -#define CONFIG_NFS_READ_SIZE 4096 - /* * SATA Configs */
Signed-off-by: Tim Harvey tharvey@gateworks.com --- board/gateworks/gw_ventana/gw_ventana.c | 4 ++++ include/configs/gw_ventana.h | 1 + 2 files changed, 5 insertions(+)
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index bb08cd2..303b13a 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -404,6 +404,10 @@ int board_eth_init(bd_t *bis) cpu_eth_init(bis); #endif
+#ifdef CONFIG_E1000 + e1000_initialize(bis); +#endif + #ifdef CONFIG_CI_UDC /* For otg ethernet*/ usb_eth_initialize(bis); diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index e60173f..76da532 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -174,6 +174,7 @@
/* Ethernet support */ #define CONFIG_FEC_MXC +#define CONFIG_E1000 #define CONFIG_MII #define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_XCV_TYPE RGMII
Gateworks Ventana boards don't all use IMX6 FEC, so lets define default ethprime based off the first detected device.
Signed-off-by: Tim Harvey tharvey@gateworks.com --- board/gateworks/gw_ventana/gw_ventana.c | 9 +++++++++ include/configs/gw_ventana.h | 1 - 2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 303b13a..84d7124 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -413,6 +413,15 @@ int board_eth_init(bd_t *bis) usb_eth_initialize(bis); #endif
+ /* default to the first detected enet dev */ + if (!getenv("ethprime")) { + struct eth_device *dev = eth_get_dev_by_index(0); + if (dev) { + setenv("ethprime", dev->name); + printf("set ethprime to %s\n", getenv("ethprime")); + } + } + return 0; }
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 76da532..28c7815 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -178,7 +178,6 @@ #define CONFIG_MII #define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" #define CONFIG_FEC_MXC_PHYADDR 0 #define CONFIG_PHYLIB #define CONFIG_ARP_TIMEOUT 200UL
Signed-off-by: Tim Harvey tharvey@gateworks.com --- board/gateworks/gw_ventana/gw_ventana.c | 2 -- 1 file changed, 2 deletions(-)
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 84d7124..dac79d1 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -671,8 +671,6 @@ static iomux_v3_cfg_t const gw54xx_gpio_pads[] = { IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), /* DIOI2C_DIS# */ IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), - /* PCICK_SSON */ - IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG), /* PCI_RST# */ IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), /* VID_EN */
The GW52xx has a MUX that can direct front-panel USB OTG to one of the miniPCIe sockets (for use with a cellular modem for example). Use hwconfig to steer this.
Signed-off-by: Tim Harvey tharvey@gateworks.com --- board/gateworks/gw_ventana/gw_ventana.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index dac79d1..51925d1 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -1111,7 +1111,9 @@ static void setup_board_gpio(int board)
/* USBOTG Select (PCISKT or FrontPanel) */ if (gpio_cfg[board].usb_sel) - gpio_direction_output(gpio_cfg[board].usb_sel, 0); + gpio_direction_output(gpio_cfg[board].usb_sel, + (hwconfig("usb_pcisel")) ? 1 : 0); +
/* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */ if (gpio_cfg[board].wdis)
Enable fast-exit precharge mode necessary for some DDR3 devices being used on Ventana boards.
Signed-off-by: Tim Harvey tharvey@gateworks.com --- board/gateworks/gw_ventana/gw_ventana_spl.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index 9712812..5d313a9 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -340,6 +340,7 @@ static void spl_dram_init(int width, int size_mb, int board_model) .bi_on = 1, /* Bank interleaving enabled */ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .pd_fast_exit = 1, /* enable precharge power-down fast exit */ };
/*
Signed-off-by: Tim Harvey tharvey@gateworks.com --- board/gateworks/gw_ventana/gw_ventana_spl.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index 5d313a9..97fd346 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -188,7 +188,7 @@ struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { .grp_b7ds = 0x00000030, };
-/* MT41K128M16JT-125 */ +/* MT41K128M16JT-125 (2Gb density) */ static struct mx6_ddr3_cfg mt41k128m16jt_125 = { .mem_speed = 1600, .density = 2, @@ -202,7 +202,7 @@ static struct mx6_ddr3_cfg mt41k128m16jt_125 = { .trasmin = 3500, };
-/* MT41K256M16HA-125 */ +/* MT41K256M16HA-125 (4Gb density) */ static struct mx6_ddr3_cfg mt41k256m16ha_125 = { .mem_speed = 1600, .density = 4, @@ -297,6 +297,19 @@ static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = { .p0_mpwrdlctl = 0x32363934, };
+static struct mx6_mmdc_calibration mx6sdl_256x32_mmdc_calib = { + /* write leveling calibration determine */ + .p0_mpwldectrl0 = 0X00480047, + .p0_mpwldectrl1 = 0X003D003F, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0X423E0241, + .p0_mpdgctrl1 = 0X022B022C, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0X49454A4A, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0X2E372C32, +}; + static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = { /* write leveling calibration determine */ .p0_mpwldectrl0 = 0X00220021, @@ -368,6 +381,8 @@ static void spl_dram_init(int width, int size_mb, int board_model) mem = &mt41k256m16ha_125; if (is_cpu_type(MXC_CPU_MX6Q)) calib = &mx6dq_256x32_mmdc_calib; + else + calib = &mx6sdl_256x32_mmdc_calib; debug("4gB density\n"); } else if (width == 64 && size_mb == 2048) { mem = &mt41k256m16ha_125;
The IMX6 Datasheets specifies that when the IMX6 LDO is enabled (internal Anatop LDO's for VDD_ARM, VDD_SOC, and VDD_xPU) you need to provide 1350mV on VDD_ARM_IN and VDD_SOC_IN for IMX6Q@1GHz (Automotive) and 1275mV for IMX6DL@800MHz (Industrial). While we are still about 50mV shy on the IMX6Q operating at 1GHz we set it to the max we can and leave it up to the kernel to implement a regulator driver for the LTC3676 and put the LDO's in bypass mode which allows us to drop the voltages by 125mV respectively.
Signed-off-by: Tim Harvey tharvey@gateworks.com --- board/gateworks/gw_ventana/gw_ventana.c | 42 ++++++++++++++++++++------------- 1 file changed, 26 insertions(+), 16 deletions(-)
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 51925d1..d93dd56 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -1025,22 +1025,32 @@ int power_init_board(void) p = pmic_get("LTC3676_PMIC"); if (p && !pmic_probe(p)) { puts("PMIC: LTC3676\n"); - /* set board-specific scalar to 1225mV for IMX6Q@1GHz */ - if (is_cpu_type(MXC_CPU_MX6Q)) { - /* mask PGOOD during SW1 transition */ - reg = 0x1d | LTC3676_PGOOD_MASK; - pmic_reg_write(p, LTC3676_DVB1B, reg); - /* set SW1 (VDD_SOC) to 1259mV */ - reg = 0x1d; - pmic_reg_write(p, LTC3676_DVB1A, reg); - - /* mask PGOOD during SW3 transition */ - reg = 0x1d | LTC3676_PGOOD_MASK; - pmic_reg_write(p, LTC3676_DVB3B, reg); - /*set SW3 (VDD_ARM) to 1259mV */ - reg = 0x1d; - pmic_reg_write(p, LTC3676_DVB3A, reg); - } + /* + * set board-specific scalar for max CPU frequency + * per CPU based on the LDO enabled Operating Ranges + * defined in the respective IMX6DQ and IMX6SDL + * datasheets. The voltage resulting from the R1/R2 + * feedback inputs on Ventana is 1308mV. Note that this + * is a bit shy of the Vmin of 1350mV in the datasheet + * for LDO enabled mode but is as high as we can go. + * + * We will rely on an OS kernel driver to properly + * regulate these per CPU operating point and use LDO + * bypass mode when using the higher frequency + * operating points to compensate as LDO bypass mode + * allows the rails be 125mV lower. + */ + /* mask PGOOD during SW1 transition */ + pmic_reg_write(p, LTC3676_DVB1B, + 0x1f | LTC3676_PGOOD_MASK); + /* set SW1 (VDD_SOC) */ + pmic_reg_write(p, LTC3676_DVB1A, 0x1f); + + /* mask PGOOD during SW3 transition */ + pmic_reg_write(p, LTC3676_DVB3B, + 0x1f | LTC3676_PGOOD_MASK); + /* set SW3 (VDD_ARM) */ + pmic_reg_write(p, LTC3676_DVB3A, 0x1f); } }
Add support for the USB mass storage gadget to enable access to on-board storage.
Example: Ventana > ums 0 mmc 0 # provide ums access to the uSD Ventana > ums 0 usb 0 # provide ums access to the first USB device Ventana > ums 0 sata 0 # provide ums access to an mSATA device
Signed-off-by: Tim Harvey tharvey@gateworks.com --- include/configs/gw_ventana.h | 12 ++++++++++++ 1 file changed, 12 insertions(+)
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 28c7815..3958ba7 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -203,6 +203,18 @@ #define CONFIG_NETCONSOLE #define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
+/* USB Mass Storage Gadget */ +#define CONFIG_USB_GADGET +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_USBDOWNLOAD_GADGET +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +/* Netchip IDs */ +#define CONFIG_G_DNL_VENDOR_NUM 0x0525 +#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5 +#define CONFIG_G_DNL_MANUFACTURER "Gateworks" + /* Framebuffer and LCD */ #define CONFIG_VIDEO #define CONFIG_VIDEO_IPUV3
Set the initrd_high env so that ramdisk range can be properly set.
See commit 7e9603e and README
Signed-off-by: Tim Harvey tharvey@gateworks.com --- include/configs/gw_ventana.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 3958ba7..658f574 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -333,6 +333,7 @@ \ "fdt_high=0xffffffff\0" \ "fdt_addr=0x18000000\0" \ + "initrd_high=0xffffffff\0" \ "loadfdt=" \ "if ${fsload} ${fdt_addr} boot/${fdt_file}; then " \ "echo Loaded DTB from boot/${fdt_file}; " \
Enable the 'i2c edid' command to query and display data from an attached HDMI monitor of LVDS display with an EDID device.
Example: Ventana > i2c dev 2 && i2c edid 0x50
Signed-off-by: Tim Harvey tharvey@gateworks.com --- include/configs/gw_ventana.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 658f574..797072e 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -98,6 +98,7 @@ #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_I2C_GSC 0 #define CONFIG_I2C_PMIC 1 +#define CONFIG_I2C_EDID
/* MMC Configs */ #define CONFIG_FSL_ESDHC
Signed-off-by: Tim Harvey tharvey@gateworks.com --- include/configs/gw_ventana.h | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 797072e..1f8a66e 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -112,6 +112,8 @@
/* Filesystem support */ #define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE #define CONFIG_CMD_FAT #define CONFIG_CMD_UBIFS #define CONFIG_DOS_PARTITION
Signed-off-by: Tim Harvey tharvey@gateworks.com --- board/gateworks/gw_ventana/gw_ventana.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index d93dd56..3914f28 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -89,16 +89,16 @@ DECLARE_GLOBAL_DATA_PTR; */ struct ventana_board_info ventana_info;
-int board_type; +static int board_type;
/* UART1: Function varies per baseboard */ -iomux_v3_cfg_t const uart1_pads[] = { +static iomux_v3_cfg_t const uart1_pads[] = { IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), };
/* UART2: Serial Console */ -iomux_v3_cfg_t const uart2_pads[] = { +static iomux_v3_cfg_t const uart2_pads[] = { IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), }; @@ -106,7 +106,7 @@ iomux_v3_cfg_t const uart2_pads[] = { #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C1: GSC */ -struct i2c_pads_info mx6q_i2c_pad_info0 = { +static struct i2c_pads_info mx6q_i2c_pad_info0 = { .scl = { .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC, .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC, @@ -118,7 +118,7 @@ struct i2c_pads_info mx6q_i2c_pad_info0 = { .gp = IMX_GPIO_NR(3, 28) } }; -struct i2c_pads_info mx6dl_i2c_pad_info0 = { +static struct i2c_pads_info mx6dl_i2c_pad_info0 = { .scl = { .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC, .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC, @@ -132,7 +132,7 @@ struct i2c_pads_info mx6dl_i2c_pad_info0 = { };
/* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */ -struct i2c_pads_info mx6q_i2c_pad_info1 = { +static struct i2c_pads_info mx6q_i2c_pad_info1 = { .scl = { .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC, .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC, @@ -144,7 +144,7 @@ struct i2c_pads_info mx6q_i2c_pad_info1 = { .gp = IMX_GPIO_NR(4, 13) } }; -struct i2c_pads_info mx6dl_i2c_pad_info1 = { +static struct i2c_pads_info mx6dl_i2c_pad_info1 = { .scl = { .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC, .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC, @@ -158,7 +158,7 @@ struct i2c_pads_info mx6dl_i2c_pad_info1 = { };
/* I2C3: Misc/Expansion */ -struct i2c_pads_info mx6q_i2c_pad_info2 = { +static struct i2c_pads_info mx6q_i2c_pad_info2 = { .scl = { .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC, .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC, @@ -170,7 +170,7 @@ struct i2c_pads_info mx6q_i2c_pad_info2 = { .gp = IMX_GPIO_NR(1, 6) } }; -struct i2c_pads_info mx6dl_i2c_pad_info2 = { +static struct i2c_pads_info mx6dl_i2c_pad_info2 = { .scl = { .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC, .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC, @@ -184,7 +184,7 @@ struct i2c_pads_info mx6dl_i2c_pad_info2 = { };
/* MMC */ -iomux_v3_cfg_t const usdhc3_pads[] = { +static iomux_v3_cfg_t const usdhc3_pads[] = { IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), @@ -196,7 +196,7 @@ iomux_v3_cfg_t const usdhc3_pads[] = { };
/* ENET */ -iomux_v3_cfg_t const enet_pads[] = { +static iomux_v3_cfg_t const enet_pads[] = { IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), @@ -220,7 +220,7 @@ iomux_v3_cfg_t const enet_pads[] = { };
/* NAND */ -iomux_v3_cfg_t const nfc_pads[] = { +static iomux_v3_cfg_t const nfc_pads[] = { IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)), IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)), IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)), @@ -285,7 +285,7 @@ static void setup_iomux_uart(void) }
#ifdef CONFIG_USB_EHCI_MX6 -iomux_v3_cfg_t const usb_pads[] = { +static iomux_v3_cfg_t const usb_pads[] = { IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG), IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG), /* OTG PWR */ @@ -328,7 +328,7 @@ int board_ehci_power(int port, int on) #endif /* CONFIG_USB_EHCI_MX6 */
#ifdef CONFIG_FSL_ESDHC -struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR }; +static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
int board_mmc_getcd(struct mmc *mmc) { @@ -734,7 +734,7 @@ struct ventana { int wdis; };
-struct ventana gpio_cfg[] = { +static struct ventana gpio_cfg[] = { /* GW5400proto */ { .gpio_pads = gw54xx_gpio_pads,
A board level errata causes the IMX6 watchdog to be unstable on the GW51xx RevA and RevB boards which can cause the watchdog to trip extremely early (under 5seconds) under certain operating conditions. Disable the watchdog node in the device-tree to work around this issue.
Signed-off-by: Tim Harvey tharvey@gateworks.com --- board/gateworks/gw_ventana/gw_ventana.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 3914f28..9ea24f4 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -1515,6 +1515,16 @@ int ft_board_setup(void *blob, bd_t *bd) { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */ }; const char *model = getenv("model"); + int i; + char rev = 0; + + /* determine board revision */ + for (i = sizeof(ventana_info.model) - 1; i > 0; i--) { + if (ventana_info.model[i] >= 'A') { + rev = ventana_info.model[i]; + break; + } + }
if (getenv("fdt_noauto")) { puts(" Skiping ft_board_setup (fdt_noauto defined)\n"); @@ -1540,6 +1550,17 @@ int ft_board_setup(void *blob, bd_t *bd) strlen((const char *)info->model) + 1);
/* + * disable wdog1/wdog2 nodes for GW51xx below revC to work around + * errata causing wdog timer to be unreliable. + */ + if (board_type == GW51xx && rev >= 'A' && rev < 'C') { + i = fdt_path_offset(blob, + "/soc/aips-bus@02000000/wdog@020bc000"); + if (i) + fdt_status_disabled(blob, i); + } + + /* * Peripheral Config: * remove nodes by alias path if EEPROM config tells us the * peripheral is not loaded on the board.
The GW551x is a small form factor board based on the IMX6 SoC that includes: * up to 512MB DDR3 memory * up to 2GB NAND flash * 1x miniPCIe socket (with USB) * HDMI out (micro-HDMI) * HDMI in (micro-HDMI) * TTL level I/O (supported by GW16111 breakout board): * I2C * 2x UART * CAN * 2x DIO (GPIO/PWM) * USB OTG
Signed-off-by: Tim Harvey tharvey@gateworks.com --- board/gateworks/gw_ventana/eeprom.c | 10 ++++- board/gateworks/gw_ventana/gw_ventana.c | 62 ++++++++++++++++++++++++----- board/gateworks/gw_ventana/gw_ventana_spl.c | 60 +++++++++++++++++++++++++++- board/gateworks/gw_ventana/ventana_eeprom.h | 1 + 4 files changed, 121 insertions(+), 12 deletions(-)
diff --git a/board/gateworks/gw_ventana/eeprom.c b/board/gateworks/gw_ventana/eeprom.c index ab3bab8..ba15969 100644 --- a/board/gateworks/gw_ventana/eeprom.c +++ b/board/gateworks/gw_ventana/eeprom.c @@ -81,8 +81,14 @@ read_eeprom(int bus, struct ventana_board_info *info) type = GW54xx; break; case '5': - type = GW552x; - break; + if (info->model[4] == '1') { + type = GW551x; + break; + } else if (info->model[4] == '2') { + type = GW552x; + break; + } + /* fall through */ default: printf("EEPROM: Unknown model in EEPROM: %s\n", info->model); type = GW_UNKNOWN; diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 9ea24f4..16f3e90 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -400,7 +400,7 @@ int board_eth_init(bd_t *bis) setup_iomux_enet();
#ifdef CONFIG_FEC_MXC - if (board_type != GW552x) + if (board_type != GW551x && board_type != GW552x) cpu_eth_init(bis); #endif
@@ -679,6 +679,15 @@ static iomux_v3_cfg_t const gw54xx_gpio_pads[] = { IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG), };
+static iomux_v3_cfg_t const gw551x_gpio_pads[] = { + /* PANLED# */ + IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), + /* PCI_RST# */ + IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), + /* PCIESKT_WDIS# */ + IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), +}; + static iomux_v3_cfg_t const gw552x_gpio_pads[] = { /* PANLEDG# */ IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), @@ -720,6 +729,7 @@ struct ventana { int num_pads; /* DIO pinmux/val */ struct dio_cfg dio_cfg[4]; + int num_gpios; /* various gpios (0 if non-existent) */ int leds[3]; int pcie_rst; @@ -765,6 +775,7 @@ static struct ventana gpio_cfg[] = { 4 }, }, + .num_gpios = 4, .leds = { IMX_GPIO_NR(4, 6), IMX_GPIO_NR(4, 10), @@ -808,6 +819,7 @@ static struct ventana gpio_cfg[] = { 4 }, }, + .num_gpios = 4, .leds = { IMX_GPIO_NR(4, 6), IMX_GPIO_NR(4, 10), @@ -850,6 +862,7 @@ static struct ventana gpio_cfg[] = { 0 }, }, + .num_gpios = 4, .leds = { IMX_GPIO_NR(4, 6), IMX_GPIO_NR(4, 7), @@ -894,6 +907,7 @@ static struct ventana gpio_cfg[] = { 0 }, }, + .num_gpios = 4, .leds = { IMX_GPIO_NR(4, 6), IMX_GPIO_NR(4, 7), @@ -937,6 +951,7 @@ static struct ventana gpio_cfg[] = { 4 }, }, + .num_gpios = 4, .leds = { IMX_GPIO_NR(4, 6), IMX_GPIO_NR(4, 7), @@ -952,10 +967,10 @@ static struct ventana gpio_cfg[] = { .wdis = IMX_GPIO_NR(5, 17), },
- /* GW552x */ + /* GW551x */ { - .gpio_pads = gw552x_gpio_pads, - .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2, + .gpio_pads = gw551x_gpio_pads, + .num_pads = ARRAY_SIZE(gw551x_gpio_pads)/2, .dio_cfg = { { { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, @@ -976,12 +991,39 @@ static struct ventana gpio_cfg[] = { 3 }, { - { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, - IMX_GPIO_NR(2, 10), - { 0, 0 }, - 0 + { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) }, + IMX_GPIO_NR(1, 18), + { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) }, + 4 + }, + }, + .num_gpios = 2, + .leds = { + IMX_GPIO_NR(4, 7), + }, + .pcie_rst = IMX_GPIO_NR(1, 0), + .wdis = IMX_GPIO_NR(7, 12), + }, + + /* GW552x */ + { + .gpio_pads = gw552x_gpio_pads, + .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2, + .dio_cfg = { + { + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, + IMX_GPIO_NR(1, 19), + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, + 2 + }, + { + { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, + IMX_GPIO_NR(1, 17), + { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, + 3 }, }, + .num_gpios = 4, .leds = { IMX_GPIO_NR(4, 6), IMX_GPIO_NR(4, 7), @@ -1138,6 +1180,8 @@ static void setup_board_gpio(int board) iomux_v3_cfg_t ctrl = DIO_PAD_CFG; unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1;
+ if (!cfg->gpio_padmux[0] && !cfg->gpio_padmux[1]) + continue; sprintf(arg, "dio%d", i); if (!hwconfig(arg)) continue; @@ -1430,7 +1474,7 @@ int misc_init_r(void) sprintf(fdt, "%s-%s.dtb", cputype, str); setenv("fdt_file1", fdt); } - if (board_type != GW552x) + if (board_type != GW551x && board_type != GW552x) str[4] = 'x'; str[5] = 'x'; str[6] = 0; diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index 97fd346..668e112 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -220,6 +220,50 @@ static struct mx6_ddr3_cfg mt41k256m16ha_125 = { * calibration - these are the various CPU/DDR3 combinations we support */
+static struct mx6_mmdc_calibration mx6dq_128x16_mmdc_calib = { + /* write leveling calibration determine */ + .p0_mpwldectrl0 = 0x00190017, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x43380347, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x3C313539, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x36393C39, +}; + +static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = { + /* write leveling calibration determine */ + .p0_mpwldectrl0 = 0x00190017, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x43380347, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x3C313539, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x36393C39, +}; + +static struct mx6_mmdc_calibration mx6sdl_128x16_mmdc_calib = { + /* write leveling calibration determine */ + .p0_mpwldectrl0 = 0x00190017, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x43380347, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x3C313539, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x36393C39, +}; + +static struct mx6_mmdc_calibration mx6sdl_256x16_mmdc_calib = { + /* write leveling calibration determine */ + .p0_mpwldectrl0 = 0x00190017, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x43380347, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x3C313539, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x36393C39, +}; + static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = { /* write leveling calibration determine */ .p0_mpwldectrl0 = 0x00190017, @@ -363,7 +407,21 @@ static void spl_dram_init(int width, int size_mb, int board_model) * mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc) * mx6_ddr_cfg - chip specific timing/layout details */ - if (width == 32 && size_mb == 512) { + if (width == 16 && size_mb == 256) { + mem = &mt41k128m16jt_125; + if (is_cpu_type(MXC_CPU_MX6Q)) + calib = &mx6dq_128x16_mmdc_calib; + else + calib = &mx6sdl_128x16_mmdc_calib; + debug("2gB density\n"); + } else if (width == 16 && size_mb == 512) { + mem = &mt41k256m16ha_125; + if (is_cpu_type(MXC_CPU_MX6Q)) + calib = &mx6dq_256x16_mmdc_calib; + else + calib = &mx6sdl_256x16_mmdc_calib; + debug("4gB density\n"); + } else if (width == 32 && size_mb == 512) { mem = &mt41k128m16jt_125; if (is_cpu_type(MXC_CPU_MX6Q)) calib = &mx6dq_128x32_mmdc_calib; diff --git a/board/gateworks/gw_ventana/ventana_eeprom.h b/board/gateworks/gw_ventana/ventana_eeprom.h index af12711..daff375 100644 --- a/board/gateworks/gw_ventana/ventana_eeprom.h +++ b/board/gateworks/gw_ventana/ventana_eeprom.h @@ -109,6 +109,7 @@ enum { GW52xx, GW53xx, GW54xx, + GW551x, GW552x, GW_UNKNOWN, GW_BADCRC,
We have encountered many USB storage devices that require more warm-up than the spec allows for.
Signed-off-by: Tim Harvey tharvey@gateworks.com --- include/configs/gw_ventana.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 1f8a66e..0069120 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -326,6 +326,7 @@ "dio0:mode=gpio;dio1:mode=gpio;dio2:mode=gpio;dio3:mode=gpio\0" \
#define CONFIG_EXTRA_ENV_SETTINGS_COMMON \ + "usb_pgood_delay=2000\0" \ "console=ttymxc1\0" \ "bootdevs=usb mmc sata flash\0" \ HWCONFIG_DEFAULT \
Signed-off-by: Tim Harvey tharvey@gateworks.com --- board/gateworks/gw_ventana/gw_ventana.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 16f3e90..9884616 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -1030,6 +1030,7 @@ static struct ventana gpio_cfg[] = { IMX_GPIO_NR(4, 15), }, .pcie_rst = IMX_GPIO_NR(1, 29), + .wdis = IMX_GPIO_NR(7, 12), }, };
Signed-off-by: Tim Harvey tharvey@gateworks.com --- board/gateworks/gw_ventana/gw_ventana.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 9884616..2906dcc 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -397,11 +397,11 @@ int board_phy_config(struct phy_device *phydev)
int board_eth_init(bd_t *bis) { - setup_iomux_enet(); - #ifdef CONFIG_FEC_MXC - if (board_type != GW551x && board_type != GW552x) + if (board_type != GW551x && board_type != GW552x) { + setup_iomux_enet(); cpu_eth_init(bis); + } #endif
#ifdef CONFIG_E1000
Added support in default boot scripts to find kernel/dtbs on a boot volume separate from rootfs volume.
Signed-off-by: Tim Harvey tharvey@gateworks.com --- include/configs/gw_ventana.h | 44 +++++++++++++++++++++++++++----------------- 1 file changed, 27 insertions(+), 17 deletions(-)
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 0069120..684f347 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -338,28 +338,29 @@ "fdt_high=0xffffffff\0" \ "fdt_addr=0x18000000\0" \ "initrd_high=0xffffffff\0" \ + "bootdir=boot\0" \ "loadfdt=" \ - "if ${fsload} ${fdt_addr} boot/${fdt_file}; then " \ - "echo Loaded DTB from boot/${fdt_file}; " \ - "elif ${fsload} ${fdt_addr} boot/${fdt_file1}; then " \ - "echo Loaded DTB from boot/${fdt_file1}; " \ - "elif ${fsload} ${fdt_addr} boot/${fdt_file2}; then " \ - "echo Loaded DTB from boot/${fdt_file2}; " \ + "if ${fsload} ${fdt_addr} ${bootdir}/${fdt_file}; then " \ + "echo Loaded DTB from ${bootdir}/${fdt_file}; " \ + "elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file1}; then " \ + "echo Loaded DTB from ${bootdir}/${fdt_file1}; " \ + "elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file2}; then " \ + "echo Loaded DTB from ${bootdir}/${fdt_file2}; " \ "fi\0" \ \ - "script=boot/6x_bootscript-ventana\0" \ + "script=6x_bootscript-ventana\0" \ "loadscript=" \ - "if ${fsload} ${loadaddr} ${script}; then " \ + "if ${fsload} ${loadaddr} ${bootdir}/${script}; then " \ "source; " \ "fi\0" \ \ - "uimage=boot/uImage\0" \ + "uimage=uImage\0" \ "mmc_root=/dev/mmcblk0p1 rootfstype=ext4 rootwait rw\0" \ "mmc_boot=" \ "setenv fsload 'ext2load mmc 0:1'; " \ "mmc dev 0 && mmc rescan && " \ "run loadscript; " \ - "if ${fsload} ${loadaddr} ${uimage}; then " \ + "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ "setenv bootargs console=${console},${baudrate} " \ "root=/dev/mmcblk0p1 rootfstype=ext4 " \ "rootwait rw ${video} ${extra}; " \ @@ -373,7 +374,7 @@ "sata_boot=" \ "setenv fsload 'ext2load sata 0:1'; sata init && " \ "run loadscript; " \ - "if ${fsload} ${loadaddr} ${uimage}; then " \ + "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ "setenv bootargs console=${console},${baudrate} " \ "root=/dev/sda1 rootfstype=ext4 " \ "rootwait rw ${video} ${extra}; " \ @@ -386,7 +387,7 @@ "usb_boot=" \ "setenv fsload 'ext2load usb 0:1'; usb start && usb dev 0 && " \ "run loadscript; " \ - "if ${fsload} ${loadaddr} ${uimage}; then " \ + "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ "setenv bootargs console=${console},${baudrate} " \ "root=/dev/sda1 rootfstype=ext4 " \ "rootwait rw ${video} ${extra}; " \ @@ -429,8 +430,8 @@ #else #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_EXTRA_ENV_SETTINGS_COMMON \ - "image_rootfs=openwrt-imx6-ventana-rootfs.ubi\0" \ \ + "image_rootfs=openwrt-imx6-ventana-rootfs.ubi\0" \ "nand_update=echo Updating NAND from ${serverip}:${image_rootfs}...; " \ "tftp ${loadaddr} ${image_rootfs} && " \ "nand erase.part rootfs && " \ @@ -438,12 +439,21 @@ \ "flash_boot=" \ "setenv fsload 'ubifsload'; " \ - "ubi part rootfs && ubifsmount ubi0:rootfs; " \ + "ubi part rootfs; " \ + "if ubi check boot; then " \ + "ubifsmount ubi0:boot; " \ + "setenv root ubi0:rootfs ubi.mtd=2 " \ + "rootfstype=squashfs,ubifs; " \ + "setenv bootdir; " \ + "elif ubi check rootfs; then " \ + "ubifsmount ubi0:rootfs; " \ + "setenv root ubi0:rootfs ubi.mtd=2 " \ + "rootfstype=ubifs; " \ + "fi; " \ "run loadscript; " \ - "if ${fsload} ${loadaddr} ${uimage}; then " \ + "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ "setenv bootargs console=${console},${baudrate} " \ - "root=ubi0:rootfs ubi.mtd=2 " \ - "rootfstype=ubifs ${video} ${extra}; " \ + "root=${root} ${video} ${extra}; " \ "if run loadfdt && fdt addr ${fdt_addr}; then " \ "ubifsumount; " \ "bootm ${loadaddr} - ${fdt_addr}; " \
The min/max of each depends not only on board but on CPU. Simplify by removing this rarely needed and difficult to maintain feature and just display the rails and their values.
Signed-off-by: Tim Harvey tharvey@gateworks.com --- board/gateworks/gw_ventana/gsc.c | 53 +++++++++++++++++----------------------- 1 file changed, 22 insertions(+), 31 deletions(-)
diff --git a/board/gateworks/gw_ventana/gsc.c b/board/gateworks/gw_ventana/gsc.c index a34a9a8..27bfeae 100644 --- a/board/gateworks/gw_ventana/gsc.c +++ b/board/gateworks/gw_ventana/gsc.c @@ -13,8 +13,6 @@
#include "gsc.h"
-#define MINMAX(n, percent) ((n)*(100-percent)/100), ((n)*(100+percent)/100) - /* * The Gateworks System Controller will fail to ACK a master transaction if * it is busy, which can occur during its 1HZ timer tick while reading ADC's. @@ -62,8 +60,7 @@ int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) }
#ifdef CONFIG_CMD_GSC -static void read_hwmon(const char *name, uint reg, uint size, uint low, - uint high) +static void read_hwmon(const char *name, uint reg, uint size) { unsigned char buf[3]; uint ui; @@ -75,15 +72,10 @@ static void read_hwmon(const char *name, uint reg, uint size, uint low, } else { ui = buf[0] | (buf[1]<<8) | (buf[2]<<16); if (ui == 0xffffff) - printf("invalid"); - else if (ui < low) - printf("%d Failed - Low", ui); - else if (ui > high) - printf("%d Failed - High", ui); + puts("invalid\n"); else - printf("%d", ui); + printf("%d\n", ui); } - puts("\n"); }
int do_gsc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) @@ -91,35 +83,34 @@ int do_gsc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) const char *model = getenv("model");
i2c_set_bus_num(0); - read_hwmon("Temp", GSC_HWMON_TEMP, 2, 0, 9000); - read_hwmon("VIN", GSC_HWMON_VIN, 3, 8000, 60000); - read_hwmon("VBATT", GSC_HWMON_VBATT, 3, 1800, 3500); - read_hwmon("VDD_3P3", GSC_HWMON_VDD_3P3, 3, MINMAX(3300, 10)); - read_hwmon("VDD_HIGH", GSC_HWMON_VDD_HIGH, 3, MINMAX(3000, 10)); - read_hwmon("VDD_DDR", GSC_HWMON_VDD_DDR, 3, MINMAX(1500, 10)); - read_hwmon("VDD_5P0", GSC_HWMON_VDD_5P0, 3, MINMAX(5000, 10)); - read_hwmon("VDD_2P5", GSC_HWMON_VDD_2P5, 3, MINMAX(2500, 10)); - read_hwmon("VDD_1P8", GSC_HWMON_VDD_1P8, 3, MINMAX(1800, 10)); - + read_hwmon("Temp", GSC_HWMON_TEMP, 2); + read_hwmon("VIN", GSC_HWMON_VIN, 3); + read_hwmon("VBATT", GSC_HWMON_VBATT, 3); + read_hwmon("VDD_3P3", GSC_HWMON_VDD_3P3, 3); + read_hwmon("VDD_HIGH", GSC_HWMON_VDD_HIGH, 3); + read_hwmon("VDD_DDR", GSC_HWMON_VDD_DDR, 3); + read_hwmon("VDD_5P0", GSC_HWMON_VDD_5P0, 3); + read_hwmon("VDD_2P5", GSC_HWMON_VDD_2P5, 3); + read_hwmon("VDD_1P8", GSC_HWMON_VDD_1P8, 3); switch (model[3]) { case '1': /* GW51xx */ - read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1175, 10)); - read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1175, 10)); + read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3); + read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3); break; case '2': /* GW52xx */ case '3': /* GW53xx */ - read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1175, 10)); - read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1175, 10)); - read_hwmon("VDD_1P0", GSC_HWMON_VDD_1P0, 3, MINMAX(1000, 10)); + read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3); + read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3); + read_hwmon("VDD_1P0", GSC_HWMON_VDD_1P0, 3); break; case '4': /* GW54xx */ - read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1375, 10)); - read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1375, 10)); - read_hwmon("VDD_1P0", GSC_HWMON_VDD_1P0, 3, MINMAX(1000, 10)); + read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3); + read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3); + read_hwmon("VDD_1P0", GSC_HWMON_VDD_1P0, 3); break; case '5': /* GW55xx */ - read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3, MINMAX(1175, 10)); - read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3, MINMAX(1175, 10)); + read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3); + read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3); break; } return 0;
Certain OS bootscripts need to know how much memory a board has to adjust kernel parameters (namely Android). This allows those boards to determine mem size in MB.
Signed-off-by: Tim Harvey tharvey@gateworks.com --- board/gateworks/gw_ventana/gw_ventana.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 2906dcc..307ffa5 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -1498,6 +1498,10 @@ int misc_init_r(void) /* board serial-number */ sprintf(str, "%6d", info->serial); setenv("serial#", str); + + /* memory MB */ + sprintf(str, "%d", (int) (gd->ram_size >> 20)); + setenv("mem_mb", str); }
Add a new voltage rail added in various -C revision PCB's.
Additionally make VDD_CORE, VDD_SOC, and VDD_IO2 common as all Ventana boards have those.
Signed-off-by: Tim Harvey tharvey@gateworks.com --- board/gateworks/gw_ventana/gsc.c | 19 +++++++++---------- board/gateworks/gw_ventana/gsc.h | 4 +++- 2 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/board/gateworks/gw_ventana/gsc.c b/board/gateworks/gw_ventana/gsc.c index 27bfeae..a62f128 100644 --- a/board/gateworks/gw_ventana/gsc.c +++ b/board/gateworks/gw_ventana/gsc.c @@ -87,30 +87,29 @@ int do_gsc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) read_hwmon("VIN", GSC_HWMON_VIN, 3); read_hwmon("VBATT", GSC_HWMON_VBATT, 3); read_hwmon("VDD_3P3", GSC_HWMON_VDD_3P3, 3); + read_hwmon("VDD_ARM", GSC_HWMON_VDD_CORE, 3); + read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3); read_hwmon("VDD_HIGH", GSC_HWMON_VDD_HIGH, 3); read_hwmon("VDD_DDR", GSC_HWMON_VDD_DDR, 3); read_hwmon("VDD_5P0", GSC_HWMON_VDD_5P0, 3); read_hwmon("VDD_2P5", GSC_HWMON_VDD_2P5, 3); read_hwmon("VDD_1P8", GSC_HWMON_VDD_1P8, 3); + read_hwmon("VDD_IO2", GSC_HWMON_VDD_IO2, 3); switch (model[3]) { case '1': /* GW51xx */ - read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3); - read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3); + read_hwmon("VDD_IO3", GSC_HWMON_VDD_IO4, 3); /* -C rev */ break; case '2': /* GW52xx */ + break; case '3': /* GW53xx */ - read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3); - read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3); - read_hwmon("VDD_1P0", GSC_HWMON_VDD_1P0, 3); + read_hwmon("VDD_IO4", GSC_HWMON_VDD_IO4, 3); /* -C rev */ + read_hwmon("VDD_GPS", GSC_HWMON_VDD_IO3, 3); break; case '4': /* GW54xx */ - read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3); - read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3); - read_hwmon("VDD_1P0", GSC_HWMON_VDD_1P0, 3); + read_hwmon("VDD_IO3", GSC_HWMON_VDD_IO4, 3); /* -C rev */ + read_hwmon("VDD_GPS", GSC_HWMON_VDD_IO3, 3); break; case '5': /* GW55xx */ - read_hwmon("VDD_CORE", GSC_HWMON_VDD_CORE, 3); - read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3); break; } return 0; diff --git a/board/gateworks/gw_ventana/gsc.h b/board/gateworks/gw_ventana/gsc.h index da970c3..0a70774 100644 --- a/board/gateworks/gw_ventana/gsc.h +++ b/board/gateworks/gw_ventana/gsc.h @@ -50,8 +50,10 @@ enum { GSC_HWMON_VDD_DDR = 0x17, GSC_HWMON_VDD_SOC = 0x11, GSC_HWMON_VDD_1P8 = 0x1d, + GSC_HWMON_VDD_IO2 = 0x20, GSC_HWMON_VDD_2P5 = 0x23, - GSC_HWMON_VDD_1P0 = 0x20, + GSC_HWMON_VDD_IO3 = 0x26, + GSC_HWMON_VDD_IO4 = 0x29, };
/*
The GW551x-A revision does not have the CSI0_DATA_EN pin connected, therefore we need to make sure that signal is not muxed to the CSI_DATA_EN signal internally and do so by steering it to the unused GPIO5_IO20.
We do this so that the kernel device-tree can properly define the signal for RevB and beyond boards that do have this hooked up properly and require it.
Signed-off-by: Tim Harvey tharvey@gateworks.com --- board/gateworks/gw_ventana/gw_ventana.c | 35 +++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+)
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 307ffa5..068c726 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -1610,6 +1610,41 @@ int ft_board_setup(void *blob, bd_t *bd) }
/* + * isolate CSI0_DATA_EN for GW551x below revB to work around + * errata causing non functional digital video in (it is not hooked up) + */ + else if (board_type == GW551x && rev == 'A') { + u32 *range = NULL; + int len; + const u32 *handle = NULL; + + i = fdt_node_offset_by_compatible(blob, -1, + "fsl,imx-tda1997x-video"); + if (i) + handle = fdt_getprop(blob, i, "pinctrl-0", NULL); + if (handle) + i = fdt_node_offset_by_phandle(blob, + fdt32_to_cpu(*handle)); + if (i) + range = (u32 *)fdt_getprop(blob, i, "fsl,pins", &len); + if (range) { + len /= sizeof(u32); + for (i = 0; i < len; i += 6) { + u32 mux_reg = fdt32_to_cpu(range[i+0]); + u32 conf_reg = fdt32_to_cpu(range[i+1]); + /* mux PAD_CSI0_DATA_EN to GPIO */ + if (is_cpu_type(MXC_CPU_MX6Q) && + mux_reg == 0x260 && conf_reg == 0x630) + range[i+3] = cpu_to_fdt32(0x5); + else if (!is_cpu_type(MXC_CPU_MX6Q) && + mux_reg == 0x08c && conf_reg == 0x3a0) + range[i+3] = cpu_to_fdt32(0x5); + } + fdt_setprop_inplace(blob, i, "fsl,pins", range, len); + } + } + + /* * Peripheral Config: * remove nodes by alias path if EEPROM config tells us the * peripheral is not loaded on the board.
Updated 16bit DDR calibration using values obtained from running the i.MX6 DDR Stress Test tool over a set of boards over full operationg temperature.
Signed-off-by: Tim Harvey tharvey@gateworks.com --- board/gateworks/gw_ventana/gw_ventana_spl.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index 668e112..baa2c6e 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -233,13 +233,15 @@ static struct mx6_mmdc_calibration mx6dq_128x16_mmdc_calib = {
static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = { /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0x00190017, + .p0_mpwldectrl0 = 0x001B0016, + .p0_mpwldectrl1 = 0x000C000E, /* Read DQS Gating calibration */ - .p0_mpdgctrl0 = 0x43380347, + .p0_mpdgctrl0 = 0x4324033A, + .p0_mpdgctrl1 = 0x00000000, /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0x3C313539, + .p0_mprddlctl = 0x40403438, /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0x36393C39, + .p0_mpwrdlctl = 0x40403D36, };
static struct mx6_mmdc_calibration mx6sdl_128x16_mmdc_calib = { @@ -255,13 +257,15 @@ static struct mx6_mmdc_calibration mx6sdl_128x16_mmdc_calib = {
static struct mx6_mmdc_calibration mx6sdl_256x16_mmdc_calib = { /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0x00190017, + .p0_mpwldectrl0 = 0x00420043, + .p0_mpwldectrl1 = 0x0016001A, /* Read DQS Gating calibration */ - .p0_mpdgctrl0 = 0x43380347, + .p0_mpdgctrl0 = 0x4238023B, + .p0_mpdgctrl1 = 0x00000000, /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0x3C313539, + .p0_mprddlctl = 0x40404849, /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0x36393C39, + .p0_mpwrdlctl = 0x40402E2F, };
static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = {
The calibration data for dual 2Gb density chips can be used for a single 2Gb density chip.
Signed-off-by: Tim Harvey tharvey@gateworks.com --- board/gateworks/gw_ventana/gw_ventana_spl.c | 27 +++------------------------ 1 file changed, 3 insertions(+), 24 deletions(-)
diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index baa2c6e..b839b89 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -220,17 +220,6 @@ static struct mx6_ddr3_cfg mt41k256m16ha_125 = { * calibration - these are the various CPU/DDR3 combinations we support */
-static struct mx6_mmdc_calibration mx6dq_128x16_mmdc_calib = { - /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0x00190017, - /* Read DQS Gating calibration */ - .p0_mpdgctrl0 = 0x43380347, - /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0x3C313539, - /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0x36393C39, -}; - static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = { /* write leveling calibration determine */ .p0_mpwldectrl0 = 0x001B0016, @@ -244,17 +233,6 @@ static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = { .p0_mpwrdlctl = 0x40403D36, };
-static struct mx6_mmdc_calibration mx6sdl_128x16_mmdc_calib = { - /* write leveling calibration determine */ - .p0_mpwldectrl0 = 0x00190017, - /* Read DQS Gating calibration */ - .p0_mpdgctrl0 = 0x43380347, - /* Read Calibration: DQS delay relative to DQ read access */ - .p0_mprddlctl = 0x3C313539, - /* Write Calibration: DQ/DM delay relative to DQS write access */ - .p0_mpwrdlctl = 0x36393C39, -}; - static struct mx6_mmdc_calibration mx6sdl_256x16_mmdc_calib = { /* write leveling calibration determine */ .p0_mpwldectrl0 = 0x00420043, @@ -412,11 +390,12 @@ static void spl_dram_init(int width, int size_mb, int board_model) * mx6_ddr_cfg - chip specific timing/layout details */ if (width == 16 && size_mb == 256) { + /* 1x 2Gb density chip - same calib as 2x 2Gb */ mem = &mt41k128m16jt_125; if (is_cpu_type(MXC_CPU_MX6Q)) - calib = &mx6dq_128x16_mmdc_calib; + calib = &mx6dq_128x32_mmdc_calib; else - calib = &mx6sdl_128x16_mmdc_calib; + calib = &mx6sdl_128x32_mmdc_calib; debug("2gB density\n"); } else if (width == 16 && size_mb == 512) { mem = &mt41k256m16ha_125;
Certain older kernels in use by some customers erroneously define a uart3 for GW54xx with a pinmux that conflicts with NAND. This will remove that node to avoid such conflicts.
Signed-off-by: Tim Harvey tharvey@gateworks.com --- board/gateworks/gw_ventana/gw_ventana.c | 11 +++++++++++ 1 file changed, 11 insertions(+)
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 068c726..06611b5 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -1599,6 +1599,17 @@ int ft_board_setup(void *blob, bd_t *bd) strlen((const char *)info->model) + 1);
/* + * disable serial2 node for GW54xx for compatibility with older + * 3.10.x kernel that improperly had this node enabled in the DT + */ + if (board_type == GW54xx) { + i = fdt_path_offset(blob, + "/soc/aips-bus@02100000/serial@021ec000"); + if (i) + fdt_del_node(blob, i); + } + + /* * disable wdog1/wdog2 nodes for GW51xx below revC to work around * errata causing wdog timer to be unreliable. */
Hi Tim,
I have no problem with the whole series, I will start to apply. Just a couple of questions:
On 08/04/2015 21:54, Tim Harvey wrote:
Certain older kernels in use by some customers erroneously define a uart3 for GW54xx with a pinmux that conflicts with NAND. This will remove that node to avoid such conflicts.
Signed-off-by: Tim Harvey tharvey@gateworks.com
board/gateworks/gw_ventana/gw_ventana.c | 11 +++++++++++ 1 file changed, 11 insertions(+)
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 068c726..06611b5 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -1599,6 +1599,17 @@ int ft_board_setup(void *blob, bd_t *bd) strlen((const char *)info->model) + 1);
/*
* disable serial2 node for GW54xx for compatibility with older* 3.10.x kernel that improperly had this node enabled in the DT*/
I understand the issue, but I guess you have a dtb file for your (Freescale) 3.10 kernel and another one for kernel mainline. So why this issue should be fixed here and not in the related DTS file ?
- if (board_type == GW54xx) {
i = fdt_path_offset(blob,"/soc/aips-bus@02100000/serial@021ec000");if (i)fdt_del_node(blob, i);- }
- /*
*/
- disable wdog1/wdog2 nodes for GW51xx below revC to work around
- errata causing wdog timer to be unreliable.
Best regards, Stefano Babic
On Thu, Apr 16, 2015 at 12:46 AM, Stefano Babic sbabic@denx.de wrote:
Hi Tim,
I have no problem with the whole series, I will start to apply. Just a couple of questions:
On 08/04/2015 21:54, Tim Harvey wrote:
Certain older kernels in use by some customers erroneously define a uart3 for GW54xx with a pinmux that conflicts with NAND. This will remove that node to avoid such conflicts.
Signed-off-by: Tim Harvey tharvey@gateworks.com
board/gateworks/gw_ventana/gw_ventana.c | 11 +++++++++++ 1 file changed, 11 insertions(+)
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 068c726..06611b5 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -1599,6 +1599,17 @@ int ft_board_setup(void *blob, bd_t *bd) strlen((const char *)info->model) + 1);
/*
* disable serial2 node for GW54xx for compatibility with older* 3.10.x kernel that improperly had this node enabled in the DT*/I understand the issue, but I guess you have a dtb file for your (Freescale) 3.10 kernel and another one for kernel mainline. So why this issue should be fixed here and not in the related DTS file ?
Stefano,
I only have a single dtb but in this case a customer has an older kernel with a bug in the dtb and for various reasons required a bootloader fix (rest of firmware was locked down). In their opinion a previous bootloader worked (and I never dug in to find out just why... likely a bootloader bug at the time) and the new one received on newer boards did not (with their locked down software). I can work around this in a bootloader script for them if you want to drop this particular one.
Tim
On 16/04/2015 15:20, Tim Harvey wrote:
On Thu, Apr 16, 2015 at 12:46 AM, Stefano Babic sbabic@denx.de wrote:
Hi Tim,
I have no problem with the whole series, I will start to apply. Just a couple of questions:
On 08/04/2015 21:54, Tim Harvey wrote:
Certain older kernels in use by some customers erroneously define a uart3 for GW54xx with a pinmux that conflicts with NAND. This will remove that node to avoid such conflicts.
Signed-off-by: Tim Harvey tharvey@gateworks.com
board/gateworks/gw_ventana/gw_ventana.c | 11 +++++++++++ 1 file changed, 11 insertions(+)
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 068c726..06611b5 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -1599,6 +1599,17 @@ int ft_board_setup(void *blob, bd_t *bd) strlen((const char *)info->model) + 1);
/*
* disable serial2 node for GW54xx for compatibility with older* 3.10.x kernel that improperly had this node enabled in the DT*/I understand the issue, but I guess you have a dtb file for your (Freescale) 3.10 kernel and another one for kernel mainline. So why this issue should be fixed here and not in the related DTS file ?
Stefano,
I only have a single dtb but in this case a customer has an older kernel with a bug in the dtb and for various reasons required a bootloader fix (rest of firmware was locked down).
ok, got it.
In their opinion a previous bootloader worked (and I never dug in to find out just why... likely a bootloader bug at the time) and the new one received on newer boards did not (with their locked down software). I can work around this in a bootloader script for them if you want to drop this particular one.
No, it is fine - thanks for clarifications.
Stefano
Add LVDS support for two LVDS LCD displays: DLC-700JMGT4 - 7" 1024x600 DLC-800FIGT3 - 8" 1024x768
Signed-off-by: Tim Harvey tharvey@gateworks.com --- board/gateworks/gw_ventana/gw_ventana.c | 42 +++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+)
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 06611b5..d8eeb6d 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -495,6 +495,48 @@ struct display_info_t const displays[] = {{ .vsync_len = 10, .sync = FB_SYNC_EXT, .vmode = FB_VMODE_NONINTERLACED +} }, { + /* DLC700JMG-T-4 */ + .bus = 0, + .addr = 0, + .detect = NULL, + .enable = enable_lvds, + .pixfmt = IPU_PIX_FMT_LVDS666, + .mode = { + .name = "DLC700JMGT4", + .refresh = 60, + .xres = 1024, /* 1024x600active pixels */ + .yres = 600, + .pixclock = 15385, /* 64MHz */ + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +} }, { + /* DLC800FIG-T-3 */ + .bus = 0, + .addr = 0, + .detect = NULL, + .enable = enable_lvds, + .pixfmt = IPU_PIX_FMT_LVDS666, + .mode = { + .name = "DLC800FIGT3", + .refresh = 60, + .xres = 1024, /* 1024x768 active pixels */ + .yres = 768, + .pixclock = 15385, /* 64MHz */ + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED } } }; size_t display_count = ARRAY_SIZE(displays);
Configure kernel device-tree for display from env var. This is useful to specify the display present when the device-tree supports multiple non-detectable display configurations.
Signed-off-by: Tim Harvey tharvey@gateworks.com --- board/gateworks/gw_ventana/gw_ventana.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index d8eeb6d..871af09 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -1606,6 +1606,7 @@ int ft_board_setup(void *blob, bd_t *bd) { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */ }; const char *model = getenv("model"); + const char *display = getenv("display"); int i; char rev = 0;
@@ -1626,6 +1627,13 @@ int ft_board_setup(void *blob, bd_t *bd) puts(" Updating MTD partitions...\n"); fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+ /* Update display timings from display env var */ + if (display) { + if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"), + display) >= 0) + printf(" Set display timings for %s...\n", display); + } + if (!model) { puts("invalid board info: Leaving FDT fully enabled\n"); return 0;
This adds information about the Gateworks System Controller to the gsc command such as the firmware version, firmware CRC and status of the GSC watchdog (if its enabled and if its tripped).
Additionally the 'gsc wd' command can be used to enable or disable the watchdog with the following usage: gsc wd enable [30|60] gsc wd disable
Note that the GSC registers are battery-backed by the GSC coincell so once eanbled, they remain enabled across power-cycles or until either the GSC firmware has been updated or FLASH has been re-programmed by the Gateworks JTAG adapter.
Signed-off-by: Tim Harvey tharvey@gateworks.com --- board/gateworks/gw_ventana/gsc.c | 80 ++++++++++++++++++++++++++++++--- board/gateworks/gw_ventana/gsc.h | 6 ++- board/gateworks/gw_ventana/gw_ventana.c | 18 +------- 3 files changed, 81 insertions(+), 23 deletions(-)
diff --git a/board/gateworks/gw_ventana/gsc.c b/board/gateworks/gw_ventana/gsc.c index a62f128..718e165 100644 --- a/board/gateworks/gw_ventana/gsc.c +++ b/board/gateworks/gw_ventana/gsc.c @@ -59,7 +59,6 @@ int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) return ret; }
-#ifdef CONFIG_CMD_GSC static void read_hwmon(const char *name, uint reg, uint size) { unsigned char buf[3]; @@ -78,11 +77,29 @@ static void read_hwmon(const char *name, uint reg, uint size) } }
-int do_gsc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int gsc_info(int verbose) { const char *model = getenv("model"); + unsigned char buf[16];
i2c_set_bus_num(0); + if (gsc_i2c_read(GSC_SC_ADDR, 0, 1, buf, 16)) + return CMD_RET_FAILURE; + + printf("GSC: v%d", buf[GSC_SC_FWVER]); + printf(" 0x%04x", buf[GSC_SC_FWCRC] | buf[GSC_SC_FWCRC+1]<<8); + printf(" WDT:%sabled", (buf[GSC_SC_CTRL1] & (1<<GSC_SC_CTRL1_WDEN)) + ? "en" : "dis"); + if (buf[GSC_SC_STATUS] & (1 << GSC_SC_IRQ_WATCHDOG)) { + buf[GSC_SC_STATUS] &= ~(1 << GSC_SC_IRQ_WATCHDOG); + puts(" WDT_RESET"); + gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, + &buf[GSC_SC_STATUS], 1); + } + puts("\n"); + if (!verbose) + return CMD_RET_SUCCESS; + read_hwmon("Temp", GSC_HWMON_TEMP, 2); read_hwmon("VIN", GSC_HWMON_VIN, 3); read_hwmon("VBATT", GSC_HWMON_VBATT, 3); @@ -115,9 +132,60 @@ int do_gsc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; }
-U_BOOT_CMD(gsc, 1, 1, do_gsc, - "GSC test", - "" -); +#ifdef CONFIG_CMD_GSC +static int do_gsc_wd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + unsigned char reg; + + if (argc < 2) + return CMD_RET_USAGE; + + if (strcasecmp(argv[1], "enable") == 0) { + int timeout = 0; + + if (argc > 2) + timeout = simple_strtoul(argv[2], NULL, 10); + i2c_set_bus_num(0); + if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) + return CMD_RET_FAILURE; + reg &= ~((1 << GSC_SC_CTRL1_WDEN) | (1 << GSC_SC_CTRL1_WDTIME)); + if (timeout == 60) + reg |= (1 << GSC_SC_CTRL1_WDTIME); + else + timeout = 30; + reg |= (1 << GSC_SC_CTRL1_WDEN); + if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) + return CMD_RET_FAILURE; + printf("GSC Watchdog enabled with timeout=%d seconds\n", + timeout); + } else if (strcasecmp(argv[1], "disable") == 0) { + i2c_set_bus_num(0); + if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) + return CMD_RET_FAILURE; + reg &= ~((1 << GSC_SC_CTRL1_WDEN) | (1 << GSC_SC_CTRL1_WDTIME)); + if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) + return CMD_RET_FAILURE; + printf("GSC Watchdog disabled\n"); + } else { + return CMD_RET_USAGE; + } + return CMD_RET_SUCCESS; +} + +static int do_gsc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if (argc < 2) + return gsc_info(1); + + if (strcasecmp(argv[1], "wd") == 0) + return do_gsc_wd(cmdtp, flag, --argc, ++argv); + + return CMD_RET_USAGE; +} + +U_BOOT_CMD( + gsc, 4, 1, do_gsc, "GSC configuration", + "[wd enable [30|60]]|[wd disable]\n" + );
#endif /* CONFIG_CMD_GSC */ diff --git a/board/gateworks/gw_ventana/gsc.h b/board/gateworks/gw_ventana/gsc.h index 0a70774..2d4969e 100644 --- a/board/gateworks/gw_ventana/gsc.h +++ b/board/gateworks/gw_ventana/gsc.h @@ -19,12 +19,15 @@ enum { GSC_SC_CTRL0 = 0x00, GSC_SC_CTRL1 = 0x01, GSC_SC_STATUS = 0x0a, + GSC_SC_FWCRC = 0x0c, GSC_SC_FWVER = 0x0e, };
/* System Controller Control1 bits */ enum { - GSC_SC_CTRL1_WDDIS = 7, /* 1 = disable watchdog */ + GSC_SC_CTRL1_WDTIME = 4, /* 1 = 60s timeout, 0 = 30s timeout */ + GSC_SC_CTRL1_WDEN = 5, /* 1 = enable, 0 = disable */ + GSC_SC_CTRL1_WDDIS = 7, /* 1 = disable boot watchdog */ };
/* System Controller Interrupt bits */ @@ -62,5 +65,6 @@ enum { */ int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len); int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len); +int gsc_info(int verbose); #endif
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 871af09..b7199f1 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -1430,15 +1430,8 @@ int checkboard(void) return 0;
/* Display GSC firmware revision/CRC/status */ - i2c_set_bus_num(CONFIG_I2C_GSC); - if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_FWVER, 1, buf, 1)) { - printf("GSC: v%d", buf[0]); - if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, buf, 4)) { - printf(" 0x%04x", buf[2] | buf[3]<<8); /* CRC */ - printf(" 0x%02x", buf[0]); /* irq status */ - } - puts("\n"); - } + gsc_info(0); + /* Display RTC */ if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) { printf("RTC: %d\n", @@ -1575,13 +1568,6 @@ int misc_init_r(void) } else { puts("Error: could not disable GSC Watchdog\n"); } - if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, ®, 1)) { - if (reg & (1 << GSC_SC_IRQ_WATCHDOG)) { /* watchdog timeout */ - puts("GSC boot watchdog timeout detected\n"); - reg &= ~(1 << GSC_SC_IRQ_WATCHDOG); /* clear flag */ - gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, ®, 1); - } - }
return 0; }
From: Pushpal Sidhu psidhu@gateworks.com
The GW522x is functionally the same as a GW52xx except for PCIE_RST# GPIO. Add a DT fixup to change this gpio upon bootup.
Signed-off-by: Pushpal Sidhu psidhu@gateworks.com Signed-off-by: Tim Harvey tharvey@gateworks.com --- board/gateworks/gw_ventana/gw_ventana.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+)
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index b7199f1..50a2a9a 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -669,6 +669,8 @@ static iomux_v3_cfg_t const gw52xx_gpio_pads[] = { IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), /* PCI_RST# */ IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), + /* PCI_RST# (GW522x) */ + IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | DIO_PAD_CFG), /* PCIESKT_WDIS# */ IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), }; @@ -1168,6 +1170,10 @@ static void setup_board_gpio(int board) }
#if !defined(CONFIG_CMD_PCI) + /* GW522x Uses GPIO3_IO23 for PCIE_RST# */ + if (board_type == GW52xx && info->model[4] == '2') + gpio_cfg[board].pcie_rst = IMX_GPIO_NR(3, 23); + /* assert PCI_RST# (released by OS when clock is valid) */ gpio_direction_output(gpio_cfg[board].pcie_rst, 0); #endif @@ -1656,6 +1662,28 @@ int ft_board_setup(void *blob, bd_t *bd) fdt_status_disabled(blob, i); }
+ /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */ + else if (board_type == GW52xx && info->model[4] == '2') { + u32 handle = 0; + u32 *range = NULL; + + i = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie"); + if (i) + range = (u32 *)fdt_getprop(blob, i, "reset-gpio", + NULL); + + if (range) { + i = fdt_path_offset(blob, + "/soc/aips-bus@02000000/gpio@020a4000"); + if (i) + handle = fdt_get_phandle(blob, i); + if (handle) { + range[0] = cpu_to_fdt32(handle); + range[1] = cpu_to_fdt32(23); + } + } + } + /* * isolate CSI0_DATA_EN for GW551x below revB to work around * errata causing non functional digital video in (it is not hooked up)
The HDMI receiver used on the GW54xx and GW551x has a 16bit video data bus interconnect between it and the IMX6 CSI. This can be used in two different modes, each having advantages and disadvantages. Allow the hdmiinfmt env var to specify which format is desired (yuv422smp or yuv422bt656).
Signed-off-by: Tim Harvey tharvey@gateworks.com --- board/gateworks/gw_ventana/gw_ventana.c | 39 +++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+)
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 50a2a9a..e6da3d5 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -1580,6 +1580,42 @@ int misc_init_r(void)
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+static int ft_sethdmiinfmt(void *blob, char *mode) +{ + int off; + + if (!mode) + return -EINVAL; + + off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x"); + if (off < 0) + return off; + + if (0 == strcasecmp(mode, "yuv422bt656")) { + u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00, + 0x00, 0x00, 0x00 }; + mode = "422_ccir"; + fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1); + fdt_setprop_u32(blob, off, "vidout_trc", 1); + fdt_setprop_u32(blob, off, "vidout_blc", 1); + fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg)); + printf(" set HDMI input mode to %s\n", mode); + } else if (0 == strcasecmp(mode, "yuv422smp")) { + u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00, + 0x82, 0x81, 0x00 }; + mode = "422_smp"; + fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1); + fdt_setprop_u32(blob, off, "vidout_trc", 0); + fdt_setprop_u32(blob, off, "vidout_blc", 0); + fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg)); + printf(" set HDMI input mode to %s\n", mode); + } else { + return -EINVAL; + } + + return 0; +} + /* * called prior to booting kernel or by 'fdt boardsetup' command * @@ -1640,6 +1676,9 @@ int ft_board_setup(void *blob, bd_t *bd) fdt_setprop(blob, 0, "board", info->model, strlen((const char *)info->model) + 1);
+ /* set desired digital video capture format */ + ft_sethdmiinfmt(blob, getenv("hdmiinfmt")); + /* * disable serial2 node for GW54xx for compatibility with older * 3.10.x kernel that improperly had this node enabled in the DT
The initial revision of the GW551x does not connect enough signals between the HDMI receiver and the IMX6 CSI for 16bit capture mode necessary for yuv422smp capture. Future revisions will, but for the initial rev force it to yuv422bt656 mode which requires an 8bit video data bus.
Signed-off-by: Tim Harvey tharvey@gateworks.com --- board/gateworks/gw_ventana/gw_ventana.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index e6da3d5..1e54912 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -1756,6 +1756,9 @@ int ft_board_setup(void *blob, bd_t *bd) } fdt_setprop_inplace(blob, i, "fsl,pins", range, len); } + + /* set BT656 video format */ + ft_sethdmiinfmt(blob, "yuv422bt656"); }
/*
From: Pushpal Sidhu psidhu@gateworks.com
Add memory configuration for an IMX6SDL + 1GB density DRAM.
Signed-off-by: Pushpal Sidhu psidhu@gateworks.com Signed-off-by: Tim Harvey tharvey@gateworks.com --- board/gateworks/gw_ventana/gw_ventana_spl.c | 60 +++++++++++++++++++++++++---- 1 file changed, 52 insertions(+), 8 deletions(-)
diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index b839b89..e3d4e57 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -188,6 +188,20 @@ struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { .grp_b7ds = 0x00000030, };
+/* MT41K64M16JT-125 (1Gb density) */ +static struct mx6_ddr3_cfg mt41k64m16jt_125 = { + .mem_speed = 1600, + .density = 1, + .width = 16, + .banks = 8, + .rowaddr = 13, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + /* MT41K128M16JT-125 (2Gb density) */ static struct mx6_ddr3_cfg mt41k128m16jt_125 = { .mem_speed = 1600, @@ -219,6 +233,18 @@ static struct mx6_ddr3_cfg mt41k256m16ha_125 = { /* * calibration - these are the various CPU/DDR3 combinations we support */ +static struct mx6_mmdc_calibration mx6sdl_64x16_mmdc_calib = { + /* write leveling calibration determine */ + .p0_mpwldectrl0 = 0x004C004E, + .p0_mpwldectrl1 = 0x00440044, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x42440247, + .p0_mpdgctrl1 = 0x02310232, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x45424746, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x33382C31, +};
static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = { /* write leveling calibration determine */ @@ -389,7 +415,14 @@ static void spl_dram_init(int width, int size_mb, int board_model) * mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc) * mx6_ddr_cfg - chip specific timing/layout details */ - if (width == 16 && size_mb == 256) { + if (width == 16 && size_mb == 128) { + mem = &mt41k64m16jt_125; + if (is_cpu_type(MXC_CPU_MX6Q)) + ; + else + calib = &mx6sdl_64x16_mmdc_calib; + debug("1gB density\n"); + } else if (width == 16 && size_mb == 256) { /* 1x 2Gb density chip - same calib as 2x 2Gb */ mem = &mt41k128m16jt_125; if (is_cpu_type(MXC_CPU_MX6Q)) @@ -404,6 +437,14 @@ static void spl_dram_init(int width, int size_mb, int board_model) else calib = &mx6sdl_256x16_mmdc_calib; debug("4gB density\n"); + } else if (width == 32 && size_mb == 256) { + /* Same calib as width==16, size==128 */ + mem = &mt41k64m16jt_125; + if (is_cpu_type(MXC_CPU_MX6Q)) + ; + else + calib = &mx6sdl_64x16_mmdc_calib; + debug("1gB density\n"); } else if (width == 32 && size_mb == 512) { mem = &mt41k128m16jt_125; if (is_cpu_type(MXC_CPU_MX6Q)) @@ -411,6 +452,16 @@ static void spl_dram_init(int width, int size_mb, int board_model) else calib = &mx6sdl_128x32_mmdc_calib; debug("2gB density\n"); + } else if (width == 32 && size_mb == 1024) { + mem = &mt41k256m16ha_125; + if (is_cpu_type(MXC_CPU_MX6Q)) + calib = &mx6dq_256x32_mmdc_calib; + else + calib = &mx6sdl_256x32_mmdc_calib; + debug("4gB density\n"); + } else if (width == 64 && size_mb == 512) { + mem = &mt41k64m16jt_125; + debug("1gB density\n"); } else if (width == 64 && size_mb == 1024) { mem = &mt41k128m16jt_125; if (is_cpu_type(MXC_CPU_MX6Q)) @@ -418,13 +469,6 @@ static void spl_dram_init(int width, int size_mb, int board_model) else calib = &mx6sdl_128x64_mmdc_calib; debug("2gB density\n"); - } else if (width == 32 && size_mb == 1024) { - mem = &mt41k256m16ha_125; - if (is_cpu_type(MXC_CPU_MX6Q)) - calib = &mx6dq_256x32_mmdc_calib; - else - calib = &mx6sdl_256x32_mmdc_calib; - debug("4gB density\n"); } else if (width == 64 && size_mb == 2048) { mem = &mt41k256m16ha_125; if (is_cpu_type(MXC_CPU_MX6Q))
From: Pushpal Sidhu psidhu@gateworks.com
This commit combines catching missing memory and calibration data into one if() block. It further prints pertinent information in determining why the failure occurred.
Signed-off-by: Pushpal Sidhu psidhu@gateworks.com Signed-off-by: Tim Harvey tharvey@gateworks.com --- board/gateworks/gw_ventana/gw_ventana_spl.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index e3d4e57..0c0fee3 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -476,12 +476,14 @@ static void spl_dram_init(int width, int size_mb, int board_model) debug("4gB density\n"); }
- if (!mem) { - puts("Error: Invalid Memory Configuration\n"); - hang(); - } - if (!calib) { - puts("Error: Invalid Board Calibration Configuration\n"); + if (!(mem && calib)) { + puts("Error: Invalid Calibration/Board Configuration\n"); + printf("MEM : %s\n", mem ? "OKAY" : "NULL"); + printf("CALIB : %s\n", calib ? "OKAY" : "NULL"); + printf("CPUTYPE: %s\n", + is_cpu_type(MXC_CPU_MX6Q) ? "IMX6Q" : "IMX6DL"); + printf("SIZE_MB: %d\n", size_mb); + printf("WIDTH : %d\n", width); hang(); }
On 08/04/2015 21:54, Tim Harvey wrote:
This collection of patches comprises a set of various updates that has been sitting in my queue for a while.
There are a couple of patches pending that this series depends on:
- fdt: add new fdt_fixup_display function to configure display
- arm: mx6: ddr: add pd_fast_exit flag to system information
Pushpal Sidhu (3): imx: ventana: add DT fixup for GW522x to change PCIE_RST# GPIO imx: ventana: Add new memory configuration imx: ventana: Update missing memory/calib handling
Tim Harvey (31): imx: ventana: disable 4k tftp/nfs packets imx: ventana: add i210 support imx: ventana: assign default ethprime dynamically imx: ventana: remove unused GPIO configuration imx: ventana: add usb_pcisel hwconfig support imx: ventana: enable precharge power-down fast-exit mode imx: ventana: add support for 4Gb density mem devices with IMX6DL imx: ventana: set LTC3676 PMIC to appropriate values per datasheet imx: ventana: config: add USB Mass Storage (ums) support imx: ventana: config: Support ramdisk imx: ventana: config: enable edid support imx: ventana: config: enable EXT4 filesystem read/write support imx: ventana: fix various sparse warnings imx: ventana: disable IMX6 watchdogs on GW51xx RevA and RevB imx: ventana: Add support for GW551x imx: ventana: add usb_pgood_delay 2sec default imx: ventana: add wdis config for GW5520 imx: ventana: only pinmux FEC enet signals for boards using it imx: ventana: update boot scripts to support ubifs boot vol imx: ventana: remove GSC hwmon voltage rail min/max test imx: ventana: add mem_mb dynamic env var imx: ventana: gsc: add new hwmon rails imx: ventana: added DT fixup for GW551x-A video input imx: ventana: updated 16bit DDR calibration imx: ventana: remove 128x16 calibration (share with 128x32) imx: ventana: add DT fixup for GW54xx compatibility with older kernels imx: ventana: add support for DLC-700JMGT4 and DLC-800FIGT3 LCD displays imx: ventana: added device-tree display configuration for LVDS displays imx: ventana: add 'gsc wd' command for enabling and disabling GSC watchdog imx: ventana: use hdmiinfmt env var to override HDMI capture format imx: ventana: set HDMI video in to yuv422bt656 for GW551x-A
board/gateworks/gw_ventana/eeprom.c | 10 +- board/gateworks/gw_ventana/gsc.c | 130 +++++++--- board/gateworks/gw_ventana/gsc.h | 10 +- board/gateworks/gw_ventana/gw_ventana.c | 367 +++++++++++++++++++++++----- board/gateworks/gw_ventana/gw_ventana_spl.c | 129 +++++++++- board/gateworks/gw_ventana/ventana_eeprom.h | 1 + include/configs/gw_ventana.h | 68 ++++-- 7 files changed, 578 insertions(+), 137 deletions(-)
The whole series applied to u-boot-imx, thanks!
Best regards, Stefano Babic
participants (2)
-
Stefano Babic -
Tim Harvey