[PATCH 0/6] PHYTEC SoM detection for phyCORE-i.MX8MP
This series adds support for EEPROM SoM detection used by different PHYTEC SoMs. The EEPROM data consist of 32 bytes containing information like PCB revision, RAM size and other SoM specific configuration.
For SoMs of the i.MX8M family the data is written to two areas of the used i2c EEPROM.
We initally add the detection support for phyCORE-i.MX8MP. Due to layout constraints phyCORE-i.MX8MP SoMs with PCB revision 2 and older can only make use of a lower RAM frequency. This changes with the use of newer PCB revisions. We make use of the factory flashed EEPROM data to detect the PCB revision and select the fitting RAM settings.
Teresa
Teresa Remmet (6): board: phytec: Add common PHYTEC SoM detection board: phytec: common: Add imx8m specific EEPROM detection support board: phytec: phycore-imx8mp: Add EEPROM detection initialisation board: phytec: phycore_imx8mp: Update 2GB RAM Timings board: phytec: common: phytec_som_detection: Add helper for PCB revision board: phytec: phycore_imx8mp: Add 4000MTS RAM timings based on PCB rev
board/phytec/common/Kconfig | 13 + board/phytec/common/Makefile | 11 + board/phytec/common/imx8m_som_detection.c | 169 ++++++++++++ board/phytec/common/imx8m_som_detection.h | 54 ++++ board/phytec/common/phytec_som_detection.c | 203 ++++++++++++++ board/phytec/common/phytec_som_detection.h | 109 ++++++++ board/phytec/phycore_imx8mp/Kconfig | 1 + board/phytec/phycore_imx8mp/lpddr4_timing.c | 278 ++++++++++---------- board/phytec/phycore_imx8mp/spl.c | 80 ++++++ configs/phycore-imx8mp_defconfig | 1 + 10 files changed, 776 insertions(+), 143 deletions(-) create mode 100644 board/phytec/common/Kconfig create mode 100644 board/phytec/common/Makefile create mode 100644 board/phytec/common/imx8m_som_detection.c create mode 100644 board/phytec/common/imx8m_som_detection.h create mode 100644 board/phytec/common/phytec_som_detection.c create mode 100644 board/phytec/common/phytec_som_detection.h
Recent shipped PHYTEC SoMs come with an i2c EEPROM containing information about the hardware such as board revision and variant. This can be used for RAM detection and loading device tree overlays during kernel start.
Signed-off-by: Teresa Remmet t.remmet@phytec.de --- board/phytec/common/Kconfig | 5 + board/phytec/common/Makefile | 10 ++ board/phytec/common/phytec_som_detection.c | 188 +++++++++++++++++++++ board/phytec/common/phytec_som_detection.h | 104 ++++++++++++ 4 files changed, 307 insertions(+) create mode 100644 board/phytec/common/Kconfig create mode 100644 board/phytec/common/Makefile create mode 100644 board/phytec/common/phytec_som_detection.c create mode 100644 board/phytec/common/phytec_som_detection.h
diff --git a/board/phytec/common/Kconfig b/board/phytec/common/Kconfig new file mode 100644 index 000000000000..d614d45b1d60 --- /dev/null +++ b/board/phytec/common/Kconfig @@ -0,0 +1,5 @@ +config PHYTEC_SOM_DETECTION + bool "Support SoM detection for PHYTEC platforms" + select SPL_CRC8 if SPL + help + Support of I2C EEPROM based SoM detection. diff --git a/board/phytec/common/Makefile b/board/phytec/common/Makefile new file mode 100644 index 000000000000..5fe8725ef684 --- /dev/null +++ b/board/phytec/common/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2023 PHYTEC Messtechnik GmbH +# Author: Teresa Remmet t.remmet@phytec.de + +ifdef CONFIG_SPL_BUILD +# necessary to create built-in.o +obj- := __dummy__.o +endif + +obj-$(CONFIG_PHYTEC_SOM_DETECTION) += phytec_som_detection.o diff --git a/board/phytec/common/phytec_som_detection.c b/board/phytec/common/phytec_som_detection.c new file mode 100644 index 000000000000..366bdd4ace4b --- /dev/null +++ b/board/phytec/common/phytec_som_detection.c @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet t.remmet@phytec.de + */ + +#include <common.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <asm/arch/sys_proto.h> +#include <dm/device.h> +#include <dm/uclass.h> +#include <i2c.h> +#include <u-boot/crc.h> + +#include "phytec_som_detection.h" + +struct phytec_eeprom_data eeprom_data; + +int phytec_eeprom_data_setup_fallback(struct phytec_eeprom_data *data, + int bus_num, int addr, int addr_fallback) +{ + int ret; + + ret = phytec_eeprom_data_init(data, bus_num, addr); + if (ret) { + pr_err("%s: init failed. Trying fall back address 0x%x\n", + __func__, addr_fallback); + ret = phytec_eeprom_data_init(data, bus_num, addr_fallback); + } + + if (ret) + pr_err("%s: EEPROM data init failed\n", __func__); + + return ret; +} + +int phytec_eeprom_data_setup(struct phytec_eeprom_data *data, + int bus_num, int addr) +{ + int ret; + + ret = phytec_eeprom_data_init(data, bus_num, addr); + if (ret) + pr_err("%s: EEPROM data init failed\n", __func__); + + return ret; +} + +int phytec_eeprom_data_init(struct phytec_eeprom_data *data, + int bus_num, int addr) +{ + int ret, i; + unsigned int crc; + int *ptr; + + if (!data) + data = &eeprom_data; + +#if CONFIG_IS_ENABLED(DM_I2C) + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(bus_num, addr, 2, &dev); + if (ret) { + pr_err("%s: i2c EEPROM not found: %i.\n", __func__, ret); + return ret; + } + + ret = dm_i2c_read(dev, 0, (uint8_t *)data, + sizeof(struct phytec_eeprom_data)); + if (ret) { + pr_err("%s: Unable to read EEPROM data\n", __func__); + return ret; + } +#else + i2c_set_bus_num(bus_num); + ret = i2c_read(addr, 0, 2, (uint8_t *)data, + sizeof(struct phytec_eeprom_data)); +#endif + + if (data->api_rev == 0xff) { + pr_err("%s: EEPROM is not flashed. Prototype?\n", __func__); + return -EINVAL; + } + + ptr = (int *)data; + for (i = 0; i < sizeof(struct phytec_eeprom_data); i += sizeof(ptr)) + if (*ptr != 0x0) + break; + + if (i == sizeof(struct phytec_eeprom_data)) { + pr_err("%s: EEPROM data is all zero. Erased?\n", __func__); + return -EINVAL; + } + + /* We are done here for early revisions */ + if (data->api_rev <= PHYTEC_API_REV1) + return 0; + + crc = crc8(0, (const unsigned char *)data, + sizeof(struct phytec_eeprom_data)); + debug("%s: crc: %x\n", __func__, crc); + + if (crc) { + pr_err("%s: CRC mismatch. EEPROM data is not usable\n", + __func__); + return -EINVAL; + } + + return 0; +} + +void __maybe_unused phytec_print_som_info(struct phytec_eeprom_data *data) +{ + struct phytec_api2_data *api2; + char pcb_sub_rev; + unsigned int ksp_no, sub_som_type1, sub_som_type2; + + if (!data) + data = &eeprom_data; + + if (data->api_rev < PHYTEC_API_REV2) + return; + + api2 = &data->data.data_api2; + + /* Calculate PCB subrevision */ + pcb_sub_rev = api2->pcb_sub_opt_rev & 0x0f; + pcb_sub_rev = pcb_sub_rev ? ((pcb_sub_rev - 1) + 'a') : ' '; + + /* print standard product string */ + if (api2->som_type <= 1) { + printf("SoM: %s-%03u-%s.%s PCB rev: %u%c\n", + phytec_som_type_str[api2->som_type], api2->som_no, + api2->opt, api2->bom_rev, api2->pcb_rev, pcb_sub_rev); + return; + } + /* print KSP/KSM string */ + if (api2->som_type <= 3) { + ksp_no = (api2->ksp_no << 8) | api2->som_no; + printf("SoM: %s-%u ", + phytec_som_type_str[api2->som_type], ksp_no); + /* print standard product based KSP/KSM strings */ + } else { + switch (api2->som_type) { + case 4: + sub_som_type1 = 0; + sub_som_type2 = 3; + break; + case 5: + sub_som_type1 = 0; + sub_som_type2 = 2; + break; + case 6: + sub_som_type1 = 1; + sub_som_type2 = 3; + break; + case 7: + sub_som_type1 = 1; + sub_som_type2 = 2; + break; + default: + break; + }; + + printf("SoM: %s-%03u-%s-%03u ", + phytec_som_type_str[sub_som_type1], + api2->som_no, phytec_som_type_str[sub_som_type2], + api2->ksp_no); + } + + printf("Option: %s BOM rev: %s PCB rev: %u%c\n", api2->opt, + api2->bom_rev, api2->pcb_rev, pcb_sub_rev); +} + +char * __maybe_unused phytec_get_opt(struct phytec_eeprom_data *data) +{ + char *opt; + + if (!data) + data = &eeprom_data; + + if (data->api_rev < PHYTEC_API_REV2) + opt = data->data.data_api0.opt; + else + opt = data->data.data_api2.opt; + + return opt; +} diff --git a/board/phytec/common/phytec_som_detection.h b/board/phytec/common/phytec_som_detection.h new file mode 100644 index 000000000000..01f7e4652ddb --- /dev/null +++ b/board/phytec/common/phytec_som_detection.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet t.remmet@phytec.de + */ + +#ifndef _PHYTEC_SOM_DETECTION_H +#define _PHYTEC_SOM_DETECTION_H + +#define PHYTEC_MAX_OPTIONS 17 +#define PHYTEC_EEPROM_INVAL 0xff + +#define PHYTEC_GET_OPTION(option) \ + (((option) > '9') ? (option) - 'A' + 10 : (option) - '0') + +enum { + PHYTEC_API_REV0 = 0, + PHYTEC_API_REV1, + PHYTEC_API_REV2, +}; + +static const char * const phytec_som_type_str[] = { + "PCM", + "PCL", + "KSM", + "KSP", +}; + +struct phytec_api0_data { + u8 pcb_rev; /* PCB revision of SoM */ + u8 som_type; /* SoM type */ + u8 ksp_no; /* KSP no */ + char opt[16]; /* SoM options */ + u8 mac[6]; /* MAC address (optional) */ + u8 pad[5]; /* padding */ + u8 cksum; /* checksum */ +} __packed; + +struct phytec_api2_data { + u8 pcb_rev; /* PCB revision of SoM */ + u8 pcb_sub_opt_rev; /* PCB subrevision and opt revision */ + u8 som_type; /* SoM type */ + u8 som_no; /* SoM number */ + u8 ksp_no; /* KSP information */ + char opt[PHYTEC_MAX_OPTIONS]; /* SoM options */ + char bom_rev[2]; /* BOM revision */ + u8 mac[6]; /* MAC address (optional) */ + u8 crc8; /* checksum */ +} __packed; + +struct phytec_eeprom_data { + u8 api_rev; + union { + struct phytec_api0_data data_api0; + struct phytec_api2_data data_api2; + } data; +} __packed; + +#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION) + +int phytec_eeprom_data_setup_fallback(struct phytec_eeprom_data *data, + int bus_num, int addr, + int addr_fallback); +int phytec_eeprom_data_setup(struct phytec_eeprom_data *data, + int bus_num, int addr); +int phytec_eeprom_data_init(struct phytec_eeprom_data *data, + int bus_num, int addr); +void __maybe_unused phytec_print_som_info(struct phytec_eeprom_data *data); + +char * __maybe_unused phytec_get_opt(struct phytec_eeprom_data *data); + +#else + +inline int phytec_eeprom_data_setup(struct phytec_eeprom_data *data, + int bus_num, int addr) +{ + return PHYTEC_EEPROM_INVAL; +} + +inline int phytec_eeprom_data_setup_fallback(struct phytec_eeprom_data *data, + int bus_num, int addr, + int addr_fallback) +{ + return PHYTEC_EEPROM_INVAL; +} + +inline int phytec_eeprom_data_init(struct phytec_eeprom_data *data, + int bus_num, int addr) +{ + return PHYTEC_EEPROM_INVAL; +} + +inline void __maybe_unused phytec_print_som_info(struct phytec_eeprom_data *data) +{ +} + +inline char *__maybe_unused phytec_get_opt(struct phytec_eeprom_data *data) +{ + return NULL; +} + +#endif /* IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION) */ + +#endif /* _PHYTEC_SOM_DETECTION_H */
Add imx8m specific detection part. Which includes checking the EEPROM data for article number options.
Signed-off-by: Teresa Remmet t.remmet@phytec.de --- board/phytec/common/Kconfig | 8 + board/phytec/common/Makefile | 1 + board/phytec/common/imx8m_som_detection.c | 169 ++++++++++++++++++++++ board/phytec/common/imx8m_som_detection.h | 54 +++++++ 4 files changed, 232 insertions(+) create mode 100644 board/phytec/common/imx8m_som_detection.c create mode 100644 board/phytec/common/imx8m_som_detection.h
diff --git a/board/phytec/common/Kconfig b/board/phytec/common/Kconfig index d614d45b1d60..3b1c5aa0d02b 100644 --- a/board/phytec/common/Kconfig +++ b/board/phytec/common/Kconfig @@ -3,3 +3,11 @@ config PHYTEC_SOM_DETECTION select SPL_CRC8 if SPL help Support of I2C EEPROM based SoM detection. + +config PHYTEC_IMX8M_SOM_DETECTION + bool "Support SoM detection for i.MX8M PHYTEC platforms" + depends on ARCH_IMX8M && PHYTEC_SOM_DETECTION + default y + help + Support of I2C EEPROM based SoM detection. Supported + for PHYTEC i.MX8MM/i.MX8MP boards diff --git a/board/phytec/common/Makefile b/board/phytec/common/Makefile index 5fe8725ef684..fe28964ce21c 100644 --- a/board/phytec/common/Makefile +++ b/board/phytec/common/Makefile @@ -8,3 +8,4 @@ obj- := __dummy__.o endif
obj-$(CONFIG_PHYTEC_SOM_DETECTION) += phytec_som_detection.o +obj-$(CONFIG_PHYTEC_IMX8M_SOM_DETECTION) += imx8m_som_detection.o diff --git a/board/phytec/common/imx8m_som_detection.c b/board/phytec/common/imx8m_som_detection.c new file mode 100644 index 000000000000..a732d619fcf3 --- /dev/null +++ b/board/phytec/common/imx8m_som_detection.c @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet t.remmet@phytec.de + */ + +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <dm/device.h> +#include <dm/uclass.h> +#include <i2c.h> +#include <u-boot/crc.h> + +#include "imx8m_som_detection.h" + +extern struct phytec_eeprom_data eeprom_data; + +/* Check if the SoM is actually one of the following products: + * - i.MX8MM + * - i.MX8MN + * - i.MX8MP + * - i.MX8MQ + * + * Returns 0 in case it's a known SoM. Otherwise, returns -1. + */ +u8 __maybe_unused phytec_imx8m_detect(struct phytec_eeprom_data *data) +{ + char *opt; + u8 som; + + /* We can not do the check for early API revsions */ + if (data->api_rev < PHYTEC_API_REV2) + return -1; + + if (!data) + data = &eeprom_data; + + som = data->data.data_api2.som_no; + debug("%s: som id: %u\n", __func__, som); + + opt = phytec_get_opt(data); + if (!opt) + return -1; + + if (som == PHYTEC_IMX8MP_SOM && is_imx8mp()) + return 0; + + if (som == PHYTEC_IMX8MM_SOM) { + if ((PHYTEC_GET_OPTION(opt[0]) != 0) && + (PHYTEC_GET_OPTION(opt[1]) == 0) && is_imx8mm()) + return 0; + else if ((PHYTEC_GET_OPTION(opt[0]) == 0) && + (PHYTEC_GET_OPTION(opt[1]) != 0) && is_imx8mn()) + return 0; + } + + if (som == PHYTEC_IMX8MQ_SOM && is_imx8mq()) + return 0; + + pr_err("%s: SoM ID does not match. Wrong EEPROM data?\n", __func__); + return -1; +} + +/* + * All PHYTEC i.MX8M boards have RAM size definition at the + * same location. + */ +u8 __maybe_unused phytec_get_imx8m_ddr_size(struct phytec_eeprom_data *data) +{ + char *opt; + u8 ddr_id; + + if (!data) + data = &eeprom_data; + + opt = phytec_get_opt(data); + if (opt) + ddr_id = PHYTEC_GET_OPTION(opt[2]) - '0'; + else + ddr_id = PHYTEC_EEPROM_INVAL; + + debug("%s: ddr id: %u\n", __func__, ddr_id); + return ddr_id; +} + +/* + * Filter SPI-NOR flash information. All i.MX8M boards have this at + * the same location. + * returns: 0x0 if no SPI is populated. Otherwise a board depended + * code for the size. PHYTEC_EEPROM_INVAL when the data is invalid. + */ +u8 __maybe_unused phytec_get_imx8m_spi(struct phytec_eeprom_data *data) +{ + char *opt; + u8 spi; + + if (!data) + data = &eeprom_data; + + if (data->api_rev < PHYTEC_API_REV2) + return PHYTEC_EEPROM_INVAL; + + opt = phytec_get_opt(data); + if (opt) + spi = PHYTEC_GET_OPTION(opt[4]); + else + spi = PHYTEC_EEPROM_INVAL; + + debug("%s: spi: %u\n", __func__, spi); + return spi; +} + +/* + * Filter ethernet phy information. All i.MX8M boards have this at + * the same location. + * returns: 0x0 if no ethernet phy is populated. 0x1 if it is populated. + * PHYTEC_EEPROM_INVAL when the data is invalid. + */ +u8 __maybe_unused phytec_get_imx8m_eth(struct phytec_eeprom_data *data) +{ + char *opt; + u8 eth; + + if (!data) + data = &eeprom_data; + + if (data->api_rev < PHYTEC_API_REV2) + return PHYTEC_EEPROM_INVAL; + + opt = phytec_get_opt(data); + if (opt) { + eth = PHYTEC_GET_OPTION(opt[5]); + eth &= 0x1; + } else { + eth = PHYTEC_EEPROM_INVAL; + } + + debug("%s: eth: %u\n", __func__, eth); + return eth; +} + +/* + * Filter RTC information for phyCORE-i.MX8MP. + * returns: 0 if no RTC is populated. 1 if it is populated. + * PHYTEC_EEPROM_INVAL when the data is invalid. + */ +u8 __maybe_unused phytec_get_imx8mp_rtc(struct phytec_eeprom_data *data) +{ + char *opt; + u8 rtc; + + if (!data) + data = &eeprom_data; + + if (data->api_rev < PHYTEC_API_REV2) + return PHYTEC_EEPROM_INVAL; + + opt = phytec_get_opt(data); + if (opt) { + rtc = PHYTEC_GET_OPTION(opt[5]); + rtc &= 0x4; + rtc = !(rtc >> 2); + } else { + rtc = PHYTEC_EEPROM_INVAL; + } + debug("%s: rtc: %u\n", __func__, rtc); + return rtc; +} + diff --git a/board/phytec/common/imx8m_som_detection.h b/board/phytec/common/imx8m_som_detection.h new file mode 100644 index 000000000000..88d3037bf363 --- /dev/null +++ b/board/phytec/common/imx8m_som_detection.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet t.remmet@phytec.de + */ + +#ifndef _PHYTEC_IMX8M_SOM_DETECTION_H +#define _PHYTEC_IMX8M_SOM_DETECTION_H + +#include "phytec_som_detection.h" + +#define PHYTEC_IMX8MQ_SOM 66 +#define PHYTEC_IMX8MM_SOM 69 +#define PHYTEC_IMX8MP_SOM 70 + +#if IS_ENABLED(CONFIG_PHYTEC_IMX8M_SOM_DETECTION) + +u8 __maybe_unused phytec_imx8m_detect(struct phytec_eeprom_data *data); +u8 __maybe_unused phytec_get_imx8m_ddr_size(struct phytec_eeprom_data *data); +u8 __maybe_unused phytec_get_imx8mp_rtc(struct phytec_eeprom_data *data); +u8 __maybe_unused phytec_get_imx8m_spi(struct phytec_eeprom_data *data); +u8 __maybe_unused phytec_get_imx8m_eth(struct phytec_eeprom_data *data); + +#else + +inline u8 __maybe_unused phytec_imx8m_detect(struct phytec_eeprom_data *data) +{ + return -1; +} + +inline u8 __maybe_unused +phytec_get_imx8m_ddr_size(struct phytec_eeprom_data *data) +{ + return PHYTEC_EEPROM_INVAL; +} + +inline u8 __maybe_unused phytec_get_imx8mp_rtc(struct phytec_eeprom_data *data) +{ + return PHYTEC_EEPROM_INVAL; +} + +inline u8 __maybe_unused phytec_get_imx8m_spi(struct phytec_eeprom_data *data) +{ + return PHYTEC_EEPROM_INVAL; +} + +inline u8 __maybe_unused phytec_get_imx8m_eth(struct phytec_eeprom_data *data) +{ + return PHYTEC_EEPROM_INVAL; +} + +#endif /* IS_ENABLED(CONFIG_PHYTEC_IMX8M_SOM_DETECTION) */ + +#endif /* _PHYTEC_IMX8M_SOM_DETECTION_H */
Hi Teresa,
On Tue, 2023-07-18 at 15:35 +0200, Teresa Remmet wrote:
Add imx8m specific detection part. Which includes checking the EEPROM data for article number options.
Signed-off-by: Teresa Remmet t.remmet@phytec.de
board/phytec/common/Kconfig | 8 + board/phytec/common/Makefile | 1 + board/phytec/common/imx8m_som_detection.c | 169 ++++++++++++++++++++++ board/phytec/common/imx8m_som_detection.h | 54 +++++++ 4 files changed, 232 insertions(+) create mode 100644 board/phytec/common/imx8m_som_detection.c create mode 100644 board/phytec/common/imx8m_som_detection.h
diff --git a/board/phytec/common/Kconfig b/board/phytec/common/Kconfig index d614d45b1d60..3b1c5aa0d02b 100644 --- a/board/phytec/common/Kconfig +++ b/board/phytec/common/Kconfig @@ -3,3 +3,11 @@ config PHYTEC_SOM_DETECTION select SPL_CRC8 if SPL help Support of I2C EEPROM based SoM detection.
+config PHYTEC_IMX8M_SOM_DETECTION + bool "Support SoM detection for i.MX8M PHYTEC platforms" + depends on ARCH_IMX8M && PHYTEC_SOM_DETECTION + default y + help + Support of I2C EEPROM based SoM detection. Supported + for PHYTEC i.MX8MM/i.MX8MP boards diff --git a/board/phytec/common/Makefile b/board/phytec/common/Makefile index 5fe8725ef684..fe28964ce21c 100644 --- a/board/phytec/common/Makefile +++ b/board/phytec/common/Makefile @@ -8,3 +8,4 @@ obj- := __dummy__.o endif obj-$(CONFIG_PHYTEC_SOM_DETECTION) += phytec_som_detection.o +obj-$(CONFIG_PHYTEC_IMX8M_SOM_DETECTION) += imx8m_som_detection.o diff --git a/board/phytec/common/imx8m_som_detection.c b/board/phytec/common/imx8m_som_detection.c new file mode 100644 index 000000000000..a732d619fcf3 --- /dev/null +++ b/board/phytec/common/imx8m_som_detection.c @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/*
- Copyright (C) 2023 PHYTEC Messtechnik GmbH
- Author: Teresa Remmet t.remmet@phytec.de
- */
+#include <common.h> +#include <asm/arch/sys_proto.h> +#include <dm/device.h> +#include <dm/uclass.h> +#include <i2c.h> +#include <u-boot/crc.h>
+#include "imx8m_som_detection.h"
+extern struct phytec_eeprom_data eeprom_data;
+/* Check if the SoM is actually one of the following products:
- i.MX8MM
- i.MX8MN
- i.MX8MP
- i.MX8MQ
- Returns 0 in case it's a known SoM. Otherwise, returns -1.
- */
+u8 __maybe_unused phytec_imx8m_detect(struct phytec_eeprom_data *data) +{ + char *opt; + u8 som;
+ /* We can not do the check for early API revsions */ + if (data->api_rev < PHYTEC_API_REV2) + return -1;
+ if (!data) + data = &eeprom_data;
+ som = data->data.data_api2.som_no; + debug("%s: som id: %u\n", __func__, som);
+ opt = phytec_get_opt(data); + if (!opt) + return -1;
+ if (som == PHYTEC_IMX8MP_SOM && is_imx8mp()) + return 0;
+ if (som == PHYTEC_IMX8MM_SOM) { + if ((PHYTEC_GET_OPTION(opt[0]) != 0) && + (PHYTEC_GET_OPTION(opt[1]) == 0) && is_imx8mm()) + return 0; + else if ((PHYTEC_GET_OPTION(opt[0]) == 0) && + (PHYTEC_GET_OPTION(opt[1]) != 0) && is_imx8mn()) + return 0; + }
+ if (som == PHYTEC_IMX8MQ_SOM && is_imx8mq()) + return 0;
+ pr_err("%s: SoM ID does not match. Wrong EEPROM data?\n", __func__); + return -1; +}
+/*
- All PHYTEC i.MX8M boards have RAM size definition at the
- same location.
- */
+u8 __maybe_unused phytec_get_imx8m_ddr_size(struct phytec_eeprom_data *data) +{ + char *opt; + u8 ddr_id;
+ if (!data) + data = &eeprom_data;
+ opt = phytec_get_opt(data); + if (opt) + ddr_id = PHYTEC_GET_OPTION(opt[2]) - '0';
Is the "- '0'" a bug? While testing, I noticed that the RAM size is not detected correctly and looking at the macro definiton this - '0' case is already covered. I assume in this line you meant to simply call the macro.
Regards, Yannic
+ else + ddr_id = PHYTEC_EEPROM_INVAL;
+ debug("%s: ddr id: %u\n", __func__, ddr_id); + return ddr_id; +}
+/*
- Filter SPI-NOR flash information. All i.MX8M boards have this at
- the same location.
- returns: 0x0 if no SPI is populated. Otherwise a board depended
- code for the size. PHYTEC_EEPROM_INVAL when the data is invalid.
- */
+u8 __maybe_unused phytec_get_imx8m_spi(struct phytec_eeprom_data *data) +{ + char *opt; + u8 spi;
+ if (!data) + data = &eeprom_data;
+ if (data->api_rev < PHYTEC_API_REV2) + return PHYTEC_EEPROM_INVAL;
+ opt = phytec_get_opt(data); + if (opt) + spi = PHYTEC_GET_OPTION(opt[4]); + else + spi = PHYTEC_EEPROM_INVAL;
+ debug("%s: spi: %u\n", __func__, spi); + return spi; +}
+/*
- Filter ethernet phy information. All i.MX8M boards have this at
- the same location.
- returns: 0x0 if no ethernet phy is populated. 0x1 if it is
populated.
- PHYTEC_EEPROM_INVAL when the data is invalid.
- */
+u8 __maybe_unused phytec_get_imx8m_eth(struct phytec_eeprom_data *data) +{ + char *opt; + u8 eth;
+ if (!data) + data = &eeprom_data;
+ if (data->api_rev < PHYTEC_API_REV2) + return PHYTEC_EEPROM_INVAL;
+ opt = phytec_get_opt(data); + if (opt) { + eth = PHYTEC_GET_OPTION(opt[5]); + eth &= 0x1; + } else { + eth = PHYTEC_EEPROM_INVAL; + }
+ debug("%s: eth: %u\n", __func__, eth); + return eth; +}
+/*
- Filter RTC information for phyCORE-i.MX8MP.
- returns: 0 if no RTC is populated. 1 if it is populated.
- PHYTEC_EEPROM_INVAL when the data is invalid.
- */
+u8 __maybe_unused phytec_get_imx8mp_rtc(struct phytec_eeprom_data *data) +{ + char *opt; + u8 rtc;
+ if (!data) + data = &eeprom_data;
+ if (data->api_rev < PHYTEC_API_REV2) + return PHYTEC_EEPROM_INVAL;
+ opt = phytec_get_opt(data); + if (opt) { + rtc = PHYTEC_GET_OPTION(opt[5]); + rtc &= 0x4; + rtc = !(rtc >> 2); + } else { + rtc = PHYTEC_EEPROM_INVAL; + } + debug("%s: rtc: %u\n", __func__, rtc); + return rtc; +}
diff --git a/board/phytec/common/imx8m_som_detection.h b/board/phytec/common/imx8m_som_detection.h new file mode 100644 index 000000000000..88d3037bf363 --- /dev/null +++ b/board/phytec/common/imx8m_som_detection.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/*
- Copyright (C) 2023 PHYTEC Messtechnik GmbH
- Author: Teresa Remmet t.remmet@phytec.de
- */
+#ifndef _PHYTEC_IMX8M_SOM_DETECTION_H +#define _PHYTEC_IMX8M_SOM_DETECTION_H
+#include "phytec_som_detection.h"
+#define PHYTEC_IMX8MQ_SOM 66 +#define PHYTEC_IMX8MM_SOM 69 +#define PHYTEC_IMX8MP_SOM 70
+#if IS_ENABLED(CONFIG_PHYTEC_IMX8M_SOM_DETECTION)
+u8 __maybe_unused phytec_imx8m_detect(struct phytec_eeprom_data *data); +u8 __maybe_unused phytec_get_imx8m_ddr_size(struct phytec_eeprom_data *data); +u8 __maybe_unused phytec_get_imx8mp_rtc(struct phytec_eeprom_data *data); +u8 __maybe_unused phytec_get_imx8m_spi(struct phytec_eeprom_data *data); +u8 __maybe_unused phytec_get_imx8m_eth(struct phytec_eeprom_data *data);
+#else
+inline u8 __maybe_unused phytec_imx8m_detect(struct phytec_eeprom_data *data) +{ + return -1; +}
+inline u8 __maybe_unused +phytec_get_imx8m_ddr_size(struct phytec_eeprom_data *data) +{ + return PHYTEC_EEPROM_INVAL; +}
+inline u8 __maybe_unused phytec_get_imx8mp_rtc(struct phytec_eeprom_data *data) +{ + return PHYTEC_EEPROM_INVAL; +}
+inline u8 __maybe_unused phytec_get_imx8m_spi(struct phytec_eeprom_data *data) +{ + return PHYTEC_EEPROM_INVAL; +}
+inline u8 __maybe_unused phytec_get_imx8m_eth(struct phytec_eeprom_data *data) +{ + return PHYTEC_EEPROM_INVAL; +}
+#endif /* IS_ENABLED(CONFIG_PHYTEC_IMX8M_SOM_DETECTION) */
+#endif /* _PHYTEC_IMX8M_SOM_DETECTION_H */
Hello Yannic,
Am Freitag, dem 28.07.2023 um 15:08 +0200 schrieb Yannic Moog:
Hi Teresa,
On Tue, 2023-07-18 at 15:35 +0200, Teresa Remmet wrote:
Add imx8m specific detection part. Which includes checking the EEPROM data for article number options.
Signed-off-by: Teresa Remmet t.remmet@phytec.de
board/phytec/common/Kconfig | 8 + board/phytec/common/Makefile | 1 + board/phytec/common/imx8m_som_detection.c | 169 ++++++++++++++++++++++ board/phytec/common/imx8m_som_detection.h | 54 +++++++ 4 files changed, 232 insertions(+) create mode 100644 board/phytec/common/imx8m_som_detection.c create mode 100644 board/phytec/common/imx8m_som_detection.h
diff --git a/board/phytec/common/Kconfig b/board/phytec/common/Kconfig index d614d45b1d60..3b1c5aa0d02b 100644 --- a/board/phytec/common/Kconfig +++ b/board/phytec/common/Kconfig @@ -3,3 +3,11 @@ config PHYTEC_SOM_DETECTION select SPL_CRC8 if SPL help Support of I2C EEPROM based SoM detection.
+config PHYTEC_IMX8M_SOM_DETECTION + bool "Support SoM detection for i.MX8M PHYTEC platforms" + depends on ARCH_IMX8M && PHYTEC_SOM_DETECTION + default y + help + Support of I2C EEPROM based SoM detection. Supported + for PHYTEC i.MX8MM/i.MX8MP boards diff --git a/board/phytec/common/Makefile b/board/phytec/common/Makefile index 5fe8725ef684..fe28964ce21c 100644 --- a/board/phytec/common/Makefile +++ b/board/phytec/common/Makefile @@ -8,3 +8,4 @@ obj- := __dummy__.o endif obj-$(CONFIG_PHYTEC_SOM_DETECTION) += phytec_som_detection.o +obj-$(CONFIG_PHYTEC_IMX8M_SOM_DETECTION) += imx8m_som_detection.o diff --git a/board/phytec/common/imx8m_som_detection.c b/board/phytec/common/imx8m_som_detection.c new file mode 100644 index 000000000000..a732d619fcf3 --- /dev/null +++ b/board/phytec/common/imx8m_som_detection.c @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/*
- Copyright (C) 2023 PHYTEC Messtechnik GmbH
- Author: Teresa Remmet t.remmet@phytec.de
- */
+#include <common.h> +#include <asm/arch/sys_proto.h> +#include <dm/device.h> +#include <dm/uclass.h> +#include <i2c.h> +#include <u-boot/crc.h>
+#include "imx8m_som_detection.h"
+extern struct phytec_eeprom_data eeprom_data;
+/* Check if the SoM is actually one of the following products:
- i.MX8MM
- i.MX8MN
- i.MX8MP
- i.MX8MQ
- Returns 0 in case it's a known SoM. Otherwise, returns -1.
- */
+u8 __maybe_unused phytec_imx8m_detect(struct phytec_eeprom_data *data) +{ + char *opt; + u8 som;
+ /* We can not do the check for early API revsions */ + if (data->api_rev < PHYTEC_API_REV2) + return -1;
+ if (!data) + data = &eeprom_data;
+ som = data->data.data_api2.som_no; + debug("%s: som id: %u\n", __func__, som);
+ opt = phytec_get_opt(data); + if (!opt) + return -1;
+ if (som == PHYTEC_IMX8MP_SOM && is_imx8mp()) + return 0;
+ if (som == PHYTEC_IMX8MM_SOM) { + if ((PHYTEC_GET_OPTION(opt[0]) != 0) && + (PHYTEC_GET_OPTION(opt[1]) == 0) && is_imx8mm()) + return 0; + else if ((PHYTEC_GET_OPTION(opt[0]) == 0) && + (PHYTEC_GET_OPTION(opt[1]) != 0) && is_imx8mn()) + return 0; + }
+ if (som == PHYTEC_IMX8MQ_SOM && is_imx8mq()) + return 0;
+ pr_err("%s: SoM ID does not match. Wrong EEPROM data?\n", __func__); + return -1; +}
+/*
- All PHYTEC i.MX8M boards have RAM size definition at the
- same location.
- */
+u8 __maybe_unused phytec_get_imx8m_ddr_size(struct phytec_eeprom_data *data) +{ + char *opt; + u8 ddr_id;
+ if (!data) + data = &eeprom_data;
+ opt = phytec_get_opt(data); + if (opt) + ddr_id = PHYTEC_GET_OPTION(opt[2]) - '0';
Is the "- '0'" a bug? While testing, I noticed that the RAM size is not detected correctly and looking at the macro definiton this - '0' case is already covered. I assume in this line you meant to simply call the macro.
Yes, this is wrong. I missed to remove it here. Will fix this in v2.
Thanks, Teresa
Regards, Yannic
+ else + ddr_id = PHYTEC_EEPROM_INVAL;
+ debug("%s: ddr id: %u\n", __func__, ddr_id); + return ddr_id; +}
+/*
- Filter SPI-NOR flash information. All i.MX8M boards have this
at
- the same location.
- returns: 0x0 if no SPI is populated. Otherwise a board depended
- code for the size. PHYTEC_EEPROM_INVAL when the data is
invalid.
- */
+u8 __maybe_unused phytec_get_imx8m_spi(struct phytec_eeprom_data *data) +{ + char *opt; + u8 spi;
+ if (!data) + data = &eeprom_data;
+ if (data->api_rev < PHYTEC_API_REV2) + return PHYTEC_EEPROM_INVAL;
+ opt = phytec_get_opt(data); + if (opt) + spi = PHYTEC_GET_OPTION(opt[4]); + else + spi = PHYTEC_EEPROM_INVAL;
+ debug("%s: spi: %u\n", __func__, spi); + return spi; +}
+/*
- Filter ethernet phy information. All i.MX8M boards have this at
- the same location.
- returns: 0x0 if no ethernet phy is populated. 0x1 if it is
populated.
- PHYTEC_EEPROM_INVAL when the data is invalid.
- */
+u8 __maybe_unused phytec_get_imx8m_eth(struct phytec_eeprom_data *data) +{ + char *opt; + u8 eth;
+ if (!data) + data = &eeprom_data;
+ if (data->api_rev < PHYTEC_API_REV2) + return PHYTEC_EEPROM_INVAL;
+ opt = phytec_get_opt(data); + if (opt) { + eth = PHYTEC_GET_OPTION(opt[5]); + eth &= 0x1; + } else { + eth = PHYTEC_EEPROM_INVAL; + }
+ debug("%s: eth: %u\n", __func__, eth); + return eth; +}
+/*
- Filter RTC information for phyCORE-i.MX8MP.
- returns: 0 if no RTC is populated. 1 if it is populated.
- PHYTEC_EEPROM_INVAL when the data is invalid.
- */
+u8 __maybe_unused phytec_get_imx8mp_rtc(struct phytec_eeprom_data *data) +{ + char *opt; + u8 rtc;
+ if (!data) + data = &eeprom_data;
+ if (data->api_rev < PHYTEC_API_REV2) + return PHYTEC_EEPROM_INVAL;
+ opt = phytec_get_opt(data); + if (opt) { + rtc = PHYTEC_GET_OPTION(opt[5]); + rtc &= 0x4; + rtc = !(rtc >> 2); + } else { + rtc = PHYTEC_EEPROM_INVAL; + } + debug("%s: rtc: %u\n", __func__, rtc); + return rtc; +}
diff --git a/board/phytec/common/imx8m_som_detection.h b/board/phytec/common/imx8m_som_detection.h new file mode 100644 index 000000000000..88d3037bf363 --- /dev/null +++ b/board/phytec/common/imx8m_som_detection.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/*
- Copyright (C) 2023 PHYTEC Messtechnik GmbH
- Author: Teresa Remmet t.remmet@phytec.de
- */
+#ifndef _PHYTEC_IMX8M_SOM_DETECTION_H +#define _PHYTEC_IMX8M_SOM_DETECTION_H
+#include "phytec_som_detection.h"
+#define PHYTEC_IMX8MQ_SOM 66 +#define PHYTEC_IMX8MM_SOM 69 +#define PHYTEC_IMX8MP_SOM 70
+#if IS_ENABLED(CONFIG_PHYTEC_IMX8M_SOM_DETECTION)
+u8 __maybe_unused phytec_imx8m_detect(struct phytec_eeprom_data *data); +u8 __maybe_unused phytec_get_imx8m_ddr_size(struct phytec_eeprom_data *data); +u8 __maybe_unused phytec_get_imx8mp_rtc(struct phytec_eeprom_data *data); +u8 __maybe_unused phytec_get_imx8m_spi(struct phytec_eeprom_data *data); +u8 __maybe_unused phytec_get_imx8m_eth(struct phytec_eeprom_data *data);
+#else
+inline u8 __maybe_unused phytec_imx8m_detect(struct phytec_eeprom_data *data) +{ + return -1; +}
+inline u8 __maybe_unused +phytec_get_imx8m_ddr_size(struct phytec_eeprom_data *data) +{ + return PHYTEC_EEPROM_INVAL; +}
+inline u8 __maybe_unused phytec_get_imx8mp_rtc(struct phytec_eeprom_data *data) +{ + return PHYTEC_EEPROM_INVAL; +}
+inline u8 __maybe_unused phytec_get_imx8m_spi(struct phytec_eeprom_data *data) +{ + return PHYTEC_EEPROM_INVAL; +}
+inline u8 __maybe_unused phytec_get_imx8m_eth(struct phytec_eeprom_data *data) +{ + return PHYTEC_EEPROM_INVAL; +}
+#endif /* IS_ENABLED(CONFIG_PHYTEC_IMX8M_SOM_DETECTION) */
+#endif /* _PHYTEC_IMX8M_SOM_DETECTION_H */
Add EEPROM detection initialisation for phyCORE-i.MX8MM and print SoM information during boot when successful.
Signed-off-by: Teresa Remmet t.remmet@phytec.de --- board/phytec/phycore_imx8mp/Kconfig | 1 + board/phytec/phycore_imx8mp/spl.c | 19 +++++++++++++++++++ configs/phycore-imx8mp_defconfig | 1 + 3 files changed, 21 insertions(+)
diff --git a/board/phytec/phycore_imx8mp/Kconfig b/board/phytec/phycore_imx8mp/Kconfig index c053a46fc9d1..f846d10bad9e 100644 --- a/board/phytec/phycore_imx8mp/Kconfig +++ b/board/phytec/phycore_imx8mp/Kconfig @@ -12,4 +12,5 @@ config SYS_CONFIG_NAME config IMX_CONFIG default "board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg"
+source "board/phytec/common/Kconfig" endif diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index faed6fc3b76d..e084fe081987 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -21,8 +21,13 @@ #include <power/pca9450.h> #include <spl.h>
+#include "../common/imx8m_som_detection.h" + DECLARE_GLOBAL_DATA_PTR;
+#define EEPROM_ADDR 0x51 +#define EEPROM_ADDR_FALLBACK 0x59 + int spl_board_boot_device(enum boot_device boot_dev_spl) { return BOOT_DEVICE_BOOTROM; @@ -30,6 +35,20 @@ int spl_board_boot_device(enum boot_device boot_dev_spl)
void spl_dram_init(void) { + int ret; + + ret = phytec_eeprom_data_setup_fallback(NULL, 0, EEPROM_ADDR, + EEPROM_ADDR_FALLBACK); + if (ret) + goto out; + + ret = phytec_imx8m_detect(NULL); + if (ret) + goto out; + + phytec_print_som_info(NULL); + +out: ddr_init(&dram_timing); }
diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index 7bf404be860b..7937e15e6422 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -12,6 +12,7 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mp-phyboard-pollux-rdk" CONFIG_SPL_TEXT_BASE=0x920000 CONFIG_TARGET_PHYCORE_IMX8MP=y +CONFIG_PHYTEC_SOM_DETECTION=y CONFIG_SYS_PROMPT="u-boot=> " CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_MMC=y
Hello Teresa,
On Tue, 2023-07-18 at 15:35 +0200, Teresa Remmet wrote:
Add EEPROM detection initialisation for phyCORE-i.MX8MM and print SoM information during boot when successful.
Signed-off-by: Teresa Remmet t.remmet@phytec.de
board/phytec/phycore_imx8mp/Kconfig | 1 + board/phytec/phycore_imx8mp/spl.c | 19 +++++++++++++++++++ configs/phycore-imx8mp_defconfig | 1 + 3 files changed, 21 insertions(+)
diff --git a/board/phytec/phycore_imx8mp/Kconfig b/board/phytec/phycore_imx8mp/Kconfig index c053a46fc9d1..f846d10bad9e 100644 --- a/board/phytec/phycore_imx8mp/Kconfig +++ b/board/phytec/phycore_imx8mp/Kconfig @@ -12,4 +12,5 @@ config SYS_CONFIG_NAME config IMX_CONFIG default "board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg" +source "board/phytec/common/Kconfig" endif diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index faed6fc3b76d..e084fe081987 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -21,8 +21,13 @@ #include <power/pca9450.h> #include <spl.h> +#include "../common/imx8m_som_detection.h"
DECLARE_GLOBAL_DATA_PTR; +#define EEPROM_ADDR 0x51 +#define EEPROM_ADDR_FALLBACK 0x59
int spl_board_boot_device(enum boot_device boot_dev_spl) { return BOOT_DEVICE_BOOTROM; @@ -30,6 +35,20 @@ int spl_board_boot_device(enum boot_device boot_dev_spl) void spl_dram_init(void) { + int ret;
+ ret = phytec_eeprom_data_setup_fallback(NULL, 0, EEPROM_ADDR, + EEPROM_ADDR_FALLBACK) ; + if (ret) + goto out;
+ ret = phytec_imx8m_detect(NULL); + if (ret) + goto out;
+ phytec_print_som_info(NULL);
Is it better to do a ddr_init here and then return? For safety reasons.
Yannic
+out: ddr_init(&dram_timing); } diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore- imx8mp_defconfig index 7bf404be860b..7937e15e6422 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -12,6 +12,7 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mp-phyboard-pollux-rdk" CONFIG_SPL_TEXT_BASE=0x920000 CONFIG_TARGET_PHYCORE_IMX8MP=y +CONFIG_PHYTEC_SOM_DETECTION=y CONFIG_SYS_PROMPT="u-boot=> " CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_MMC=y
Hello Yannic,
Am Donnerstag, dem 03.08.2023 um 10:10 +0200 schrieb Yannic Moog:
Hello Teresa,
On Tue, 2023-07-18 at 15:35 +0200, Teresa Remmet wrote:
Add EEPROM detection initialisation for phyCORE-i.MX8MM and print SoM information during boot when successful.
Signed-off-by: Teresa Remmet t.remmet@phytec.de
board/phytec/phycore_imx8mp/Kconfig | 1 + board/phytec/phycore_imx8mp/spl.c | 19 +++++++++++++++++++ configs/phycore-imx8mp_defconfig | 1 + 3 files changed, 21 insertions(+)
diff --git a/board/phytec/phycore_imx8mp/Kconfig b/board/phytec/phycore_imx8mp/Kconfig index c053a46fc9d1..f846d10bad9e 100644 --- a/board/phytec/phycore_imx8mp/Kconfig +++ b/board/phytec/phycore_imx8mp/Kconfig @@ -12,4 +12,5 @@ config SYS_CONFIG_NAME config IMX_CONFIG default "board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg" +source "board/phytec/common/Kconfig" endif diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index faed6fc3b76d..e084fe081987 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -21,8 +21,13 @@ #include <power/pca9450.h> #include <spl.h> +#include "../common/imx8m_som_detection.h"
DECLARE_GLOBAL_DATA_PTR; +#define EEPROM_ADDR 0x51 +#define EEPROM_ADDR_FALLBACK 0x59
int spl_board_boot_device(enum boot_device boot_dev_spl) { return BOOT_DEVICE_BOOTROM; @@ -30,6 +35,20 @@ int spl_board_boot_device(enum boot_device boot_dev_spl) void spl_dram_init(void) { + int ret;
+ ret = phytec_eeprom_data_setup_fallback(NULL, 0, EEPROM_ADDR, + EEPROM_ADDR_FALLBAC K) ; + if (ret) + goto out;
+ ret = phytec_imx8m_detect(NULL); + if (ret) + goto out;
+ phytec_print_som_info(NULL);
Is it better to do a ddr_init here and then return? For safety reasons.
I will just remove the second goto. As it is not needed.
Thanks, Teresa
Yannic
+out: ddr_init(&dram_timing); } diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore- imx8mp_defconfig index 7bf404be860b..7937e15e6422 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -12,6 +12,7 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mp-phyboard-pollux-rdk" CONFIG_SPL_TEXT_BASE=0x920000 CONFIG_TARGET_PHYCORE_IMX8MP=y +CONFIG_PHYTEC_SOM_DETECTION=y CONFIG_SYS_PROMPT="u-boot=> " CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPL_MMC=y
Due to PCB layout constraints in PCB revisions until including 1549.2, a RAM frequency of 2 GHz can cause rare instabilities. Set the RAM frequency to 1.5 GHz to achieve a stable system under all conditions.
Signed-off-by: Teresa Remmet t.remmet@phytec.de --- board/phytec/phycore_imx8mp/lpddr4_timing.c | 278 ++++++++++---------- 1 file changed, 135 insertions(+), 143 deletions(-)
diff --git a/board/phytec/phycore_imx8mp/lpddr4_timing.c b/board/phytec/phycore_imx8mp/lpddr4_timing.c index e59dd74377cb..f2707b859606 100644 --- a/board/phytec/phycore_imx8mp/lpddr4_timing.c +++ b/board/phytec/phycore_imx8mp/lpddr4_timing.c @@ -13,63 +13,68 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d400304, 0x1 }, { 0x3d400030, 0x1 }, { 0x3d400000, 0xa1080020 }, - { 0x3d400020, 0x323 }, - { 0x3d400024, 0x1e84800 }, - { 0x3d400064, 0x7a0118 }, - { 0x3d4000d0, 0xc00307a3 }, - { 0x3d4000d4, 0xc50000 }, - { 0x3d4000dc, 0xf4003f }, - { 0x3d4000e0, 0x330000 }, + { 0x3d400020, 0x1223 }, + { 0x3d400024, 0x16e3600 }, + { 0x3d400064, 0x5b00d2 }, + { 0x3d400070, 0x7027f90 }, + { 0x3d400074, 0x790 }, + { 0x3d4000d0, 0xc00305ba }, + { 0x3d4000d4, 0x940000 }, + { 0x3d4000dc, 0xd4002d }, + { 0x3d4000e0, 0xf10000 }, { 0x3d4000e8, 0x660048 }, { 0x3d4000ec, 0x160048 }, - { 0x3d400100, 0x2028222a }, - { 0x3d400104, 0x807bf }, - { 0x3d40010c, 0xe0e000 }, - { 0x3d400110, 0x12040a12 }, - { 0x3d400114, 0x2050f0f }, - { 0x3d400118, 0x1010009 }, - { 0x3d40011c, 0x501 }, - { 0x3d400130, 0x20800 }, - { 0x3d400134, 0xe100002 }, - { 0x3d400138, 0x120 }, - { 0x3d400144, 0xc80064 }, - { 0x3d400180, 0x3e8001e }, - { 0x3d400184, 0x3207a12 }, + { 0x3d400100, 0x191e1920 }, + { 0x3d400104, 0x60630 }, + { 0x3d40010c, 0xb0b000 }, + { 0x3d400110, 0xe04080e }, + { 0x3d400114, 0x2040c0c }, + { 0x3d400118, 0x1010007 }, + { 0x3d40011c, 0x401 }, + { 0x3d400130, 0x20600 }, + { 0x3d400134, 0xc100002 }, + { 0x3d400138, 0xd8 }, + { 0x3d400144, 0x96004b }, + { 0x3d400180, 0x2ee0017 }, + { 0x3d400184, 0x2605b8e }, { 0x3d400188, 0x0 }, - { 0x3d400190, 0x49f820e }, + { 0x3d400190, 0x49b820a }, { 0x3d400194, 0x80303 }, - { 0x3d4001b4, 0x1f0e }, + { 0x3d4001b4, 0x1b0a }, { 0x3d4001a0, 0xe0400018 }, { 0x3d4001a4, 0xdf00e4 }, { 0x3d4001a8, 0x80000000 }, { 0x3d4001b0, 0x11 }, - { 0x3d4001c0, 0x1 }, + { 0x3d4001c0, 0x7 }, { 0x3d4001c4, 0x1 }, { 0x3d4000f4, 0xc99 }, - { 0x3d400108, 0x9121c1c }, + { 0x3d400108, 0x7101817 }, { 0x3d400200, 0x1f }, + { 0x3d400208, 0x0 }, { 0x3d40020c, 0x0 }, { 0x3d400210, 0x1f1f }, { 0x3d400204, 0x80808 }, { 0x3d400214, 0x7070707 }, { 0x3d400218, 0x7070707 }, - { 0x3d40021c, 0xf07 }, - { 0x3d400250, 0x1f05 }, - { 0x3d400254, 0x1f }, - { 0x3d400264, 0x90003ff }, - { 0x3d40026c, 0x20003ff }, + { 0x3d40021c, 0xf0f }, + { 0x3d400250, 0x1705 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, { 0x3d400400, 0x111 }, + { 0x3d400404, 0x72ff }, { 0x3d400408, 0x72ff }, - { 0x3d400494, 0x1000e00 }, - { 0x3d400498, 0x3ff0000 }, - { 0x3d40049c, 0x1000e00 }, - { 0x3d4004a0, 0x3ff0000 }, - { 0x3d402020, 0x21 }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x1021 }, { 0x3d402024, 0x30d400 }, - { 0x3d402050, 0x20d040 }, + { 0x3d402050, 0x20d000 }, { 0x3d402064, 0xc001c }, { 0x3d4020dc, 0x840000 }, - { 0x3d4020e0, 0x330000 }, + { 0x3d4020e0, 0xf30000 }, { 0x3d4020e8, 0x660048 }, { 0x3d4020ec, 0x160048 }, { 0x3d402100, 0xa040305 }, @@ -89,12 +94,12 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d402194, 0x80303 }, { 0x3d4021b4, 0x100 }, { 0x3d4020f4, 0xc99 }, - { 0x3d403020, 0x21 }, + { 0x3d403020, 0x1021 }, { 0x3d403024, 0xc3500 }, - { 0x3d403050, 0x20d040 }, + { 0x3d403050, 0x20d000 }, { 0x3d403064, 0x30007 }, { 0x3d4030dc, 0x840000 }, - { 0x3d4030e0, 0x330000 }, + { 0x3d4030e0, 0xf30000 }, { 0x3d4030e8, 0x660048 }, { 0x3d4030ec, 0x160048 }, { 0x3d403100, 0xa010102 }, @@ -137,12 +142,12 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x110a7, 0x6 }, { 0x120a0, 0x0 }, { 0x120a1, 0x1 }, - { 0x120a2, 0x3 }, - { 0x120a3, 0x2 }, - { 0x120a4, 0x5 }, - { 0x120a5, 0x4 }, - { 0x120a6, 0x7 }, - { 0x120a7, 0x6 }, + { 0x120a2, 0x2 }, + { 0x120a3, 0x3 }, + { 0x120a4, 0x4 }, + { 0x120a5, 0x5 }, + { 0x120a6, 0x6 }, + { 0x120a7, 0x7 }, { 0x130a0, 0x0 }, { 0x130a1, 0x1 }, { 0x130a2, 0x2 }, @@ -185,7 +190,7 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x7055, 0x1ff }, { 0x8055, 0x1ff }, { 0x9055, 0x1ff }, - { 0x200c5, 0x18 }, + { 0x200c5, 0x19 }, { 0x1200c5, 0x7 }, { 0x2200c5, 0x7 }, { 0x2002e, 0x2 }, @@ -194,11 +199,11 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x90204, 0x0 }, { 0x190204, 0x0 }, { 0x290204, 0x0 }, - { 0x20024, 0x1e3 }, + { 0x20024, 0x1a3 }, { 0x2003a, 0x2 }, - { 0x120024, 0x1e3 }, + { 0x120024, 0x1a3 }, { 0x2003a, 0x2 }, - { 0x220024, 0x1e3 }, + { 0x220024, 0x1a3 }, { 0x2003a, 0x2 }, { 0x20056, 0x3 }, { 0x120056, 0x3 }, @@ -264,7 +269,7 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x20018, 0x3 }, { 0x20075, 0x4 }, { 0x20050, 0x0 }, - { 0x20008, 0x3e8 }, + { 0x20008, 0x2ee }, { 0x120008, 0x64 }, { 0x220008, 0x19 }, { 0x20088, 0x9 }, @@ -310,19 +315,15 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x200f6, 0x0 }, { 0x200f7, 0xf000 }, { 0x20025, 0x0 }, - { 0x2002d, 0x0 }, - { 0x12002d, 0x0 }, - { 0x22002d, 0x0 }, + { 0x2002d, 0x1 }, + { 0x12002d, 0x1 }, + { 0x22002d, 0x1 }, { 0x2007d, 0x212 }, { 0x12007d, 0x212 }, { 0x22007d, 0x212 }, { 0x2007c, 0x61 }, { 0x12007c, 0x61 }, { 0x22007c, 0x61 }, - { 0x1004a, 0x500 }, - { 0x1104a, 0x500 }, - { 0x1204a, 0x500 }, - { 0x1304a, 0x500 }, { 0x2002c, 0x0 }, };
@@ -1052,7 +1053,7 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { /* P0 message block paremeter for training firmware */ static struct dram_cfg_param ddr_fsp0_cfg[] = { { 0xd0000, 0x0 }, - { 0x54003, 0xfa0 }, + { 0x54003, 0xbb8 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, { 0x54006, 0x14 }, @@ -1061,26 +1062,26 @@ static struct dram_cfg_param ddr_fsp0_cfg[] = { { 0x5400b, 0x2 }, { 0x5400f, 0x100 }, { 0x54012, 0x110 }, - { 0x54019, 0x3ff4 }, - { 0x5401a, 0x33 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0xf1 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, - { 0x5401f, 0x3ff4 }, - { 0x54020, 0x33 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0xf1 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, - { 0x54032, 0xf400 }, - { 0x54033, 0x333f }, + { 0x54032, 0xd400 }, + { 0x54033, 0xf12d }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, - { 0x54038, 0xf400 }, - { 0x54039, 0x333f }, + { 0x54038, 0xd400 }, + { 0x54039, 0xf12d }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1102,25 +1103,25 @@ static struct dram_cfg_param ddr_fsp1_cfg[] = { { 0x5400f, 0x100 }, { 0x54012, 0x110 }, { 0x54019, 0x84 }, - { 0x5401a, 0x33 }, + { 0x5401a, 0xf3 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, { 0x5401f, 0x84 }, - { 0x54020, 0x33 }, + { 0x54020, 0xf3 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, { 0x54032, 0x8400 }, - { 0x54033, 0x3300 }, + { 0x54033, 0xf300 }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, { 0x54038, 0x8400 }, - { 0x54039, 0x3300 }, + { 0x54039, 0xf300 }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1142,25 +1143,25 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = { { 0x5400f, 0x100 }, { 0x54012, 0x110 }, { 0x54019, 0x84 }, - { 0x5401a, 0x33 }, + { 0x5401a, 0xf3 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, { 0x5401f, 0x84 }, - { 0x54020, 0x33 }, + { 0x54020, 0xf3 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, { 0x54032, 0x8400 }, - { 0x54033, 0x3300 }, + { 0x54033, 0xf300 }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, { 0x54038, 0x8400 }, - { 0x54039, 0x3300 }, + { 0x54039, 0xf300 }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1171,37 +1172,36 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = { /* P0 2D message block paremeter for training firmware */ static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { { 0xd0000, 0x0 }, - { 0x54003, 0xfa0 }, + { 0x54003, 0xbb8 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, { 0x54006, 0x14 }, { 0x54008, 0x61 }, { 0x54009, 0xc8 }, { 0x5400b, 0x2 }, - { 0x5400d, 0x100 }, { 0x5400f, 0x100 }, { 0x54010, 0x1f7f }, { 0x54012, 0x110 }, - { 0x54019, 0x3ff4 }, - { 0x5401a, 0x33 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0xf1 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, - { 0x5401f, 0x3ff4 }, - { 0x54020, 0x33 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0xf1 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, - { 0x54032, 0xf400 }, - { 0x54033, 0x333f }, + { 0x54032, 0xd400 }, + { 0x54033, 0xf12d }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, - { 0x54038, 0xf400 }, - { 0x54039, 0x333f }, + { 0x54038, 0xd400 }, + { 0x54039, 0xf12d }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1629,67 +1629,58 @@ static struct dram_cfg_param ddr_phy_pie[] = { { 0x90155, 0x20 }, { 0x90156, 0x2aa }, { 0x90157, 0x9 }, - { 0x90158, 0x0 }, - { 0x90159, 0x400 }, - { 0x9015a, 0x10e }, - { 0x9015b, 0x8 }, - { 0x9015c, 0xe8 }, - { 0x9015d, 0x109 }, - { 0x9015e, 0x0 }, - { 0x9015f, 0x8140 }, - { 0x90160, 0x10c }, - { 0x90161, 0x10 }, - { 0x90162, 0x8138 }, - { 0x90163, 0x10c }, - { 0x90164, 0x8 }, - { 0x90165, 0x7c8 }, - { 0x90166, 0x101 }, - { 0x90167, 0x8 }, - { 0x90168, 0x448 }, + { 0x90158, 0x8 }, + { 0x90159, 0xe8 }, + { 0x9015a, 0x109 }, + { 0x9015b, 0x0 }, + { 0x9015c, 0x8140 }, + { 0x9015d, 0x10c }, + { 0x9015e, 0x10 }, + { 0x9015f, 0x8138 }, + { 0x90160, 0x104 }, + { 0x90161, 0x8 }, + { 0x90162, 0x448 }, + { 0x90163, 0x109 }, + { 0x90164, 0xf }, + { 0x90165, 0x7c0 }, + { 0x90166, 0x109 }, + { 0x90167, 0x0 }, + { 0x90168, 0xe8 }, { 0x90169, 0x109 }, - { 0x9016a, 0xf }, - { 0x9016b, 0x7c0 }, + { 0x9016a, 0x47 }, + { 0x9016b, 0x630 }, { 0x9016c, 0x109 }, - { 0x9016d, 0x0 }, - { 0x9016e, 0xe8 }, + { 0x9016d, 0x8 }, + { 0x9016e, 0x618 }, { 0x9016f, 0x109 }, - { 0x90170, 0x47 }, - { 0x90171, 0x630 }, + { 0x90170, 0x8 }, + { 0x90171, 0xe0 }, { 0x90172, 0x109 }, - { 0x90173, 0x8 }, - { 0x90174, 0x618 }, + { 0x90173, 0x0 }, + { 0x90174, 0x7c8 }, { 0x90175, 0x109 }, { 0x90176, 0x8 }, - { 0x90177, 0xe0 }, - { 0x90178, 0x109 }, + { 0x90177, 0x8140 }, + { 0x90178, 0x10c }, { 0x90179, 0x0 }, - { 0x9017a, 0x7c8 }, + { 0x9017a, 0x478 }, { 0x9017b, 0x109 }, - { 0x9017c, 0x8 }, - { 0x9017d, 0x8140 }, - { 0x9017e, 0x10c }, - { 0x9017f, 0x0 }, - { 0x90180, 0x478 }, - { 0x90181, 0x109 }, - { 0x90182, 0x0 }, - { 0x90183, 0x1 }, - { 0x90184, 0x8 }, - { 0x90185, 0x8 }, - { 0x90186, 0x4 }, - { 0x90187, 0x8 }, - { 0x90188, 0x8 }, - { 0x90189, 0x7c8 }, - { 0x9018a, 0x101 }, - { 0x90006, 0x0 }, - { 0x90007, 0x0 }, - { 0x90008, 0x8 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x1 }, + { 0x9017e, 0x8 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x4 }, + { 0x90181, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, { 0x90009, 0x0 }, - { 0x9000a, 0x0 }, - { 0x9000b, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, { 0xd00e7, 0x400 }, { 0x90017, 0x0 }, { 0x9001f, 0x29 }, - { 0x90026, 0x6a }, + { 0x90026, 0x68 }, { 0x400d0, 0x0 }, { 0x400d1, 0x101 }, { 0x400d2, 0x105 }, @@ -1699,15 +1690,16 @@ static struct dram_cfg_param ddr_phy_pie[] = { { 0x400d6, 0x20a }, { 0x400d7, 0x20b }, { 0x2003a, 0x2 }, - { 0x2000b, 0x7d }, - { 0x2000c, 0xfa }, - { 0x2000d, 0x9c4 }, + { 0x200be, 0x3 }, + { 0x2000b, 0x34b }, + { 0x2000c, 0xbb }, + { 0x2000d, 0x753 }, { 0x2000e, 0x2c }, - { 0x12000b, 0xc }, + { 0x12000b, 0x70 }, { 0x12000c, 0x19 }, { 0x12000d, 0xfa }, { 0x12000e, 0x10 }, - { 0x22000b, 0x3 }, + { 0x22000b, 0x1c }, { 0x22000c, 0x6 }, { 0x22000d, 0x3e }, { 0x22000e, 0x10 }, @@ -1804,8 +1796,8 @@ static struct dram_cfg_param ddr_phy_pie[] = {
static struct dram_fsp_msg ddr_dram_fsp_msg[] = { { - /* P0 4000mts 1D */ - .drate = 4000, + /* P0 3000mts 1D */ + .drate = 3000, .fw_type = FW_1D_IMAGE, .fsp_cfg = ddr_fsp0_cfg, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), @@ -1825,8 +1817,8 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = { .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), }, { - /* P0 4000mts 2D */ - .drate = 4000, + /* P0 3000mts 2D */ + .drate = 3000, .fw_type = FW_2D_IMAGE, .fsp_cfg = ddr_fsp0_2d_cfg, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), @@ -1845,5 +1837,5 @@ struct dram_timing_info dram_timing = { .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), .ddrphy_pie = ddr_phy_pie, .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 4000, 400, 100, }, + .fsp_table = { 3000, 400, 100, }, };
Hello Teresa,
On Tue, 2023-07-18 at 15:35 +0200, Teresa Remmet wrote:
Due to PCB layout constraints in PCB revisions until including 1549.2, a RAM frequency of 2 GHz can cause rare instabilities. Set the RAM frequency to 1.5 GHz to achieve a stable system under all conditions.
Signed-off-by: Teresa Remmet t.remmet@phytec.de
board/phytec/phycore_imx8mp/lpddr4_timing.c | 278 ++++++++++--------
1 file changed, 135 insertions(+), 143 deletions(-)
diff --git a/board/phytec/phycore_imx8mp/lpddr4_timing.c b/board/phytec/phycore_imx8mp/lpddr4_timing.c index e59dd74377cb..f2707b859606 100644 --- a/board/phytec/phycore_imx8mp/lpddr4_timing.c +++ b/board/phytec/phycore_imx8mp/lpddr4_timing.c @@ -13,63 +13,68 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d400304, 0x1 }, { 0x3d400030, 0x1 }, { 0x3d400000, 0xa1080020 }, - { 0x3d400020, 0x323 }, - { 0x3d400024, 0x1e84800 }, - { 0x3d400064, 0x7a0118 }, - { 0x3d4000d0, 0xc00307a3 }, - { 0x3d4000d4, 0xc50000 }, - { 0x3d4000dc, 0xf4003f }, - { 0x3d4000e0, 0x330000 }, + { 0x3d400020, 0x1223 }, + { 0x3d400024, 0x16e3600 }, + { 0x3d400064, 0x5b00d2 }, + { 0x3d400070, 0x7027f90 }, + { 0x3d400074, 0x790 }, + { 0x3d4000d0, 0xc00305ba }, + { 0x3d4000d4, 0x940000 }, + { 0x3d4000dc, 0xd4002d }, + { 0x3d4000e0, 0xf10000 }, { 0x3d4000e8, 0x660048 }, { 0x3d4000ec, 0x160048 }, - { 0x3d400100, 0x2028222a }, - { 0x3d400104, 0x807bf }, - { 0x3d40010c, 0xe0e000 }, - { 0x3d400110, 0x12040a12 }, - { 0x3d400114, 0x2050f0f }, - { 0x3d400118, 0x1010009 }, - { 0x3d40011c, 0x501 }, - { 0x3d400130, 0x20800 }, - { 0x3d400134, 0xe100002 }, - { 0x3d400138, 0x120 }, - { 0x3d400144, 0xc80064 }, - { 0x3d400180, 0x3e8001e }, - { 0x3d400184, 0x3207a12 }, + { 0x3d400100, 0x191e1920 }, + { 0x3d400104, 0x60630 }, + { 0x3d40010c, 0xb0b000 }, + { 0x3d400110, 0xe04080e }, + { 0x3d400114, 0x2040c0c }, + { 0x3d400118, 0x1010007 }, + { 0x3d40011c, 0x401 }, + { 0x3d400130, 0x20600 }, + { 0x3d400134, 0xc100002 }, + { 0x3d400138, 0xd8 }, + { 0x3d400144, 0x96004b }, + { 0x3d400180, 0x2ee0017 }, + { 0x3d400184, 0x2605b8e }, { 0x3d400188, 0x0 }, - { 0x3d400190, 0x49f820e }, + { 0x3d400190, 0x49b820a }, { 0x3d400194, 0x80303 }, - { 0x3d4001b4, 0x1f0e }, + { 0x3d4001b4, 0x1b0a }, { 0x3d4001a0, 0xe0400018 }, { 0x3d4001a4, 0xdf00e4 }, { 0x3d4001a8, 0x80000000 }, { 0x3d4001b0, 0x11 }, - { 0x3d4001c0, 0x1 }, + { 0x3d4001c0, 0x7 }, { 0x3d4001c4, 0x1 }, { 0x3d4000f4, 0xc99 }, - { 0x3d400108, 0x9121c1c }, + { 0x3d400108, 0x7101817 }, { 0x3d400200, 0x1f },
+ { 0x3d400208, 0x0 },
Are you sure this line is correct? Recheck, please.
Yannic
{ 0x3d40020c, 0x0 }, { 0x3d400210, 0x1f1f }, { 0x3d400204, 0x80808 }, { 0x3d400214, 0x7070707 }, { 0x3d400218, 0x7070707 }, - { 0x3d40021c, 0xf07 }, - { 0x3d400250, 0x1f05 }, - { 0x3d400254, 0x1f }, - { 0x3d400264, 0x90003ff }, - { 0x3d40026c, 0x20003ff }, + { 0x3d40021c, 0xf0f }, + { 0x3d400250, 0x1705 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, { 0x3d400400, 0x111 }, + { 0x3d400404, 0x72ff }, { 0x3d400408, 0x72ff }, - { 0x3d400494, 0x1000e00 }, - { 0x3d400498, 0x3ff0000 }, - { 0x3d40049c, 0x1000e00 }, - { 0x3d4004a0, 0x3ff0000 }, - { 0x3d402020, 0x21 }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x1021 }, { 0x3d402024, 0x30d400 }, - { 0x3d402050, 0x20d040 }, + { 0x3d402050, 0x20d000 }, { 0x3d402064, 0xc001c }, { 0x3d4020dc, 0x840000 }, - { 0x3d4020e0, 0x330000 }, + { 0x3d4020e0, 0xf30000 }, { 0x3d4020e8, 0x660048 }, { 0x3d4020ec, 0x160048 }, { 0x3d402100, 0xa040305 }, @@ -89,12 +94,12 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d402194, 0x80303 }, { 0x3d4021b4, 0x100 }, { 0x3d4020f4, 0xc99 }, - { 0x3d403020, 0x21 }, + { 0x3d403020, 0x1021 }, { 0x3d403024, 0xc3500 }, - { 0x3d403050, 0x20d040 }, + { 0x3d403050, 0x20d000 }, { 0x3d403064, 0x30007 }, { 0x3d4030dc, 0x840000 }, - { 0x3d4030e0, 0x330000 }, + { 0x3d4030e0, 0xf30000 }, { 0x3d4030e8, 0x660048 }, { 0x3d4030ec, 0x160048 }, { 0x3d403100, 0xa010102 }, @@ -137,12 +142,12 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x110a7, 0x6 }, { 0x120a0, 0x0 }, { 0x120a1, 0x1 }, - { 0x120a2, 0x3 }, - { 0x120a3, 0x2 }, - { 0x120a4, 0x5 }, - { 0x120a5, 0x4 }, - { 0x120a6, 0x7 }, - { 0x120a7, 0x6 }, + { 0x120a2, 0x2 }, + { 0x120a3, 0x3 }, + { 0x120a4, 0x4 }, + { 0x120a5, 0x5 }, + { 0x120a6, 0x6 }, + { 0x120a7, 0x7 }, { 0x130a0, 0x0 }, { 0x130a1, 0x1 }, { 0x130a2, 0x2 }, @@ -185,7 +190,7 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x7055, 0x1ff }, { 0x8055, 0x1ff }, { 0x9055, 0x1ff }, - { 0x200c5, 0x18 }, + { 0x200c5, 0x19 }, { 0x1200c5, 0x7 }, { 0x2200c5, 0x7 }, { 0x2002e, 0x2 }, @@ -194,11 +199,11 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x90204, 0x0 }, { 0x190204, 0x0 }, { 0x290204, 0x0 }, - { 0x20024, 0x1e3 }, + { 0x20024, 0x1a3 }, { 0x2003a, 0x2 }, - { 0x120024, 0x1e3 }, + { 0x120024, 0x1a3 }, { 0x2003a, 0x2 }, - { 0x220024, 0x1e3 }, + { 0x220024, 0x1a3 }, { 0x2003a, 0x2 }, { 0x20056, 0x3 }, { 0x120056, 0x3 }, @@ -264,7 +269,7 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x20018, 0x3 }, { 0x20075, 0x4 }, { 0x20050, 0x0 }, - { 0x20008, 0x3e8 }, + { 0x20008, 0x2ee }, { 0x120008, 0x64 }, { 0x220008, 0x19 }, { 0x20088, 0x9 }, @@ -310,19 +315,15 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x200f6, 0x0 }, { 0x200f7, 0xf000 }, { 0x20025, 0x0 }, - { 0x2002d, 0x0 }, - { 0x12002d, 0x0 }, - { 0x22002d, 0x0 }, + { 0x2002d, 0x1 }, + { 0x12002d, 0x1 }, + { 0x22002d, 0x1 }, { 0x2007d, 0x212 }, { 0x12007d, 0x212 }, { 0x22007d, 0x212 }, { 0x2007c, 0x61 }, { 0x12007c, 0x61 }, { 0x22007c, 0x61 }, - { 0x1004a, 0x500 }, - { 0x1104a, 0x500 }, - { 0x1204a, 0x500 }, - { 0x1304a, 0x500 }, { 0x2002c, 0x0 }, }; @@ -1052,7 +1053,7 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { /* P0 message block paremeter for training firmware */ static struct dram_cfg_param ddr_fsp0_cfg[] = { { 0xd0000, 0x0 }, - { 0x54003, 0xfa0 }, + { 0x54003, 0xbb8 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, { 0x54006, 0x14 }, @@ -1061,26 +1062,26 @@ static struct dram_cfg_param ddr_fsp0_cfg[] = { { 0x5400b, 0x2 }, { 0x5400f, 0x100 }, { 0x54012, 0x110 }, - { 0x54019, 0x3ff4 }, - { 0x5401a, 0x33 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0xf1 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, - { 0x5401f, 0x3ff4 }, - { 0x54020, 0x33 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0xf1 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, - { 0x54032, 0xf400 }, - { 0x54033, 0x333f }, + { 0x54032, 0xd400 }, + { 0x54033, 0xf12d }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, - { 0x54038, 0xf400 }, - { 0x54039, 0x333f }, + { 0x54038, 0xd400 }, + { 0x54039, 0xf12d }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1102,25 +1103,25 @@ static struct dram_cfg_param ddr_fsp1_cfg[] = { { 0x5400f, 0x100 }, { 0x54012, 0x110 }, { 0x54019, 0x84 }, - { 0x5401a, 0x33 }, + { 0x5401a, 0xf3 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, { 0x5401f, 0x84 }, - { 0x54020, 0x33 }, + { 0x54020, 0xf3 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, { 0x54032, 0x8400 }, - { 0x54033, 0x3300 }, + { 0x54033, 0xf300 }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, { 0x54038, 0x8400 }, - { 0x54039, 0x3300 }, + { 0x54039, 0xf300 }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1142,25 +1143,25 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = { { 0x5400f, 0x100 }, { 0x54012, 0x110 }, { 0x54019, 0x84 }, - { 0x5401a, 0x33 }, + { 0x5401a, 0xf3 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, { 0x5401f, 0x84 }, - { 0x54020, 0x33 }, + { 0x54020, 0xf3 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, { 0x54032, 0x8400 }, - { 0x54033, 0x3300 }, + { 0x54033, 0xf300 }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, { 0x54038, 0x8400 }, - { 0x54039, 0x3300 }, + { 0x54039, 0xf300 }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1171,37 +1172,36 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = { /* P0 2D message block paremeter for training firmware */ static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { { 0xd0000, 0x0 }, - { 0x54003, 0xfa0 }, + { 0x54003, 0xbb8 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, { 0x54006, 0x14 }, { 0x54008, 0x61 }, { 0x54009, 0xc8 }, { 0x5400b, 0x2 }, - { 0x5400d, 0x100 }, { 0x5400f, 0x100 }, { 0x54010, 0x1f7f }, { 0x54012, 0x110 }, - { 0x54019, 0x3ff4 }, - { 0x5401a, 0x33 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0xf1 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, - { 0x5401f, 0x3ff4 }, - { 0x54020, 0x33 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0xf1 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, - { 0x54032, 0xf400 }, - { 0x54033, 0x333f }, + { 0x54032, 0xd400 }, + { 0x54033, 0xf12d }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, - { 0x54038, 0xf400 }, - { 0x54039, 0x333f }, + { 0x54038, 0xd400 }, + { 0x54039, 0xf12d }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1629,67 +1629,58 @@ static struct dram_cfg_param ddr_phy_pie[] = { { 0x90155, 0x20 }, { 0x90156, 0x2aa }, { 0x90157, 0x9 }, - { 0x90158, 0x0 }, - { 0x90159, 0x400 }, - { 0x9015a, 0x10e }, - { 0x9015b, 0x8 }, - { 0x9015c, 0xe8 }, - { 0x9015d, 0x109 }, - { 0x9015e, 0x0 }, - { 0x9015f, 0x8140 }, - { 0x90160, 0x10c }, - { 0x90161, 0x10 }, - { 0x90162, 0x8138 }, - { 0x90163, 0x10c }, - { 0x90164, 0x8 }, - { 0x90165, 0x7c8 }, - { 0x90166, 0x101 }, - { 0x90167, 0x8 }, - { 0x90168, 0x448 }, + { 0x90158, 0x8 }, + { 0x90159, 0xe8 }, + { 0x9015a, 0x109 }, + { 0x9015b, 0x0 }, + { 0x9015c, 0x8140 }, + { 0x9015d, 0x10c }, + { 0x9015e, 0x10 }, + { 0x9015f, 0x8138 }, + { 0x90160, 0x104 }, + { 0x90161, 0x8 }, + { 0x90162, 0x448 }, + { 0x90163, 0x109 }, + { 0x90164, 0xf }, + { 0x90165, 0x7c0 }, + { 0x90166, 0x109 }, + { 0x90167, 0x0 }, + { 0x90168, 0xe8 }, { 0x90169, 0x109 }, - { 0x9016a, 0xf }, - { 0x9016b, 0x7c0 }, + { 0x9016a, 0x47 }, + { 0x9016b, 0x630 }, { 0x9016c, 0x109 }, - { 0x9016d, 0x0 }, - { 0x9016e, 0xe8 }, + { 0x9016d, 0x8 }, + { 0x9016e, 0x618 }, { 0x9016f, 0x109 }, - { 0x90170, 0x47 }, - { 0x90171, 0x630 }, + { 0x90170, 0x8 }, + { 0x90171, 0xe0 }, { 0x90172, 0x109 }, - { 0x90173, 0x8 }, - { 0x90174, 0x618 }, + { 0x90173, 0x0 }, + { 0x90174, 0x7c8 }, { 0x90175, 0x109 }, { 0x90176, 0x8 }, - { 0x90177, 0xe0 }, - { 0x90178, 0x109 }, + { 0x90177, 0x8140 }, + { 0x90178, 0x10c }, { 0x90179, 0x0 }, - { 0x9017a, 0x7c8 }, + { 0x9017a, 0x478 }, { 0x9017b, 0x109 }, - { 0x9017c, 0x8 }, - { 0x9017d, 0x8140 }, - { 0x9017e, 0x10c }, - { 0x9017f, 0x0 }, - { 0x90180, 0x478 }, - { 0x90181, 0x109 }, - { 0x90182, 0x0 }, - { 0x90183, 0x1 }, - { 0x90184, 0x8 }, - { 0x90185, 0x8 }, - { 0x90186, 0x4 }, - { 0x90187, 0x8 }, - { 0x90188, 0x8 }, - { 0x90189, 0x7c8 }, - { 0x9018a, 0x101 }, - { 0x90006, 0x0 }, - { 0x90007, 0x0 }, - { 0x90008, 0x8 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x1 }, + { 0x9017e, 0x8 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x4 }, + { 0x90181, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, { 0x90009, 0x0 }, - { 0x9000a, 0x0 }, - { 0x9000b, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, { 0xd00e7, 0x400 }, { 0x90017, 0x0 }, { 0x9001f, 0x29 }, - { 0x90026, 0x6a }, + { 0x90026, 0x68 }, { 0x400d0, 0x0 }, { 0x400d1, 0x101 }, { 0x400d2, 0x105 }, @@ -1699,15 +1690,16 @@ static struct dram_cfg_param ddr_phy_pie[] = { { 0x400d6, 0x20a }, { 0x400d7, 0x20b }, { 0x2003a, 0x2 }, - { 0x2000b, 0x7d }, - { 0x2000c, 0xfa }, - { 0x2000d, 0x9c4 }, + { 0x200be, 0x3 }, + { 0x2000b, 0x34b }, + { 0x2000c, 0xbb }, + { 0x2000d, 0x753 }, { 0x2000e, 0x2c }, - { 0x12000b, 0xc }, + { 0x12000b, 0x70 }, { 0x12000c, 0x19 }, { 0x12000d, 0xfa }, { 0x12000e, 0x10 }, - { 0x22000b, 0x3 }, + { 0x22000b, 0x1c }, { 0x22000c, 0x6 }, { 0x22000d, 0x3e }, { 0x22000e, 0x10 }, @@ -1804,8 +1796,8 @@ static struct dram_cfg_param ddr_phy_pie[] = { static struct dram_fsp_msg ddr_dram_fsp_msg[] = { { - /* P0 4000mts 1D */ - .drate = 4000, + /* P0 3000mts 1D */ + .drate = 3000, .fw_type = FW_1D_IMAGE, .fsp_cfg = ddr_fsp0_cfg, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), @@ -1825,8 +1817,8 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = { .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), }, { - /* P0 4000mts 2D */ - .drate = 4000, + /* P0 3000mts 2D */ + .drate = 3000, .fw_type = FW_2D_IMAGE, .fsp_cfg = ddr_fsp0_2d_cfg, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), @@ -1845,5 +1837,5 @@ struct dram_timing_info dram_timing = { .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), .ddrphy_pie = ddr_phy_pie, .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 4000, 400, 100, }, + .fsp_table = { 3000, 400, 100, }, };
Hello Yannic,
Am Dienstag, dem 08.08.2023 um 09:25 +0200 schrieb Yannic Moog:
Hello Teresa,
On Tue, 2023-07-18 at 15:35 +0200, Teresa Remmet wrote:
Due to PCB layout constraints in PCB revisions until including 1549.2, a RAM frequency of 2 GHz can cause rare instabilities. Set the RAM frequency to 1.5 GHz to achieve a stable system under all conditions.
Signed-off-by: Teresa Remmet t.remmet@phytec.de
board/phytec/phycore_imx8mp/lpddr4_timing.c | 278 ++++++++++------
-- 1 file changed, 135 insertions(+), 143 deletions(-)
diff --git a/board/phytec/phycore_imx8mp/lpddr4_timing.c b/board/phytec/phycore_imx8mp/lpddr4_timing.c index e59dd74377cb..f2707b859606 100644 --- a/board/phytec/phycore_imx8mp/lpddr4_timing.c +++ b/board/phytec/phycore_imx8mp/lpddr4_timing.c @@ -13,63 +13,68 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d400304, 0x1 }, { 0x3d400030, 0x1 }, { 0x3d400000, 0xa1080020 }, - { 0x3d400020, 0x323 }, - { 0x3d400024, 0x1e84800 }, - { 0x3d400064, 0x7a0118 }, - { 0x3d4000d0, 0xc00307a3 }, - { 0x3d4000d4, 0xc50000 }, - { 0x3d4000dc, 0xf4003f }, - { 0x3d4000e0, 0x330000 }, + { 0x3d400020, 0x1223 }, + { 0x3d400024, 0x16e3600 }, + { 0x3d400064, 0x5b00d2 }, + { 0x3d400070, 0x7027f90 }, + { 0x3d400074, 0x790 }, + { 0x3d4000d0, 0xc00305ba }, + { 0x3d4000d4, 0x940000 }, + { 0x3d4000dc, 0xd4002d }, + { 0x3d4000e0, 0xf10000 }, { 0x3d4000e8, 0x660048 }, { 0x3d4000ec, 0x160048 }, - { 0x3d400100, 0x2028222a }, - { 0x3d400104, 0x807bf }, - { 0x3d40010c, 0xe0e000 }, - { 0x3d400110, 0x12040a12 }, - { 0x3d400114, 0x2050f0f }, - { 0x3d400118, 0x1010009 }, - { 0x3d40011c, 0x501 }, - { 0x3d400130, 0x20800 }, - { 0x3d400134, 0xe100002 }, - { 0x3d400138, 0x120 }, - { 0x3d400144, 0xc80064 }, - { 0x3d400180, 0x3e8001e }, - { 0x3d400184, 0x3207a12 }, + { 0x3d400100, 0x191e1920 }, + { 0x3d400104, 0x60630 }, + { 0x3d40010c, 0xb0b000 }, + { 0x3d400110, 0xe04080e }, + { 0x3d400114, 0x2040c0c }, + { 0x3d400118, 0x1010007 }, + { 0x3d40011c, 0x401 }, + { 0x3d400130, 0x20600 }, + { 0x3d400134, 0xc100002 }, + { 0x3d400138, 0xd8 }, + { 0x3d400144, 0x96004b }, + { 0x3d400180, 0x2ee0017 }, + { 0x3d400184, 0x2605b8e }, { 0x3d400188, 0x0 }, - { 0x3d400190, 0x49f820e }, + { 0x3d400190, 0x49b820a }, { 0x3d400194, 0x80303 }, - { 0x3d4001b4, 0x1f0e }, + { 0x3d4001b4, 0x1b0a }, { 0x3d4001a0, 0xe0400018 }, { 0x3d4001a4, 0xdf00e4 }, { 0x3d4001a8, 0x80000000 }, { 0x3d4001b0, 0x11 }, - { 0x3d4001c0, 0x1 }, + { 0x3d4001c0, 0x7 }, { 0x3d4001c4, 0x1 }, { 0x3d4000f4, 0xc99 }, - { 0x3d400108, 0x9121c1c }, + { 0x3d400108, 0x7101817 }, { 0x3d400200, 0x1f },
+ { 0x3d400208, 0x0 },
Are you sure this line is correct? Recheck, please.
this line is fine. The 0x0 reflects the reset value of the register. What it makes it confusing is that RAM timings generated by old NXP DDR spreadsheet versions do not explicit initialize this value. So it is then missing in the array. But newer version of the sheet set it.
Teresa
Yannic
{ 0x3d40020c, 0x0 }, { 0x3d400210, 0x1f1f }, { 0x3d400204, 0x80808 }, { 0x3d400214, 0x7070707 }, { 0x3d400218, 0x7070707 }, - { 0x3d40021c, 0xf07 }, - { 0x3d400250, 0x1f05 }, - { 0x3d400254, 0x1f }, - { 0x3d400264, 0x90003ff }, - { 0x3d40026c, 0x20003ff }, + { 0x3d40021c, 0xf0f }, + { 0x3d400250, 0x1705 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, { 0x3d400400, 0x111 }, + { 0x3d400404, 0x72ff }, { 0x3d400408, 0x72ff }, - { 0x3d400494, 0x1000e00 }, - { 0x3d400498, 0x3ff0000 }, - { 0x3d40049c, 0x1000e00 }, - { 0x3d4004a0, 0x3ff0000 }, - { 0x3d402020, 0x21 }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x1021 }, { 0x3d402024, 0x30d400 }, - { 0x3d402050, 0x20d040 }, + { 0x3d402050, 0x20d000 }, { 0x3d402064, 0xc001c }, { 0x3d4020dc, 0x840000 }, - { 0x3d4020e0, 0x330000 }, + { 0x3d4020e0, 0xf30000 }, { 0x3d4020e8, 0x660048 }, { 0x3d4020ec, 0x160048 }, { 0x3d402100, 0xa040305 }, @@ -89,12 +94,12 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d402194, 0x80303 }, { 0x3d4021b4, 0x100 }, { 0x3d4020f4, 0xc99 }, - { 0x3d403020, 0x21 }, + { 0x3d403020, 0x1021 }, { 0x3d403024, 0xc3500 }, - { 0x3d403050, 0x20d040 }, + { 0x3d403050, 0x20d000 }, { 0x3d403064, 0x30007 }, { 0x3d4030dc, 0x840000 }, - { 0x3d4030e0, 0x330000 }, + { 0x3d4030e0, 0xf30000 }, { 0x3d4030e8, 0x660048 }, { 0x3d4030ec, 0x160048 }, { 0x3d403100, 0xa010102 }, @@ -137,12 +142,12 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x110a7, 0x6 }, { 0x120a0, 0x0 }, { 0x120a1, 0x1 }, - { 0x120a2, 0x3 }, - { 0x120a3, 0x2 }, - { 0x120a4, 0x5 }, - { 0x120a5, 0x4 }, - { 0x120a6, 0x7 }, - { 0x120a7, 0x6 }, + { 0x120a2, 0x2 }, + { 0x120a3, 0x3 }, + { 0x120a4, 0x4 }, + { 0x120a5, 0x5 }, + { 0x120a6, 0x6 }, + { 0x120a7, 0x7 }, { 0x130a0, 0x0 }, { 0x130a1, 0x1 }, { 0x130a2, 0x2 }, @@ -185,7 +190,7 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x7055, 0x1ff }, { 0x8055, 0x1ff }, { 0x9055, 0x1ff }, - { 0x200c5, 0x18 }, + { 0x200c5, 0x19 }, { 0x1200c5, 0x7 }, { 0x2200c5, 0x7 }, { 0x2002e, 0x2 }, @@ -194,11 +199,11 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x90204, 0x0 }, { 0x190204, 0x0 }, { 0x290204, 0x0 }, - { 0x20024, 0x1e3 }, + { 0x20024, 0x1a3 }, { 0x2003a, 0x2 }, - { 0x120024, 0x1e3 }, + { 0x120024, 0x1a3 }, { 0x2003a, 0x2 }, - { 0x220024, 0x1e3 }, + { 0x220024, 0x1a3 }, { 0x2003a, 0x2 }, { 0x20056, 0x3 }, { 0x120056, 0x3 }, @@ -264,7 +269,7 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x20018, 0x3 }, { 0x20075, 0x4 }, { 0x20050, 0x0 }, - { 0x20008, 0x3e8 }, + { 0x20008, 0x2ee }, { 0x120008, 0x64 }, { 0x220008, 0x19 }, { 0x20088, 0x9 }, @@ -310,19 +315,15 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x200f6, 0x0 }, { 0x200f7, 0xf000 }, { 0x20025, 0x0 }, - { 0x2002d, 0x0 }, - { 0x12002d, 0x0 }, - { 0x22002d, 0x0 }, + { 0x2002d, 0x1 }, + { 0x12002d, 0x1 }, + { 0x22002d, 0x1 }, { 0x2007d, 0x212 }, { 0x12007d, 0x212 }, { 0x22007d, 0x212 }, { 0x2007c, 0x61 }, { 0x12007c, 0x61 }, { 0x22007c, 0x61 }, - { 0x1004a, 0x500 }, - { 0x1104a, 0x500 }, - { 0x1204a, 0x500 }, - { 0x1304a, 0x500 }, { 0x2002c, 0x0 }, }; @@ -1052,7 +1053,7 @@ static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { /* P0 message block paremeter for training firmware */ static struct dram_cfg_param ddr_fsp0_cfg[] = { { 0xd0000, 0x0 }, - { 0x54003, 0xfa0 }, + { 0x54003, 0xbb8 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, { 0x54006, 0x14 }, @@ -1061,26 +1062,26 @@ static struct dram_cfg_param ddr_fsp0_cfg[] = { { 0x5400b, 0x2 }, { 0x5400f, 0x100 }, { 0x54012, 0x110 }, - { 0x54019, 0x3ff4 }, - { 0x5401a, 0x33 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0xf1 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, - { 0x5401f, 0x3ff4 }, - { 0x54020, 0x33 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0xf1 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, - { 0x54032, 0xf400 }, - { 0x54033, 0x333f }, + { 0x54032, 0xd400 }, + { 0x54033, 0xf12d }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, - { 0x54038, 0xf400 }, - { 0x54039, 0x333f }, + { 0x54038, 0xd400 }, + { 0x54039, 0xf12d }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1102,25 +1103,25 @@ static struct dram_cfg_param ddr_fsp1_cfg[] = { { 0x5400f, 0x100 }, { 0x54012, 0x110 }, { 0x54019, 0x84 }, - { 0x5401a, 0x33 }, + { 0x5401a, 0xf3 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, { 0x5401f, 0x84 }, - { 0x54020, 0x33 }, + { 0x54020, 0xf3 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, { 0x54032, 0x8400 }, - { 0x54033, 0x3300 }, + { 0x54033, 0xf300 }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, { 0x54038, 0x8400 }, - { 0x54039, 0x3300 }, + { 0x54039, 0xf300 }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1142,25 +1143,25 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = { { 0x5400f, 0x100 }, { 0x54012, 0x110 }, { 0x54019, 0x84 }, - { 0x5401a, 0x33 }, + { 0x5401a, 0xf3 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, { 0x5401f, 0x84 }, - { 0x54020, 0x33 }, + { 0x54020, 0xf3 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, { 0x54032, 0x8400 }, - { 0x54033, 0x3300 }, + { 0x54033, 0xf300 }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, { 0x54038, 0x8400 }, - { 0x54039, 0x3300 }, + { 0x54039, 0xf300 }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1171,37 +1172,36 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = { /* P0 2D message block paremeter for training firmware */ static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { { 0xd0000, 0x0 }, - { 0x54003, 0xfa0 }, + { 0x54003, 0xbb8 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, { 0x54006, 0x14 }, { 0x54008, 0x61 }, { 0x54009, 0xc8 }, { 0x5400b, 0x2 }, - { 0x5400d, 0x100 }, { 0x5400f, 0x100 }, { 0x54010, 0x1f7f }, { 0x54012, 0x110 }, - { 0x54019, 0x3ff4 }, - { 0x5401a, 0x33 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0xf1 }, { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, { 0x5401e, 0x16 }, - { 0x5401f, 0x3ff4 }, - { 0x54020, 0x33 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0xf1 }, { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x1 }, - { 0x54032, 0xf400 }, - { 0x54033, 0x333f }, + { 0x54032, 0xd400 }, + { 0x54033, 0xf12d }, { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, { 0x54037, 0x1600 }, - { 0x54038, 0xf400 }, - { 0x54039, 0x333f }, + { 0x54038, 0xd400 }, + { 0x54039, 0xf12d }, { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1629,67 +1629,58 @@ static struct dram_cfg_param ddr_phy_pie[] = { { 0x90155, 0x20 }, { 0x90156, 0x2aa }, { 0x90157, 0x9 }, - { 0x90158, 0x0 }, - { 0x90159, 0x400 }, - { 0x9015a, 0x10e }, - { 0x9015b, 0x8 }, - { 0x9015c, 0xe8 }, - { 0x9015d, 0x109 }, - { 0x9015e, 0x0 }, - { 0x9015f, 0x8140 }, - { 0x90160, 0x10c }, - { 0x90161, 0x10 }, - { 0x90162, 0x8138 }, - { 0x90163, 0x10c }, - { 0x90164, 0x8 }, - { 0x90165, 0x7c8 }, - { 0x90166, 0x101 }, - { 0x90167, 0x8 }, - { 0x90168, 0x448 }, + { 0x90158, 0x8 }, + { 0x90159, 0xe8 }, + { 0x9015a, 0x109 }, + { 0x9015b, 0x0 }, + { 0x9015c, 0x8140 }, + { 0x9015d, 0x10c }, + { 0x9015e, 0x10 }, + { 0x9015f, 0x8138 }, + { 0x90160, 0x104 }, + { 0x90161, 0x8 }, + { 0x90162, 0x448 }, + { 0x90163, 0x109 }, + { 0x90164, 0xf }, + { 0x90165, 0x7c0 }, + { 0x90166, 0x109 }, + { 0x90167, 0x0 }, + { 0x90168, 0xe8 }, { 0x90169, 0x109 }, - { 0x9016a, 0xf }, - { 0x9016b, 0x7c0 }, + { 0x9016a, 0x47 }, + { 0x9016b, 0x630 }, { 0x9016c, 0x109 }, - { 0x9016d, 0x0 }, - { 0x9016e, 0xe8 }, + { 0x9016d, 0x8 }, + { 0x9016e, 0x618 }, { 0x9016f, 0x109 }, - { 0x90170, 0x47 }, - { 0x90171, 0x630 }, + { 0x90170, 0x8 }, + { 0x90171, 0xe0 }, { 0x90172, 0x109 }, - { 0x90173, 0x8 }, - { 0x90174, 0x618 }, + { 0x90173, 0x0 }, + { 0x90174, 0x7c8 }, { 0x90175, 0x109 }, { 0x90176, 0x8 }, - { 0x90177, 0xe0 }, - { 0x90178, 0x109 }, + { 0x90177, 0x8140 }, + { 0x90178, 0x10c }, { 0x90179, 0x0 }, - { 0x9017a, 0x7c8 }, + { 0x9017a, 0x478 }, { 0x9017b, 0x109 }, - { 0x9017c, 0x8 }, - { 0x9017d, 0x8140 }, - { 0x9017e, 0x10c }, - { 0x9017f, 0x0 }, - { 0x90180, 0x478 }, - { 0x90181, 0x109 }, - { 0x90182, 0x0 }, - { 0x90183, 0x1 }, - { 0x90184, 0x8 }, - { 0x90185, 0x8 }, - { 0x90186, 0x4 }, - { 0x90187, 0x8 }, - { 0x90188, 0x8 }, - { 0x90189, 0x7c8 }, - { 0x9018a, 0x101 }, - { 0x90006, 0x0 }, - { 0x90007, 0x0 }, - { 0x90008, 0x8 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x1 }, + { 0x9017e, 0x8 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x4 }, + { 0x90181, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, { 0x90009, 0x0 }, - { 0x9000a, 0x0 }, - { 0x9000b, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, { 0xd00e7, 0x400 }, { 0x90017, 0x0 }, { 0x9001f, 0x29 }, - { 0x90026, 0x6a }, + { 0x90026, 0x68 }, { 0x400d0, 0x0 }, { 0x400d1, 0x101 }, { 0x400d2, 0x105 }, @@ -1699,15 +1690,16 @@ static struct dram_cfg_param ddr_phy_pie[] = { { 0x400d6, 0x20a }, { 0x400d7, 0x20b }, { 0x2003a, 0x2 }, - { 0x2000b, 0x7d }, - { 0x2000c, 0xfa }, - { 0x2000d, 0x9c4 }, + { 0x200be, 0x3 }, + { 0x2000b, 0x34b }, + { 0x2000c, 0xbb }, + { 0x2000d, 0x753 }, { 0x2000e, 0x2c }, - { 0x12000b, 0xc }, + { 0x12000b, 0x70 }, { 0x12000c, 0x19 }, { 0x12000d, 0xfa }, { 0x12000e, 0x10 }, - { 0x22000b, 0x3 }, + { 0x22000b, 0x1c }, { 0x22000c, 0x6 }, { 0x22000d, 0x3e }, { 0x22000e, 0x10 }, @@ -1804,8 +1796,8 @@ static struct dram_cfg_param ddr_phy_pie[] = { static struct dram_fsp_msg ddr_dram_fsp_msg[] = { { - /* P0 4000mts 1D */ - .drate = 4000, + /* P0 3000mts 1D */ + .drate = 3000, .fw_type = FW_1D_IMAGE, .fsp_cfg = ddr_fsp0_cfg, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), @@ -1825,8 +1817,8 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = { .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), }, { - /* P0 4000mts 2D */ - .drate = 4000, + /* P0 3000mts 2D */ + .drate = 3000, .fw_type = FW_2D_IMAGE, .fsp_cfg = ddr_fsp0_2d_cfg, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), @@ -1845,5 +1837,5 @@ struct dram_timing_info dram_timing = { .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), .ddrphy_pie = ddr_phy_pie, .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 4000, 400, 100, }, + .fsp_table = { 3000, 400, 100, }, };
Add helper function to read out the PCB revision of a PHYTEC SoM.
Signed-off-by: Teresa Remmet t.remmet@phytec.de --- board/phytec/common/phytec_som_detection.c | 15 +++++++++++++++ board/phytec/common/phytec_som_detection.h | 5 +++++ 2 files changed, 20 insertions(+)
diff --git a/board/phytec/common/phytec_som_detection.c b/board/phytec/common/phytec_som_detection.c index 366bdd4ace4b..55562731270b 100644 --- a/board/phytec/common/phytec_som_detection.c +++ b/board/phytec/common/phytec_som_detection.c @@ -186,3 +186,18 @@ char * __maybe_unused phytec_get_opt(struct phytec_eeprom_data *data)
return opt; } + +u8 __maybe_unused phytec_get_rev(struct phytec_eeprom_data *data) +{ + struct phytec_api2_data *api2; + + if (!data) + data = &eeprom_data; + + if (data->api_rev < PHYTEC_API_REV2) + return PHYTEC_EEPROM_INVAL; + + api2 = &data->data.data_api2; + + return api2->pcb_rev; +} diff --git a/board/phytec/common/phytec_som_detection.h b/board/phytec/common/phytec_som_detection.h index 01f7e4652ddb..c68e2302cc42 100644 --- a/board/phytec/common/phytec_som_detection.h +++ b/board/phytec/common/phytec_som_detection.h @@ -68,6 +68,7 @@ int phytec_eeprom_data_init(struct phytec_eeprom_data *data, void __maybe_unused phytec_print_som_info(struct phytec_eeprom_data *data);
char * __maybe_unused phytec_get_opt(struct phytec_eeprom_data *data); +u8 __maybe_unused phytec_get_rev(struct phytec_eeprom_data *data);
#else
@@ -99,6 +100,10 @@ inline char *__maybe_unused phytec_get_opt(struct phytec_eeprom_data *data) return NULL; }
+u8 __maybe_unused phytec_get_rev(struct phytec_eeprom_data *data) +{ + return PHYTEC_EEPROM_INVAL; +} #endif /* IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION) */
#endif /* _PHYTEC_SOM_DETECTION_H */
Starting with PCB revision 3 we can safely make use of higher RAM frequency again. Make use of the EEPROM detection to determine the revision and use the updated RAM timings for new SoMs.
Signed-off-by: Teresa Remmet t.remmet@phytec.de --- board/phytec/phycore_imx8mp/spl.c | 61 +++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+)
diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index e084fe081987..2929c3c50001 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -48,6 +48,67 @@ void spl_dram_init(void)
phytec_print_som_info(NULL);
+ ret = phytec_get_rev(NULL); + if (ret >= 3 && ret != PHYTEC_EEPROM_INVAL) { + dram_timing.ddrc_cfg[3].val = 0x1233; + dram_timing.ddrc_cfg[4].val = 0x1e84800; + dram_timing.ddrc_cfg[5].val = 0x7a0118; + dram_timing.ddrc_cfg[8].val = 0xc00307a3; + dram_timing.ddrc_cfg[9].val = 0xc50000; + dram_timing.ddrc_cfg[10].val = 0xf4003f; + dram_timing.ddrc_cfg[11].val = 0xf30000; + dram_timing.ddrc_cfg[14].val = 0x2028222a; + dram_timing.ddrc_cfg[15].val = 0x8083f; + dram_timing.ddrc_cfg[16].val = 0xe0e000; + dram_timing.ddrc_cfg[17].val = 0x12040a12; + dram_timing.ddrc_cfg[18].val = 0x2050f0f; + dram_timing.ddrc_cfg[19].val = 0x1010009; + dram_timing.ddrc_cfg[20].val = 0x502; + dram_timing.ddrc_cfg[21].val = 0x20800; + dram_timing.ddrc_cfg[22].val = 0xe100002; + dram_timing.ddrc_cfg[23].val = 0x120; + dram_timing.ddrc_cfg[24].val = 0xc80064; + dram_timing.ddrc_cfg[25].val = 0x3e8001e; + dram_timing.ddrc_cfg[26].val = 0x3207a12; + dram_timing.ddrc_cfg[28].val = 0x4a3820e; + dram_timing.ddrc_cfg[30].val = 0x230e; + dram_timing.ddrc_cfg[37].val = 0x799; + dram_timing.ddrc_cfg[38].val = 0x9141d1c; + dram_timing.ddrc_cfg[74].val = 0x302; + dram_timing.ddrc_cfg[83].val = 0x599; + dram_timing.ddrc_cfg[99].val = 0x302; + dram_timing.ddrc_cfg[108].val = 0x599; + dram_timing.ddrphy_cfg[66].val = 0x18; + dram_timing.ddrphy_cfg[75].val = 0x1e3; + dram_timing.ddrphy_cfg[77].val = 0x1e3; + dram_timing.ddrphy_cfg[79].val = 0x1e3; + dram_timing.ddrphy_cfg[145].val = 0x3e8; + dram_timing.fsp_msg[0].drate = 4000; + dram_timing.fsp_msg[0].fsp_cfg[1].val = 0xfa0; + dram_timing.fsp_msg[0].fsp_cfg[10].val = 0x3ff4; + dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xf3; + dram_timing.fsp_msg[0].fsp_cfg[15].val = 0x3ff4; + dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xf3; + dram_timing.fsp_msg[0].fsp_cfg[22].val = 0xf400; + dram_timing.fsp_msg[0].fsp_cfg[23].val = 0xf33f; + dram_timing.fsp_msg[0].fsp_cfg[28].val = 0xf400; + dram_timing.fsp_msg[0].fsp_cfg[29].val = 0xf33f; + dram_timing.fsp_msg[3].drate = 4000; + dram_timing.fsp_msg[3].fsp_cfg[1].val = 0xbb8; + dram_timing.fsp_msg[3].fsp_cfg[11].val = 0x3ff4; + dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xf3; + dram_timing.fsp_msg[3].fsp_cfg[16].val = 0x3ff4; + dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xf3; + dram_timing.fsp_msg[3].fsp_cfg[23].val = 0xf400; + dram_timing.fsp_msg[3].fsp_cfg[24].val = 0xf33f; + dram_timing.fsp_msg[3].fsp_cfg[29].val = 0xf400; + dram_timing.fsp_msg[3].fsp_cfg[30].val = 0xf33f; + dram_timing.ddrphy_pie[480].val = 0x465; + dram_timing.ddrphy_pie[481].val = 0xfa; + dram_timing.ddrphy_pie[482].val = 0x9c4; + dram_timing.fsp_table[0] = 4000; + } + out: ddr_init(&dram_timing); }
Hello Teresa,
On Tue, 2023-07-18 at 15:35 +0200, Teresa Remmet wrote:
Starting with PCB revision 3 we can safely make use of higher RAM frequency again. Make use of the EEPROM detection to determine the revision and use the updated RAM timings for new SoMs.
Signed-off-by: Teresa Remmet t.remmet@phytec.de
board/phytec/phycore_imx8mp/spl.c | 61 +++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+)
diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index e084fe081987..2929c3c50001 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -48,6 +48,67 @@ void spl_dram_init(void) phytec_print_som_info(NULL); + ret = phytec_get_rev(NULL); + if (ret >= 3 && ret != PHYTEC_EEPROM_INVAL) {
+ dram_timing.ddrc_cfg[3].val = 0x1233;
I believe you swapped to digits here, it should be 0x1323.
+ dram_timing.ddrc_cfg[4].val = 0x1e84800; + dram_timing.ddrc_cfg[5].val = 0x7a0118; + dram_timing.ddrc_cfg[8].val = 0xc00307a3; + dram_timing.ddrc_cfg[9].val = 0xc50000; + dram_timing.ddrc_cfg[10].val = 0xf4003f; + dram_timing.ddrc_cfg[11].val = 0xf30000; + dram_timing.ddrc_cfg[14].val = 0x2028222a; + dram_timing.ddrc_cfg[15].val = 0x8083f; + dram_timing.ddrc_cfg[16].val = 0xe0e000; + dram_timing.ddrc_cfg[17].val = 0x12040a12; + dram_timing.ddrc_cfg[18].val = 0x2050f0f; + dram_timing.ddrc_cfg[19].val = 0x1010009; + dram_timing.ddrc_cfg[20].val = 0x502; + dram_timing.ddrc_cfg[21].val = 0x20800; + dram_timing.ddrc_cfg[22].val = 0xe100002; + dram_timing.ddrc_cfg[23].val = 0x120; + dram_timing.ddrc_cfg[24].val = 0xc80064; + dram_timing.ddrc_cfg[25].val = 0x3e8001e; + dram_timing.ddrc_cfg[26].val = 0x3207a12; + dram_timing.ddrc_cfg[28].val = 0x4a3820e; + dram_timing.ddrc_cfg[30].val = 0x230e; + dram_timing.ddrc_cfg[37].val = 0x799; + dram_timing.ddrc_cfg[38].val = 0x9141d1c; + dram_timing.ddrc_cfg[74].val = 0x302; + dram_timing.ddrc_cfg[83].val = 0x599; + dram_timing.ddrc_cfg[99].val = 0x302; + dram_timing.ddrc_cfg[108].val = 0x599; + dram_timing.ddrphy_cfg[66].val = 0x18; + dram_timing.ddrphy_cfg[75].val = 0x1e3; + dram_timing.ddrphy_cfg[77].val = 0x1e3; + dram_timing.ddrphy_cfg[79].val = 0x1e3; + dram_timing.ddrphy_cfg[145].val = 0x3e8; + dram_timing.fsp_msg[0].drate = 4000; + dram_timing.fsp_msg[0].fsp_cfg[1].val = 0xfa0; + dram_timing.fsp_msg[0].fsp_cfg[10].val = 0x3ff4; + dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xf3; + dram_timing.fsp_msg[0].fsp_cfg[15].val = 0x3ff4; + dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xf3; + dram_timing.fsp_msg[0].fsp_cfg[22].val = 0xf400; + dram_timing.fsp_msg[0].fsp_cfg[23].val = 0xf33f; + dram_timing.fsp_msg[0].fsp_cfg[28].val = 0xf400; + dram_timing.fsp_msg[0].fsp_cfg[29].val = 0xf33f; + dram_timing.fsp_msg[3].drate = 4000;
+ dram_timing.fsp_msg[3].fsp_cfg[1].val = 0xbb8;
And for this entry, I get 0xfa0.
Yannic
+ dram_timing.fsp_msg[3].fsp_cfg[11].val = 0x3ff4; + dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xf3; + dram_timing.fsp_msg[3].fsp_cfg[16].val = 0x3ff4; + dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xf3; + dram_timing.fsp_msg[3].fsp_cfg[23].val = 0xf400; + dram_timing.fsp_msg[3].fsp_cfg[24].val = 0xf33f; + dram_timing.fsp_msg[3].fsp_cfg[29].val = 0xf400; + dram_timing.fsp_msg[3].fsp_cfg[30].val = 0xf33f; + dram_timing.ddrphy_pie[480].val = 0x465; + dram_timing.ddrphy_pie[481].val = 0xfa; + dram_timing.ddrphy_pie[482].val = 0x9c4; + dram_timing.fsp_table[0] = 4000; + }
out: ddr_init(&dram_timing); }
Hello Yannic,
Am Donnerstag, dem 03.08.2023 um 11:09 +0200 schrieb Yannic Moog:
Hello Teresa,
On Tue, 2023-07-18 at 15:35 +0200, Teresa Remmet wrote:
Starting with PCB revision 3 we can safely make use of higher RAM frequency again. Make use of the EEPROM detection to determine the revision and use the updated RAM timings for new SoMs.
Signed-off-by: Teresa Remmet t.remmet@phytec.de
board/phytec/phycore_imx8mp/spl.c | 61 +++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+)
diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index e084fe081987..2929c3c50001 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -48,6 +48,67 @@ void spl_dram_init(void) phytec_print_som_info(NULL); + ret = phytec_get_rev(NULL); + if (ret >= 3 && ret != PHYTEC_EEPROM_INVAL) {
+ dram_timing.ddrc_cfg[3].val = 0x1233;
I believe you swapped to digits here, it should be 0x1323.
argh.. yes. Thanks for the review. I will fix this one and the one below in v2.
Teresa
+ dram_timing.ddrc_cfg[4].val = 0x1e84800; + dram_timing.ddrc_cfg[5].val = 0x7a0118; + dram_timing.ddrc_cfg[8].val = 0xc00307a3; + dram_timing.ddrc_cfg[9].val = 0xc50000; + dram_timing.ddrc_cfg[10].val = 0xf4003f; + dram_timing.ddrc_cfg[11].val = 0xf30000; + dram_timing.ddrc_cfg[14].val = 0x2028222a; + dram_timing.ddrc_cfg[15].val = 0x8083f; + dram_timing.ddrc_cfg[16].val = 0xe0e000; + dram_timing.ddrc_cfg[17].val = 0x12040a12; + dram_timing.ddrc_cfg[18].val = 0x2050f0f; + dram_timing.ddrc_cfg[19].val = 0x1010009; + dram_timing.ddrc_cfg[20].val = 0x502; + dram_timing.ddrc_cfg[21].val = 0x20800; + dram_timing.ddrc_cfg[22].val = 0xe100002; + dram_timing.ddrc_cfg[23].val = 0x120; + dram_timing.ddrc_cfg[24].val = 0xc80064; + dram_timing.ddrc_cfg[25].val = 0x3e8001e; + dram_timing.ddrc_cfg[26].val = 0x3207a12; + dram_timing.ddrc_cfg[28].val = 0x4a3820e; + dram_timing.ddrc_cfg[30].val = 0x230e; + dram_timing.ddrc_cfg[37].val = 0x799; + dram_timing.ddrc_cfg[38].val = 0x9141d1c; + dram_timing.ddrc_cfg[74].val = 0x302; + dram_timing.ddrc_cfg[83].val = 0x599; + dram_timing.ddrc_cfg[99].val = 0x302; + dram_timing.ddrc_cfg[108].val = 0x599; + dram_timing.ddrphy_cfg[66].val = 0x18; + dram_timing.ddrphy_cfg[75].val = 0x1e3; + dram_timing.ddrphy_cfg[77].val = 0x1e3; + dram_timing.ddrphy_cfg[79].val = 0x1e3; + dram_timing.ddrphy_cfg[145].val = 0x3e8; + dram_timing.fsp_msg[0].drate = 4000; + dram_timing.fsp_msg[0].fsp_cfg[1].val = 0xfa0; + dram_timing.fsp_msg[0].fsp_cfg[10].val = 0x3ff4; + dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xf3; + dram_timing.fsp_msg[0].fsp_cfg[15].val = 0x3ff4; + dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xf3; + dram_timing.fsp_msg[0].fsp_cfg[22].val = 0xf400; + dram_timing.fsp_msg[0].fsp_cfg[23].val = 0xf33f; + dram_timing.fsp_msg[0].fsp_cfg[28].val = 0xf400; + dram_timing.fsp_msg[0].fsp_cfg[29].val = 0xf33f; + dram_timing.fsp_msg[3].drate = 4000;
+ dram_timing.fsp_msg[3].fsp_cfg[1].val = 0xbb8;
And for this entry, I get 0xfa0.
Yannic
+ dram_timing.fsp_msg[3].fsp_cfg[11].val = 0x3ff4; + dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xf3; + dram_timing.fsp_msg[3].fsp_cfg[16].val = 0x3ff4; + dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xf3; + dram_timing.fsp_msg[3].fsp_cfg[23].val = 0xf400; + dram_timing.fsp_msg[3].fsp_cfg[24].val = 0xf33f; + dram_timing.fsp_msg[3].fsp_cfg[29].val = 0xf400; + dram_timing.fsp_msg[3].fsp_cfg[30].val = 0xf33f; + dram_timing.ddrphy_pie[480].val = 0x465; + dram_timing.ddrphy_pie[481].val = 0xfa; + dram_timing.ddrphy_pie[482].val = 0x9c4; + dram_timing.fsp_table[0] = 4000; + }
out: ddr_init(&dram_timing); }
participants (3)
-
Teresa Remmet -
Teresa Remmet
-
Yannic Moog