[U-Boot] Socfpga: configure FPGA to SDRAM interface without reprogramming the FPGA
Hi all, Here is another question on the FPGA to SDRAM interface of the Cyclone V SoC. Is is possible to configure the the interface in U-Boot or SPL, without reprogramming the FPGA? Maybe through the usage of the generated header files from the Quartus synthesis? The SDRAM controller's registers only differ in eight entries in Linux when the FPGA is programmed or not.
+----------+-------------+------------+----------------+ | address | name | programmed | not programmed | +----------+-------------+------------+----------------+ | FFC25064 | | 00044003 | 00044FFF | | FFC25068 | | 2C000000 | 2C03FFFF | | FFC2506c | | 00B00000 | 00B3FFFF | | FFC25070 | | 00760000 | 0076FFFF | | FFC25074 | | 00980000 | 0098FFFF | | FFC25078 | | 0005A003 | 0005AFFF | | FFC2507c | portcfg | 00000000 | 0000003F | | FFC25080 | fpgaportrst | 000001FF | 00000000 | +----------+-------------+------------+----------------+
The registers 0xFFC25064-0xFFC25078 don't show up on the HPS' memory map [1], so are they even intended to be configured?
Thanks
[1] https://www.altera.com/hps/cyclone-v/hps.html#topic/sfo1411577380716.html#sf...
On 12/18/2017 09:44 PM, Jan Siegmund wrote:
Hi all,
Hi,
Here is another question on the FPGA to SDRAM interface of the Cyclone V SoC. Is is possible to configure the the interface in U-Boot or SPL,
What is "the interface" ?
If you mean DRAM, then yes, the CV/AV do _not_ configure the FPGA in SPL at all. They just configure the IOMUX/clock rings, but that's all.
without reprogramming the FPGA? Maybe through the usage of the generated header files from the Quartus synthesis? The SDRAM controller's registers only differ in eight entries in Linux when the FPGA is programmed or not.
+----------+-------------+------------+----------------+ | address | name | programmed | not programmed | +----------+-------------+------------+----------------+ | FFC25064 | | 00044003 | 00044FFF | | FFC25068 | | 2C000000 | 2C03FFFF | | FFC2506c | | 00B00000 | 00B3FFFF | | FFC25070 | | 00760000 | 0076FFFF | | FFC25074 | | 00980000 | 0098FFFF | | FFC25078 | | 0005A003 | 0005AFFF | | FFC2507c | portcfg | 00000000 | 0000003F | | FFC25080 | fpgaportrst | 000001FF | 00000000 | +----------+-------------+------------+----------------+
The registers 0xFFC25064-0xFFC25078 don't show up on the HPS' memory map [1], so are they even intended to be configured?
Thanks
[1] https://www.altera.com/hps/cyclone-v/hps.html#topic/sfo1411577380716.html#sf...
Am 18.12.2017 um 22:05 schrieb Marek Vasut:
On 12/18/2017 09:44 PM, Jan Siegmund wrote:
Hi Marek,
Hi all,
Hi,
Here is another question on the FPGA to SDRAM interface of the Cyclone V SoC. Is is possible to configure the the interface in U-Boot or SPL,
What is "the interface" ?
I am sorry I did not specify it further. I meant the FPGA-to-HPS SDRAM interface [2], sometimes called FPGA2SDRAM bridge.
If you mean DRAM, then yes, the CV/AV do _not_ configure the FPGA in SPL at all. They just configure the IOMUX/clock rings, but that's all.
I know the FPGA is not configured in SPL, but does the FPGA need to be configured in SPL or U-Boot, to use the FPGA-to-HPS SDRAM interface? Would it be possible to just preset the registers for later configuration? My preferred usecase would be configuring the registers in the table below in SPL and configuring the FPGA in Linux, with a design using the FPGA-to-HPS SDRAM interface.
For example, the last bits in the portcfg register define whether the FPGA-to-HPS SDRAM interface's protocol is AXI or Avalon MM. The problem is, that this register can't be written to in U-Boot, even though it is specified as rw [3]. Can this register just be set by programming the FPGA?
without reprogramming the FPGA? Maybe through the usage of the generated header files from the Quartus synthesis? The SDRAM controller's registers only differ in eight entries in Linux when the FPGA is programmed or not.
+----------+-------------+------------+----------------+ | address | name | programmed | not programmed | +----------+-------------+------------+----------------+ | FFC25064 | | 00044003 | 00044FFF | | FFC25068 | | 2C000000 | 2C03FFFF | | FFC2506c | | 00B00000 | 00B3FFFF | | FFC25070 | | 00760000 | 0076FFFF | | FFC25074 | | 00980000 | 0098FFFF | | FFC25078 | | 0005A003 | 0005AFFF | | FFC2507c | portcfg | 00000000 | 0000003F | | FFC25080 | fpgaportrst | 000001FF | 00000000 | +----------+-------------+------------+----------------+
The registers 0xFFC25064-0xFFC25078 don't show up on the HPS' memory map [1], so are they even intended to be configured?
Thanks
[1] https://www.altera.com/hps/cyclone-v/hps.html#topic/sfo1411577380716.html#sf...
Best regards, Jan
[2] https://www.altera.com/documentation/sfo1410143707420.html#sfo1411577336440_...
[3] https://www.altera.com/hps/cyclone-v/hps.html#topic/sfo1411577375739.html
On 12/20/2017 12:29 AM, Jan Siegmund wrote:
Am 18.12.2017 um 22:05 schrieb Marek Vasut:
On 12/18/2017 09:44 PM, Jan Siegmund wrote:
Hi Marek,
Hi,
Hi all,
Hi,
Here is another question on the FPGA to SDRAM interface of the Cyclone V SoC. Is is possible to configure the the interface in U-Boot or SPL,
What is "the interface" ?
I am sorry I did not specify it further. I meant the FPGA-to-HPS SDRAM interface [2], sometimes called FPGA2SDRAM bridge.
Oh OK. The F2S bridge is a bit special indeed.
If you mean DRAM, then yes, the CV/AV do _not_ configure the FPGA in SPL at all. They just configure the IOMUX/clock rings, but that's all.
I know the FPGA is not configured in SPL, but does the FPGA need to be configured in SPL or U-Boot, to use the FPGA-to-HPS SDRAM interface?
No
Would it be possible to just preset the registers for later configuration?
Yes
My preferred usecase would be configuring the registers in the table below in SPL and configuring the FPGA in Linux, with a design using the FPGA-to-HPS SDRAM interface.
For example, the last bits in the portcfg register define whether the FPGA-to-HPS SDRAM interface's protocol is AXI or Avalon MM. The problem is, that this register can't be written to in U-Boot, even though it is specified as rw [3]. Can this register just be set by programming the FPGA?
You might need to regenerate the SPL if you changed those kinds of settings. The SPL programs these based on the handoff files IIRC.
without reprogramming the FPGA? Maybe through the usage of the generated header files from the Quartus synthesis? The SDRAM controller's registers only differ in eight entries in Linux when the FPGA is programmed or not.
+----------+-------------+------------+----------------+ | address | name | programmed | not programmed | +----------+-------------+------------+----------------+ | FFC25064 | | 00044003 | 00044FFF | | FFC25068 | | 2C000000 | 2C03FFFF | | FFC2506c | | 00B00000 | 00B3FFFF | | FFC25070 | | 00760000 | 0076FFFF | | FFC25074 | | 00980000 | 0098FFFF | | FFC25078 | | 0005A003 | 0005AFFF | | FFC2507c | portcfg | 00000000 | 0000003F | | FFC25080 | fpgaportrst | 000001FF | 00000000 | +----------+-------------+------------+----------------+
The registers 0xFFC25064-0xFFC25078 don't show up on the HPS' memory map [1], so are they even intended to be configured?
Thanks
[1] https://www.altera.com/hps/cyclone-v/hps.html#topic/sfo1411577380716.html#sf...
Best regards, Jan
[2] https://www.altera.com/documentation/sfo1410143707420.html#sfo1411577336440_...
[3] https://www.altera.com/hps/cyclone-v/hps.html#topic/sfo1411577375739.html
Am 20.12.2017 um 10:35 schrieb Marek Vasut:
On 12/20/2017 12:29 AM, Jan Siegmund wrote:
Am 18.12.2017 um 22:05 schrieb Marek Vasut:
On 12/18/2017 09:44 PM, Jan Siegmund wrote:
Hi Marek,
Hi,
Hi Marek,
Hi all,
Hi,
Here is another question on the FPGA to SDRAM interface of the Cyclone V SoC. Is is possible to configure the the interface in U-Boot or SPL,
What is "the interface" ?
I am sorry I did not specify it further. I meant the FPGA-to-HPS SDRAM interface [2], sometimes called FPGA2SDRAM bridge.
Oh OK. The F2S bridge is a bit special indeed.
If you mean DRAM, then yes, the CV/AV do _not_ configure the FPGA in SPL at all. They just configure the IOMUX/clock rings, but that's all.
I know the FPGA is not configured in SPL, but does the FPGA need to be configured in SPL or U-Boot, to use the FPGA-to-HPS SDRAM interface?
No
Would it be possible to just preset the registers for later configuration?
Yes
My preferred usecase would be configuring the registers in the table below in SPL and configuring the FPGA in Linux, with a design using the FPGA-to-HPS SDRAM interface.
For example, the last bits in the portcfg register define whether the FPGA-to-HPS SDRAM interface's protocol is AXI or Avalon MM. The problem is, that this register can't be written to in U-Boot, even though it is specified as rw [3]. Can this register just be set by programming the FPGA?
You might need to regenerate the SPL if you changed those kinds of settings. The SPL programs these based on the handoff files IIRC.
I generated the headers using the bsp-editor from Quartus 17 and converted them using the qts-filter.sh script in U-Boot. Since then, I did not change any settings.
sdram.h in board/.../qts and mach-socfpga/
#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10
wrap_sdram_config.c .port_cfg = (CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN << SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB),
sdram.c debug("Configuring PORTCFG\n"); writel(cfg->port_cfg, &sdr_ctrl->port_cfg);
When I add some debug printing around the code shown above, SPL console shows this:
U-Boot SPL 2018.01-rc1-00129-ga8548b9-dirty (Dec 18 2017 - 14:13:21) Content of ffc2507c is 3f Wrote 0 to ffc2507c Content of ffc2507c is 3f drivers/ddr/altera/sequencer.c: Preparing to start memory calibration drivers/ddr/altera/sequencer.c: CALIBRATION PASSED drivers/ddr/altera/sequencer.c: Calibration complete Trying to boot from MMC1
Maybe the portprotocol part of portcfg is just a status register. But then again, why would it be specified as rw?
Do you have any idea what I might be missing, to get the f2s running without programming the FPGA?
without reprogramming the FPGA? Maybe through the usage of the generated header files from the Quartus synthesis? The SDRAM controller's registers only differ in eight entries in Linux when the FPGA is programmed or not.
+----------+-------------+------------+----------------+ | address | name | programmed | not programmed | +----------+-------------+------------+----------------+ | FFC25064 | | 00044003 | 00044FFF | | FFC25068 | | 2C000000 | 2C03FFFF | | FFC2506c | | 00B00000 | 00B3FFFF | | FFC25070 | | 00760000 | 0076FFFF | | FFC25074 | | 00980000 | 0098FFFF | | FFC25078 | | 0005A003 | 0005AFFF | | FFC2507c | portcfg | 00000000 | 0000003F | | FFC25080 | fpgaportrst | 000001FF | 00000000 | +----------+-------------+------------+----------------+
The registers 0xFFC25064-0xFFC25078 don't show up on the HPS' memory map [1], so are they even intended to be configured?
Thanks
[1] https://www.altera.com/hps/cyclone-v/hps.html#topic/sfo1411577380716.html#sf...
Best regards, Jan
[2] https://www.altera.com/documentation/sfo1410143707420.html#sfo1411577336440_...
[3] https://www.altera.com/hps/cyclone-v/hps.html#topic/sfo1411577375739.html
Best regards, Jan
On 12/20/2017 12:51 PM, Jan Siegmund wrote: [...]
My preferred usecase would be configuring the registers in the table below in SPL and configuring the FPGA in Linux, with a design using the FPGA-to-HPS SDRAM interface.
For example, the last bits in the portcfg register define whether the FPGA-to-HPS SDRAM interface's protocol is AXI or Avalon MM. The problem is, that this register can't be written to in U-Boot, even though it is specified as rw [3]. Can this register just be set by programming the FPGA?
You might need to regenerate the SPL if you changed those kinds of settings. The SPL programs these based on the handoff files IIRC.
I generated the headers using the bsp-editor from Quartus 17 and converted them using the qts-filter.sh script in U-Boot. Since then, I did not change any settings.
sdram.h in board/.../qts and mach-socfpga/
#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10
wrap_sdram_config.c .port_cfg = (CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN << SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB),
sdram.c debug("Configuring PORTCFG\n"); writel(cfg->port_cfg, &sdr_ctrl->port_cfg);
When I add some debug printing around the code shown above, SPL console shows this:
U-Boot SPL 2018.01-rc1-00129-ga8548b9-dirty (Dec 18 2017 - 14:13:21) Content of ffc2507c is 3f Wrote 0 to ffc2507c Content of ffc2507c is 3f drivers/ddr/altera/sequencer.c: Preparing to start memory calibration drivers/ddr/altera/sequencer.c: CALIBRATION PASSED drivers/ddr/altera/sequencer.c: Calibration complete Trying to boot from MMC1
Maybe the portprotocol part of portcfg is just a status register. But then again, why would it be specified as rw?
It should be RW actually.
Do you have any idea what I might be missing, to get the f2s running without programming the FPGA?
CCing Dinh and Chin.
participants (2)
-
Jan Siegmund -
Marek Vasut