[U-Boot] [PATCH 1/3] arm: ls102x: add get_svr and IS_SVR_REV helper
Signed-off-by: Shengzhou Liu Shengzhou.Liu@freescale.com --- arch/arm/cpu/armv7/ls102xa/cpu.c | 8 ++++++++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 5 +++++ 2 files changed, 13 insertions(+)
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index 14ae2a3..74cd2cb 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -209,6 +209,14 @@ void enable_caches(void) } #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+ +uint get_svr(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + + return in_be32(&gur->svr); +} + #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo(void) { diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index c59c93a..2d0832a 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -11,6 +11,8 @@ #define SVR_MIN(svr) (((svr) >> 0) & 0xf) #define SVR_SOC_VER(svr) (((svr) >> 8) & 0x7ff) #define IS_E_PROCESSOR(svr) (svr & 0x80000) +#define IS_SVR_REV(svr, maj, min) \ + ((SVR_MAJ(svr) == maj) && (SVR_MIN(svr) == min))
#define SOC_VER_SLS1020 0x00 #define SOC_VER_LS1020 0x10 @@ -427,4 +429,7 @@ struct ccsr_ahci { u32 pberr; /* port 0/1 BIST error */ u32 cmds; /* port 0/1 CMD status error */ }; + +uint get_svr(void); + #endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */
move arch/powerpc/include/asm/fsl_errata.h to include/fsl_errata.h to make it public for both ARM and POWER SoCs.
Signed-off-by: Shengzhou Liu Shengzhou.Liu@freescale.com --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 2 +- arch/powerpc/cpu/mpc85xx/cpu_init.c | 2 +- arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c | 2 +- arch/powerpc/include/asm/fsl_errata.h | 53 ---------------------- include/fsl_errata.h | 61 ++++++++++++++++++++++++++ 5 files changed, 64 insertions(+), 56 deletions(-) delete mode 100644 arch/powerpc/include/asm/fsl_errata.h create mode 100644 include/fsl_errata.h
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index b368562..a493556 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -7,7 +7,7 @@ #include <common.h> #include <command.h> #include <linux/compiler.h> -#include <asm/fsl_errata.h> +#include <fsl_errata.h> #include <asm/processor.h> #include <fsl_usb.h> #include "fsl_corenet_serdes.h" diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index eb0534b..51b5f5e 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -19,7 +19,7 @@ #include <asm/io.h> #include <asm/cache.h> #include <asm/mmu.h> -#include <asm/fsl_errata.h> +#include <fsl_errata.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> #include <asm/fsl_srio.h> diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c index acb1353..f89c94e 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c @@ -11,7 +11,7 @@ #include <asm/processor.h> #include <asm/fsl_law.h> #include <asm/errno.h> -#include <asm/fsl_errata.h> +#include <fsl_errata.h> #include "fsl_corenet2_serdes.h"
#ifdef CONFIG_SYS_FSL_SRDS_1 diff --git a/arch/powerpc/include/asm/fsl_errata.h b/arch/powerpc/include/asm/fsl_errata.h deleted file mode 100644 index 4861e3bf..0000000 --- a/arch/powerpc/include/asm/fsl_errata.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ASM_FSL_ERRATA_H -#define _ASM_FSL_ERRATA_H - -#include <common.h> -#include <asm/processor.h> - -#ifdef CONFIG_SYS_FSL_ERRATUM_A006379 -static inline bool has_erratum_a006379(void) -{ - u32 svr = get_svr(); - if (((SVR_SOC_VER(svr) == SVR_T4240) && SVR_MAJ(svr) <= 1) || - ((SVR_SOC_VER(svr) == SVR_T4160) && SVR_MAJ(svr) <= 1) || - ((SVR_SOC_VER(svr) == SVR_T4080) && SVR_MAJ(svr) <= 1) || - ((SVR_SOC_VER(svr) == SVR_B4860) && SVR_MAJ(svr) <= 2) || - ((SVR_SOC_VER(svr) == SVR_B4420) && SVR_MAJ(svr) <= 2) || - ((SVR_SOC_VER(svr) == SVR_T2080) && SVR_MAJ(svr) <= 1) || - ((SVR_SOC_VER(svr) == SVR_T2081) && SVR_MAJ(svr) <= 1)) - return true; - - return false; -} -#endif -#endif - -#ifdef CONFIG_SYS_FSL_ERRATUM_A007186 -static inline bool has_erratum_a007186(void) -{ - u32 svr = get_svr(); - u32 soc = SVR_SOC_VER(svr); - - switch (soc) { - case SVR_T4240: - return IS_SVR_REV(svr, 2, 0); - case SVR_T4160: - return IS_SVR_REV(svr, 2, 0); - case SVR_B4860: - return IS_SVR_REV(svr, 2, 0); - case SVR_B4420: - return IS_SVR_REV(svr, 2, 0); - case SVR_T2081: - case SVR_T2080: - return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1); - } - - return false; -} -#endif diff --git a/include/fsl_errata.h b/include/fsl_errata.h new file mode 100644 index 0000000..8f81e4c --- /dev/null +++ b/include/fsl_errata.h @@ -0,0 +1,61 @@ +/* + * Copyright 2013 - 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _FSL_ERRATA_H +#define _FSL_ERRATA_H + +#include <common.h> +#if defined(CONFIG_PPC) +#include <asm/processor.h> +#elif defined(CONFIG_LS102XA) +#include <asm/arch-ls102xa/immap_ls102xa.h> +#elif defined(CONFIG_FSL_LSCH3) +#include <asm/arch-fsl-lsch3/soc.h> +#endif + + +#ifdef CONFIG_SYS_FSL_ERRATUM_A006379 +static inline bool has_erratum_a006379(void) +{ + u32 svr = get_svr(); + if (((SVR_SOC_VER(svr) == SVR_T4240) && SVR_MAJ(svr) <= 1) || + ((SVR_SOC_VER(svr) == SVR_T4160) && SVR_MAJ(svr) <= 1) || + ((SVR_SOC_VER(svr) == SVR_T4080) && SVR_MAJ(svr) <= 1) || + ((SVR_SOC_VER(svr) == SVR_B4860) && SVR_MAJ(svr) <= 2) || + ((SVR_SOC_VER(svr) == SVR_B4420) && SVR_MAJ(svr) <= 2) || + ((SVR_SOC_VER(svr) == SVR_T2080) && SVR_MAJ(svr) <= 1) || + ((SVR_SOC_VER(svr) == SVR_T2081) && SVR_MAJ(svr) <= 1)) + return true; + + return false; +} +#endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_A007186 +static inline bool has_erratum_a007186(void) +{ + u32 svr = get_svr(); + u32 soc = SVR_SOC_VER(svr); + + switch (soc) { + case SVR_T4240: + return IS_SVR_REV(svr, 2, 0); + case SVR_T4160: + return IS_SVR_REV(svr, 2, 0); + case SVR_B4860: + return IS_SVR_REV(svr, 2, 0); + case SVR_B4420: + return IS_SVR_REV(svr, 2, 0); + case SVR_T2081: + case SVR_T2080: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1); + } + + return false; +} +#endif + +#endif /* _FSL_ERRATA_H */
On 11/20/2015 03:52 PM, Shengzhou Liu wrote:
move arch/powerpc/include/asm/fsl_errata.h to include/fsl_errata.h to make it public for both ARM and POWER SoCs.
Signed-off-by: Shengzhou Liu Shengzhou.Liu@freescale.com
Applied to fsl-qoriq master. Awaiting upstream.
York
DDR errata-A008378 applies to LS1021-20-22A-R1.0, T1023-R1.0, T1024-R1.0, T1040-42-20-22-R1.0/R1.1, it has been fixed on LS102x Rev2.
Signed-off-by: Shengzhou Liu Shengzhou.Liu@freescale.com --- arch/powerpc/include/asm/config_mpc85xx.h | 2 ++ drivers/ddr/fsl/fsl_ddr_gen4.c | 9 ++++++--- include/fsl_errata.h | 31 +++++++++++++++++++++++++++++++ 3 files changed, 39 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index aabe253..6308c6e 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -797,6 +797,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 #define CONFIG_SYS_FSL_SFP_VER_3_0 +#define CONFIG_SYS_FSL_ERRATUM_A008378
#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) @@ -844,6 +845,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 #define CONFIG_SYS_FSL_SFP_VER_3_0 +#define CONFIG_SYS_FSL_ERRATUM_A008378
#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) #define CONFIG_E6500 diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index 4eef047..1ef220b 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -10,6 +10,7 @@ #include <asm/processor.h> #include <fsl_immap.h> #include <fsl_ddr.h> +#include <fsl_errata.h>
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL @@ -175,9 +176,11 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, /* Erratum applies when accumulated ECC is used, or DBI is enabled */ #define IS_ACC_ECC_EN(v) ((v) & 0x4) #define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2) - if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) || - IS_DBI(regs->ddr_sdram_cfg_3)) - ddr_setbits32(ddr->debug[28], 0x9 << 20); + if (has_erratum_a008378()) { + if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) || + IS_DBI(regs->ddr_sdram_cfg_3)) + ddr_setbits32(&ddr->debug[28], 0x9 << 20); + } #endif
/* diff --git a/include/fsl_errata.h b/include/fsl_errata.h index 8f81e4c..283cfcf 100644 --- a/include/fsl_errata.h +++ b/include/fsl_errata.h @@ -58,4 +58,35 @@ static inline bool has_erratum_a007186(void) } #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008378 +static inline bool has_erratum_a008378(void) +{ + u32 svr = get_svr(); + u32 soc = SVR_SOC_VER(svr); + + + switch (soc) { +#ifdef CONFIG_LS102XA + case SOC_VER_LS1020: + case SOC_VER_LS1021: + case SOC_VER_LS1022: + case SOC_VER_SLS1020: + return IS_SVR_REV(svr, 1, 0); +#endif +#ifdef CONFIG_PPC + case SVR_T1023: + case SVR_T1024: + return IS_SVR_REV(svr, 1, 0); + case SVR_T1020: + case SVR_T1022: + case SVR_T1040: + case SVR_T1042: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1); +#endif + default: + return false; + } +} +#endif + #endif /* _FSL_ERRATA_H */
On 11/20/2015 03:52 PM, Shengzhou Liu wrote:
DDR errata-A008378 applies to LS1021-20-22A-R1.0, T1023-R1.0, T1024-R1.0, T1040-42-20-22-R1.0/R1.1, it has been fixed on LS102x Rev2.
Signed-off-by: Shengzhou Liu Shengzhou.Liu@freescale.com
Applied to fsl-qoriq master. Awaiting upstream.
York
On 11/20/2015 03:52 PM, Shengzhou Liu wrote:
Signed-off-by: Shengzhou Liu Shengzhou.Liu@freescale.com
Applied to fsl-qoriq master. Awaiting upstream.
York
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York Sun