[U-Boot] [RFC PATCH 2/9] mx6memcal: zero values for MPWRDLCTL cause read DQS calibration errors

Signed-off-by: Eric Nelson eric@nelint.com --- board/freescale/mx6memcal/spl.c | 4 ++++ 1 file changed, 4 insertions(+)

diff --git a/board/freescale/mx6memcal/spl.c b/board/freescale/mx6memcal/spl.c index 90e240f..4e63e34 100644 --- a/board/freescale/mx6memcal/spl.c +++ b/board/freescale/mx6memcal/spl.c @@ -400,6 +400,10 @@ void board_init_f(ulong dummy)

memset((void *)gd, 0, sizeof(struct global_data));

+ /* write leveling calibration defaults */ + calibration.p0_mpwrdlctl = 0x40404040; + calibration.p1_mpwrdlctl = 0x40404040; + /* setup AIPS and disable watchdog */ arch_cpu_init();