From: Reinhard Meyer info@emk-elektronik.de
Signed-off-by: Reinhard Meyer u-boot@emk-elektronik.de --- drivers/mtd/spi/Makefile | 1 + drivers/mtd/spi/ramtron.c | 297 ++++++++++++++++++++++++++++++++++ drivers/mtd/spi/spi_flash.c | 13 ++ drivers/mtd/spi/spi_flash_internal.h | 2 + 4 files changed, 313 insertions(+), 0 deletions(-) create mode 100644 drivers/mtd/spi/ramtron.c
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile index 4f11b36..a082ca7 100644 --- a/drivers/mtd/spi/Makefile +++ b/drivers/mtd/spi/Makefile @@ -32,6 +32,7 @@ COBJS-$(CONFIG_SPI_FLASH_SPANSION) += spansion.o COBJS-$(CONFIG_SPI_FLASH_SST) += sst.o COBJS-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.o COBJS-$(CONFIG_SPI_FLASH_WINBOND) += winbond.o +COBJS-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.o COBJS-$(CONFIG_SPI_M95XXX) += eeprom_m95xxx.o
COBJS := $(COBJS-y) diff --git a/drivers/mtd/spi/ramtron.c b/drivers/mtd/spi/ramtron.c new file mode 100644 index 0000000..9271e5b --- /dev/null +++ b/drivers/mtd/spi/ramtron.c @@ -0,0 +1,297 @@ +/* + * (C) Copyright 2010 + * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Note: RAMTRON SPI FRAMs are ferroelectric, nonvolatile RAMs + * with an interface identical to SPI flash devices. + * However since they behave like RAM there are no delays or + * busy polls required. They can sustain read or write at the + * allowed SPI bus speed, which can be 40 MHz for some devices. + * + * Unfortunately, some RAMTRON FRAMs do not have a means of + * identifying them. We use an environment variable to select + * the device we will handle. The variable "fram_device" should + * be set from VPD data. + */ + +#define DEBUG 1 /* remove this once its been thoroughly tested */ + +#include <common.h> +#include <malloc.h> +#include <spi_flash.h> +#include "spi_flash_internal.h" + +/* RAMTRON commands common to all devices */ +#define CMD_RAMTRON_WREN 0x06 /* Write Enable */ +#define CMD_RAMTRON_WRDI 0x04 /* Write Disable */ +#define CMD_RAMTRON_RDSR 0x05 /* Read Status Register */ +#define CMD_RAMTRON_WRSR 0x01 /* Write Status Register */ +#define CMD_RAMTRON_READ 0x03 /* Read Data Bytes */ +#define CMD_RAMTRON_WRITE 0x02 /* Write Data Bytes */ +/* not all have those: */ +#define CMD_RAMTRON_FSTRD 0x0b /* Fast Read (for compatibility - not used here) */ +#define CMD_RAMTRON_SLEEP 0xb9 /* Enter Sleep Mode */ +#define CMD_RAMTRON_RDID 0x9f /* Read ID */ +#define CMD_RAMTRON_SNR 0xc3 /* Read Serial Number */ + +#define ENV_VARIABLE "fram_device" + +/* + * Properties of supported FRAMs + * Note: speed is currently not used because we have no method to deliver that + * value to the upper layers + */ +struct ramtron_spi_fram_params { + u32 size; /* size in bytes */ + u8 addr_len; /* number of address bytes */ + u8 merge_cmd; /* some address bits are in the command byte */ + u8 id1; /* device ID 1 (family, density) */ + u8 id2; /* device ID 2 (sub, rev, rsvd) */ + u32 speed; /* max. SPI clock in Hz */ + const char *name; /* name for display and/or matching */ +}; + +struct ramtron_spi_fram { + struct spi_flash flash; + const struct ramtron_spi_fram_params *params; +}; + +static inline struct ramtron_spi_fram *to_ramtron_spi_fram(struct spi_flash + *flash) +{ + return container_of(flash, struct ramtron_spi_fram, flash); +} + +/* + * table describing supported FRAM chips: + * chips without RDID command must have the values 0xff for id1 and id2 + */ +static const struct ramtron_spi_fram_params ramtron_spi_fram_table[] = { + /* FM25V02: */ + {.size = 32*1024, .addr_len = 2, .merge_cmd = 0, + .id1 = 0x22, .id2 = 0x00, .speed = 40000000, .name = "FM25V02", }, + /* FM25VN02: */ + {.size = 32*1024, .addr_len = 2, .merge_cmd = 0, + .id1 = 0x22, .id2 = 0x01, .speed = 40000000, .name = "FM25VN02", }, + /* FM25V05: */ + { .size = 64*1024, .addr_len = 2, .merge_cmd = 0, + .id1 = 0x23, .id2 = 0x00, .speed = 40000000, .name = "FM25V05", }, + /* FM25VN05: */ + {.size = 64*1024, .addr_len = 2, .merge_cmd = 0, + .id1 = 0x23, .id2 = 0x01, .speed = 40000000, .name = "FM25VN05", }, + /* FM25V10: */ + {.size = 128*1024, .addr_len = 3, .merge_cmd = 0, + .id1 = 0x24, .id2 = 0x00, .speed = 40000000, .name = "FM25V10", }, + /* FM25VN10: */ + {.size = 128*1024, .addr_len = 3, .merge_cmd = 0, + .id1 = 0x24, .id2 = 0x01, .speed = 40000000, .name = "FM25VN10", }, + /* FM25H20: no identification */ + {.size = 256*1024, .addr_len = 3, .merge_cmd = 0, + .id1 = 0xff, .id2 = 0xff, .speed = 40000000, .name = "FM25H20", }, +}; + +static int ramtron_read(struct spi_flash *flash, + u32 offset, size_t len, void *buf) +{ + struct ramtron_spi_fram *sn = to_ramtron_spi_fram(flash); + u8 cmd[4]; + u8 cmd_len = 1; + int ret; + + if (sn->params->addr_len == 3 && sn->params->merge_cmd == 0) { + cmd[0] = CMD_RAMTRON_READ; + cmd[1] = offset >> 16; + cmd[2] = offset >> 8; + cmd[3] = offset; + cmd_len = 4; + } + else if (sn->params->addr_len == 2 && sn->params->merge_cmd == 0) { + cmd[0] = CMD_RAMTRON_READ; + cmd[1] = offset >> 8; + cmd[2] = offset; + cmd_len = 3; + } + else { + printf("SF: unsupported addr_len or merge_cmd\n"); + return -1; + } + + debug("READ: 0x%x => cmd = { 0x%02x 0x%02x%02x%02x } len = 0x%x\n", + offset, cmd[0], cmd[1], cmd[2], cmd[3], len); + + /* claim the bus */ + ret = spi_claim_bus(flash->spi); + if (ret) { + debug("SF: Unable to claim SPI bus\n"); + return ret; + } + + /* read the data */ + ret = spi_flash_read_common(flash, cmd, cmd_len, buf, len); + if (ret < 0) + debug("SF: Read failed\n"); + + /* release the bus */ + spi_release_bus(flash->spi); + return ret; +} + +static int ramtron_write(struct spi_flash *flash, + u32 offset, size_t len, const void *buf) +{ + struct ramtron_spi_fram *sn = to_ramtron_spi_fram(flash); + u8 cmd[4]; + u8 cmd_len = 1; + int ret; + + if (sn->params->addr_len == 3 && sn->params->merge_cmd == 0) { + cmd[0] = CMD_RAMTRON_WRITE; + cmd[1] = offset >> 16; + cmd[2] = offset >> 8; + cmd[3] = offset; + cmd_len = 4; + } + else if (sn->params->addr_len == 2 && sn->params->merge_cmd == 0) { + cmd[0] = CMD_RAMTRON_WRITE; + cmd[1] = offset >> 8; + cmd[2] = offset; + cmd_len = 3; + } + else { + printf("SF: unsupported addr_len or merge_cmd\n"); + return -1; + } + + debug("WRITE: 0x%x => cmd = { 0x%02x 0x%02x%02x%02x } len = 0x%x\n", + offset, cmd[0], cmd[1], cmd[2], cmd[3], len); + + /* claim the bus */ + ret = spi_claim_bus(flash->spi); + if (ret) { + debug("SF: Unable to claim SPI bus\n"); + return ret; + } + + /* send WREN */ + ret = spi_flash_cmd(flash->spi, CMD_RAMTRON_WREN, NULL, 0); + if (ret < 0) { + debug("SF: Enabling Write failed\n"); + goto releasebus; + } + + /* write the data */ + ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len, buf, len); + if (ret < 0) + debug("SF: Write failed\n"); + +releasebus: + /* release the bus */ + spi_release_bus(flash->spi); + return ret; +} + +int ramtron_erase(struct spi_flash *flash, u32 offset, size_t len) +{ + debug("SF: Erase of RAMTRON FRAMs is pointless\n"); + return -1; +} + +struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi) +{ + const struct ramtron_spi_fram_params *params; + struct ramtron_spi_fram *sn; + unsigned int i; + u8 idcode[10]; + int ret; + const char *device_name = getenv (ENV_VARIABLE); + + /* NOTE: the bus has been claimed before this function is called! */ + + /* try to get an ID first */ + ret = spi_flash_cmd(spi, CMD_RAMTRON_RDID, &idcode, sizeof(idcode)); + if (ret) { + debug("SF: Read ID command failed\n"); + return NULL; + } + + debug("SF: Got idcode %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", + idcode[0], idcode[1], idcode[2], idcode[3], idcode[4], + idcode[5], idcode[6], idcode[7], idcode[8], idcode[9]); + + /* + * RAMTRON chips without RDID command support will keep their Q output + * tristated. Depending on MISO termination we will read noise. + * Chips with RDID command support will answer 6*0x7f, 0xc2, id1, id2. + */ + if (idcode[0]==0x7f && idcode[1]==0x7f && idcode[2]==0x7f && idcode[3]==0x7f && + idcode[4]==0x7f && idcode[5]==0x7f && idcode[6]==0xc2) { + for (i = 0; i < ARRAY_SIZE(ramtron_spi_fram_table); i++) { + params = &ramtron_spi_fram_table[i]; + if (idcode[7]==params->id1 && idcode[8]==params->id2) + goto found; + } + debug("SF: Unsupported RAMTRON device id1=%02x id2=%02x\n", + idcode[7], idcode[8]); + return NULL; + } + + /* + * If no ID was found, we will try the environment variable, + * but we will only match chips that do not support RDID command + */ + if (device_name) { + for (i = 0; i < ARRAY_SIZE(ramtron_spi_fram_table); i++) { + params = &ramtron_spi_fram_table[i]; + if (params->id1==0xff && params->id2==0xff && + !strcmp(params->name, device_name)) + goto found; + } + debug("SF: Unsupported RAMTRON device %s\n", device_name); + return NULL; + } + + /* no success with either method... */ + return NULL; + +found: + sn = malloc(sizeof(struct ramtron_spi_fram)); + if (!sn) { + debug("SF: Failed to allocate memory\n"); + return NULL; + } + + sn->params = params; + sn->flash.spi = spi; + sn->flash.name = params->name; + + sn->flash.write = ramtron_write; + sn->flash.read = ramtron_read; + sn->flash.erase = ramtron_erase; + sn->flash.size = params->size; + + printf("SF: Detected %s with size ", params->name); + print_size(sn->flash.size, "\n"); + + return &sn->flash; +} + diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index ea875dc..328366b 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -116,6 +116,19 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, goto err_claim_bus; }
+#ifdef CONFIG_SPI_FRAM_RAMTRON + /* + * not all RAMTRON FRAMs do have a READ_ID command, + * let the ramtron code figure out details + */ + flash = spi_fram_probe_ramtron(spi); + if (flash) { + spi_release_bus(spi); + return flash; + } + /* if spi_fram_probe did not find anything, continue normal probe */ +#endif + /* Read the ID codes */ ret = spi_flash_cmd(spi, CMD_READ_ID, &idcode, sizeof(idcode)); if (ret) diff --git a/drivers/mtd/spi/spi_flash_internal.h b/drivers/mtd/spi/spi_flash_internal.h index 08546fb..0f1b8da 100644 --- a/drivers/mtd/spi/spi_flash_internal.h +++ b/drivers/mtd/spi/spi_flash_internal.h @@ -50,3 +50,5 @@ struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode); struct spi_flash *spi_flash_probe_sst(struct spi_slave *spi, u8 *idcode); struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 *idcode); struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode); +struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi); +