Hi Stefan,
Stefan Roese wrote:
I just looked at the datasheet of your flash part as well as datasheet of a couple of intel flash parts as well as the current code. As I suspected for your particular part, it looks like they are using the same values for "Erase Bank Area 1" and "Erase Bank Area 2" irrespective of top boot or bottom boot flash. I think, this is fundamentally wrong and non-compliant with the general CFI standard.
I will look at some AMD part datasheets. If this is generally available on all AMD and AMD like parts, we can add it as a patch for AMD only. Otherwise, we will either add CONFIG_GEOMETRY_REVERSED definition or restrict a patch to specific vendor ids (and possibly part ids) which is then a pain to manage.
I suggest that we also look at the linux mtd cfi driver to see, if and how those devices are handled. I remember seeing something like "broken CFI table" in the linux bootlog on some boards.
I will check MTD CFI driver when I have a bit of free time. I just sent an email to the list regarding what I learned from AMD CFI specifications. It looks like if we can enumerate those early top/bottom devices that use AMD CFI 1.0 specification, we can come up with a patch that can handle this case transparently. AMD specification specifies two devices. Perhaps we can prepare patch based on these and if there happens to be more like these we can expand the list using future patches.
Tolunay