diff -purN OLD/MAINTAINERS NEW/MAINTAINERS
--- OLD/MAINTAINERS	Tue Nov 15 11:36:37 2005
+++ NEW/MAINTAINERS	Thu Nov 24 15:03:09 2005
@@ -474,6 +474,9 @@ Wolfgang Denk <wd@denx.de>
 Thomas Lange <thomas@corelatus.se>
 	dbau1x00		MIPS32 Au1000
 
+Jakob Sandgren <jakob.sandgren@i3micro.com>
+	mood300			MIPS32 Au1550
+
 #########################################################################
 # Nios-32 Systems:							#
 #									#
diff -purN OLD/MAKEALL NEW/MAKEALL
--- OLD/MAKEALL	Tue Nov 15 11:36:37 2005
+++ NEW/MAKEALL	Tue Nov 15 16:05:14 2005
@@ -223,7 +223,10 @@ LIST_mips4kc="incaip"
 
 LIST_mips5kc="purple"
 
-LIST_au1xx0="dbau1000 dbau1100 dbau1500 dbau1550 dbau1550_el"
+LIST_au1xx0="	\
+	dbau1000 dbau1100 dbau1500 dbau1550 dbau1550_el            \
+	i3micro_mood300						   \
+"
 
 LIST_mips="${LIST_mips4kc} ${LIST_mips5kc} ${LIST_au1xx0}"
 
diff -purN OLD/Makefile NEW/Makefile
--- OLD/Makefile	Tue Nov 15 11:36:37 2005
+++ NEW/Makefile	Thu Nov 17 16:10:48 2005
@@ -1700,6 +1700,11 @@ pb1000_config		: 	unconfig
 	@ >include/config.h
 	@echo "#define CONFIG_PB1000 1" >>include/config.h
 	@./mkconfig -a pb1x00 mips mips pb1x00
+
+i3micro_mood300_config        :       unconfig
+	@ >include/config.h
+	@echo "#define CONFIG_I3_MOOD300 1" >>include/config.h
+	@./mkconfig -a mood300 mips mips mood300 i3micro
 
 #########################################################################
 ## MIPS64 5Kc
diff -purN OLD/board/i3micro/mood300/Makefile NEW/board/i3micro/mood300/Makefile
--- OLD/board/i3micro/mood300/Makefile	Thu Jan  1 01:00:00 1970
+++ NEW/board/i3micro/mood300/Makefile	Thu Nov 24 13:50:10 2005
@@ -0,0 +1,32 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR) / config.mk
+  LIB = lib$(BOARD).a
+  OBJS = $(BOARD).o
+  SOBJS = lowlevel_init.o
+$(LIB):.depend $(OBJS) $(SOBJS) $(AR) crv $ @ $(OBJS) $(SOBJS)
+#########################################################################
+.depend:Makefile $(SOBJS:.o =.S) $(OBJS:.o =.c)
+$(CC) - M $(CFLAGS) $(SOBJS:.o =.S) $(OBJS:.o =.c) > $ @ sinclude.depend
+#########################################################################
diff -purN OLD/board/i3micro/mood300/config.mk NEW/board/i3micro/mood300/config.mk
--- OLD/board/i3micro/mood300/config.mk	Thu Jan  1 01:00:00 1970
+++ NEW/board/i3micro/mood300/config.mk	Thu Nov 24 13:50:10 2005
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# I3 Micro IP Set-top box series 300
+#
+
+# ROM version
+TEXT_BASE = 0xbfc00000
+# RAM version
+#TEXT_BASE = 0x80100000
diff -purN OLD/board/i3micro/mood300/lowlevel_init.S NEW/board/i3micro/mood300/lowlevel_init.S
--- OLD/board/i3micro/mood300/lowlevel_init.S	Thu Jan  1 01:00:00 1970
+++ NEW/board/i3micro/mood300/lowlevel_init.S	Thu Nov 17 15:05:46 2005
@@ -0,0 +1,630 @@
+/* Memory sub-system initialization code */
+
+#include <config.h>
+#include <version.h>
+#include <asm/regdef.h>
+#include <asm/au1x00.h>
+#include <asm/mipsregs.h>
+
+#define AU1500_SYS_ADDR		0xB1900000
+#define sys_endian		0x0038
+#define CP0_Config0		$16
+#define CPU_SCALE		((CFG_MHZ) / 12) /* CPU clock is a multiple of 12 MHz */
+#define MEM_1MS			((CFG_MHZ) * 1000)
+
+	.text
+	.set noreorder
+	.set mips32
+
+	.globl	lowlevel_init
+lowlevel_init:
+	/* Init secondary gpio */
+	li	t0, 0xb1700000
+	li	t1, 3
+	sw	t1, 0x14(t0)
+	sync
+	li	t1, 1
+	sw	t1, 0x14(t0)
+	sync
+/*	li	t1, 0x00001018 */
+	li	t1, 0x0000183f
+	sw	t1, 0(t0)
+	sync
+
+	/* Turn on LED:s */
+	li	t1, 0x10181018
+	sw	t1, 0x8(t0)
+
+	/* Set SPI CS:s high (off) */
+	li	t1, 0x00060006
+	sw	t1, 0x8(t0)
+
+	/* Disable NAND write protect */
+	li	t1, 0x00200020
+	sw	t1, 0x8(t0)
+
+	/* Disable NOR write protect */
+	li	t1, 0x08000800
+	sw	t1, 0x8(t0)
+
+	/* Change Au1 core to little endian */
+	li	t0, AU1500_SYS_ADDR
+	li	t1, 1
+	sw	t1, sys_endian(t0)
+	mfc0	t2, CP0_CONFIG
+	mtc0	t2, CP0_CONFIG
+	nop
+	nop
+
+	/* Check for rescue request */
+#define AU1XX0_PINCONF       0x0036263e
+	li	t0, SYS_PINFUNC
+	li	t1, AU1XX0_PINCONF
+	sw	t1, 0(t0)
+#undef AU1XX0_PINCONF
+	/* wait 1mS before test */
+	li	t1, MEM_1MS
+1:	add	t1, -1
+	bne	t1, zero, 1b
+	nop
+	
+	/* Read GPIO20 */
+	li	t0, SYS_PINSTATERD
+	lw	t1, 0(t0)
+	li	t2, 0x00100000
+	and	t1, t2, t1
+	beq	zero, t1, norescue /* Pin high if rescue requested */
+	nop
+
+	/* Indicate rescue pin set
+	 * UGLY HACK WARNING:	this value is read back in misc_init_r()
+	 *			so don't fiddle with the led:s until then :)
+	 */	
+	li	t0, 0xb1700000
+	li	t1, 0x00080000
+	sw	t1, 0x8(t0)
+
+norescue:		
+
+	/* Read GPIO21 */
+	li	t0, SYS_PINSTATERD
+	lw	t1, 0(t0)
+	li	t2, 0x00200000
+	and	t1, t2, t1
+	bne	zero, t1, norestore /* Pin low if rescue requested */
+	nop
+
+	/* Indicate rescue pin set
+	 * UGLY HACK WARNING:	this value is read back in misc_init_r()
+	 *			so don't fiddle with the led:s until then :)
+	 */	
+	li	t0, 0xb1700000
+	li	t1, 0x00100000
+	sw	t1, 0x8(t0)
+
+norestore:
+	
+	/*
+	 * Step 2) Establish Status Register
+	 * (set BEV, clear ERL, clear EXL, clear IE)
+	 */
+	li	t1, 0x00400000
+	mtc0	t1, CP0_STATUS
+
+	/*
+	 * Step 3) Establish CP0 Config0
+	 * (set OD, set K0=3)
+	 */
+	li	t1, 0x00080003
+	mtc0	t1, CP0_CONFIG
+
+	/*
+	 * Step 4) Disable Watchpoint facilities
+	 */
+	li t1, 0x00000000
+	mtc0	t1, CP0_WATCHLO
+	mtc0	t1, CP0_IWATCHLO
+	/*
+	 * Step 5) Disable the performance counters
+	 */
+	mtc0	zero, CP0_PERFORMANCE
+	nop
+
+	/*
+	 * Step 6) Establish EJTAG Debug register
+	 */
+	mtc0	zero, CP0_DEBUG
+	nop
+
+	/*
+	 * Step 7) Establish Cause
+	 * (set IV bit)
+	 */
+	li	t1, 0x00800000
+	mtc0	t1, CP0_CAUSE
+
+	/* No workaround if running from ram */
+	lui	t0, 0xffc0
+	lui	t3, 0xbfc0
+	and	t1, ra, t0
+	bne	t1, t3, neverMind
+	nop
+	
+	/*** From YAMON ***/
+	/*
+	 * Step 8) Initialize the caches
+	 */
+	li		t0, (16*1024)
+	li		t1, 32
+	li		t2, 0x80000000
+	addu	t3, t0, t2
+cacheloop:
+	cache	0, 0(t2)
+	cache	1, 0(t2)
+	addu	t2, t1
+	bne		t2, t3, cacheloop
+	nop
+
+	/* lel - Save ra */
+	move		t3, ra
+
+	/* Run from cacheable space now */
+	bal		cachehere
+	nop
+cachehere:
+	li		t1, ~0x20000000 /* convert to KSEG0 */
+	and		t0, ra, t1
+	addi	t0, 5*4			/* 5 insns beyond cachehere */
+	jr		t0
+	nop
+
+	/* lel - Restore ra */
+	move		ra, t3	
+	
+	/*
+	 * Step 9) Initialize the TLB
+	 */
+	li		t0, 0		 	# index value
+	li		t1, 0x00000000		# entryhi value
+	li		t2, 32		   	# 32 entries
+	
+tlbloop:
+        /* Probe TLB for matching EntryHi */
+        mtc0    t1, CP0_ENTRYHI
+        tlbp
+        nop
+
+        /* Examine Index[P], 1=no matching entry */
+        mfc0    t3, CP0_INDEX
+        li      t4, 0x80000000
+        and     t3, t4, t3
+        addiu   t1, t1, 1               # increment t1 (asid)
+        beq     zero, t3, tlbloop
+        nop
+
+        /* Initialize the TLB entry */
+        mtc0    t0, CP0_INDEX
+        mtc0    zero, CP0_ENTRYLO0
+        mtc0    zero, CP0_ENTRYLO1
+        mtc0    zero, CP0_PAGEMASK
+        tlbwi
+
+        /* Do it again */
+        addiu   t0, t0, 1       
+        bne     t0, t2, tlbloop
+        nop
+
+        /* Establish Wired (and Random) */
+        mtc0    zero, CP0_WIRED
+        nop
+	
+	/* First setup pll:s to make serial work ok */
+	/* We have a 12 MHz crystal */
+	li	t0, SYS_CPUPLL
+	li	t1, CPU_SCALE  /* CPU clock */
+	sw	t1, 0(t0)
+	sync
+	nop
+	nop
+
+	/*
+	 * Step 11) Establish system bus divider
+	 */
+	li	t0, SYS_POWERCTRL
+	sw	zero, 0(t0)
+	sync
+
+	/* Setup AUX PLL */
+	li	t0, SYS_AUXPLL
+	li	t1, 0x18 /* 288 MHz */
+	sw	t1, 0(t0) /* aux pll */
+	sync
+
+	/*  Static memory controller */
+	/* RCE0 - can not change while fetching, do so from icache */
+	move		t2, ra /* Store return address */
+	bal		getAddr
+	nop
+
+getAddr:
+	move		t1, ra
+	move		ra, t2 /* Move return addess back */
+	
+	cache	0x14,0(t1)
+	cache	0x14,32(t1)
+	/*** /From YAMON ***/
+
+neverMind:
+	/*  Static memory controller */
+	li	t0, MEM_STTIME0
+	li	t1, 0x00014C0F
+	sw	t1, 0(t0)
+	
+	/* RCE0 AMD 2 Mb NOR Flash */
+	li	t0, MEM_STCFG0
+	li	t1, 0x00040043
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR0
+	li	t1, 0x11FC3FF0
+	sw	t1, 0(t0)
+	sync
+
+	/* RCE1 (unused) */
+	li	t0, MEM_STCFG1
+	li	t1, 0
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STTIME1
+	li	t1, 0
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR1
+	li	t1, 0
+	sw	t1, 0(t0)
+
+	/* RCE2 NAND Flash */
+	li	t0, MEM_STCFG2
+	li	t1, 0x00400005
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STTIME2
+	li	t1, 0x00007774
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR2
+	li	t1, 0x11FB3FFC
+	sw	t1, 0(t0)
+
+	/* RCE3 (unused) */
+	li	t0, MEM_STCFG3
+	li	t1, 0
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STTIME3
+	li	t1, 0
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR3
+	li	t1, 0
+	sw	t1, 0(t0)
+	
+	sync
+
+	/* Set peripherals to a known state */
+	li	t0, IC0_CFG0CLR
+	li	t1, 0xFFFFFFFF
+	sw	t1, 0(t0)
+
+	li	t0, IC0_CFG0CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_CFG1CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_CFG2CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_SRCSET
+	sw	t1, 0(t0)
+
+	li	t0, IC0_ASSIGNSET
+	sw	t1, 0(t0)
+
+	li	t0, IC0_WAKECLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_RISINGCLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_FALLINGCLR
+	sw	t1, 0(t0)
+
+	li	t0, IC0_TESTBIT
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, IC1_CFG0CLR
+	li	t1, 0xFFFFFFFF
+	sw	t1, 0(t0)
+
+	li	t0, IC1_CFG0CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_CFG1CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_CFG2CLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_SRCSET
+	sw	t1, 0(t0)
+
+	li	t0, IC1_ASSIGNSET
+	sw	t1, 0(t0)
+
+	li	t0, IC1_WAKECLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_RISINGCLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_FALLINGCLR
+	sw	t1, 0(t0)
+
+	li	t0, IC1_TESTBIT
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, SYS_FREQCTRL0
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, SYS_FREQCTRL1
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, SYS_CLKSRC
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, SYS_PININPUTEN
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, 0xB1100100
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, 0xB1400100
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+
+	li	t0, SYS_WAKEMSK
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	li	t0, SYS_WAKESRC
+	li	t1, 0x00000000
+	sw	t1, 0(t0)
+
+	/* wait 1mS before setup */
+	li	t1, MEM_1MS
+1:	add	t1, -1
+	bne	t1, zero, 1b
+	nop
+
+
+/* SDCS 0,1,2 DDR SDRAM */
+	li	t0, MEM_SDMODE0
+	li	t1, 0x04276221
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDMODE1
+	li	t1, 0x04276221
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDMODE2
+	li	t1, 0
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDADDR0
+	li	t1, 0xe21003f0
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDADDR1
+	li	t1, 0xe21043f0
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDADDR2
+	li	t1, 0
+	sw	t1, 0(t0)
+
+	sync
+
+	li	t0, MEM_SDCONFIGA
+	li	t1, 0x9030060a /* Program refresh - disabled */
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDCONFIGB
+	li	t1, 0x00028000
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDPRECMD /* Precharge all */
+	li	t1, 0
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDWRMD0
+	li	t1, 0x40000000
+	sw	t1, 0(t0)
+	sync
+	
+	li	t0, MEM_SDWRMD1
+	li	t1, 0x40000000
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDWRMD0
+	li	t1, 0x00000063
+	sw	t1, 0(t0)
+	sync
+	
+	li	t0, MEM_SDWRMD1
+	li	t1, 0x00000063
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDPRECMD /* Precharge all */
+	sw	zero, 0(t0)
+	sync
+
+	/* Issue 2 autoref */
+	li	t0, MEM_SDAUTOREF
+	sw	zero, 0(t0)
+	sync		
+	
+	li	t0, MEM_SDAUTOREF
+	sw	zero, 0(t0)
+	sync
+	
+	/* Enable refresh */
+	li	t0, MEM_SDCONFIGA
+	li	t1, 0x9830060a /* Program refresh - enabled */
+	sw	t1, 0(t0)
+	sync
+
+	/* wait 1mS after setup */
+	li	t1, MEM_1MS
+1:	add	t1, -1
+	bne	t1, zero, 1b
+	nop
+
+	/* Init primary GPIO */
+#define AU1XX0_PINCONF       0x00362636
+#define AU1XX0_TRIOUTCONF    0x0e01ffd0
+#define AU1XX0_OUTPUTSETCONF 0x04016000
+#define AU1XX0_OUTPUTCLRCONF 0x0a009fd0
+	li	t0, SYS_PINFUNC
+	li	t1, AU1XX0_PINCONF
+	sw	t1, 0(t0)
+
+	li	t0, SYS_TRIOUTCLR
+	li	t1, AU1XX0_TRIOUTCONF
+	sw	t1, 0(t0)
+
+	li	t0, SYS_PININPUTEN
+	sw	zero, 0(t0)
+	
+	li	t0, SYS_OUTPUTSET
+	li	t1, AU1XX0_OUTPUTSETCONF
+	sw	t1, 0(t0)
+	
+	li	t0, SYS_OUTPUTCLR
+	li	t1, AU1XX0_OUTPUTCLRCONF
+	sw	t1, 0(t0)
+	sync
+
+	/* Init frequency control 0:
+	 * Freq0:	CPU/6     = 54 MHz (PCI)
+	 * Freq1:	AUXPLL/6  = 48 MHz (USB/I2C)
+	 * Freq2:	AUXPLL/36 =  8 MHz (AVR)
+	 */
+	li	t0, SYS_FREQCTRL0
+	li	t1, 0x04702c0a
+	sw	t1, 0(t0)
+
+	/* Init clock source control:
+	 * EXTCLK1:		Freq2
+	 * EXTCLK0/PSC3:	Freq1
+	 * PCICLK:		Freq0
+	 * PSC1CLK:		disabled
+	 * PSC0CLK:		disabled
+	 * USBCLK/PSC2:		Freq1
+	 */
+	li	t0, SYS_CLKSRC
+	li	t1, 0x20c4000c
+	sw	t1, 0(t0)
+
+	sync
+
+pcireset:
+#define AU1550_PCI_ADDR		0xB4005000
+#define pci_cmem		0x0000
+#define pci_config		0x0004
+#define pci_b2bmask_cch		0x0008
+#define pci_b2bbase0_venid	0x000C
+#define pci_b2bbase1_id		0x0010
+#define pci_mwmask_dev		0x0014
+#define pci_mwbase_rev_ccl	0x0018
+#define pci_err_addr		0x001C
+#define pci_spec_intack		0x0020
+#define pci_id			0x0100
+#define pci_statcmd		0x0104
+#define pci_classrev		0x0108
+#define pci_hdrtype		0x010C
+#define pci_mbar		0x0110
+#define pci_timeout		0x0140
+	/* wait 1mS */
+	li		t1, MEM_1MS
+1:	add		t1, -1
+	bne		t1, zero, 1b
+	nop
+
+	/* De-assert PCI_RST# */
+	li		t0, 0xb1700008
+	li		t1, (1<<16)|(1<<0)
+	sw		t1, 0(t0)
+	sync
+
+	/* Wait 6 PCI clock cycles */
+	li		t1, MEM_1MS
+1:	add		t1, -1
+	bne		t1, zero, 1b
+	nop
+	sync
+
+	/* Setup PCI Host - See Au1500 PCI app note */
+	li		t0, AU1550_PCI_ADDR
+	li		t1, 0x00000000
+	sw		t1, pci_cmem(t0)
+	li		t1, 0x0008000F
+	sw		t1, pci_config(t0)
+	li		t1, 0xFFFF0000
+	sw		t1, pci_b2bmask_cch(t0)
+	li		t1, 0x00000000
+	sw		t1, pci_b2bbase0_venid(t0)
+	li		t1, 0x00000000
+	sw		t1, pci_b2bbase1_id(t0)
+	li		t1, 0xE0000000
+	sw		t1, pci_mwmask_dev(t0)
+	li		t1, 0x00000000
+	sw		t1, pci_mwbase_rev_ccl(t0)
+	li		t1, 0x02A00356
+	sw		t1, pci_statcmd(t0)
+	li		t1, 0x00000000
+	sw		t1, pci_hdrtype(t0)
+	li		t1, 0x00000008
+	sw		t1, pci_mbar(t0)
+	li		t1, 0x00000000
+	sw		t1, pci_timeout(t0)
+
+#define DB1550_BCSR_ADDR 0xAF000000
+	/* Take AMD PHYs out of reset */
+	li		t0, DB1550_BCSR_ADDR
+	li		t1, 3
+	sh		t1, 0x0C(t0)
+	
+	/* Relese AVR reset */
+	li	t0, SYS_OUTPUTSET
+	li	t1, 0x00008000
+	sw	t1, 0(t0)
+	
+	j	ra
+	nop
diff -purN OLD/board/i3micro/mood300/mood300.c NEW/board/i3micro/mood300/mood300.c
--- OLD/board/i3micro/mood300/mood300.c	Thu Jan  1 01:00:00 1970
+++ NEW/board/i3micro/mood300/mood300.c	Thu Nov 24 13:50:11 2005
@@ -0,0 +1,377 @@
+/*
+ * (C) Copyright 2004
+ * Leif.Lindholm@i3micro.com
+ *
+ * Modified/srtipped down version of dbau1x00.c by Thomas.Lange@corelatus.se
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/au1x00.h>
+#include <asm/mipsregs.h>
+
+#include "sysflash.h"
+
+long int initdram(int board_type)
+{
+  /* Sdram is setup by assembler code */
+  /* If memory could be changed, we should return the true value here */
+  return MEM_SIZE * 1024 * 1024;
+}
+
+
+int checkboard(void)
+{
+  u32 proc_id;
+
+  proc_id = read_32bit_cp0_register(CP0_PRID);
+
+  switch (proc_id >> 24)
+  {
+  case 3:
+    puts("Board: Mood 300 Series\n");
+    printf("CPU: Au1550, id: 0x%02x, rev: 0x%02x\n",
+	   (proc_id >> 8) & 0xFF, proc_id & 0xFF);
+
+    break;
+  default:
+    printf("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
+    return 1;
+  }
+
+  return 0;
+}
+
+int sysflash_checksum(struct flash_system_area *fsa)
+{
+  unsigned long crc_lookup_table[256];
+  int i, j, topbit;
+  unsigned long reg;
+  unsigned long crc = 0;
+  int size;
+  unsigned char *p;
+
+  if (fsa->rom.check.magic != FSA_MAGIC)
+    return 1;
+
+  /* for all possible byte values */
+  for (i = 0; i < 256; i++)
+  {
+    reg = i << 24;
+    /* for all bits in a byte */
+    for (j = 0; j < 8; ++j)
+    {
+      topbit = (reg & 0x80000000);
+      reg <<= 1;
+      if (topbit)
+	reg ^= CRC_KEY;
+    }
+    crc_lookup_table[i] = reg;
+  }
+
+  size = PARAM_SIZE;
+  p = (unsigned char *)fsa;
+  while (size--)
+  {
+    crc = (crc << 8) ^ crc_lookup_table[(crc >> 24) ^ *p++];
+  }
+
+  return crc;
+}
+
+
+int wipe_flash(void)
+{
+  printf("Erasing NAND\n");
+
+  if (run_command("nand erase", 0) != 1)
+  {
+    return 1;
+  }
+
+  return restore_sysdef();
+}
+
+
+int restore_sysdef(void)
+{
+  char cmdbuf[128];
+
+  printf("Restoring parameter area\n");
+
+  sprintf(cmdbuf, "protect off 0x%08x 0x%08x", MAIN_PARAM_AREA,
+	  (MAIN_PARAM_AREA + PARAM_SIZE - 1));
+  if (run_command(cmdbuf, 0) != 1)
+  {
+    return 1;
+  }
+
+  sprintf(cmdbuf, "erase 0x%08x 0x%08x", MAIN_PARAM_AREA,
+	  (MAIN_PARAM_AREA + PARAM_SIZE - 1));
+  if (run_command(cmdbuf, 0) != 1)
+  {
+    return 1;
+  }
+
+  sprintf(cmdbuf, "cp.b 0x%08x 0x%08x 0x%08x", SYSDEF_PARAM_AREA,
+	  MAIN_PARAM_AREA, PARAM_SIZE);
+  if (run_command("cp.b 0xbfc40000 0xbfc30000 0x10000", 0) != 1)
+  {
+    return 1;
+  }
+
+  return 0;
+}
+
+
+/* Initialize I3 environment */
+int misc_init_r(void)
+{
+  volatile u32 *gpio2_set = (u32 *) (GPIO2_DATA_EN);
+  volatile u32 *gpio2_get = (u32 *) (GPIO2_PIN_STATE);
+  volatile u32 *trioutrd = (u32 *) (SYS_TRIOUTRD);
+  volatile u32 *trioutclr = (u32 *) (SYS_TRIOUTCLR);
+  volatile u32 *outputset = (u32 *) (SYS_OUTPUTSET);
+
+  struct flash_system_area *fsa = MAIN_PARAM_AREA;
+  unsigned char tmpbuf[64];
+  unsigned char *ea;
+  int ret;
+
+  if (sysflash_checksum(fsa) != 0)
+  {
+    printf("Parameter area checksum failure - restoring.");
+
+    /* Restore default area */
+    (void)restore_sysdef();
+
+    if (sysflash_checksum(fsa) != 0)
+    {
+      printf("Parameter area still invalid - using defaults!\n");
+      fsa = SYSDEF_PARAM_AREA;
+    }
+  }
+
+  ea = &(fsa->rom.param.mac);
+  sprintf(tmpbuf, "%02x:%02x:%02x:%02x:%02x:%02x", ea[0], ea[1], ea[2], ea[3],
+	  ea[4], ea[5]);
+  setenv("ethaddr", tmpbuf);
+
+  sprintf(tmpbuf, "%s-%s", fsa->rom.param.product_id, fsa->rom.param.serial);
+  setenv("serial", tmpbuf);
+
+  sprintf(tmpbuf, "mood300_recover_%.4s.img", fsa->rom.param.product_id);
+  setenv("defaultfile", tmpbuf);
+
+  setenv("bootargs", "root=/dev/ram0 rw console=ttyS0,115200");
+
+  if (*fsa->rom.param.vendorclassid)
+  {
+    strncpy(tmpbuf, fsa->rom.param.vendorclassid,
+	    sizeof(fsa->rom.param.vendorclassid));
+    strcat(tmpbuf, "R");
+    printf("Using DHCP Vendor Class ID override: %s\n", tmpbuf);
+    setenv("dhcp_vendor-class-identifier", tmpbuf);
+  }
+  else
+  {
+    setenv("dhcp_vendor-class-identifier", "i3 micro STB Mood 300R");
+  }
+
+  /* Check for debug adapter */
+  if ((*gpio2_get & (1 << 13)) == 0)
+  {
+    printf("Debug adapter present\n");
+    /* Configure AVR reset to open drain */
+    *outputset = 0x00008000;
+    *trioutclr = *trioutrd & 0x00008000;
+  }
+  else
+  {
+    /* Disable console input */
+    printf("No debug adapter present - disabling input\n");
+    *gpio2_set = 0x10000000;
+    setenv("noinput", "true");
+  }
+
+  /* Check for rescue trigger
+   * UGLY HACK WARNING:
+   * The rightmost LED is turned off in memsetup.S if rescue is triggered.
+   * Check status of LED, then turn it on if not lit.
+   */
+  if ((*gpio2_get & 0x00000008) == 0)
+  {
+    printf("rescue enabled - forcing netboot\n");
+    *gpio2_set = 0x00080008;
+
+    sprintf(tmpbuf, "dhcp; bootm");
+    setenv("bootcmd", tmpbuf);
+  }
+
+  if ((*gpio2_get & 0x00000010) == 0)
+  {
+    printf("\n<<<restore triggered>>>\n");
+    wipe_flash();
+    printf("<<<restore done>>>\n");
+    *gpio2_set = 0x00100010;
+  }
+
+  printf("\n");
+
+  return 0;
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+extern ulong nand_probe(ulong physadr);
+
+void nand_init(void)
+{
+  ulong totlen = 0;
+
+//        printf ("Probing at 0x%.8x)\n", NAND_PHYS_ADDR);
+  totlen += nand_probe(NAND_PHYS_ADDR);
+
+  printf("%4lu MB\n", totlen >> 20);
+}
+
+u8 au1550_write_nand_address(u8 d, u8 * adr)
+{
+  volatile u8 *ptr = (u8 *) (adr + NAND_ADDR_REG);
+
+//    printf("write_address(0x%02x, 0x%08x)\n", d & 0xff, ptr);
+
+  *ptr = d;
+
+  au_sync();
+
+  return d;
+}
+
+u8 au1550_write_nand_command(u8 d, u8 * adr)
+{
+  volatile u8 *ptr = (u8 *) (adr + NAND_CMD_REG);
+
+//    printf("write_command(0x%02x, 0x%08x)\n", d & 0xff, ptr);
+
+  *ptr = d;
+
+  au_sync();
+
+  return d;
+}
+
+u8 au1550_write_nand_data(u8 d, u8 * adr)
+{
+  volatile u8 *ptr = (u8 *) (adr + NAND_DATA_REG);
+
+//    printf("write_data(0x%02x, 0x%08x)\n", d & 0xff, ptr);
+
+  *ptr = d;
+
+  au_sync();
+
+  return d;
+}
+
+u8 au1550_read_nand_data(u8 * adr)
+{
+  volatile u8 *ptr = (u8 *) (adr + NAND_DATA_REG);
+  u8 tmp;
+
+  tmp = *ptr;
+
+//    printf("read_data(0x%02x, 0x%08x)\n", tmp & 0xff, ptr);
+
+  au_sync();
+
+  return tmp;
+}
+
+u8 au1550_wait_nand_ready(u32 * adr)
+{
+  volatile u32 *ststat = (u32 *) MEM_STSTAT;
+
+//    printf("wait_nand_ready()\n");
+
+  while ((*ststat & 0x1) == 0);
+
+  return 0;
+}
+
+
+void au1550_nand_disable_ce(u32 * nand)
+{
+  volatile u32 *stndctl = (u32 *) MEM_STNDCTL;
+
+//    printf("nand_disable_ce()\n");
+
+  /* deassert chip enable */
+  *stndctl = *stndctl & ~0xf0;
+}
+
+
+void au1550_nand_enable_ce(u32 * nand)
+{
+  volatile u32 *stndctl = (u32 *) MEM_STNDCTL;
+
+//    printf("nand_enable_ce()\n");
+
+  /* assert (force assert) chip enable */
+  *stndctl = (*stndctl & ~0xf0) | 0x40;
+}
+
+#endif
+
+#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_VENDOREX)
+/* ------------------------------------------------------------------------- */
+
+u8 *dhcp_vendorex_prep(u8 * e)
+{
+  char *ptr;
+
+/* DHCP vendor-class-identifier = 60 */
+  if ((ptr = getenv("dhcp_vendor-class-identifier")))
+  {
+    *e++ = 60;
+    *e++ = strlen(ptr);
+    while (*ptr)
+      *e++ = *ptr++;
+  }
+/* my DHCP_CLIENT_IDENTIFIER = 61 */
+  if ((ptr = getenv("serial")))
+  {
+    *e++ = 61;
+    *e++ = strlen(ptr) + 1;
+    *e++ = 0;			/* HW type */
+    while (*ptr)
+      *e++ = *ptr++;
+  }
+
+  return e;
+}
+
+
+/* ------------------------------------------------------------------------- */
+u8 *dhcp_vendorex_proc(u8 * popt)
+{
+  return NULL;
+}
+#endif /* (CONFIG_BOOTP_MASK & CONFIG_BOOTP_VENDOREX) */
diff -purN OLD/board/i3micro/mood300/sysflash.h NEW/board/i3micro/mood300/sysflash.h
--- OLD/board/i3micro/mood300/sysflash.h	Thu Jan  1 01:00:00 1970
+++ NEW/board/i3micro/mood300/sysflash.h	Thu Nov 24 13:50:11 2005
@@ -0,0 +1,44 @@
+/*
+ * sysflash.h
+ * 
+ * Definitions for the flash system area
+ * Author: Kjell Christenson
+ * Modified for u-boot by Leif Lindholm
+ * (c) i3 Micro Technology AB, 2002
+ *
+ */
+
+#define MAIN_PARAM_AREA   0xbfc30000	/* main area, used if it's CRC is OK */
+#define SYSDEF_PARAM_AREA 0xbfc40000	/* system default area, used if main is bad */
+
+#define PARAM_SIZE	(64*1024)	/* size of the two parameter areas */
+#define FSA_MAGIC	0x46736131	/* magic word: Fsa1 (Flash System Area v1) */
+#define CRC_KEY         0x04c11db7
+
+struct flash_system_area
+{
+  union
+  {
+    struct
+    {
+      /* ------------------------------------------------ */
+      unsigned char mac[6];
+      unsigned char product_id[13];
+      unsigned char serial[11];
+      /* ------------------------------------------------ */
+      unsigned char settings[746];
+      unsigned char vendorclassid[30];	/* Override dhcp request option 60 with this string */
+      unsigned char savefile[PARAM_SIZE - 806 - 8];
+      unsigned char check[8];
+    }
+    param;
+    struct
+    {
+      unsigned char filler[PARAM_SIZE - 8];	/* filler to place checksum last in area */
+      unsigned int magic;	/* magic number */
+      unsigned char checksum[4];	/* crc checksum */
+    }
+    check;
+  }
+  rom;
+};
diff -purN OLD/board/i3micro/mood300/u-boot.lds NEW/board/i3micro/mood300/u-boot.lds
--- OLD/board/i3micro/mood300/u-boot.lds	Thu Jan  1 01:00:00 1970
+++ NEW/board/i3micro/mood300/u-boot.lds	Thu Nov 24 13:50:11 2005
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
+*/
+OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradbigmips",
+	      "elf32-tradlittlemips") OUTPUT_ARCH(mips) ENTRY(_start) SECTIONS
+{
+  . = 0x00000000;
+
+  . = ALIGN(4);
+.text:
+  {
+  *(.text)}
+
+  . = ALIGN(4);
+.rodata:{
+  *(.rodata)}
+
+  . = ALIGN(4);
+.data:{
+  *(.data)}
+
+  . = ALIGN(4);
+.sdata:{
+  *(.sdata)}
+
+  _gp = ALIGN(16);
+
+  __got_start =.;
+.got:{
+  *(.got)}
+  __got_end =.;
+
+.sdata:{
+  *(.sdata)}
+
+  . =.;
+  __u_boot_cmd_start =.;
+.u_boot_cmd:{
+  *(.u_boot_cmd)}
+  __u_boot_cmd_end =.;
+
+  uboot_end_data =.;
+  num_got_entries = (__got_end - __got_start) >> 2;
+
+  . = ALIGN(4);
+.sbss:{
+  *(.sbss)}
+.bss:{
+  *(.bss)}
+  uboot_end =.;
+}
diff -purN OLD/cpu/mips/config.mk NEW/cpu/mips/config.mk
--- OLD/cpu/mips/config.mk	Tue Nov 15 11:36:37 2005
+++ NEW/cpu/mips/config.mk	Thu Nov 17 16:41:37 2005
@@ -21,7 +21,7 @@
 # MA 02111-1307 USA
 #
 v=$(shell \
-mips-linux-as --version|grep "GNU assembler"|awk '{print $$3}'|awk -F . '{print $$2}')
+$(CROSS_COMPILE)as --version|grep "GNU assembler"|awk '{print $$3}'|awk -F . '{print $$2}')
 MIPSFLAGS=$(shell \
 if [ "$v" -lt "14" ]; then \
 	echo "-mcpu=4kc"; \
@@ -32,7 +32,9 @@ fi)
 ifneq (,$(findstring 4KCle,$(CROSS_COMPILE)))
 ENDIANNESS = -EL
 else
+ifeq (,$(findstring mipsel,$(CROSS_COMPILE))) # mipsel does not support -EL?
 ENDIANNESS = -EB
+endif
 endif
 
 MIPSFLAGS += $(ENDIANNESS) -mabicalls
diff -purN OLD/cpu/mips/cpu.c NEW/cpu/mips/cpu.c
--- OLD/cpu/mips/cpu.c	Tue Nov 15 11:36:37 2005
+++ NEW/cpu/mips/cpu.c	Tue Nov 15 16:33:52 2005
@@ -30,7 +30,7 @@ int do_reset(cmd_tbl_t *cmdtp, int flag,
 {
 #if defined(CONFIG_INCA_IP)
 	*INCA_IP_WDT_RST_REQ = 0x3f;
-#elif defined(CONFIG_PURPLE) || defined(CONFIG_TB0229)
+#elif defined(CONFIG_PURPLE) || defined(CONFIG_TB0229) || defined(CONFIG_I3_MOOD300)
 	void (*f)(void) = (void *) 0xbfc00000;
 
 	f();
diff -purN OLD/include/configs/mood300.h NEW/include/configs/mood300.h
--- OLD/include/configs/mood300.h	Thu Jan  1 01:00:00 1970
+++ NEW/include/configs/mood300.h	Thu Nov 24 13:47:12 2005
@@ -0,0 +1,203 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This file contains the configuration parameters for the dbau1x00 board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MIPS32		1	/* MIPS32 CPU core   */
+#define CONFIG_DBAU1X00		1
+#define CONFIG_AU1X00		1	/* alchemy series cpu */
+
+#ifdef CONFIG_I3_MOOD300
+#define CONFIG_AU1550
+#else
+#error "Invalid board type"
+#endif
+
+#define CONFIG_OVERWRITE_ETHADDR_ONCE 1	/* FIXME */
+
+#define CONFIG_ETHADDR		DE:AD:BE:EF:01:01	/* Ethernet address */
+
+#define CONFIG_BOOTDELAY	1	/* autoboot after 1 second      */
+
+#define CONFIG_BAUDRATE		115200
+
+/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define	CONFIG_TIMESTAMP	/* Print image info with timestamp */
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"addmisc=setenv bootargs $(bootargs) "				\
+		"console=ttyS0,$(baudrate) "				\
+		"panic=1\0"						\
+	"load=tftp 80500000 $(u-boot)\0"				\
+	""
+/* Boot from NOR flash as default, revert to bootp/tftp */
+#define CONFIG_BOOTCOMMAND	"nboot 0x81000000 0; bootm; dhcp; bootm"
+
+#define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_VENDOREX)
+
+#define CONFIG_COMMANDS		((CONFIG_CMD_DFL | \
+                                  CFG_CMD_FLASH  | \
+                                  CFG_CMD_LOADB  | \
+                                  CFG_CMD_DHCP  | \
+				  CFG_CMD_NAND | \
+				  CFG_CMD_NET) &			\
+				 ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FPGA | CFG_CMD_IDE | \
+				   CFG_CMD_MII | CFG_CMD_RUN | \
+				   CFG_CMD_BDI | CFG_CMD_BEDBUG | CFG_CMD_NFS | CFG_CMD_ELF | \
+				   CFG_CMD_PCMCIA | CFG_CMD_I2C | CFG_CMD_LOADS))
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP		/* undef to save memory      */
+
+#define CFG_PROMPT              "Mood 300 # "	/* Monitor Command Prompt    */
+
+#define	CFG_CBSIZE		256	/* Console I/O Buffer Size   */
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define	CFG_MAXARGS		16	/* max number of command args */
+
+#define CFG_MALLOC_LEN		128*1024
+
+#define CFG_BOOTPARAMS_LEN	128*1024
+
+#define CFG_MHZ			324
+
+#if (CFG_MHZ % 12) != 0
+#error "Invalid CPU frequency - must be multiple of 12!"
+#endif
+
+#define CFG_HZ                  (CFG_MHZ * 1000000)	/* FIXME causes overflow in net.c */
+
+#define CFG_SDRAM_BASE		0x80000000	/* Cached addr */
+
+#define	CFG_LOAD_ADDR		0x81000000	/* default load address  */
+
+#define CFG_MEMTEST_START	0x80100000
+#define CFG_MEMTEST_END		0x80800000
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CFG_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
+
+#define PHYS_FLASH		0xbfc00000	/* Flash Bank #2 */
+
+#define CFG_FLASH_CFI           1
+#define CFG_FLASH_CFI_DRIVER    1
+
+/* The following #defines are needed to get flash environment right */
+#define	CFG_MONITOR_BASE	TEXT_BASE
+#define	CFG_MONITOR_LEN		(320 << 10)
+
+#define CFG_INIT_SP_OFFSET	0x400000
+
+/* We boot from this flash, selected with dip switch */
+#define CFG_FLASH_BASE		PHYS_FLASH
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(2 * CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(2 * CFG_HZ)	/* Timeout for Flash Write */
+
+#define	CFG_ENV_IS_NOWHERE	1
+
+/* Address and size of Primary Environment Sector	*/
+#define CFG_ENV_ADDR		0xB0030000
+#define CFG_ENV_SIZE		0x10000
+
+#define CONFIG_FLASH_16BIT
+
+/*-----------------------------------------------------------------------
+ * NAND flash support
+ */
+
+/* NAND stuff */
+#define MEM_STNDCTL   0xB4001100
+#define MEM_STSTAT    0xB4001104
+
+#define NAND_PHYS_ADDR 0xBFB00000
+
+#define NAND_CMD_REG  (0x00)
+#define NAND_ADDR_REG (0x04)
+#define NAND_DATA_REG (0x20)
+
+#define CFG_MAX_NAND_DEVICE     1
+
+#define SECTORSIZE              512
+#define ADDR_COLUMN             1
+#define ADDR_PAGE               2
+#define ADDR_COLUMN_PAGE        3
+#define NAND_ChipID_UNKNOWN     0x00
+#define NAND_MAX_FLOORS         1
+#define NAND_MAX_CHIPS          1
+
+#define WRITE_NAND_ADDRESS(d, adr)      au1550_write_nand_address(d, adr)
+#define WRITE_NAND_COMMAND(d, adr)      au1550_write_nand_command(d, adr)
+#define WRITE_NAND(d, adr)              au1550_write_nand_data(d, adr)
+#define READ_NAND(adr)                  au1550_read_nand_data(adr)
+#define NAND_WAIT_READY(nand)           au1550_wait_nand_ready(nand)
+#define NAND_DISABLE_CE(nand)           au1550_nand_disable_ce(nand)
+#define NAND_ENABLE_CE(nand)            au1550_nand_enable_ce(nand)
+
+#define NAND_CTL_CLRALE(nandptr)	/* nop */
+#define NAND_CTL_SETALE(nandptr)	/* nop */
+#define NAND_CTL_CLRCLE(nandptr)	/* nop */
+#define NAND_CTL_SETCLE(nandptr)	/* nop */
+
+/* Uncomment the line below to enable the UNSAFE parts of the NAND
+ * support. NEVER USE FOR RELEASE - ONLY FOR DEBUG!
+ */
+/* #define CONFIG_MTD_NAND_UNSAFE */
+
+/*---------------------------------------------------------------------*/
+
+#define CONFIG_NR_DRAM_BANKS	2
+
+#define CONFIG_NET_MULTI
+
+#define MEM_SIZE 128
+
+#define CONFIG_MEMSIZE_IN_BYTES
+
+#define CONFIG_MISC_INIT_R
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE		16384
+#define CFG_ICACHE_SIZE		16384
+#define CFG_CACHELINE_SIZE	32
+
+#define DB1000_BCSR_ADDR 0xAE000000
+
+#endif /* __CONFIG_H */
diff -purN OLD/include/linux/mtd/nand.h NEW/include/linux/mtd/nand.h
--- OLD/include/linux/mtd/nand.h	Tue Nov 15 11:36:38 2005
+++ NEW/include/linux/mtd/nand.h	Thu Nov 24 13:30:13 2005
@@ -130,6 +130,7 @@ struct nand_chip {
  */
 #define NAND_MFR_TOSHIBA	0x98
 #define NAND_MFR_SAMSUNG	0xec
+#define NAND_MFR_STMICRO	0x20
 
 /*
  * NAND Flash Device ID Structure
diff -purN OLD/lib_mips/board.c NEW/lib_mips/board.c
--- OLD/lib_mips/board.c	Tue Nov 15 11:36:38 2005
+++ NEW/lib_mips/board.c	Mon Nov 21 18:33:22 2005
@@ -29,6 +29,10 @@
 #include <net.h>
 #include <environment.h>
 
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+void nand_init (void);
+#endif
+
 #if ( ((CFG_ENV_ADDR+CFG_ENV_SIZE) < CFG_MONITOR_BASE) || \
       (CFG_ENV_ADDR >= (CFG_MONITOR_BASE + CFG_MONITOR_LEN)) ) || \
     defined(CFG_ENV_IS_IN_NVRAM)
@@ -368,6 +372,11 @@ void board_init_r (gd_t *id, ulong dest_
 	mem_malloc_init();
 	malloc_bin_reloc();
 
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+        puts ("NAND:");
+        nand_init();            /* go init the NAND */
+#endif
+
 	/* relocate environment function pointers etc. */
 	env_relocate();
 