Update the GW74xx PMIC configuration: - increase VDD_SOC DVS1 to 0.85V per datasheet - increase VDD_SOC DVS0 to 0.95V before first DRAM access - increase VDD_ARM DVS0 to 0.95V to support kernel overdrive voltage (OD) - remove unnecessary changes to VDD_DRAM as we don't use 3GHz DRAM - remove unnecessary change to LDO2 as it is unused
Signed-off-by: Tim Harvey tharvey@gateworks.com v2: update commit log with more detail --- board/gateworks/venice/spl.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c index 56a985ed668f..98931c04754e 100644 --- a/board/gateworks/venice/spl.c +++ b/board/gateworks/venice/spl.c @@ -156,17 +156,15 @@ static int power_init_board(void) /* Buck 1 DVS control through PMIC_STBY_REQ */ dm_i2c_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
- /* Set DVS1 to 0.8v for suspend */ - dm_i2c_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x10); + /* Set DVS1 to 0.85v for suspend */ + dm_i2c_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
- /* increase VDD_DRAM to 0.95v for 3Ghz DDR */ - dm_i2c_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1C); + /* increase VDD_SOC to 0.95V before first DRAM access */ + dm_i2c_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C);
- /* VDD_DRAM off in suspend: B1_ENMODE=10 */ - dm_i2c_reg_write(dev, PCA9450_BUCK3CTRL, 0x4a); - - /* set VDD_SNVS_0V8 from default 0.85V */ - dm_i2c_reg_write(dev, PCA9450_LDO2CTRL, 0xC0); + /* Kernel uses OD/OD freq for SOC */ + /* To avoid timing risk from SOC to ARM, increase VDD_ARM to OD voltage 0.95v */ + dm_i2c_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C);
/* set WDOG_B_CFG to cold reset */ dm_i2c_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);