On Wed, Jan 16, 2013 at 01:14:03PM -0800, Tom Warren wrote:
This provides SPL support for T114 boards - AVP early init, plus CPU (A15) init/jump to main U-Boot.
Signed-off-by: Tom Warren twarren@nvidia.com
arch/arm/cpu/arm720t/tegra-common/cpu.c | 23 ++- arch/arm/cpu/arm720t/tegra-common/cpu.h | 13 +- arch/arm/cpu/arm720t/tegra114/Makefile | 42 ++++ arch/arm/cpu/arm720t/tegra114/config.mk | 19 ++ arch/arm/cpu/arm720t/tegra114/cpu.c | 328 +++++++++++++++++++++++++++++++ 5 files changed, 411 insertions(+), 14 deletions(-) create mode 100644 arch/arm/cpu/arm720t/tegra114/Makefile create mode 100644 arch/arm/cpu/arm720t/tegra114/config.mk create mode 100644 arch/arm/cpu/arm720t/tegra114/cpu.c
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c index 693d584..846163c 100644 --- a/arch/arm/cpu/arm720t/tegra-common/cpu.c +++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c @@ -40,7 +40,7 @@ enum tegra_family_t get_family(void) chip_id = reg >> 8; chip_id &= 0xff; debug(" tegra_get_family: chip_id = %x\n", chip_id);
if (chip_id == 0x30)
if (chip_id >= 0x30)
Should this be CHIPID_TEGRA30? And it would probably be better to do:
if (chipid == CHIPID_TEGRA30 || chipid == CHIPID_TEGRA114) return TEGRA_FAMILY_T3x; else if (chipid == CHIPID_TEGRA20) return TEGRA_FAMILY_T2x; else fail;
That forces the person doing the support for the next tegra chip to have to make a conscious decision about what to do here.
return TEGRA_FAMILY_T3x; else return TEGRA_FAMILY_T2x;@@ -56,6 +56,7 @@ int get_num_cpus(void) */ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { /* T20: 1 GHz */
/* n, m, p, cpcon */ {{ 1000, 13, 0, 12}, /* OSC 13M */ { 625, 12, 0, 8}, /* OSC 19.2M */ { 1000, 12, 0, 12}, /* OSC 12M */@@ -76,11 +77,11 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { { 700, 13, 0, 8}, },
/* TEGRA_SOC2_SLOW: 312 MHz */{{ 312, 13, 0, 12}, /* OSC 13M */{ 260, 16, 0, 8}, /* OSC 19.2M */{ 312, 12, 0, 12}, /* OSC 12M */{ 312, 26, 0, 12}, /* OSC 26M */
Removing TEGRA_SOC2_SLOW should probably be a separate patch, since it doesn't hae anything to do with t114.
/* T114: 1.4 GHz */{{ 862, 8, 0, 8},{ 583, 8, 0, 4},{ 696, 12, 0, 8},{ 700, 13, 0, 8}, },};
@@ -166,8 +167,8 @@ void init_pllx(void) sel = &tegra_pll_x_table[chip_type][osc]; pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
/* adjust PLLP_out1-4 on T30 */if (chip_type == TEGRA_SOC_T30) {
/* adjust PLLP_out1-4 on T30/T114 */if (chip_type >= TEGRA_SOC_T30) {
same comment here about >= T30
debug(" init_pllx: adjusting PLLP out freqs\n"); adjust_pllp_out_freqs(); }@@ -203,7 +204,7 @@ void enable_cpu_clock(int enable) */ clk = readl(&clkrst->crc_clk_cpu_cmplx); clk |= 1 << CPU1_CLK_STP_SHIFT; -#if defined(CONFIG_TEGRA30) +#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
Can this be runtime instead of #ifdef?
clk |= 1 << CPU2_CLK_STP_SHIFT; clk |= 1 << CPU3_CLK_STP_SHIFT;#endif @@ -308,7 +309,7 @@ void clock_enable_coresight(int enable) * Clock divider request for 204MHz would setup CSITE clock as * 144MHz for PLLP base 216MHz and 204MHz for PLLP base 408MHz */
if (tegra_get_chip_type() == TEGRA_SOC_T30)
if (tegra_get_chip_type() >= TEGRA_SOC_T30)
same comment here about >= T30
src = CLK_DIVIDER(NVBL_PLLP_KHZ, 204000); else src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);@@ -318,7 +319,7 @@ void clock_enable_coresight(int enable) rst = CORESIGHT_UNLOCK; writel(rst, CSITE_CPU_DBG0_LAR); writel(rst, CSITE_CPU_DBG1_LAR); -#if defined(CONFIG_TEGRA30) +#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
same comment here about runtime vs ifdef
writel(rst, CSITE_CPU_DBG2_LAR); writel(rst, CSITE_CPU_DBG3_LAR);#endif diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.h b/arch/arm/cpu/arm720t/tegra-common/cpu.h index 3e2ea3a..45b346d 100644 --- a/arch/arm/cpu/arm720t/tegra-common/cpu.h +++ b/arch/arm/cpu/arm720t/tegra-common/cpu.h @@ -22,14 +22,21 @@ */ #include <asm/types.h>
+#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif
u-boot seems a little inconsistent here, but it looks like most of u-boot uses C99 "true" and "false"
/* Stabilization delays, in usec */ #define PLL_STABILIZATION_DELAY (300) #define IO_STABILIZATION_DELAY (1000)
-#if defined(CONFIG_TEGRA30) -#define NVBL_PLLP_KHZ (408000) -#else /* Tegra20 */ +#if defined(CONFIG_TEGRA20) #define NVBL_PLLP_KHZ (216000) +#else /* Tegra30/Tegra114 */ +#define NVBL_PLLP_KHZ (408000) #endif
Again here it's probably better to explicitly do:
#if defined(CONFIG_TEGRA20) ... #elsif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) ... #else #error "unknown tegra chip" #endif
Or better yet, make it runtime if possible.
/* Set polarity to 0 (normal) and enable CPUPWRREQ_OE */reg = readl(&pmc->pmc_cntrl);reg &= ~(CPUPWRREQ_POL);reg |= CPUPWRREQ_OE;writel(reg, &pmc->pmc_cntrl);
clrsetbits_le32() instead?
/** Set CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2_0_CAR2PMC_CPU_ACK_WIDTH* to 408 to satisfy the requirement of having at least 16 CPU clock* cycles before clamp removal.*/reg = readl(&clkrst->crc_cpu_softrst_ctrl2);reg &= 0xFFFFF000; /* bits 11:0 */reg |= 408;writel(reg, &clkrst->crc_cpu_softrst_ctrl2);
clrsetbits_le32() instead?
val = (0 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) |(1 << CLK_SYS_RATE_AHB_RATE_SHIFT) |(0 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT) |(0 << CLK_SYS_RATE_APB_RATE_SHIFT);
Remove the 0's?
writel(val, &clkrst->crc_clk_sys_rate);
-Allen