From: Tom Warren twarren.nvidia@gmail.com
Some clock sources have 3-bit muxes in bits 31:29. Implement core support for this mux field.
Signed-off-by: Tom Warren twarren@nvidia.com [swarren, extracted from a larger patch by Tom] Signed-off-by: Stephen Warren swarren@nvidia.com --- arch/arm/cpu/tegra-common/clock.c | 22 ++++++++++++++++++---- arch/arm/include/asm/arch-tegra/clk_rst.h | 3 +++ 2 files changed, 21 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/tegra-common/clock.c b/arch/arm/cpu/tegra-common/clock.c index 96b705f2f6a4..33bb19084b8c 100644 --- a/arch/arm/cpu/tegra-common/clock.c +++ b/arch/arm/cpu/tegra-common/clock.c @@ -304,13 +304,27 @@ static int adjust_periph_pll(enum periph_id periph_id, int source, /* work out the source clock and set it */ if (source < 0) return -1; - if (mux_bits == MASK_BITS_31_28) { - clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK, - source << OUT_CLK_SOURCE_31_28_SHIFT); - } else { + + switch (mux_bits) { + case MASK_BITS_31_30: clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK, source << OUT_CLK_SOURCE_31_30_SHIFT); + break; + + case MASK_BITS_31_29: + clrsetbits_le32(reg, OUT_CLK_SOURCE_31_29_MASK, + source << OUT_CLK_SOURCE_31_29_SHIFT); + break; + + case MASK_BITS_31_28: + clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK, + source << OUT_CLK_SOURCE_31_28_SHIFT); + break; + + default: + return -1; } + udelay(2); return 0; } diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h index 9f81237d2865..f07b83d26af4 100644 --- a/arch/arm/include/asm/arch-tegra/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra/clk_rst.h @@ -236,6 +236,9 @@ enum { #define OUT_CLK_SOURCE_31_30_SHIFT 30 #define OUT_CLK_SOURCE_31_30_MASK (3U << OUT_CLK_SOURCE_31_30_SHIFT)
+#define OUT_CLK_SOURCE_31_29_SHIFT 29 +#define OUT_CLK_SOURCE_31_29_MASK (7U << OUT_CLK_SOURCE_31_29_SHIFT) + /* Note: See comment for MASK_BITS_31_28 in arch-tegra/clock.h */ #define OUT_CLK_SOURCE_31_28_SHIFT 28 #define OUT_CLK_SOURCE_31_28_MASK (15U << OUT_CLK_SOURCE_31_28_SHIFT)