On 11/21/19 11:08 AM, Tan, Ley Foon wrote: [...]
Hi,
In case the SPL on Gen5 loads U-Boot from NAND, unreset the NAND IP explicitly in the platform code as the denali-spl driver is not aware of DM at all.
Signed-off-by: Marek Vasut marex@denx.de Cc: Chin Liang See chin.liang.see@intel.com Cc: Dalon Westergreen dwesterg@gmail.com Cc: Dinh Nguyen dinguyen@kernel.org Cc: Ley Foon Tan ley.foon.tan@intel.com Cc: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com Cc: Tien Fong Chee tien.fong.chee@intel.com
arch/arm/mach-socfpga/spl_gen5.c | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach- socfpga/spl_gen5.c index 47e63709ad..408e409375 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -138,6 +138,13 @@ void board_init_f(ulong dummy) if (ret) debug("Reset init failed: %d\n", ret);
+#ifdef CONFIG_SPL_NAND_DENALI
- struct socfpga_reset_manager *reset_manager_base =
(struct socfpga_reset_manager*)SOCFPGA_RSTMGR_ADDRESS;
- clrbits_le32(&reset_manager_base->per_mod_reset, BIT(4)); #endif
Normal Denali Nand driver (denali_dt_probe()) is not running in SPL Gen5?
Nope, I tried to put the whole MTD subsystem into SPL, but it just does not fit into the 64 kiB we have on Gen5. It does fit on A10 which has 256 kiB of OCRAM, but I can't easily replace the SoC here. Hence this denali-spl.
I am enabling NAND for Agilex recently, but didn't notice need to de-assert NAND reset outside of denali nand driver.
How much OCRAM does Agilex have again ? :-)