create_tlb1_entry and create_tlb0_entry creates TLB entries with IPROT bit set by default. Any TLB entries with IPROT = 1 can not be invalidated.
Add IPROT as input argument for TLB entry creation APIs.
Signed-off-by: Prabhakar Kushwaha prabhakar@freescale.com --- Based upon git://git.denx.de/u-boot.git branch master
arch/powerpc/cpu/mpc85xx/start.S | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 4f0480b..cbe166d 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -174,11 +174,11 @@ l2_disabled: mtspr DBSR,r1 /* Clear all valid bits */
- .macro create_tlb1_entry esel ts tsize epn wimg rpn perm phy_high scratch + .macro create_tlb1_entry esel iprot ts tsize epn wimg rpn perm phy_high scratch lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l mtspr MAS0, \scratch - lis \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@h + lis \scratch, FSL_BOOKE_MAS1(1, \iprot, 0, \ts, \tsize)@h ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@l mtspr MAS1, \scratch lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h @@ -196,11 +196,11 @@ l2_disabled: isync .endm
- .macro create_tlb0_entry esel ts tsize epn wimg rpn perm phy_high scratch + .macro create_tlb0_entry esel iprot ts tsize epn wimg rpn perm phy_high scratch lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l mtspr MAS0, \scratch - lis \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@h + lis \scratch, FSL_BOOKE_MAS1(1, \iprot, 0, \ts, \tsize)@h ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@l mtspr MAS1, \scratch lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h @@ -357,7 +357,7 @@ l2_disabled: */
/* create a temp mapping TLB0[0] for LBCR */ - create_tlb0_entry 0, \ + create_tlb0_entry 0, 1,\ 0, BOOKE_PAGESZ_4K, \ CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G, \ CONFIG_SYS_LBC_ADDR, MAS3_SW|MAS3_SR, \ @@ -484,14 +484,14 @@ nexti: mflr r1 /* R1 = our PC */ * bacause flash's virtual address maps to 0xff800000 - 0xffffffff. * and this window is outside of 4K boot window. */ - create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \ + create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, 0,\ 0, BOOKE_PAGESZ_4M, \ CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \ 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \ 0, r6
#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) - create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \ + create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, 0,\ 0, BOOKE_PAGESZ_1M, \ CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \ CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \ @@ -501,7 +501,7 @@ nexti: mflr r1 /* R1 = our PC */ * TLB entry is created for IVPR + IVOR15 to map on valid OP code address * because "nexti" will resize TLB to 4K */ - create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \ + create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, 0,\ 0, BOOKE_PAGESZ_256K, \ CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS2_I, \ CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS3_SX|MAS3_SW|MAS3_SR, \ @@ -536,7 +536,7 @@ create_ccsr_new_tlb: ori r8, r8, CONFIG_SYS_CCSRBAR@l lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l - create_tlb0_entry 0, \ + create_tlb0_entry 0, 1,\ 0, BOOKE_PAGESZ_4K, \ CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, \ CONFIG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \ @@ -546,7 +546,7 @@ create_ccsr_new_tlb: * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000). */ create_ccsr_old_tlb: - create_tlb0_entry 1, \ + create_tlb0_entry 1, 1,\ 0, BOOKE_PAGESZ_4K, \ CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \ CONFIG_SYS_CCSRBAR_DEFAULT, MAS3_SW|MAS3_SR, \ @@ -712,7 +712,7 @@ create_ccsr_l2_tlb: * Create a TLB for the MMR location of CCSR * to access L2CSR0 register */ - create_tlb0_entry 0, \ + create_tlb0_entry 0, 1\ 0, BOOKE_PAGESZ_4K, \ CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \ CONFIG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \ @@ -1041,7 +1041,7 @@ create_init_ram_area:
#ifdef NOR_BOOT /* create a temp mapping in AS=1 to the 4M boot window */ - create_tlb1_entry 15, \ + create_tlb1_entry 15, 1,\ 1, BOOKE_PAGESZ_4M, \ CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \ 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \ @@ -1051,7 +1051,7 @@ create_init_ram_area: /* create a temp mapping in AS = 1 for Flash mapping * created by PBL for ISBC code */ - create_tlb1_entry 15, \ + create_tlb1_entry 15, 1,\ 1, BOOKE_PAGESZ_1M, \ CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \ CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ @@ -1061,7 +1061,7 @@ create_init_ram_area: * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage. */ - create_tlb1_entry 15, \ + create_tlb1_entry 15, 1,\ 1, BOOKE_PAGESZ_1M, \ CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \ CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ @@ -1071,14 +1071,14 @@ create_init_ram_area: /* create a temp mapping in AS=1 to the stack */ #if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \ defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH) - create_tlb1_entry 14, \ + create_tlb1_entry 14, 1,\ 1, BOOKE_PAGESZ_16K, \ CONFIG_SYS_INIT_RAM_ADDR, 0, \ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \ CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6
#else - create_tlb1_entry 14, \ + create_tlb1_entry 14, 1,\ 1, BOOKE_PAGESZ_16K, \ CONFIG_SYS_INIT_RAM_ADDR, 0, \ CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \