From: T Karthik Reddy t.karthik.reddy@xilinx.com
In DDR mode, current default spi_mem_dtr_supports_op() function does not allow mixed DTR operation functionality. So implement cadence specific cadence_spi_mem_dtr_supports_op() function to verifying only the command buswidth and command opcode bytes which satisfies the DTR protocol.
Signed-off-by: T Karthik Reddy t.karthik.reddy@xilinx.com Signed-off-by: Tejas Bhumkar tejas.arvind.bhumkar@amd.com --- drivers/spi/cadence_qspi.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 710c4a532d..282028c845 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -718,6 +718,21 @@ static int cadence_spi_mem_exec_op(struct spi_slave *spi, return err; }
+static bool cadence_spi_mem_dtr_supports_op(struct spi_slave *slave, + const struct spi_mem_op *op) +{ + /* + * In DTR mode, except op->cmd all other parameters like address, + * dummy and data could be 0. + * So lets only check if the cmd buswidth and number of opcode bytes + * are true for DTR to support. + */ + if (op->cmd.buswidth == 8 && op->cmd.nbytes % 2) + return false; + + return true; +} + static bool cadence_spi_mem_supports_op(struct spi_slave *slave, const struct spi_mem_op *op) { @@ -740,7 +755,7 @@ static bool cadence_spi_mem_supports_op(struct spi_slave *slave, return false;
if (all_true) - return spi_mem_dtr_supports_op(slave, op); + return cadence_spi_mem_dtr_supports_op(slave, op); else return spi_mem_default_supports_op(slave, op); }