Hi Marek,
On 11/26/19 1:34 AM, Marek Vasut wrote:
This patch adds support for iMX6SX MMDC into the DDR calibration code. The only difference between MX6DQ and MX6SX is that the SX has 2 SDQS registers, while the DQ has 8.
Signed-off-by: Marek Vasut marex@denx.de Cc: Eric Nelson eric@nelint.com Cc: Fabio Estevam fabio.estevam@nxp.com Cc: Stefano Babic sbabic@denx.de
arch/arm/mach-imx/mx6/ddr.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-imx/mx6/ddr.c b/arch/arm/mach-imx/mx6/ddr.c index b2402f75db..8ed8b79c8b 100644 --- a/arch/arm/mach-imx/mx6/ddr.c +++ b/arch/arm/mach-imx/mx6/ddr.c @@ -247,12 +247,22 @@ int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo)
static void mmdc_set_sdqs(bool set) {
- struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux =
- struct mx6dq_iomux_ddr_regs *mx6dq_ddr_iomux = (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
- u32 sdqs = (u32)(&mx6_ddr_iomux->dram_sdqs0);
- int i;
- struct mx6sx_iomux_ddr_regs *mx6sx_ddr_iomux =
(struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE;- int i, sdqs_cnt;
- u32 sdqs;
- if (is_mx6sx()) {
sdqs = (u32)(&mx6sx_ddr_iomux->dram_sdqs0);sdqs_cnt = 2;- } else { /* MX6DQ */
sdqs = (u32)(&mx6dq_ddr_iomux->dram_sdqs0);sdqs_cnt = 8;- }
- for (i = 0; i < 8; i++) {
- for (i = 0; i < sdqs_cnt; i++) { if (set) setbits_le32(sdqs + (4 * i), 0x7000); else
Reviewed-by: Eric Nelson eric@nelint.com