Re: [U-Boot] [PATCH v3 5/7] riscv: ax25: Andes specific cache shall only support in M-mode

On Mon, 2019-04-01 at 16:24 +0800, Andes wrote:

From: Rick Chen rick@andestech.com

Limit the cache configuration only can be supported in M mode. It can not be manipulated in S mode.

Signed-off-by: Rick Chen rick@andestech.com Cc: Greentime Hu greentime@andestech.com Reviewed-by: Bin Meng bmeng.cn@gmail.com

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arch/riscv/cpu/ax25/Kconfig | 1 + 1 file changed, 1 insertion(+)

Reviewed-by: Lukas Auer lukas.auer@aisec.fraunhofer.de