On 03.02.2019 00:02, Lukasz Majewski wrote:
Provide function to enable I2C clocks for vf610 - in the generic code. This function overrides the default weak function implementation (which only returns 1).
Signed-off-by: Lukasz Majewski lukma@denx.de
Reviewed-by: Stefan Agner stefan.agner@toradex.com
-- Stefan
Changes in v3:
- Add code to enable I2C0 code as suggested by Stefan (so the code can be reused by other boards without regressions)
- Exclude the pcm052.c related code to a separate patch
Changes in v2: None
arch/arm/cpu/armv7/vf610/generic.c | 22 ++++++++++++++++++++++ arch/arm/include/asm/arch-vf610/clock.h | 3 +++ 2 files changed, 25 insertions(+)
diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c index cbd3391918..e0c0b1bcb0 100644 --- a/arch/arm/cpu/armv7/vf610/generic.c +++ b/arch/arm/cpu/armv7/vf610/generic.c @@ -375,3 +375,25 @@ void enable_caches(void) mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR, IRAM_SIZE, option); } #endif
+#ifdef CONFIG_SYS_I2C_MXC +/* i2c_num can be from 0 - 3 */ +int enable_i2c_clk(unsigned char enable, unsigned int i2c_num) +{
- struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
- switch (i2c_num) {
- case 0:
clrsetbits_le32(&ccm->ccgr4, CCM_CCGR4_I2C0_CTRL_MASK,CCM_CCGR4_I2C0_CTRL_MASK);- case 2:
clrsetbits_le32(&ccm->ccgr10, CCM_CCGR10_I2C2_CTRL_MASK,CCM_CCGR10_I2C2_CTRL_MASK);break;- default:
return -EINVAL;- }
- return 0;
+} +#endif diff --git a/arch/arm/include/asm/arch-vf610/clock.h b/arch/arm/include/asm/arch-vf610/clock.h index 3bd73a01f3..72184fd608 100644 --- a/arch/arm/include/asm/arch-vf610/clock.h +++ b/arch/arm/include/asm/arch-vf610/clock.h @@ -22,6 +22,9 @@ enum mxc_clock { void enable_ocotp_clk(unsigned char enable); unsigned int mxc_get_clock(enum mxc_clock clk); u32 get_lpuart_clk(void); +#ifdef CONFIG_SYS_I2C_MXC +int enable_i2c_clk(unsigned char enable, unsigned int i2c_num); +#endif
#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK)