Add a clock driver for the MPC83xx architecture.
Signed-off-by: Mario Six mario.six@gdsys.cc ---
Notes: v3 -> v4: * Gotten rid of all #ifdefs (SoC is now determined by compatible string) * Added MPC83xx-wide functions to get properties of SoCs * Gotten rid of most clock variables in global data * Marked more files as static * Improved error handling and debug reporting * Simplified bitmask handling * Added binding file * Added full documentation
v2 -> v3: * Added driver files to MAINTAINERS
v1 -> v2: * Added binding of sysreset driver
.../devicetree/bindings/clk/fsl,mpc83xx-clk.txt | 23 ++ MAINTAINERS | 3 + arch/powerpc/cpu/mpc83xx/speed.c | 4 + arch/powerpc/include/asm/arch-mpc83xx/soc.h | 74 ++++ arch/powerpc/include/asm/config.h | 2 +- arch/powerpc/include/asm/global_data.h | 4 + drivers/clk/Kconfig | 6 + drivers/clk/Makefile | 1 + drivers/clk/mpc83xx_clk.c | 410 +++++++++++++++++++++ drivers/clk/mpc83xx_clk.h | 379 +++++++++++++++++++ include/dt-bindings/clk/mpc83xx-clk.h | 33 ++ 11 files changed, 938 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clk/fsl,mpc83xx-clk.txt create mode 100644 arch/powerpc/include/asm/arch-mpc83xx/soc.h create mode 100644 drivers/clk/mpc83xx_clk.c create mode 100644 drivers/clk/mpc83xx_clk.h create mode 100644 include/dt-bindings/clk/mpc83xx-clk.h
diff --git a/Documentation/devicetree/bindings/clk/fsl,mpc83xx-clk.txt b/Documentation/devicetree/bindings/clk/fsl,mpc83xx-clk.txt new file mode 100644 index 00000000000..8313da85076 --- /dev/null +++ b/Documentation/devicetree/bindings/clk/fsl,mpc83xx-clk.txt @@ -0,0 +1,23 @@ +MPC83xx system clock devices + +MPC83xx SoCs supply a variety of clocks to drive various components of a +system. + +Required properties: +- compatible: must be one of "fsl,mpc8308-clk", + "fsl,mpc8309-clk", + "fsl,mpc8313-clk", + "fsl,mpc8315-clk", + "fsl,mpc832x-clk", + "fsl,mpc8349-clk", + "fsl,mpc8360-clk", + "fsl,mpc8379-clk" + depending on which SoC is employed +- #clock-cells: Must be 1 + +Example: + +socclocks: clocks { + compatible = "fsl,mpc832x-clk"; + #clock-cells = <1>; +}; diff --git a/MAINTAINERS b/MAINTAINERS index 801e47897f6..7710989ea4f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -499,6 +499,9 @@ F: drivers/ram/mpc83xx_sdram.c F: include/dt-bindings/memory/mpc83xx-sdram.h F: drivers/sysreset/sysreset_mpc83xx.c F: drivers/sysreset/sysreset_mpc83xx.h +F: drivers/clk/mpc83xx_clk.c +F: drivers/clk/mpc83xx_clk.h +F: include/dt-bindings/clk/mpc83xx-clk.h F: arch/powerpc/cpu/mpc83xx/ F: arch/powerpc/include/asm/arch-mpc83xx/
diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index f0945281cd2..39bc1c53406 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -6,6 +6,8 @@ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. */
+#ifndef CONFIG_CLK_MPC83XX + #include <common.h> #include <mpc83xx.h> #include <command.h> @@ -590,3 +592,5 @@ U_BOOT_CMD(clocks, 1, 0, do_clocks, "print clock configuration", " clocks" ); + +#endif diff --git a/arch/powerpc/include/asm/arch-mpc83xx/soc.h b/arch/powerpc/include/asm/arch-mpc83xx/soc.h new file mode 100644 index 00000000000..39bf7d5a7f9 --- /dev/null +++ b/arch/powerpc/include/asm/arch-mpc83xx/soc.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2018 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + */ + +#ifndef _MPC83XX_SOC_H_ +#define _MPC83XX_SOC_H_ + +enum soc_type { + SOC_MPC8308, + SOC_MPC8309, + SOC_MPC8313, + SOC_MPC8315, + SOC_MPC832X, + SOC_MPC8349, + SOC_MPC8360, + SOC_MPC8379, +}; + +bool mpc83xx_has_sdhc(int type) +{ + return (type == SOC_MPC8308) || + (type == SOC_MPC8309) || + (type == SOC_MPC8379); +} + +bool mpc83xx_has_tsec(int type) +{ + return (type == SOC_MPC8308) || + (type == SOC_MPC8313) || + (type == SOC_MPC8315) || + (type == SOC_MPC8349) || + (type == SOC_MPC8379); +} + +bool mpc83xx_has_pcie1(int type) +{ + return (type == SOC_MPC8308) || + (type == SOC_MPC8315) || + (type == SOC_MPC8379); +} + +bool mpc83xx_has_pcie2(int type) +{ + return (type == SOC_MPC8315) || + (type == SOC_MPC8379); +} + +bool mpc83xx_has_sata(int type) +{ + return (type == SOC_MPC8315) || + (type == SOC_MPC8379); +} + +bool mpc83xx_has_pci(int type) +{ + return type != SOC_MPC8308; +} + +bool mpc83xx_has_second_i2c(int type) +{ + return (type != SOC_MPC8315) && + (type != SOC_MPC832X); +} + +bool mpc83xx_has_quicc_engine(int type) +{ + return (type == SOC_MPC8309) || + (type == SOC_MPC832X) || + (type == SOC_MPC8360); +} + +#endif /* _MPC83XX_SOC_H_ */ diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index bf11f40e231..849a69acedc 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -75,7 +75,7 @@ /* All PPC boards must swap IDE bytes */ #define CONFIG_IDE_SWAP_IO
-#if defined(CONFIG_DM_SERIAL) +#if defined(CONFIG_DM_SERIAL) && !defined(CONFIG_CLK_MPC83XX) /* * TODO: Convert this to a clock driver exists that can give us the UART * clock here. diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index 07d5beaf0e9..d00cee95fbb 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -30,6 +30,9 @@ struct arch_global_data { #endif /* TODO: sjg@chromium.org: Should these be unslgned long? */ #if defined(CONFIG_MPC83xx) +#ifdef CONFIG_CLK_MPC83XX + u32 core_clk; +#else /* There are other clocks in the MPC83XX */ u32 csb_clk; # if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ @@ -62,6 +65,7 @@ struct arch_global_data { u32 mem_sec_clk; # endif /* CONFIG_MPC8360 */ #endif +#endif #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) u32 lbc_clk; void *cpu; diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 18bf8a6d28b..65720a1a19a 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -99,4 +99,10 @@ config ICS8N3QV01 Crystal Oscillator). The output frequency can be programmed via an I2C interface.
+config CLK_MPC83XX + bool "Enable MPC83xx clock driver" + depends on CLK + help + Support for the clock driver of the MPC83xx series of SoCs. + endmenu diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 146283c7232..ae9c9373f5d 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o obj-$(CONFIG_CLK_BOSTON) += clk_boston.o obj-$(CONFIG_CLK_EXYNOS) += exynos/ obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o +obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o obj-$(CONFIG_CLK_OWL) += owl/ obj-$(CONFIG_CLK_RENESAS) += renesas/ obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o diff --git a/drivers/clk/mpc83xx_clk.c b/drivers/clk/mpc83xx_clk.c new file mode 100644 index 00000000000..489004190eb --- /dev/null +++ b/drivers/clk/mpc83xx_clk.c @@ -0,0 +1,410 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2017 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <dm/lists.h> +#include <dt-bindings/clk/mpc83xx-clk.h> +#include <asm/arch/soc.h> + +#include "mpc83xx_clk.h" + +DECLARE_GLOBAL_DATA_PTR; + +/** + * struct mpc83xx_clk_priv - Private data structure for the MPC83xx clock + * driver + * @speed: Array containing the speed values of all system clocks (initialized + * once, then only read back) + */ +struct mpc83xx_clk_priv { + u32 speed[MPC83XX_CLK_COUNT]; +}; + +/** + * is_clk_valid() - Check if clock ID is valid for given clock device + * @clk: The clock device for which to check a clock ID + * @id: The clock ID to check + * + * Return: true if clock ID is valid for clock device, false if not + */ +static inline bool is_clk_valid(struct udevice *clk, int id) +{ + ulong type = dev_get_driver_data(clk); + + switch (id) { + case MPC83XX_CLK_MEM: + return true; + case MPC83XX_CLK_MEM_SEC: + return type == SOC_MPC8360; + case MPC83XX_CLK_ENC: + return (type == SOC_MPC8308) || (type == SOC_MPC8309); + case MPC83XX_CLK_I2C1: + return true; + case MPC83XX_CLK_TDM: + return type == SOC_MPC8315; + case MPC83XX_CLK_SDHC: + return mpc83xx_has_sdhc(type); + case MPC83XX_CLK_TSEC1: + case MPC83XX_CLK_TSEC2: + return mpc83xx_has_tsec(type); + case MPC83XX_CLK_USBDR: + return type == SOC_MPC8360; + case MPC83XX_CLK_USBMPH: + return type == SOC_MPC8349; + case MPC83XX_CLK_PCIEXP1: + return mpc83xx_has_pcie1(type); + case MPC83XX_CLK_PCIEXP2: + return mpc83xx_has_pcie2(type); + case MPC83XX_CLK_SATA: + return mpc83xx_has_sata(type); + case MPC83XX_CLK_DMAC: + return (type == SOC_MPC8308) || (type == SOC_MPC8309); + case MPC83XX_CLK_PCI: + return mpc83xx_has_pci(type); + case MPC83XX_CLK_CSB: + return true; + case MPC83XX_CLK_I2C2: + return mpc83xx_has_second_i2c(type); + case MPC83XX_CLK_QE: + case MPC83XX_CLK_BRG: + return mpc83xx_has_quicc_engine(type) && (type != SOC_MPC8309); + case MPC83XX_CLK_LCLK: + case MPC83XX_CLK_LBIU: + case MPC83XX_CLK_CORE: + return true; + } + + return false; +} + +/** + * init_single_clk() - Initialize a clock with a given ID + * @dev: The clock device for which to initialize the clock + * @clk: The clock ID + * + * The clock speed is read from the hardware's registers, and stored in the + * private data structure of the driver. From there it is only retrieved, and + * not set. + * + * Return: 0 if OK, -ve on error + */ +static int init_single_clk(struct udevice *dev, int clk) +{ + struct mpc83xx_clk_priv *priv = dev_get_priv(dev); + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + ulong type = dev_get_driver_data(dev); + struct clk_mode mode; + ulong mask; + u32 csb_clk = get_csb_clk(im); + int ret; + + ret = retrieve_mode(clk, type, &mode); + if (ret) { + debug("%s: Could not retrieve mode for clk %d (ret = %d)\n", + dev->name, clk, ret); + return ret; + } + + if (mode.type == TYPE_INVALID) { + debug("%s: clock %d invalid\n", dev->name, clk); + return -EINVAL; + } + + if (mode.type == TYPE_SCCR_STANDARD) { + mask = GENMASK(31 - mode.low, 31 - mode.high); + + switch (sccr_field(im, mask)) { + case 0: + priv->speed[clk] = 0; + break; + case 1: + priv->speed[clk] = csb_clk; + break; + case 2: + priv->speed[clk] = csb_clk / 2; + break; + case 3: + priv->speed[clk] = csb_clk / 3; + break; + default: + priv->speed[clk] = 0; + } + + return 0; + } + + if (mode.type == TYPE_SPMR_DIRECT_MULTIPLY) { + mask = GENMASK(31 - mode.low, 31 - mode.high); + + priv->speed[clk] = csb_clk * (1 + sccr_field(im, mask)); + return 0; + } + + if (clk == MPC83XX_CLK_CSB || clk == MPC83XX_CLK_I2C2) { + priv->speed[clk] = csb_clk; /* i2c-2 clk is equal to csb clk */ + return 0; + } + + if (clk == MPC83XX_CLK_QE || clk == MPC83XX_CLK_BRG) { + u32 pci_sync_in = get_pci_sync_in(im); + u32 qepmf = spmr_field(im, SPMR_CEPMF); + u32 qepdf = spmr_field(im, SPMR_CEPDF); + u32 qe_clk = (pci_sync_in * qepmf) / (1 + qepdf); + + if (clk == MPC83XX_CLK_QE) + priv->speed[clk] = qe_clk; + else + priv->speed[clk] = qe_clk / 2; + + return 0; + } + + if (clk == MPC83XX_CLK_LCLK || clk == MPC83XX_CLK_LBIU) { + u32 lbiu_clk = csb_clk * + (1 + spmr_field(im, SPMR_LBIUCM)); + u32 clkdiv = lcrr_field(im, LCRR_CLKDIV); + + if (clk == MPC83XX_CLK_LBIU) + priv->speed[clk] = lbiu_clk; + + switch (clkdiv) { + case 2: + case 4: + case 8: + priv->speed[clk] = lbiu_clk / clkdiv; + break; + default: + /* unknown lcrr */ + priv->speed[clk] = 0; + } + + return 0; + } + + if (clk == MPC83XX_CLK_CORE) { + u8 corepll = spmr_field(im, SPMR_COREPLL); + u32 corecnf_tab_index = ((corepll & 0x1F) << 2) | + ((corepll & 0x60) >> 5); + + if (corecnf_tab_index > (ARRAY_SIZE(corecnf_tab))) { + debug("%s: Core configuration index %02x too high; possible wrong value", + dev->name, corecnf_tab_index); + return -EINVAL; + } + + switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) { + case RAT_BYP: + case RAT_1_TO_1: + priv->speed[clk] = csb_clk; + break; + case RAT_1_5_TO_1: + priv->speed[clk] = (3 * csb_clk) / 2; + break; + case RAT_2_TO_1: + priv->speed[clk] = 2 * csb_clk; + break; + case RAT_2_5_TO_1: + priv->speed[clk] = (5 * csb_clk) / 2; + break; + case RAT_3_TO_1: + priv->speed[clk] = 3 * csb_clk; + break; + default: + /* unknown core to csb ratio */ + priv->speed[clk] = 0; + } + + return 0; + } + + /* Unknown clk value -> error */ + debug("%s: clock %d invalid\n", dev->name, clk); + return -EINVAL; +} + +/** + * init_all_clks() - Initialize all clocks of a clock device + * @dev: The clock device whose clocks should be initialized + * + * Return: 0 if OK, -ve on error + */ +static inline int init_all_clks(struct udevice *dev) +{ + int i; + + for (i = 0; i < MPC83XX_CLK_COUNT; i++) { + int ret; + + if (!is_clk_valid(dev, i)) + continue; + + ret = init_single_clk(dev, i); + if (ret) { + debug("%s: Failed to initialize %s clock\n", + dev->name, names[i]); + return ret; + } + } + + return 0; +} + +static int mpc83xx_clk_request(struct clk *clock) +{ + /* Reject requests of clocks that are not available */ + if (is_clk_valid(clock->dev, clock->id)) + return 0; + else + return -ENODEV; +} + +static ulong mpc83xx_clk_get_rate(struct clk *clk) +{ + struct mpc83xx_clk_priv *priv = dev_get_priv(clk->dev); + + if (clk->id >= MPC83XX_CLK_COUNT) { + debug("%s: clock index %lu invalid\n", __func__, clk->id); + return 0; + } + + return priv->speed[clk->id]; +} + +int get_clocks(void) +{ + /* Empty implementation to keep the prototype in common.h happy */ + return 0; +} + +int get_serial_clock(void) +{ + struct mpc83xx_clk_priv *priv; + struct udevice *clk; + int ret; + + ret = uclass_first_device_err(UCLASS_CLK, &clk); + if (ret) { + debug("%s: Could not get clock device\n", __func__); + return ret; + } + + priv = dev_get_priv(clk); + + return priv->speed[MPC83XX_CLK_CSB]; +} + +const struct clk_ops mpc83xx_clk_ops = { + .request = mpc83xx_clk_request, + .get_rate = mpc83xx_clk_get_rate, +}; + +static const struct udevice_id mpc83xx_clk_match[] = { + { .compatible = "fsl,mpc8308-clk", .data = SOC_MPC8308 }, + { .compatible = "fsl,mpc8309-clk", .data = SOC_MPC8309 }, + { .compatible = "fsl,mpc8313-clk", .data = SOC_MPC8313 }, + { .compatible = "fsl,mpc8315-clk", .data = SOC_MPC8315 }, + { .compatible = "fsl,mpc832x-clk", .data = SOC_MPC832X }, + { .compatible = "fsl,mpc8349-clk", .data = SOC_MPC8349 }, + { .compatible = "fsl,mpc8360-clk", .data = SOC_MPC8360 }, + { .compatible = "fsl,mpc8379-clk", .data = SOC_MPC8379 }, + { /* sentinel */ } +}; + +static int mpc83xx_clk_probe(struct udevice *dev) +{ + struct mpc83xx_clk_priv *priv = dev_get_priv(dev); + ulong type; + int ret; + + ret = init_all_clks(dev); + if (ret) { + debug("%s: Could not initialize all clocks (ret = %d)\n", + dev->name, ret); + return ret; + } + + type = dev_get_driver_data(dev); + + if (mpc83xx_has_sdhc(type)) + gd->arch.sdhc_clk = priv->speed[MPC83XX_CLK_SDHC]; + + gd->arch.core_clk = priv->speed[MPC83XX_CLK_CORE]; + gd->arch.i2c1_clk = priv->speed[MPC83XX_CLK_I2C1]; + if (mpc83xx_has_second_i2c(type)) + gd->arch.i2c2_clk = priv->speed[MPC83XX_CLK_I2C2]; + + gd->mem_clk = priv->speed[MPC83XX_CLK_MEM]; + + if (mpc83xx_has_pci(type)) + gd->pci_clk = priv->speed[MPC83XX_CLK_PCI]; + + gd->cpu_clk = priv->speed[MPC83XX_CLK_CORE]; + gd->bus_clk = priv->speed[MPC83XX_CLK_CSB]; + + return 0; +} + +static int mpc83xx_clk_bind(struct udevice *dev) +{ + int ret; + struct udevice *sys_child; + + /* + * Since there is no corresponding device tree entry, and since the + * clock driver has to be present in either case, bind the sysreset + * driver here. + */ + ret = device_bind_driver(dev, "mpc83xx_sysreset", "sysreset", + &sys_child); + if (ret) + debug("%s: No sysreset driver: ret=%d\n", + dev->name, ret); + + return 0; +} + +U_BOOT_DRIVER(mpc83xx_clk) = { + .name = "mpc83xx_clk", + .id = UCLASS_CLK, + .of_match = mpc83xx_clk_match, + .ops = &mpc83xx_clk_ops, + .probe = mpc83xx_clk_probe, + .priv_auto_alloc_size = sizeof(struct mpc83xx_clk_priv), + .bind = mpc83xx_clk_bind, +}; + +static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int i; + char buf[32]; + struct udevice *clk; + int ret; + struct mpc83xx_clk_priv *priv; + + ret = uclass_first_device_err(UCLASS_CLK, &clk); + if (ret) { + debug("%s: Could not get clock device\n", __func__); + return ret; + } + + for (i = 0; i < MPC83XX_CLK_COUNT; i++) { + if (!is_clk_valid(clk, i)) + continue; + + priv = dev_get_priv(clk); + + printf("%s = %s MHz\n", names[i], strmhz(buf, priv->speed[i])); + } + + return 0; +} + +U_BOOT_CMD(clocks, 1, 1, do_clocks, + "display values of SoC's clocks", + "" +); diff --git a/drivers/clk/mpc83xx_clk.h b/drivers/clk/mpc83xx_clk.h new file mode 100644 index 00000000000..7fb88029204 --- /dev/null +++ b/drivers/clk/mpc83xx_clk.h @@ -0,0 +1,379 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2018 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + */ + +/** + * enum ratio - Description of a core clock ratio + * @RAT_UNK: Unknown ratio + * @RAT_BYP: Bypass + * @RAT_1_TO_8: Ratio 1:8 + * @RAT_1_TO_4: Ratio 1:4 + * @RAT_1_TO_2: Ratio 1:2 + * @RAT_1_TO_1: Ratio 1:1 + * @RAT_1_5_TO_1: Ratio 1.5:1 + * @RAT_2_TO_1: Ratio 2:1 + * @RAT_2_5_TO_1: Ratio 2.5:1 + * @RAT_3_TO_1: Ratio 3:1 + */ +enum ratio { + RAT_UNK, + RAT_BYP, + RAT_1_TO_8, + RAT_1_TO_4, + RAT_1_TO_2, + RAT_1_TO_1, + RAT_1_5_TO_1, + RAT_2_TO_1, + RAT_2_5_TO_1, + RAT_3_TO_1 +}; + +/** + * struct corecnf - Description for a core clock configuration + * @core_csb_ratio: Core clock frequency to CSB clock frequency ratio + * @vco_divider: VCO divider (Core VCO frequency = Core frequency * VCO divider) + */ +struct corecnf { + int core_csb_ratio; + int vco_divider; +}; + +/* + * Table with all valid Core CSB frequency ratio / VCO divider combinations as + * indexed by the COREPLL field of the SPMR + */ +static const struct corecnf corecnf_tab[] = { + {RAT_BYP, RAT_BYP}, /* 0x00 */ + {RAT_BYP, RAT_BYP}, /* 0x01 */ + {RAT_BYP, RAT_BYP}, /* 0x02 */ + {RAT_BYP, RAT_BYP}, /* 0x03 */ + {RAT_BYP, RAT_BYP}, /* 0x04 */ + {RAT_BYP, RAT_BYP}, /* 0x05 */ + {RAT_BYP, RAT_BYP}, /* 0x06 */ + {RAT_BYP, RAT_BYP}, /* 0x07 */ + {RAT_1_TO_1, RAT_1_TO_2}, /* 0x08 */ + {RAT_1_TO_1, RAT_1_TO_4}, /* 0x09 */ + {RAT_1_TO_1, RAT_1_TO_8}, /* 0x0A */ + {RAT_1_TO_1, RAT_1_TO_8}, /* 0x0B */ + {RAT_1_5_TO_1, RAT_1_TO_2}, /* 0x0C */ + {RAT_1_5_TO_1, RAT_1_TO_4}, /* 0x0D */ + {RAT_1_5_TO_1, RAT_1_TO_8}, /* 0x0E */ + {RAT_1_5_TO_1, RAT_1_TO_8}, /* 0x0F */ + {RAT_2_TO_1, RAT_1_TO_2}, /* 0x10 */ + {RAT_2_TO_1, RAT_1_TO_4}, /* 0x11 */ + {RAT_2_TO_1, RAT_1_TO_8}, /* 0x12 */ + {RAT_2_TO_1, RAT_1_TO_8}, /* 0x13 */ + {RAT_2_5_TO_1, RAT_1_TO_2}, /* 0x14 */ + {RAT_2_5_TO_1, RAT_1_TO_4}, /* 0x15 */ + {RAT_2_5_TO_1, RAT_1_TO_8}, /* 0x16 */ + {RAT_2_5_TO_1, RAT_1_TO_8}, /* 0x17 */ + {RAT_3_TO_1, RAT_1_TO_2}, /* 0x18 */ + {RAT_3_TO_1, RAT_1_TO_4}, /* 0x19 */ + {RAT_3_TO_1, RAT_1_TO_8}, /* 0x1A */ + {RAT_3_TO_1, RAT_1_TO_8}, /* 0x1B */ +}; + +/** + * enum reg_type - Register to read a field from + * @REG_SCCR: Use the SCCR register + * @REG_SPMR: Use the SPMR register + */ +enum reg_type { + REG_SCCR, + REG_SPMR, +}; + +/** + * enum mode_type - Description of how to read a specific frequency value + * @TYPE_INVALID: Unknown type, will provoke error + * @TYPE_SCCR_STANDARD: Read a field from the SCCR register, and use it + * as a divider for the CSB clock to compute the + * frequency + * @TYPE_SCCR_ONOFF: The field describes a bit flag that can turn the + * clock on or off + * @TYPE_SPMR_DIRECT_MULTIPLY: Read a field from the SPMR register, and use it + * as a multiplier for the CSB clock to compute the + * frequency + * @TYPE_SPECIAL: The frequency is calculated in a non-standard way + */ +enum mode_type { + TYPE_INVALID = 0, + TYPE_SCCR_STANDARD, + TYPE_SCCR_ONOFF, + TYPE_SPMR_DIRECT_MULTIPLY, + TYPE_SPECIAL, +}; + +/* Map of each clock index to its human-readable name */ +static const char * const names[] = { + [MPC83XX_CLK_CORE] = "Core", + [MPC83XX_CLK_CSB] = "Coherent System Bus", + [MPC83XX_CLK_QE] = "QE", + [MPC83XX_CLK_BRG] = "BRG", + [MPC83XX_CLK_LBIU] = "Local Bus Controller", + [MPC83XX_CLK_LCLK] = "Local Bus", + [MPC83XX_CLK_MEM] = "DDR", + [MPC83XX_CLK_MEM_SEC] = "DDR Secondary", + [MPC83XX_CLK_ENC] = "SEC", + [MPC83XX_CLK_I2C1] = "I2C1", + [MPC83XX_CLK_I2C2] = "I2C2", + [MPC83XX_CLK_TDM] = "TDM", + [MPC83XX_CLK_SDHC] = "SDHC", + [MPC83XX_CLK_TSEC1] = "TSEC1", + [MPC83XX_CLK_TSEC2] = "TSEC2", + [MPC83XX_CLK_USBDR] = "USB DR", + [MPC83XX_CLK_USBMPH] = "USB MPH", + [MPC83XX_CLK_PCIEXP1] = "PCIEXP1", + [MPC83XX_CLK_PCIEXP2] = "PCIEXP2", + [MPC83XX_CLK_SATA] = "SATA", + [MPC83XX_CLK_DMAC] = "DMAC", + [MPC83XX_CLK_PCI] = "PCI", +}; + +/** + * struct clk_mode - Structure for clock mode descriiptions + * @low: The low bit of the data field to read for this mode (may not apply to + * some modes) + * @high: The high bit of the data field to read for this mode (may not apply to + * some modes) + * @type: The type of the mode description (one of enum mode_type) + */ +struct clk_mode { + u8 low; + u8 high; + int type; +}; + +/** + * set_mode() - Build a clock mode description from data + * @mode: The clock mode description to be filled out + * @low: The low bit of the data field to read for this mode (may not apply to + * some modes) + * @high: The high bit of the data field to read for this mode (may not apply to + * some modes) + * @type: The type of the mode description (one of enum mode_type) + * + * Clock mode descriptions are a succinct description of how to read a specific + * clock's rate from the hardware; usually by reading a specific field of a + * register, such a s the SCCR register, but some types use different methods + * for obtaining the clock rate. + */ +static void set_mode(struct clk_mode *mode, u8 low, u8 high, int type) +{ + mode->low = low; + mode->high = high; + mode->type = type; +} + +/** + * retrieve_mode() - Get the clock mode description for a specific clock + * @clk: The identifier of the clock for which the clock description should + * be retrieved + * @soc_type: The type of MPC83xx SoC for which the clock description should be + * retrieved + * @mode: Pointer to a clk_mode structure to be filled with data for the + * clock + * + * Since some clock rate are stored in different places on different MPC83xx + * SoCs, the SoC type has to be supplied along with the clock's identifier. + * + * Return: 0 if OK, -ve on error + */ +static int retrieve_mode(int clk, int soc_type, struct clk_mode *mode) +{ + switch (clk) { + case MPC83XX_CLK_CORE: + case MPC83XX_CLK_CSB: + case MPC83XX_CLK_QE: + case MPC83XX_CLK_BRG: + case MPC83XX_CLK_LCLK: + case MPC83XX_CLK_I2C2: + set_mode(mode, 0, 0, TYPE_SPECIAL); + break; + case MPC83XX_CLK_MEM: + set_mode(mode, 1, 1, TYPE_SPMR_DIRECT_MULTIPLY); + break; + case MPC83XX_CLK_LBIU: + case MPC83XX_CLK_MEM_SEC: + set_mode(mode, 0, 0, TYPE_SPMR_DIRECT_MULTIPLY); + break; + case MPC83XX_CLK_TSEC1: + set_mode(mode, 0, 1, TYPE_SCCR_STANDARD); + break; + case MPC83XX_CLK_TSEC2: + if (soc_type == SOC_MPC8313) /* I2C and TSEC2 are the same register */ + set_mode(mode, 2, 3, TYPE_SCCR_STANDARD); + else /* FIXME(mario.six@gdsys.cc): This has separate enable/disable bit! */ + set_mode(mode, 0, 1, TYPE_SCCR_STANDARD); + break; + case MPC83XX_CLK_SDHC: + set_mode(mode, 4, 5, TYPE_SCCR_STANDARD); + break; + case MPC83XX_CLK_ENC: + set_mode(mode, 6, 7, TYPE_SCCR_STANDARD); + break; + case MPC83XX_CLK_I2C1: + if (soc_type == SOC_MPC8349) + set_mode(mode, 2, 3, TYPE_SCCR_STANDARD); + else /* I2C and ENC are the same register */ + set_mode(mode, 6, 7, TYPE_SCCR_STANDARD); + break; + case MPC83XX_CLK_PCIEXP1: + set_mode(mode, 10, 11, TYPE_SCCR_STANDARD); + break; + case MPC83XX_CLK_PCIEXP2: + set_mode(mode, 12, 13, TYPE_SCCR_STANDARD); + break; + case MPC83XX_CLK_USBDR: + if (soc_type == SOC_MPC8313 || soc_type == SOC_MPC8349) + set_mode(mode, 10, 11, TYPE_SCCR_STANDARD); + else + set_mode(mode, 8, 9, TYPE_SCCR_STANDARD); + break; + case MPC83XX_CLK_USBMPH: + set_mode(mode, 8, 9, TYPE_SCCR_STANDARD); + break; + case MPC83XX_CLK_PCI: + set_mode(mode, 15, 15, TYPE_SCCR_ONOFF); + break; + case MPC83XX_CLK_DMAC: + set_mode(mode, 26, 27, TYPE_SCCR_STANDARD); + break; + case MPC83XX_CLK_SATA: + /* FIXME(mario.six@gdsys.cc): All SATA controllers must have the same clock ratio */ + if (soc_type == SOC_MPC8379) { + set_mode(mode, 24, 25, TYPE_SCCR_STANDARD); + set_mode(mode, 26, 27, TYPE_SCCR_STANDARD); + set_mode(mode, 28, 29, TYPE_SCCR_STANDARD); + set_mode(mode, 30, 31, TYPE_SCCR_STANDARD); + } else { + set_mode(mode, 18, 19, TYPE_SCCR_STANDARD); + set_mode(mode, 20, 21, TYPE_SCCR_STANDARD); + } + break; + case MPC83XX_CLK_TDM: + set_mode(mode, 26, 27, TYPE_SCCR_STANDARD); + break; + default: + debug("%s: Unknown clock type %d on soc type %d\n", + __func__, clk, soc_type); + set_mode(mode, 0, 0, TYPE_INVALID); + return -EINVAL; + } + + return 0; +} + +/** + * get_spmr() - Read the SPMR (System PLL Mode Register) + * @im: Pointer to the MPC83xx main register map in question + * + * Return: The SPMR value as a 32-bit number. + */ +static inline u32 get_spmr(immap_t *im) +{ + u32 res = in_be32(&im->clk.spmr); + + return res; +} + +/** + * get_sccr() - Read the SCCR (System Clock Control Register) + * @im: Pointer to the MPC83xx main register map in question + * + * Return: The SCCR value as a 32-bit number. + */ +static inline u32 get_sccr(immap_t *im) +{ + u32 res = in_be32(&im->clk.sccr); + + return res; +} + +/** + * get_lcrr() - Read the LCRR (Clock Ratio Register) + * @im: Pointer to the MPC83xx main register map in question + * + * Return: The LCRR value as a 32-bit number. + */ +static inline u32 get_lcrr(immap_t *im) +{ + u32 res = in_be32(&im->im_lbc.lcrr); + + return res; +} + +/** + * get_pci_sync_in() - Read the PCI synchronization clock speed + * @im: Pointer to the MPC83xx main register map in question + * + * Return: The PCI synchronization clock speed value as a 32-bit number. + */ +static inline u32 get_pci_sync_in(immap_t *im) +{ + u8 clkin_div; + + clkin_div = (get_spmr(im) & SPMR_CKID) >> SPMR_CKID_SHIFT; + return CONFIG_SYS_CLK_FREQ / (1 + clkin_div); +} + +/** + * get_csb_clk() - Read the CSB (Coheren System Bus) clock speed + * @im: Pointer to the MPC83xx main register map in question + * + * Return: The CSB clock speed value as a 32-bit number. + */ +static inline u32 get_csb_clk(immap_t *im) +{ + u8 spmf; + + spmf = (get_spmr(im) & SPMR_SPMF) >> SPMR_SPMF_SHIFT; + return CONFIG_SYS_CLK_FREQ * spmf; +} + +/** + * spmr_field() - Read a specific SPMR field + * @im: Pointer to the MPC83xx main register map in question + * @mask: A bitmask that describes the bitfield to be read + * + * Return: The value of the bit field as a 32-bit number. + */ +static inline uint spmr_field(immap_t *im, u32 mask) +{ + /* Extract shift from bitmask */ + uint shift = mask ? ffs(mask) - 1 : 0; + + return (get_spmr(im) & mask) >> shift; +} + +/** + * sccr_field() - Read a specific SCCR field + * @im: Pointer to the MPC83xx main register map in question + * @mask: A bitmask that describes the bitfield to be read + * + * Return: The value of the bit field as a 32-bit number. + */ +static inline uint sccr_field(immap_t *im, u32 mask) +{ + /* Extract shift from bitmask */ + uint shift = mask ? ffs(mask) - 1 : 0; + + return (get_sccr(im) & mask) >> shift; +} + +/** + * lcrr_field() - Read a specific LCRR field + * @im: Pointer to the MPC83xx main register map in question + * @mask: A bitmask that describes the bitfield to be read + * + * Return: The value of the bit field as a 32-bit number. + */ +static inline uint lcrr_field(immap_t *im, u32 mask) +{ + /* Extract shift from bitmask */ + uint shift = mask ? ffs(mask) - 1 : 0; + + return (get_lcrr(im) & mask) >> shift; +} diff --git a/include/dt-bindings/clk/mpc83xx-clk.h b/include/dt-bindings/clk/mpc83xx-clk.h new file mode 100644 index 00000000000..db4ea15cf42 --- /dev/null +++ b/include/dt-bindings/clk/mpc83xx-clk.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2018 + * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc + */ + +#ifndef DT_BINDINGS_MPC83XX_CLK_H +#define DT_BINDINGS_MPC83XX_CLK_H +#define MPC83XX_CLK_CORE 0 +#define MPC83XX_CLK_CSB 1 +#define MPC83XX_CLK_QE 2 +#define MPC83XX_CLK_BRG 3 +#define MPC83XX_CLK_LBIU 4 +#define MPC83XX_CLK_LCLK 5 +#define MPC83XX_CLK_MEM 6 +#define MPC83XX_CLK_MEM_SEC 7 +#define MPC83XX_CLK_ENC 8 +#define MPC83XX_CLK_I2C1 9 +#define MPC83XX_CLK_I2C2 10 +#define MPC83XX_CLK_TDM 11 +#define MPC83XX_CLK_SDHC 12 +#define MPC83XX_CLK_TSEC1 13 +#define MPC83XX_CLK_TSEC2 14 +#define MPC83XX_CLK_USBDR 15 +#define MPC83XX_CLK_USBMPH 16 +#define MPC83XX_CLK_PCIEXP1 17 +#define MPC83XX_CLK_PCIEXP2 18 +#define MPC83XX_CLK_SATA 19 +#define MPC83XX_CLK_DMAC 20 +#define MPC83XX_CLK_PCI 21 +/* Count */ +#define MPC83XX_CLK_COUNT 22 +#endif /* DT_BINDINGS_MPC83XX_CLK_H */