From: Dinh Nguyen dinguyen@opensource.altera.com
Add config for the Arria10 SoC Development Kit.
Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com --- v2: clean up socfpga_arria10_socdk.h to use socfpga_common.h --- include/configs/socfpga_arria10_socdk.h | 157 ++++++++++++++++++++++++++++++++ 1 file changed, 157 insertions(+) create mode 100644 include/configs/socfpga_arria10_socdk.h
diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h new file mode 100644 index 0000000..c1a5b4a --- /dev/null +++ b/include/configs/socfpga_arria10_socdk.h @@ -0,0 +1,157 @@ +/* + * Copyright (C) 2015 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __CONFIG_SOCFGPA_ARRIA10_H__ +#define __CONFIG_SOCFGPA_ARRIA10_H__ + +#include <asm/arch/base_addr_a10.h> +/* U-Boot Commands */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_DOS_PARTITION +#define CONFIG_FAT_WRITE +#define CONFIG_HW_WATCHDOG + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_EXT4_WRITE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_PING + +/* Default load address */ +#define CONFIG_SYS_LOAD_ADDR 0x8000 + +/* + * Display CPU and Board Info + */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_DISPLAY_BOARDINFO_LATE + +/* + * Environment setup + */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* + * Can't poll in semihosting; so turn off automatic boot command + */ +#define CONFIG_BOOTCOMMAND "run callscript; run mmcload;" \ + "run set_initswstate; run mmcboot" + +/* + * arguments passed to the bootz command. The value of + * CONFIG_BOOTARGS goes into the environment value "bootargs". + * Do note the value will overide also the chosen node in FDT blob. + */ +#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=n\0" \ + "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "bootimage=zImage\0" \ + "fdt_addr=100\0" \ + "fdtimage=socfpga.dtb\0" \ + "fsloadcmd=ext2load\0" \ + "bootm ${loadaddr} - ${fdt_addr}\0" \ + "mmcroot=/dev/mmcblk0p2\0" \ + "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${mmcroot} rw rootwait;" \ + "bootz ${loadaddr} - ${fdt_addr}\0" \ + "mmcload=mmc rescan;" \ + "load mmc 0:1 ${loadaddr} ${bootimage};" \ + "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ + "qspiroot=/dev/mtdblock0\0" \ + "qspirootfstype=jffs2\0" \ + "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ + "bootm ${loadaddr} - ${fdt_addr}\0" + +/* + * Memory configurations + */ +#define PHYS_SDRAM_1_SIZE 0x2000000 + +/* + * network support + */ +#define CONFIG_DESIGNWARE_ETH +#ifdef CONFIG_DESIGNWARE_ETH +#define CONFIG_NET_MULTI +#define CONFIG_DW_ALTDESCRIPTOR +#define CONFIG_DW_SEARCH_PHY +#define CONFIG_PHY_GIGE +#define CONFIG_DW_AUTONEG +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +/* phy */ +#define CONFIG_EPHY0_PHY_ADDR 7 +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9031 +#endif /* CONFIG_DESIGNWARE_ETH */ + + +/* + * MMC support + */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0/* device 0 */ +#define CONFIG_ENV_OFFSET 512/* just after the MBR */ + +#define CONFIG_CMD_FAT +#define CONFIG_CMD_MMC +/* Enable FAT write support */ +#define CONFIG_FAT_WRITE + +/* configure a clustsize smaller than the default 64k */ +#define CONFIG_FS_FAT_MAX_CLUSTSIZE 16384 +/* MMC support */ +#define CONFIG_SDMMC_BASE (SOCFPGA_SDMMC_ADDRESS) +#define CONFIG_GENERIC_MMC +#define CONFIG_DWMMC +#define CONFIG_SOCFPGA_DWMMC +#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3 +#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0 +#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 +/* using smaller max blk cnt to avoid flooding the limited stack we have */ +#define CONFIG_SOCFPGA_DWMMC_BUS_HZ CONFIG_HPS_CLK_SDMMC_HZ +#define CONFIG_SOCFPGA_DWMMC_BUS_WIDTH 4 +/* requird for dw_mmc driver */ +#define CONFIG_BOUNCE_BUFFER +#else +#define CONFIG_ENV_IS_NOWHERE +#endif /* CONFIG_MMC */ + +/* + * NAND + */ +#ifdef CONFIG_NAND_DENALI +#define CONFIG_CMD_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#define CONFIG_SYS_NAND_REGS_BASE 0xff200000 +#define CONFIG_SYS_NAND_DATA_BASE 0xff300000 +#define CONFIG_SYS_NAND_BASE 0xff400000 +#define CONFIG_SYS_NAND_ONFI_DETECTION +/* The ECC size which either 512 or 1024 */ +#define CONFIG_NAND_DENALI_ECC_SIZE (512) +#endif /* CONFIG_NAND_DENALI */ + +/* The rest of the configuration is shared */ +#include <configs/socfpga_common.h> +#endif /* __CONFIG_H */