On Tue, 2013-12-10 at 20:46 -0600, Liu Po-B43644 wrote:
Sorry for late reply since the email system crash.
-----Original Message----- From: Scott Wood [mailto:scottwood@freescale.com] Sent: Saturday, December 07, 2013 9:22 AM To: Liu Po-B43644 Cc: u-boot@lists.denx.de; Sun York-R58495; Kushwaha
Prabhakar-B32579
Subject: Re: [PATCH v2 2/2] powerpc/c29xpcie: 8k page size NAND
boot
support base on TPL/SPL
On Thu, 2013-12-05 at 14:19 +0800, Po Liu wrote:
diff --git a/board/freescale/c29xpcie/spl.c b/board/freescale/c29xpcie/spl.c new file mode 100644 index 0000000..7bc8ce1 --- /dev/null +++ b/board/freescale/c29xpcie/spl.c @@ -0,0 +1,73 @@ +/* Copyright 2013 Freescale Semiconductor, Inc.
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <ns16550.h> +#include <malloc.h> +#include <mmc.h> +#include <nand.h> +#include <i2c.h>
+DECLARE_GLOBAL_DATA_PTR;
+ulong get_effective_memsize(void) +{
- return CONFIG_SYS_L2_SIZE;
+}
+void board_init_f(ulong bootflag) +{
- u32 plat_ratio;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
- console_init_f();
- /* initialize selected port with appropriate baud rate */
- plat_ratio = in_be32(&gur->porpllsr) &
MPC85xx_PORPLLSR_PLAT_RATIO;
- plat_ratio >>= 1;
- gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
gd->bus_clk / 16 / CONFIG_BAUDRATE);- /* copy code to RAM and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- other blocks can be read.
- */
- relocate_code(CONFIG_SPL_RELOC_STACK, 0,
+CONFIG_SPL_RELOC_TEXT_BASE); }
+void board_init_r(gd_t *gd, ulong dest_addr) {
- /* Pointer is writable since we allocated a register for it */
- gd = (gd_t *)CONFIG_SPL_GD_ADDR;
- bd_t *bd;
- memset(gd, 0, sizeof(gd_t));
- bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
- memset(bd, 0, sizeof(bd_t));
- gd->bd = bd;
- bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
- bd->bi_memsize = CONFIG_SYS_L2_SIZE;
- probecpu();
- get_clocks();
- mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);- /* relocate environment function pointers etc. */
- nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)CONFIG_ENV_ADDR);gd->env_addr = (ulong)(CONFIG_ENV_ADDR);- gd->env_valid = 1;
- i2c_init_all();
- gd->ram_size = initdram(0);
- puts("\nTertiary program loader running in sram...");
Why do you assume tertiary? Couldn't this be SPL for SD/SPI? Or
was it
a copy/paste error that you added things to the board config file
for
SD/SPI (after all, the subject line says it's a NAND patch)?
Yes, I assume this patch only for NAND boot for C29XPCIE.
Then why did you add a "#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)" section in the board config file?
-Scott