Signed-off-by: Alexander Stein alexander.stein@systec-electronic.com --- board/atmel/at91sam9260ek/at91sam9260ek.c | 88 +++++++++++++--------------- board/atmel/at91sam9260ek/led.c | 12 ++-- include/configs/at91sam9260ek.h | 12 ++-- 3 files changed, 53 insertions(+), 59 deletions(-)
diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c index 063ddbf..8126c4f 100644 --- a/board/atmel/at91sam9260ek/at91sam9260ek.c +++ b/board/atmel/at91sam9260ek/at91sam9260ek.c @@ -29,6 +29,7 @@ #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> +#include <asm/arch/at91_matrix.h> #include <asm/arch/gpio.h> #include <asm/arch/io.h> #include <asm/arch/hardware.h> @@ -48,48 +49,55 @@ DECLARE_GLOBAL_DATA_PTR; static void at91sam9260ek_nand_hw_init(void) { unsigned long csa; + at91_smc_t *smc = (at91_smc_t *) AT91_SMC_BASE; + at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
/* Enable CS3 */ - csa = at91_sys_read(AT91_MATRIX_EBICSA); - at91_sys_write(AT91_MATRIX_EBICSA, - csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); + csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A; + writel(csa, &matrix->csa);
/* Configure SMC CS3 for NAND/SmartMedia */ - at91_sys_write(AT91_SMC_SETUP(3), - AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(3), - AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | - AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); - at91_sys_write(AT91_SMC_CYCLE(3), - AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); - at91_sys_write(AT91_SMC_MODE(3), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | #ifdef CONFIG_SYS_NAND_DBW_16 - AT91_SMC_DBW_16 | + AT91_SMC_MODE_DBW_16 | #else /* CONFIG_SYS_NAND_DBW_8 */ - AT91_SMC_DBW_8 | + AT91_SMC_MODE_DBW_8 | #endif - AT91_SMC_TDF_(2)); + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode);
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC); + writel(1 << AT91SAM9260_ID_PIOC, &pmc->pcer);
/* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + at91_set_pio_input(CONFIG_SYS_NAND_ENABLE_PIN, 1); } #endif
#ifdef CONFIG_MACB static void at91sam9260ek_macb_hw_init(void) { - unsigned long rstc; + unsigned long erstl; + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE; + at91_rstc_t *rstc = (at91_rstc_t *) AT91_RSTC_BASE;
/* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC); + writel(1 << AT91SAM9260_ID_EMAC, &pmc->pcer);
/* * Disable pull-up on: @@ -102,39 +110,25 @@ static void at91sam9260ek_macb_hw_init(void) * * PHY has internal pull-down */ - writel(pin_to_mask(AT91_PIN_PA14) | - pin_to_mask(AT91_PIN_PA15) | - pin_to_mask(AT91_PIN_PA17) | - pin_to_mask(AT91_PIN_PA25) | - pin_to_mask(AT91_PIN_PA26) | - pin_to_mask(AT91_PIN_PA28), - pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
- rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL; + writel((1 << 17) | (1 << 14) | (1 << 15) | (1 << 25) | (1 << 26) | (1 << 28), &pio->pioa.pudr);
- /* Need to reset PHY -> 500ms reset */ - at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - (AT91_RSTC_ERSTL & (0x0D << 8)) | - AT91_RSTC_URSTEN); + erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
- at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); + /* Need to reset PHY -> 500ms reset */ + writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) | + AT91_RSTC_MR_URSTEN, &rstc->mr);
+ writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); /* Wait for end hardware reset */ - while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); + while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) + ;
/* Restore NRST value */ - at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - (rstc) | - AT91_RSTC_URSTEN); + writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
/* Re-enable pull-up */ - writel(pin_to_mask(AT91_PIN_PA14) | - pin_to_mask(AT91_PIN_PA15) | - pin_to_mask(AT91_PIN_PA17) | - pin_to_mask(AT91_PIN_PA25) | - pin_to_mask(AT91_PIN_PA26) | - pin_to_mask(AT91_PIN_PA28), - pin_to_controller(AT91_PIN_PA0) + PIO_PUER); + writel((1 << 17) | (1 << 14) | (1 << 15) | (1 << 25) | (1 << 26) | (1 << 28), &pio->pioa.puer);
at91_macb_hw_init(); } @@ -186,7 +180,7 @@ int board_eth_init(bd_t *bis) { int rc = 0; #ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00); + rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x00); #endif return rc; } diff --git a/board/atmel/at91sam9260ek/led.c b/board/atmel/at91sam9260ek/led.c index 2424d27..fd29dd8 100644 --- a/board/atmel/at91sam9260ek/led.c +++ b/board/atmel/at91sam9260ek/led.c @@ -30,12 +30,14 @@
void coloured_LED_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOA); + writel(1 << AT91SAM9260_ID_PIOA, &pmc->pcer);
- at91_set_gpio_output(CONFIG_RED_LED, 1); - at91_set_gpio_output(CONFIG_GREEN_LED, 1); + at91_set_pio_output(CONFIG_RED_LED, 1); + at91_set_pio_output(CONFIG_GREEN_LED, 1);
- at91_set_gpio_value(CONFIG_RED_LED, 0); - at91_set_gpio_value(CONFIG_GREEN_LED, 1); + at91_set_pio_output(CONFIG_RED_LED, 0); + at91_set_pio_output(CONFIG_GREEN_LED, 1); } diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 8aee5a6..bcce5d1 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -29,8 +29,6 @@
#include <asm/sizes.h>
-#define CONFIG_AT91_LEGACY - /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ #define CONFIG_SYS_HZ 1000 @@ -65,8 +63,8 @@
/* LED */ #define CONFIG_AT91_LED -#define CONFIG_RED_LED AT91_PIN_PA9 /* this is the power led */ -#define CONFIG_GREEN_LED AT91_PIN_PA6 /* this is the user led */ +#define CONFIG_RED_LED AT91_PIO_PORTA, 9 /* this is the power led */ +#define CONFIG_GREEN_LED AT91_PIO_PORTA, 6 /* this is the user led */
#define CONFIG_BOOTDELAY 3
@@ -101,7 +99,7 @@
/* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI -#define CONFIG_HAS_DATAFLASH 1 +#define CONFIG_HAS_DATAFLASH #define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 2 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ @@ -125,8 +123,8 @@ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTC, 13
#endif