Re: [U-Boot] [PATCH 5/8] net: zynq: Wait till packet is sent

On Tue, Oct 27, 2015 at 10:17 AM, Michal Simek michal.simek@xilinx.com wrote:

Wait till BD is process to ensure that packet was sent successfully.

process -> processed

Signed-off-by: Michal Simek michal.simek@xilinx.com

drivers/net/zynq_gem.c | 33 ++++++++++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-)

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index e49aa86127d1..c56e02132ae9 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -23,6 +23,7 @@ #include <asm/system.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> +#include <asm-generic/errno.h>

#if !defined(CONFIG_PHYLIB) # error XILINX_GEM_ETHERNET requires PHYLIB @@ -86,6 +87,8 @@ ZYNQ_GEM_DMACR_TXSIZE | \ ZYNQ_GEM_DMACR_RXBUF)

+#define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */

/* Use MII register 1 (MII status register) to detect PHY */ #define PHY_DETECT_REG 1

@@ -427,6 +430,33 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) return 0; }

+static inline int wait_for_bit(const char *func, u32 *reg, const u32 mask,

•                          bool set, unsigned int timeout)
  

There is no need to specify "inline" here.

+{

•   u32 val;
  

•   unsigned long start = get_timer(0);
  

•   while (1) {
  

•           val = readl(reg);
  

•           if (!set)
  

•                   val = ~val;
  

•           if ((val & mask) == mask)
  

•                   return 0;
  

•           if (get_timer(start) > timeout)
  

•                   break;
  

•           udelay(1);
  

•   }
  

•   debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
  

•         func, reg, mask, set);
  

•   return -ETIMEDOUT;
  

+}

static int zynq_gem_send(struct eth_device *dev, void *ptr, int len) { u32 addr, size; @@ -467,7 +497,8 @@ static int zynq_gem_send(struct eth_device *dev, void *ptr, int len) if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED) printf("TX buffers exhausted in mid frame\n");

•   return 0;
  

•   return wait_for_bit(__func__, &regs->txsr, ZYNQ_GEM_TSR_DONE,
  

•                       true, 20000);
  

}

/* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */

2.5.0

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